JP2016218211A - Display device, display module having display device, and electronic apparatus having display device or display module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel display device having reduced power consumption.SOLUTION: A display device has a liquid crystal material held between a first substrate and a second substrate, the first substrate has a plurality of pixels, the pixel has first to third pixel electrodes, the first to third pixel electrodes have light reflectivity and conductivity, the second pixel electrode has a region overlapping the upper part of the first pixel electrode through an insulation film, the third pixel electrode has a region overlapping the upper part of the second pixel electrode through the insulation film, the third pixel electrode has a region overlapping the upper part of the first pixel electrode of an adjacent pixel through the insulation film, the second substrate has color filters showing first to third hues, and the color filters showing first to third hues are disposed so as to face the first to third pixel electrodes.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a display device. In particular, the present invention relates to a liquid crystal display device having a liquid crystal element.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

  Note that in this specification and the like, a display device refers to all devices having a display function. The display device may include a semiconductor device such as a transistor, an arithmetic device, a memory device, and the like. In addition, the display device includes a drive circuit that drives a plurality of pixels. In addition, the display device includes a control circuit, a power supply circuit, a signal generation circuit, and the like which are arranged on another substrate.

  In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, a memory device, a display device, and an electronic device may include a semiconductor device.

  Display devices are becoming more commoditized as a result of recent technological innovations. In the future, products with higher added value are required, and technological development is active.

  As one of the added values required for a display device, reduction of power consumption has attracted attention for the purpose of extending the usage time in mobile devices and the like.

JP2011-237760A

  An object of one embodiment of the present invention is to provide a novel display device that does not impair display quality. Another object of one embodiment of the present invention is to provide a novel display device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide a novel display module including the display device or a novel electronic device including the display module. Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a display device in which a liquid crystal material is sandwiched between a first substrate and a second substrate. The first substrate includes a plurality of pixels, and the pixels include first to third pixel electrodes. The first to third pixel electrodes have light reflectivity and conductivity, and the second pixel electrode has a region overlapping with the first pixel electrode with an insulating film interposed therebetween. The third pixel electrode has a region overlapping with the upper part of the second pixel electrode via the insulating film, and the third pixel electrode overlaps with the upper part of the first pixel electrode of the adjacent pixel via the insulating film. The second substrate has color filters showing the first to third hues, and the color filters of the first to third hues are arranged so as to face the first to third pixel electrodes. It is the display device characterized by being made.

  Another embodiment of the present invention is a display device including a conductive film on a surface of the first to third color filters facing the liquid crystal material.

  Another embodiment of the present invention is characterized in that a film having a property of transmitting part of incident light and reflecting the rest is provided on the surface of the first to third color filters facing the liquid crystal material. Display device.

In one embodiment of the present invention, the transmission wavelength of the color filters of the first to third hues is λ _x (x = 1, 2, 3), the refractive index of the liquid crystal is n, and the first to third pixel electrodes The display device is characterized by satisfying the relationship of the expression (1) which is an optical resonance condition when the distance between the surface and the surface of the conductive or light reflective film is L _x .

  Another embodiment of the present invention is a display device in which a pixel includes a switching element.

  Another embodiment of the present invention is a display device in which the switching element is a field-effect transistor.

  Another embodiment of the present invention is a display device in which the switching element includes an oxide semiconductor.

  According to one embodiment of the present invention, a novel display device that does not impair display quality can be provided. Alternatively, according to one embodiment of the present invention, a novel display device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided. Alternatively, according to one embodiment of the present invention, a novel display module including the display device or a novel electronic device including the display module can be provided.

FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. The schematic diagram which shows the relationship between the polarizing element and the orientation direction of a liquid-crystal layer. FIG. 6 shows optical characteristics of a display device. FIG. 14 is a top view illustrating one embodiment of a display device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a display device. FIG. FIG. 11 is a block diagram illustrating a structure of a display device. FIG. 14 illustrates a structure of a display portion of a display device. FIG. 14 illustrates a structure of a display portion of a display device. The circuit diagram of the display part of a display apparatus. FIG. 6 illustrates source line inversion driving and dot inversion driving of a display device. 4 is a timing chart illustrating source line inversion driving and dot inversion driving of a display device. 4A and 4B illustrate a structure of a display device and an example of a display method on the display device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. 9 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 8A and 8B illustrate a method for forming a CAAC-OS. FIG. 6 illustrates a crystal of InMZnO ₄ . 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. The figure explaining a band structure. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 14 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a display device. 8A and 8B illustrate an example of a display method on a display device. 8A and 8B illustrate an example of a display method on a display device. 8A and 8B illustrate an example of a display method on a display device. 8A and 8B illustrate an example of a display method on a display device. The figure explaining a display module. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, one embodiment of the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the gist and scope of the present invention. The Therefore, one embodiment of the present invention is not construed as being limited to the description of the following embodiment modes. In the embodiments described below, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated.

  Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

  In addition, the first and second ordinal numbers used in this specification and the like are given in order to avoid mixing of constituent elements, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. Further, the boundary between the “semiconductor” and the “insulator” is ambiguous, and it may be difficult to strictly distinguish them. Therefore, the “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. Alternatively, the “insulator” in this specification and the like can be referred to as a “semi-insulator” in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and it may be difficult to strictly distinguish them. Therefore, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.

  Note that the functions of the “source” and “drain” of the transistor may be interchanged when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  Note that in this specification and the like, patterning uses a photolithography process. However, the patterning is not limited to the photolithography process, and a process other than the photolithography process can be used. The mask formed in the photolithography process is removed after the etching process.

  Note that in this specification and the like, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen, preferably 55 to 65 atomic% oxygen and 1 atomic% nitrogen. More than 20 atomic%, silicon is included in a range of 25 atomic% to 35 atomic%, and hydrogen is included in a range of 0.1 atomic% to 10 atomic%. The silicon nitride oxide film refers to a film having a nitrogen content higher than that of oxygen as a composition. Preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, and silicon is included. This refers to a concentration range of 25 atomic% to 35 atomic% and hydrogen in a concentration range of 0.1 atomic% to 10 atomic%.

(Embodiment 1)
A display device which is one embodiment of the present invention will be described with reference to FIGS. FIG. 1 schematically shows a cross section of a pixel portion of a display portion of a display device which is one embodiment of the present invention. Embodiments described later are referred to for a display portion having a pixel portion and a display device having a display portion in the display device.

<Configuration of Pixel Unit of Display Device>
A pixel portion 1000a illustrated in FIG. 1 includes a substrate 1010, pixels 1011, pixel electrodes 1011a, 1011b, and 1011c, insulating layers 1012a, 1012b, 1012c, and 1012d, a substrate 1020, color filters 1021a, 1021b, and 1021c, a liquid crystal layer 1030, and a liquid crystal layer 1030. An element 51 is included.

  The pixel 1011 is a minimum unit for displaying an image on the display device which is one embodiment of the present invention, and the pixel 1011 includes pixel electrodes 1011a, 1011b, and 1011c. Part or all of the pixel electrodes 1011a, 1011b, and 1011c may have aluminum, silver, or the like which is a conductive film that reflects visible light. Alternatively, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used as the conductive film that transmits visible light. The same material as the conductive film 120 described in Embodiment 7 can be used. The pixel electrodes 1011a, 1011b, and 1011c may have a flat surface as shown in FIG. 1, or may have irregularities on the surface (not shown) as another form. Further, the pixel electrodes 1011a, 1011b, and 1011c preferably have a thickness in the range of 50 nm to 500 nm, preferably 100 nm to 300 nm. In FIG. 1, the pixel electrodes 1011a, 1011b, and 1011c are shown as having the same film thickness, but the present invention is not limited to this, and the film thicknesses may be different.

  The substrate 1010 includes a circuit for applying a potential to the pixel electrodes 1011a, 1011b, and 1011c. In addition, the pixel electrodes 1011a, 1011b, and 1011c may have a structure for electrical connection with a circuit included in the substrate 1010. Further, a control device for controlling a potential applied to the pixel electrodes 1011a, 1011b, and 1011c may be provided. A semiconductor device can be used as such a control device. Other embodiments can be referred to for a structure and a formation method of a substrate including such a circuit or a semiconductor device.

  A liquid crystal element 51 is formed by sandwiching a liquid crystal layer 1030 between a substrate 1010 having pixel electrodes 1011a, 1011b, and 1011c and the substrate 1020. In the liquid crystal element 51, the polarization characteristics exhibited by the liquid crystal layer 1030 can be changed by controlling the potential applied to the pixel electrodes 1011a, 1011b, and 1011c. The liquid crystal element 51 illustrated in FIG. 1 includes a pixel electrode 1011b, a liquid crystal layer 1030, and a color filter 1021b. However, the liquid crystal element is similarly applied to a combination of another pixel electrode, an upper liquid crystal layer, and a color filter. Is configured.

  As the liquid crystal forming the liquid crystal layer 1030, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a nematic phase, a cholesteric phase, a smectic phase, a blue phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

  The insulating layers 1012a, 1012b, 1012c, and 1012d are arranged so that independent potentials can be applied to the pixel electrodes 1011a, 1011b, and 1011c, respectively.

  As shown in FIG. 1, the pixel electrode 1011b is arranged above a partial region of the pixel electrode 1011a. The pixel electrode 1011c is disposed above a partial region of the pixel electrode 1011b. The pixel electrode 1011c is disposed above a partial region of the pixel electrode 1011a.

  An insulating layer 1012a is disposed in a portion where 1011b overlaps with the pixel electrode 1011a to insulate the pixel electrodes 1011a and 1011b from each other. An insulating layer 1012b is provided in a portion where 1011c overlaps with the pixel electrode 1011b to insulate the pixel electrodes 1011b and 1011c from each other. An insulating layer 1012c is disposed in a portion where 1011c overlaps with the pixel electrode 1011a to insulate the pixel electrodes 1011a and 1011c from each other.

  The insulating layers 1012a, 1012b, 1012c, and 1012d may be formed using a light-transmitting material or may include a material that absorbs light. Further, a silicon oxide film or a silicon oxynitride film can be used. Moreover, hydrogen may be included. For example, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. The insulating layers 1012a, 1012b, 1012c, and 1012d may be made of the same material or different materials.

  The substrate 1020 is a substrate on which the color filters 1021a, 1021b, and 1021c are formed, and is preferably a light-transmitting material that can withstand the process of forming the color filter.

  The color filters 1021a, 1021b, and 1021c can use materials that exhibit different hues. The color filter includes, for example, a plurality of colors such as red (R), green (G), blue (B), which are the three primary colors of light, or cyan (C), magenta (M), yellow (Y) which are complementary colors. Filters can be appropriately combined and arranged. By using the color filter, the color reproducibility can be increased as compared with the case where the color filter is not used.

  Further, although not shown in FIG. 1, white light in an area not having a color filter is directly used for display by arranging an area having a color filter and an area not having a color filter. It doesn't matter. By disposing a region that does not have a color filter in part, a decrease in luminance due to the light absorption layer can be reduced during white display, and power consumption can be reduced by approximately 20% to 30%.

  Moreover, you may perform the process (alignment process) for improving the orientation of a liquid crystal layer so that a desired optical characteristic can be exhibited. An alignment film is preferably used for the alignment treatment, and the alignment film can be subjected to a treatment such as a rubbing method or a photo-alignment method. It is also possible to use an orientation film such as an obliquely deposited film, a Langmuir / Blodget film, or a self-assembled film. For example, FIG. 2 shows an example in which alignment films 1014 and 1027 are used. The alignment films 1014 and 1027 may use the same material or different materials. When the alignment films 1014 and 1027 are provided, they are formed on the surface in contact with the pixel electrodes 1011a, 1011b, and 1011c, the insulating layers 1012a, 1012b, 1012c, and 1012d as shown in FIG. The liquid crystal layer 1030 and the alignment films 1014 and 1027 are in contact with each other.

  In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the phase transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition in which a polymer of several weight percent or more is mixed is used for the liquid crystal layer. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a polymer has a short response speed and is optically isotropic. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a polymer or the like does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

  Note that the color filter may be disposed on the surface where the liquid crystal layer is present as shown in FIG. 1 or may be disposed on the surface opposite to the surface where the liquid crystal layer is present.

  The substrates 1010 and 1020 are overlapped with each other so that the boundaries between the pixel electrodes 1011a, 1011b, and 1011c and the color filters 1021a, 1021b, and 1021c are not displaced.

  As an operation mode of the liquid crystal of the pixel unit 1000a having the liquid crystal element 51, a TN (Twisted Nematic) mode, an MTN mode (Mixed-mode Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching). Mode, ASM (Axial Symmetrically Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Frequential Liquid mode).

  In order to improve the display quality of the display device having the pixel portion 1000a shown in FIG. 1, the member shown in FIG. 2 may be used.

  The pixel portion 1000b illustrated in FIG. 2 is different from the pixel portion 1000a illustrated in FIG. 1 in that the alignment films 1014 and 1027, the scattering plate 1044, the retardation plate 1042, the polarizing element 1040, the reflection plate 1050, the sealing material 1060, and the spacers 1025 and 1062 are provided. This is an example in which a filler 1064 is arranged.

  For example, depending on the operation mode of the liquid crystal, the polarizing element 1040 may be used if necessary. FIG. 2 shows an example in which the polarizing element 1040 is arranged on the opposite side of the substrate 1020 where the color filters 1021a, 1021b, and 1021c are formed. For example, the color filters 1021a, 1021b, and 1021c are arranged. It is also possible to provide it on the surface on the side.

  In addition, when a part of the pixels has light transmissivity, the reflection plate 1050 can be used. Furthermore, by using the scattering plate 1044, it is possible to perform good display while suppressing the viewing angle dependency of the display portion. Further, a phase difference plate 1042 may be used. For example, the pixel portion 1000a is a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode, and the reflector 1050 is disposed outside the liquid crystal element 51 as shown in FIG. May be. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, or the like can be used.

  As the spacer 1025, a silicon oxide film or a silicon oxynitride film can be used. The spacer 1025 can be formed using a heat-resistant organic material such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin.

  As shown in FIG. 2, the counter electrode 1023 may be arranged on the surface of the color filters 1021a, 1021b, and 1021c on the side facing the liquid crystal layer 1030 so that an electric field can be applied to the liquid crystal layer 1030. . The counter electrode 1023 may be arranged so as to cover the color filters 1021a, 1021b, and 1021c, or may be arranged in an island shape by patterning.

  A film that enhances reflection may be disposed in the vicinity of the counter electrode. For example, as shown in FIG. 2, a semi-transmissive film 1068 for enhancing reflection between the color filter and the counter electrode can be disposed in a desired region. The semi-transmissive film 1068 has light reflectivity, and has a property of transmitting a part of incident light and reflecting the rest. A part of the light reflected by the pixel electrodes 1011a, 1011b, and 1011c is incident on the semi-transmissive film 1068 and a part of the light is transmitted as it is, but the remaining proportion of the light is reflected and travels again toward the pixel electrodes 1011a, 1011b, and 1011c. In some cases, the optical resonance action (also referred to as a cavity) is promoted by repeating light reflection and confining light. As an example of disposing such a film for enhancing reflection, FIG. 2 shows an example of disposing the film at the boundary between adjacent pixel electrodes. However, the film may be disposed above the pixel electrode. It is possible to select appropriately according to the specifications.

  The reflection enhancing film can be made of a metal material having high reflectivity such as aluminum or silver, and in addition, a multilayer film is laminated by combining two kinds of light transmissive dielectrics having different refractive indexes. It is also possible to use a dielectric multilayer film.

  When a film that enhances reflection is disposed, a transmissive film 1066 may be disposed between the semi-transmissive films 1068 as shown in FIG.

  In addition, the substrate 1010 and the substrate 1020 are bonded to each other with a sealant 1060 disposed in a region different from the region where the pixel electrodes 1011a, 1011b, and 1011c are formed. The sealant 1060 has a function of preventing the liquid crystal material constituting the liquid crystal layer 1030 from leaking to the outside, and also has a function of suppressing entry of impurities such as moisture from the outside.

  As the sealing material 1060, for example, an acrylic resin or an epoxy resin can be used. As the sealant 1060, a photo-curing type, a thermosetting type, or a combined type of photo-curing and thermosetting can be used.

  Further, the sealant 1060 may be mixed with a spacer 1062 for maintaining the distance between the substrate 1010 and the substrate 1020 and a filler 1064 for adjusting the viscosity of the sealant and further suppressing the intrusion of impurities such as moisture. The spacer 1062 can be formed using an inorganic material such as silicon oxide or an organic material such as divinylbenzene. Alternatively, the spacer 1062 can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. The filler 1064 can be formed using an inorganic material such as silicon oxide, aluminum oxide, or talc, or an organic material such as divinylbenzene.

  As a method for disposing the liquid crystal layer 1030 between the substrate 1010 and the substrate 1020, for example, in the case of using a one-drop filling method (abbreviation ODF), the substrate 1010 on which the pixel electrodes 1011a, 1011b, and 1011c are formed. An alignment film is formed on the substrate 1010 as necessary, and a liquid crystal material constituting the liquid crystal layer 1030 is dropped on the substrate 1010 that has been subjected to the alignment treatment, and the color filters 1021a, 1021b, 1021c, and further if necessary. A display portion can be formed through a process of overlapping the counter electrode 1023 and the substrate 1020 having the alignment film 1027.

  As another method, a substrate 1010 on which pixel electrodes 1011a, 1011b, and 1011c are formed and color filters 1021a, 1021b, and 1021c are formed as in a so-called vacuum injection method, and the counter electrode 1023 is further formed as necessary. Alternatively, the liquid crystal layer 1030 may be disposed by overlapping the substrate 1020 on which the alignment film 1027 is formed and immersing a liquid crystal material therebetween.

  In this embodiment mode, the pixel electrodes 1011a, 1011b, and 1011c are overlapped in part of the region with the insulating layers 1012a, 1012b, and 1012c interposed therebetween, and are formed in a staircase shape. As a result, the intervals between the color filters 1021a, 1021b, and 1021c can be set to different values for each pixel electrode. From another viewpoint, the thickness (also referred to as a cell gap) of the liquid crystal layer 1030 is different for each pixel electrode. Therefore, it is possible to exhibit reflection characteristics that match the wavelength of the light source. Therefore, the purity of the color can be improved and the display quality can be improved.

For example, in a reflective display device having the pixel portion 1000b, the main wavelength (wavelength at which the transmittance is maximum) of the color filter is λ _x , the refractive index of the liquid crystal layer is n, and the pixel electrodes 1011a, 1011b, 1011c Assuming that the distance of 1023 is d _x , when the condition of the above formula (1) is satisfied, the light of the wavelength d _x among the light incident on each pixel electrode meets the resonance condition. The light confinement between the two is promoted, and the intensity is enhanced. On the other hand, light of wavelengths other than the main wavelength deviates from the resonance condition, and the intensity is attenuated. As a result, the intensity of unnecessary wavelength components is reduced, and the color purity is improved.

Refractive index n _o is the refractive index n of the liquid crystal with respect to ordinary _light, there is a refractive index n _e for extraordinary light, the alignment state of the liquid crystal molecules in the liquid crystal element, conforming the refractive index in Equation (1) in accordance with the operation mode of liquid crystals Select a value. Further, since the alignment state of the liquid crystal molecules is sometimes better to use a value between n _o and n _e, the range of n becomes n _o to n _e.

  In the operation mode in which the alignment state of the liquid crystal molecules in the liquid crystal layer 1030 is controlled by an electric field and the polarization state is controlled, the display device is configured in combination with the polarization element. The contrast ratio of the display device (bright state and dark state) (Brightness ratio) is directly related to the display quality, and the optical characteristics of the liquid crystal material may be appropriately selected so that the contrast ratio becomes larger.

For good bright state of the display device, appropriately selecting the values of the refractive index anisotropy [Delta] n (difference between n _e and n _o) of the liquid crystal material. In this case, it is necessary to grasp the polarization characteristics of the liquid crystal element, and the Jones matrix method, the Berreman 4 × 4 matrix method, the Mueller matrix method, or the like can be used as a calculation method.

  As an example of obtaining the polarization characteristics, in the MTN mode (Mixed-mode Twisted Nematic) that can be used for a reflective liquid crystal display device, the relationship between the reflectance and the parameter of the liquid crystal element is obtained by using the above-described Jones matrix method. It can be expressed as in equation (2).

  Here, Γ and X have the following relationship, respectively.

  Here, Φ is the twist angle of the liquid crystal layer, β is the orientation direction of the liquid crystal layer in the vicinity of the element substrate with respect to the optical axis (transmission axis) of the polarizing element (hereinafter referred to as the orientation angle), or the liquid crystal layer in the vicinity of the counter substrate. It is an orientation direction.

  FIG. 3 shows the relationship between the transmission axis 181 of the polarizing element, the orientation direction 183 of the liquid crystal layer closer to the polarizing element, the orientation direction 185 farther from the polarizing element, the orientation angle 187 (β), and the twist angle 189 (Φ). Indicated. FIG. 3A is a perspective view schematically showing only the polarizing element 1040 and the liquid crystal layer 1030 in order to explain the relationship between these angles, and FIG. 3B is a side closer to the polarizing element. The alignment direction 183 of the liquid crystal layer, the alignment direction 185 far from the polarizing element, the alignment angle 187, and the twist angle 189 are shown on the same plane.

  It is possible to improve the color purity while improving the reflection efficiency of the liquid crystal element by finding the optimum range with the parameter value obtained by the expression (2) and further satisfying the relationship of the expression (1). It becomes.

  Here, an example of a method for obtaining the parameter value is shown.

  When manufacturing a liquid crystal panel, the substrate is bonded to the substrate as described above, and the liquid crystal is sandwiched between them. To reduce power consumption, the same voltage is applied to increase the electric field strength. Therefore, the cell gap should be made thinner if possible.

  However, even if an attempt is made to reduce the cell gap by applying pressure, there is a limit to the thickness of the sealing material that bonds the element substrate and the counter substrate. In addition, since it is necessary to manufacture the liquid crystal element with a high yield, the thickness of the cell gap is generally limited to 1.0 μm, and preferably at least 1.5 μm.

  With this condition in mind, the cell parameters are obtained. As an example, a nematic liquid crystal ZLI4792 made by Merck is used as a liquid crystal that can be used in the MTN mode, and the cell gap of a blue pixel is set to 2 μm in consideration of the above-described conditions. The characteristics of the liquid crystal are Δn = 0.0968, refractive index no = 1.4794 for ordinary light, and refractive index ne = 1.5762 for extraordinary light.

Is close to 2μm cell gap, m satisfying Equation (1), d, n is, m = 13, d = 1.977 , n = n o = 1.4794 , or,, m = 14, d = 1.998 , N = n _e = 1.5762.

  In the aforementioned MTN mode, when no voltage is applied, the liquid crystal molecules of the liquid crystal layer are aligned so that the major axis of the liquid crystal molecules is parallel to the substrate, so that the refractive index is a value for extraordinary light. This is ne. For example, when m = 14, d = 1.99 μm is obtained.

  Next, the orientation angle and twist angle of the liquid crystal layer are determined. The initial value of the twist angle 189 of the liquid crystal layer is 90 °, which is generally used in the TN mode, and the relationship between the orientation angle 187 and the reflectance is shown in FIG.

  Note that the vertical axis shown in FIG. 4A is reflectance, and the intensity of incident linearly polarized light is 1, and light is incident on the liquid crystal element so that the reflective pixel electrode has a reflectance of 1. When the light reflected and again transmitted through the liquid crystal layer and the polarizing element is 1, the reflectance is 1. In the actual liquid crystal element, there are other factors that attenuate the intensity of light, such as absorption and scattering, but here, the description will be made without considering the above-mentioned factors, specializing in changes in polarization characteristics.

  The horizontal axis is the aforementioned alignment angle 187, which indicates the angle between the alignment direction of the liquid crystal layer and the incident linearly polarized light. When the liquid crystal layer is viewed microscopically, the liquid crystal molecules contained in the liquid crystal layer are aligned in one direction on average while the major axis direction of the liquid crystal molecules shows fluctuation due to heat with respect to the direction in which they are easily aligned. This direction is an orientation vector. An orientation angle 187 which is the horizontal axis in FIG. 4 is an angle formed by the above-described linearly polarized electric field vector and the orientation vector. In an actual liquid crystal element, alignment is performed in a predetermined direction by a method such as rubbing or photo-alignment, and the alignment direction is parallel to the alignment vector.

  In FIG. 4A, the dotted line 402 shows the relationship between the orientation angle 187 and the reflectance when the twist angle 189 of the liquid crystal layer is 90 °. The orientation angle 187 at which the reflectance is 0.8 or more is 9 ° to 27 °.

  Therefore, β = 18 ° is selected as the orientation angle 187 that maximizes the reflectance under these conditions. The reflectance is β = 18 °, which is 0.88 which is the maximum in the range of the condition, but there is a possibility of further improvement. Therefore, the orientation angle is fixed at this angle, and the optimum condition of the twist angle is obtained this time. When β = 18 °, the reflectance is 80% or more when the twist angle Φ is 55 ° to 100 °.

  Here, the twist angle Φ is an angle formed by the alignment direction of the pair of substrates sandwiching the liquid crystal of the liquid crystal element. The liquid crystal molecules of the liquid crystal layer are aligned so that both ends are fixed in the aforementioned alignment direction and the free energy of the liquid crystal layer is minimized between them. When the alignment direction between the pair of substrates is non-parallel, the alignment vector indicates a so-called twisted alignment in which the alignment vector is twisted between the pair of substrates.

  In FIG. 4B, a relationship between the twist angle 189 and the reflectance when the orientation angle 187 is fixed at β = 18 ° is shown by a line 404.

  As the twist angle 189, Φ = 75 ° at which the reflectance is maximized is selected. Then, the reflectance is improved to 95%. In order to obtain a more optimal condition, the twist angle 189 may be set to Φ = 75 °, and the optimum condition for the orientation angle 187 may be obtained again. In FIG. 4A, the relationship between the orientation angle 187 and the reflectance when the twist angle 189 is Φ = 75 ° is shown by a line 406. At this time, it can be seen that by setting β = 12 °, the reflectance is improved to 0.996.

  The parameters of the liquid crystal element can also be obtained for the red and green pixel electrodes under the condition of the orientation angle β = 12 ° and the twist angle = 75 °. These are summarized as follows.

  In the case of a red pixel (670 nm), if the cell thickness is in the range of 2.6 μm to 3.6 μm, the reflectance is 90% or more. Similarly, m = 14 and d = 2.98 μm are obtained by setting the refractive index of the liquid crystal to ne = 1.5762 as the value corresponding to the highest reflectance in this range and the resonance condition.

  In the case of a green pixel (520 nm), the reflectance is higher than 90% when the cell thickness is in the range of 1.9 μm to 2.7 μm. Within the range, m = 14 and d = 2.3 μm are obtained as the value corresponding to the highest reflectance and the resonance condition, with the liquid crystal refractive index ne = 1.5762.

  The MTN mode has been described above as an example for explaining one embodiment of the present invention. However, when the other liquid crystal operation modes described above are used, a liquid crystal cell parameter that maximizes the reflectance can be found by the same method. Good.

  In this way, the space between the pixel electrode and the counter electrode is different for each pixel electrode to improve the light extraction efficiency and the color purity. However, the display quality can also be improved by making the area of the pixel electrode different. It is also possible to improve.

(Embodiment 2)

<Method for Forming Semiconductor Device Having Pixel Electrode>
In this embodiment, an example of a method for forming a semiconductor device having a pixel electrode that can be used for the display device described in Embodiment 1 will be described with reference to FIGS. Note that an embodiment described later can be referred to for a semiconductor device that can be used in this embodiment.

  FIG. 5 is a top view schematically showing a semiconductor device having a pixel electrode that can be used in the display device which is one embodiment of the present invention. 11A corresponds to a cross-sectional view of the cross section taken along the dashed-dotted line AB in FIG. 5, and FIG. 11B corresponds to a cross-sectional view of the cross section taken along the dashed-dotted line CD in FIG.

  As shown in FIG. 11A, the wiring 112 included in the semiconductor device is connected to the transistor 134 through the source electrode 112a in order to apply potential to the pixel electrodes 1011a, 1011b, and 1011c, and the drain electrode 112b of the transistor 134 is connected. The pixel electrodes 1011a, 1011b, and 1011c are electrically connected through openings 148a, 148b, and 148c.

  The wiring 112 and the scanning line 133 are electrically insulated by insulating films 106 and 107.

  The wiring 112 and the source electrode 112a are electrically connected. In addition, the same material can be used for the wiring 112, the source electrode 112a, and the drain electrode 112b.

  Further, the scan line 133 and the gate electrode 104 are electrically connected, and the same material can be used for the scan line 133 and the gate electrode 104.

  Further, as shown in FIGS. 5 and 11B, a capacitor electrode 136 may be provided to hold a potential applied to the pixel electrodes 1011a, 1011b, and 1011c.

  As shown in FIGS. 11A and 11B, the pixel electrode 1011a and the pixel electrode 1011b, and the pixel electrode 1011c and the pixel electrode 1011a partially overlap. In FIG. 5, the apparent areas of the pixel electrode 1011a, the pixel electrode 1011b, and the pixel electrode 1011c are shown as different from each other, but they may be arranged so that the apparent areas are equal. Further, the area of the pixel electrode may be different in consideration of the color balance indicated by the display device. For example, when it is desired to increase the intensity of the blue region, it can be handled by making the area of the pixel electrode in the blue region larger than that of the other pixel electrodes.

  Examples of a method for manufacturing a semiconductor device having the pixel electrode of FIG. 5 are shown in FIGS.

  As shown in FIG. 6A, the semiconductor device 152 includes an insulating film 118. Further, an insulating film 119a is formed over the insulating film 118 (see FIG. 6B). As the insulating film 119a, for example, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. An organic resin film is formed on the insulating film, patterned to leave a desired region, and then unnecessary regions are etched.

  Next, the insulating film 118 is etched using the insulating film 119a having the opening as a mask, so that the opening 148a is formed (see FIG. 7A). Since the insulating film 119a can be used as a mask, a new mask for forming the opening 148a is unnecessary and patterning can be omitted. Therefore, the manufacturing cost of the semiconductor device can be reduced.

  Next, a conductive film is formed over the insulating film 119a so as to cover the opening 148a, and patterning and etching are performed so that a desired shape of the conductive film remains, so that a pixel electrode 1011a is formed (FIG. 7B). reference).

  Next, an insulating film 119b is formed over the pixel electrode 1011a (see FIG. 8A). The material of the insulating film 119b can be the same material as the insulating film 119a.

  Patterning is performed so that a desired region remains by the same method as that for forming the opening 148a described above, and then an unnecessary region is etched to form an opening 148b (see FIG. 8B).

  Next, the opening 148b is formed by etching the insulating film 118 using the insulating film 119a and the insulating film 119b as masks. Next, a conductive film is formed over the insulating film 119b so as to cover the opening 148b, and patterning and etching are performed so that a desired shape of the conductive film remains, so that a pixel electrode 1011b is formed (FIG. 9A). reference).

  Next, an insulating film 119c is formed over the pixel electrode 1011b (see FIG. 9B). The material of the insulating film 119c can be the same material as the insulating films 119a and 119b.

  Next, patterning is performed so that a desired region remains by the same method as described above, and then an unnecessary region is etched to form an opening 148c (see FIG. 10A).

  Next, a conductive film is formed over the insulating film 119c so as to cover the opening 148c, and patterning and etching are performed so that a desired shape of the conductive film remains by the same method as described above, so that the pixel electrode 1011c is formed. (See FIG. 10B).

  Next, the insulating films 119b and 119c are etched using the pixel electrodes 1011b and 1011c as a mask, so that the insulating films over the pixel electrodes 1011a, 1011b, and 1011c are removed. (See FIGS. 11A and 11B).

  In the first embodiment, the insulating layers 1012a, 1012b, 1012c, and 1012d for insulating the pixel electrodes 1011a, 1011b, and 1011c are individually arranged, and the manufacturing process may be complicated. By the manufacturing method 2, the insulating properties of the pixel electrodes 1011a, 1011b, and 1011c can be maintained while the insulating layers 1012e and 1012f are arranged by a simple method.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, an example of a liquid crystal display device which is a display device using a display portion having a liquid crystal layer will be described with reference to FIGS. Note that another embodiment mode can be referred to for the structure of the liquid crystal display device applied to this embodiment mode.

  FIG. 12 is a block diagram illustrating a structure of a liquid crystal display device having a display function of one embodiment of the present invention.

  13A and 13B are a block diagram and a circuit diagram illustrating a structure of a display portion of a liquid crystal display device having a display function of one embodiment of the present invention.

<1. Configuration of liquid crystal display device>
In this embodiment mode, a liquid crystal display device 600 having a display function described with reference to FIG. 12 includes an arithmetic device 620, a control unit 610, a display unit 630, and an input unit 500.

  Further, the display portion 630 includes a pixel portion 631, the pixel portion 631 includes a plurality of pixels 631 p, and the pixel 631 p includes a pixel circuit 634.

  Next, the outline of the relationship between each component is shown. First, the arithmetic device 620 outputs a primary control signal 625_C and a primary image signal 625_V to the control unit 610.

  Further, by providing the input unit 500 so that a control signal can be output to the arithmetic unit 620, a signal based on information supplied to the input unit by the user can be output from the arithmetic unit 620 to the control unit 610.

  The control unit 610 controls the S drive circuit 633 and the G drive circuit 632.

  The G driving circuit 632 outputs a G signal 632_G and controls the G signal 632_G, whereby the frequency of selecting one from the plurality of pixel circuits 634 provided in the pixel portion 631 can be changed.

  By using the configuration of the present embodiment, an operation mode for performing smooth moving image display, an operation mode for displaying at a lower frame frequency in order to reduce power consumption, reduce flicker, and perform display that is easy on the eyes, and Can be switched and displayed on the same display device.

  Specifically, there are a first mode in which G signals for selecting pixels are output at a frequency of 60 Hz or more and a second mode in which a G signal is output at a frequency of 1 Hz or less, preferably 0.2 Hz or less.

  As a result, a liquid crystal display device having a display function in which eye fatigue that can be given to a person who uses the liquid crystal display device 600 is reduced can be provided.

  The individual elements included in the liquid crystal display device having a display function of one embodiment of the present invention are described below.

<2. Arithmetic unit>
The arithmetic device 620 generates a primary image signal 625_V and a primary control signal 625_C.

  Further, the arithmetic device 620 generates a primary control signal 625_C including a mode switching signal.

  For example, the arithmetic device 620 may output the primary control signal 625_C including the mode switching signal in response to the image switching signal 500_C input from the input unit 500.

<3. Control unit>
The controller 610 outputs a secondary image signal 615_V generated from the primary image signal 625_V. In the case of FIG. 12, the secondary image signal 615_V is output to the S driver circuit 633, but the present invention is not limited to this, and the primary image signal 625_V may be directly output to the display portion 630.

  The control unit 610 generates a secondary control signal 615_C such as a start pulse signal, a latch signal, and a pulse width control signal by using a primary control signal 625_C including a synchronization signal such as a vertical synchronization signal and a horizontal synchronization signal, and a display unit 630 has a function to supply to 630. Note that the secondary control signal 615_C includes a clock signal and the like.

  Further, an inversion control circuit may be provided in the control unit 610, and the control unit 610 may have a function of inverting the polarity of the secondary image signal 615_V in accordance with the timing notified by the inversion control circuit. Specifically, inversion of the polarity of the secondary image signal 615_V may be performed in the control unit 610, or may be performed in the display unit 630 in accordance with a command from the control unit 610.

  The inversion control circuit has a function of determining the timing at which the polarity of the secondary image signal 615_V is inverted using a synchronization signal. The illustrated inversion control circuit includes a counter and a signal generation circuit.

  The counter has a function of counting the number of frame periods using the pulse of the horizontal synchronization signal.

  The signal generation circuit uses the information on the number of frame periods obtained by the counter to perform timing for inverting the polarity of the secondary image signal 615_V so as to invert the polarity of the secondary image signal 615_V for each of a plurality of consecutive frame periods. Is notified to the control unit 610.

<4. Display>
The display portion 630 includes a pixel portion 631 having a display element 635 in each pixel, and drive circuits such as an S drive circuit 633 and a G drive circuit 632. The pixel portion 631 includes a plurality of pixels 631p provided with a display element 635 (see FIG. 12).

  The secondary image signal 615_V input from the control unit 610 to the display unit 630 is supplied to the S drive circuit 633. The power supply potential and the secondary control signal 615_C are supplied to the S drive circuit 633 and the G drive circuit 632.

  The S driver circuit 633 holds a first drive signal (also referred to as an S signal) 633_S that is input, and the pixel portion 631 having a pixel circuit 634 that includes a display element 635 that displays an image in accordance with the S signal 633_S. A signal 633_S is output.

  The G drive circuit 632 outputs a second drive signal (also referred to as a G signal) 632_G for selecting the pixel circuit 634 to the pixel circuit 634.

  Note that the secondary control signal 615_C includes an S drive circuit start pulse signal that controls the operation of the S drive circuit 633, an S drive circuit clock signal, a latch signal, and a G drive that controls the operation of the G drive circuit 632. A start pulse signal for the circuit, a clock signal for the G drive circuit, a pulse width control signal, and the like are included.

  Next, an example of a structure of the display portion 630 is illustrated in FIG.

  A display portion 630 illustrated in FIG. 13A includes a pixel portion 631, a plurality of pixels 631p, a plurality of scanning lines G for selecting the pixels 631p for each row, and a secondary image on the selected pixel 631p. A plurality of signal lines S for supplying an S signal 633_S generated from the signal 615_V is provided.

  The input of the G signal 632_G to the scanning line G is controlled by the G driving circuit 632. The input of the S signal 633_S to the signal line S is controlled by the S drive circuit 633. The plurality of pixels 631p are connected to at least one of the scanning lines G and at least one of the signal lines S, respectively.

  Note that the type and number of wirings provided in the pixel portion 631 can be determined by the configuration, number, and arrangement of the pixels 631p. Specifically, in the case of the pixel portion 631 illustrated in FIG. 13A, x columns × y rows of pixels 631p are arranged in a matrix, and the signal lines S1 to Sx and the scan lines G1 to Gy are included. The case where it is arranged in the pixel portion 631 is illustrated.

<4-1. Pixel>
Each pixel 631p includes a display element 635 and a pixel circuit 634 including the display element 635.

<4-2. Pixel circuit>
In this embodiment, as an example of the pixel circuit 634, a structure in which the liquid crystal element 635LC is applied to the display element 635 is illustrated in FIG.

  The pixel circuit 634 includes a transistor 634t that controls supply of the S signal 633_S to the liquid crystal element 635LC. An example of a connection relation between the transistor 634t and the display element 635 will be described.

  The gate of the transistor 634t is connected to any one of the scanning line G1 to the scanning line Gy. One of a source and a drain of the transistor 634t is connected to any one of the signal lines S1 to Sx, and the other of the source and the drain of the transistor 634t is connected to the first electrode of the display element 635.

  Note that the pixel 631p includes other elements such as a transistor, a diode, a resistor, a capacitor, and an inductor, as well as a capacitor 634c for holding a voltage between the first electrode and the second electrode of the liquid crystal element 635LC. You may have a circuit element.

  A pixel 631p illustrated in FIG. 13B uses one transistor 634t as a switching element that controls input of the S signal 633_S to the pixel 631p. However, a plurality of transistors functioning as one switching element may be used for the pixel 631p. When a plurality of transistors function as one switching element, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in combination of series and parallel. Good.

  Note that the capacitance of the pixel circuit 634 may be adjusted as appropriate. For example, in the second mode, in the case where the S signal 633_S is held for a relatively long period (specifically, 1/60 sec or more), the capacitor 634c is provided. Further, the capacitance of the pixel circuit 634 may be adjusted by using a configuration other than the capacitor 634c. For example, the capacitor element may be substantially formed by a structure in which the first electrode and the second electrode of the liquid crystal element 635LC are provided to overlap each other.

  Further, the capacitor can use an oxide semiconductor as an electrode, and may be a first electrode or a second electrode.

  In addition, the pixel circuit 634 can be used by selecting a structure in accordance with the type of the display element 635 or the driving method.

  Further, another embodiment is referred to for a method for using an oxide semiconductor as an electrode of a capacitor.

<4-2a. Display element>
The liquid crystal element 635LC includes a liquid crystal layer including a first electrode, a second electrode, and a liquid crystal material to which a voltage between the first electrode and the second electrode is applied. In the liquid crystal element 635LC, the alignment of liquid crystal molecules changes according to the value of the voltage applied between the first electrode and the second electrode, and the transmittance changes. Therefore, the display element 635 can display grayscale by controlling the transmittance with the potential of the S signal 633_S.

<4-2b. Transistor>
The transistor 634t controls whether or not to apply the potential of the signal line S to the first electrode of the display element 635. A predetermined reference potential Vcom is applied to the second electrode of the display element 635.

  Note that as the transistor suitable for the liquid crystal display device of one embodiment of the present invention, a transistor including an oxide semiconductor can be used. Embodiments 7 to 11 and Embodiment 13 can be referred to for the details of the transistor including an oxide semiconductor.

<5. Light supply section>
In the case where a liquid crystal element is used for the display element 635, the light supply portion 650 is provided in the display portion 630. The light supply unit 650 is provided with a plurality of light sources. The control unit 610 controls driving of the light source included in the light supply unit 650.

  Note that in the case of a reflective liquid crystal display device, sunlight outdoors, indoor illumination light, or the like can be used as a light source, and thus the light supply portion 650 may not be provided. However, if it is assumed that there is no light source, or the light is dark even when there is a light source, and the light is used in a dark place, a light supply unit 650 is provided to supply light to the pixel unit 631 provided with a liquid crystal element. By doing so, the display image can be recognized even in a dark place.

  As a light source of the light supply unit 650, a cold cathode fluorescent lamp, a light emitting diode (LED), an OLED element that generates luminescence (electroluminescence) when an electric field is applied, and the like can be used. Further, as a colorization method of the light source of the light supply unit 650, a method using red, green, and blue light emission (three-color method), and a method for converting a part of light emission from the blue light emission into red and green (color) Conversion method, quantum dot method), a method of converting a part of light emission from white light emission into red, green, and blue by passing a color filter (color filter method) can be applied.

<6. Input means>
As the input unit 500, a touch panel, a touch pad, a joystick, a trackball, a data glove, an imaging device, or the like can be used. The arithmetic device 620 can associate the electric signal input from the input unit 500 with the coordinates of the display unit. Thereby, the user can input a command for processing information displayed on the display unit.

  Information input by the user from the input unit 500 includes, for example, a drag command for changing the display position of the image displayed on the display unit, and a swipe to display the next image by sending the displayed image. In addition to commands, scroll commands for sequentially sending scroll-shaped images, commands for selecting specific images, commands for pinching to change the size of image display, commands for inputting handwritten characters, etc. it can.

When there are a plurality of display modes, for example, when there are two modes of the first mode and the second mode, the G drive circuit 632 operating in the second mode is connected to the G driving circuit 632 via the control unit 610. When the image switching signal 500_C is input from the input unit 500, the G driving circuit 632 switches from the second mode to the first mode, outputs the G signal one or more times, and then switches to the second mode.
<7. Example of operation>

  For example, when the input unit 500 detects a page turning operation, the input unit 500 outputs an image switching signal 500_C to the arithmetic device 620.

  The arithmetic device 620 generates a primary image signal 625_V including a page turning operation signal, and outputs the primary image signal 625_V together with a primary control signal 625_C including an image switching signal 500_C.

  The control unit 610 outputs the image switching signal 500_C to the G drive circuit 632 and outputs the secondary image signal 615_V including the page turning operation signal to the S drive circuit 633.

  The G drive circuit 632 outputs a G signal 632_G to the pixel at a frequency of 30 times or more per second, preferably 60 times or more and less than 960 times per second, and 1 or more times a day. It has a second mode of outputting at a frequency of less than 0.1 times per second, preferably at least once per hour and less than once per second.

  Note that the G drive circuit 632 switches between the first mode and the second mode in accordance with the input mode switching signal.

  The G drive circuit 632 switches from the second mode to the first mode, and outputs a signal of the G signal 632_G at such a speed that the observer cannot identify the change in the image that changes every time the signal is rewritten.

  On the other hand, the S drive circuit 633 outputs an S signal 633_S generated from the secondary image signal 615_V including the page turning operation signal to the pixel circuit 634.

  Thus, the pixel 631p can display a large number of frame images including the page turning operation in a short time by receiving the secondary image signal 615_V including the page turning operation signal, and thus can display a smooth page turning operation.

  Further, the arithmetic device 620 determines whether the primary image signal 625_V output to the display unit 630 is a moving image or a still image, and when the primary image signal 625_V is a moving image, a switching signal for selecting the first mode is In the case of a still image, the calculation device 620 may output a switching signal for selecting the second mode.

  As a method for determining whether the image is a moving image or a still image, when the difference between the signal of one frame included in the primary image signal 625_V and the preceding and succeeding frames is larger than a predetermined difference, What is necessary is just to distinguish with a still image at the following times.

  In addition, when the second mode is switched to the first mode, the G signal 632_G may be output a predetermined number of times one or more times and then switched to the second mode.

  With the configuration shown in Embodiment Mode 3, it is possible to reduce the burden on the eyes during use.

  Note that one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention will be described. Note that one embodiment of the present invention is not limited thereto. That is, in this embodiment and other embodiments, various aspects of the invention are described; therefore, one embodiment of the present invention is not limited to a particular aspect. For example, although an example in which a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
<Partial drive>
In this embodiment, an example of a method for driving the liquid crystal display device described in Embodiment 3 will be described with reference to FIGS.

  13A and 13B are a block diagram and a circuit diagram illustrating a structure of a display portion of a liquid crystal display device having a display function of one embodiment of the present invention.

FIG. 14 is a block diagram illustrating a modification of the structure of the display portion of the liquid crystal display device having a display function of one embodiment of the present invention.
<1. Method of writing S signal to pixel portion>
An example of a method for writing the S signal 633_S to the pixel portion 631 illustrated in FIG. Specifically, a method for writing the S signal 633_S to each of the pixels 631p including the pixel circuit illustrated in FIG. 13B in the pixel portion 631 is described.

<Writing signals to the pixel section>
In the first frame period, the scan line G1 is selected by inputting a G signal 632_G having a pulse to the scan line G1. In each of the plurality of pixels 631p connected to the selected scanning line G1, the transistor 634t is turned on.

  When the transistor 634t is in a conductive state (one line period), the potential of the S signal 633_S generated from the secondary image signal 615_V is applied from the signal line S1 to the signal line Sx. Then, electric charge corresponding to the potential of the S signal 633_S is accumulated in the capacitor 634c through the conductive transistor 634t, and the potential of the S signal 633_S is supplied to the first electrode of the liquid crystal element 635LC.

  In a period in which the scanning line G1 in the first frame period is selected, the S signal 633_S having a positive polarity is sequentially input to all the signal lines S1 to Sx. A positive polarity S signal 633_S is supplied to the first electrode (G1S1) to the first electrode (G1Sx) in the pixel 631p connected to the scan line G1 and the signal lines S1 to Sx, respectively. Accordingly, the transmittance of the liquid crystal element 635LC is controlled by the potential of the S signal 633_S, and each pixel displays a gradation.

  Similarly, the scanning line G2 to the scanning line Gy are sequentially selected, and the same operation as in the period when the scanning line G1 is selected is sequentially performed in the pixels 631p connected to the scanning lines G2 to Gy. Repeated. Through the above operation, the pixel portion 631 can display the first frame image.

  Note that in one embodiment of the present invention, the scan lines G1 to Gy are not necessarily selected in order.

  Note that dot sequential driving in which the S signal 633_S is sequentially input from the S driving circuit 633 to the signal lines S1 to Sx can be used, or line sequential driving in which the S signal 633_S is simultaneously input can be used. Alternatively, a driving method of inputting the S signal 633_S in order for each of the plurality of signal lines S may be used.

  Further, not only the scanning line G selection method using the progressive method, but also the scanning line G may be selected using the interlace method.

  Further, even if the polarity of the S signal 633_S input to all the signal lines is the same in any one frame period, the S signal input to the pixel for each signal line in any one frame period. The polarity of 633_S may be reversed.

<Writing a signal to a pixel portion divided into a plurality of regions>
A modification of the configuration of the display unit 630 is shown in FIG.

  A display portion 630 illustrated in FIG. 14 includes a plurality of pixels 631p and a pixel 631p in a pixel portion 631 (specifically, a first region 631a, a second region 631b, and a third region 631c) divided into a plurality of regions. Are provided for each row, and a plurality of signal lines S for supplying the S signal 633_S to the selected pixel 631p are provided.

  Input of the G signal 632_G to the scanning line G provided in each region is controlled by each G driving circuit 632. The input of the S signal 633_S to the signal line S is controlled by the S drive circuit 633. The plurality of pixels 631p are connected to at least one of the scanning lines G and at least one of the signal lines S, respectively.

  With such a structure, the pixel portion 631 can be divided and driven.

  For example, when inputting information from the touch panel as the input unit 500, only the G drive circuit 632 that acquires the coordinates for specifying the area where the information is input and drives the area corresponding to the coordinates is set as the first mode. Other regions may be set as the second mode. With this operation, it is possible to stop the operation of the G drive circuit in a region where information is not input from the touch panel, that is, a region where the display image does not need to be rewritten.

<2. First Mode and Second Mode G Drive Circuit>
The S signal 633_S is input to the pixel circuit 634 to which the G signal 632_G output from the G drive circuit 632 is input. In a period in which the G signal 632_G is not input, the pixel circuit 634 holds the potential of the S signal 633_S. In other words, the pixel circuit 634 holds a state where the potential of the S signal 633_S is written.

  The pixel circuit 634 in which the display data is written maintains a display state corresponding to the S signal 633_S. Note that maintaining the display state refers to maintaining the display state so that the change in the display state does not become larger than a certain range. The certain range is a range that is set as appropriate. For example, when the user views the display image, it is preferable to set the range to a display state that can be recognized as the same display image.

  The G drive circuit 632 has a first mode and a second mode.

<2-1. First mode>
In the first mode of the G driving circuit 632, the G signal 632_G is output to the pixel at a frequency of 30 times or more per second, preferably 60 times or more and less than 960 times per second.

  The G driving circuit 632 in the first mode rewrites the signal at such a speed that the observer cannot identify the change in the image that changes every time the signal is rewritten. As a result, a moving image can be displayed smoothly.

<2-2. Second mode>
In the second mode of the G driving circuit 632, the G signal 632_G is sent to the pixel at a frequency of once or more per day and less than 0.1 times per second, preferably at least once per hour and less than once per second. Output.

  During the period when the G signal 632_G is not input, the pixel circuit 634 holds the S signal 633_S and continuously maintains the display state corresponding to the potential.

  Thus, in the second mode, display without flicker (also referred to as flicker) associated with rewriting of pixel display can be performed.

  As a result, the eyestrain of the user of the liquid crystal display device having the display function can be reduced.

  Note that the power consumed by the G drive circuit 632 is reduced during a period when the G drive circuit 632 does not operate.

  Note that a pixel circuit driven using the G driver circuit 632 having the second mode preferably holds the S signal 633_S for a long period. For example, the leakage current of the transistor 634t is preferably as small as possible in the off state.

  Another embodiment can be referred to for an example of a structure of the transistor 634t having a small leakage current in the off state.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(Embodiment 5)
<Reverse drive>
In this embodiment, an example of a method for driving the liquid crystal display device described in any of Embodiments 3 and 4 will be described with reference to FIGS.

  FIG. 15 is a circuit diagram illustrating a liquid crystal display device having a display function of one embodiment of the present invention.

  FIG. 16 illustrates source line inversion driving and dot inversion driving of a liquid crystal display device having a display function of one embodiment of the present invention.

  FIG. 17 is a timing chart illustrating source line inversion driving and dot inversion driving of a liquid crystal display device having a display function of one embodiment of the present invention.

<1. Overdrive drive>
A liquid crystal generally has a response time of about several tens of milliseconds after the voltage is applied until the transmittance converges. Therefore, the slow response of the liquid crystal is likely to be visually recognized as blurring of the moving image.

  Thus, in one embodiment of the present invention, overdrive driving in which the voltage applied to the display element 635 using a liquid crystal element is temporarily increased to quickly change the alignment of the liquid crystal may be used. By using overdrive drive, the response speed of the liquid crystal can be increased, blurring of moving images can be prevented, and the image quality of moving images can be improved.

  In addition, even after the transistor 634t is turned off, if the transmittance of the display element 635 using a liquid crystal element continues to change without convergence, the relative permittivity of the liquid crystal changes. The voltage held by the display element 635 is likely to change.

  For example, when the capacitor 634c is not connected in parallel to the display element 635 using a liquid crystal element, or when the capacitance value of the connected capacitor 634c is small, the voltage held by the display element 635 using the above-described liquid crystal element is reduced. Changes are likely to occur significantly. However, since the response time can be shortened by using the overdrive driving, the change in transmittance of the display element 635 using the liquid crystal element after the transistor 634t is turned off can be reduced. it can. Therefore, even when the capacitance value of the capacitor 634c connected in parallel to the display element 635 using a liquid crystal element is small, the voltage held by the display element 635 using the liquid crystal element after the transistor 634t is turned off. Can be prevented from changing.

<2. Source line inversion drive and dot inversion drive>
In the pixel 631p connected to the signal line Si of the pixel circuit illustrated in FIG. 16, the pixel electrode 635_1 is placed in the pixel 631p so as to be sandwiched between the signal line Si and the signal line Si + 1 adjacent to the signal line Si. Is arranged. If the transistor 634t is off, the pixel electrode 635_1 and the signal line Si are ideally electrically separated. Also, the pixel electrode 635_1 and the signal line Si + 1 are ideally electrically separated. However, actually, a parasitic capacitance 634c (i) exists between the pixel electrode 635_1 and the signal line Si, and a parasitic capacitance 634c (i + 1) exists between the pixel electrode 635_1 and the signal line Si + 1. (See FIG. 16C). Note that FIG. 16C illustrates a pixel electrode 635_1 functioning as the first electrode or the second electrode of the liquid crystal element 635LC instead of the liquid crystal element 635LC illustrated in FIG.

  In the case where the first electrode and the second electrode of the liquid crystal element 635LC are provided to overlap with each other, the overlapping of the two electrodes is used as a substantial capacitor element, so that the liquid crystal element 635LC is formed using a capacitor wiring. In some cases, the capacitance element 634c connected is not connected, or the capacitance value of the capacitance element 634c connected to the liquid crystal element 635LC is small. In such a case, the potential of the pixel electrode 635_1 functioning as the first electrode or the second electrode of the liquid crystal element is easily affected by the parasitic capacitance 634c (i) and the parasitic capacitance 634c (i + 1).

  Accordingly, a phenomenon in which the potential of the pixel electrode 635_1 fluctuates in conjunction with a change in the potential of the signal line Si or the signal line Si + 1 even when the transistor 634t holds the potential of the image signal in the off state. Is likely to occur.

  A phenomenon in which the potential of the pixel electrode fluctuates in conjunction with the change in the potential of the pixel electrode in a period in which the potential of the image signal is held is called a crosstalk phenomenon. When the crosstalk phenomenon occurs, the display contrast decreases. For example, when a normally white liquid crystal is used for the liquid crystal element 635LC, the image becomes whitish.

  Therefore, in one embodiment of the present invention, driving is performed in which image signals having opposite polarities are input to the signal line Si and the signal line Si + 1 that are provided with the pixel electrode 635_1 interposed therebetween in an arbitrary frame period. A method may be used.

  Note that the image signal having the opposite polarity is an image signal having a potential higher than the reference potential and an image signal having a potential lower than the reference potential when the potential of the common electrode of the liquid crystal element is set as the reference potential. Means.

  Two methods (source line inversion and dot inversion) can be cited as examples of methods for sequentially writing image signals having opposite polarities alternately to a plurality of selected pixels.

  In any method, in the first frame period, an image signal having a positive (+) polarity is input to the signal line Si, and an image signal having a negative (−) polarity is input to the signal line Si + 1. Next, in the second frame period, an image signal having a negative (−) polarity is input to the signal line Si, and an image signal having a positive (+) polarity is input to the signal line Si + 1. Next, in the third frame period, an image signal having a positive (+) polarity is input to the signal line Si, and an image signal having a negative (−) polarity is input to the signal line Si + 1 (see FIG. 16C). ).

  When such a driving method is used, the potentials of a pair of signal lines fluctuate in opposite directions, so that fluctuations in potential received by any pixel electrode are cancelled. Therefore, occurrence of crosstalk can be suppressed.

<2-1. Source line inversion drive>
In the source line inversion, the polarity is reversed between a plurality of pixels connected to one signal line and a plurality of pixels connected to another signal line adjacent to the signal line in any one frame period. The input image signal is input.

  The polarities of the image signals given to the pixels when source line inversion is used are schematically shown in FIGS. 16A-1 and 16A-2. In an image signal given in any one frame period, a positive polarity pixel is indicated by a + symbol, and a negative polarity pixel is indicated by a-symbol. A frame illustrated in FIG. 16A-2 is a frame that follows the frame illustrated in FIG.

<2-2. Dot inversion drive>
Dot inversion reverses polarity between a plurality of pixels connected to one signal line and a plurality of pixels connected to another signal line adjacent to the signal line in an arbitrary frame period. In addition, an image signal having a reverse polarity is input to adjacent pixels in a plurality of pixels connected to the same signal line.

  The polarities of image signals given to pixels when dot inversion is used are schematically shown in FIGS. 16B-1 and 16B-2. In an image signal given in any one frame period, a positive polarity pixel is indicated by a + symbol, and a negative polarity pixel is indicated by a-symbol. A frame illustrated in FIG. 16B-2 is a frame following the frame illustrated in FIG.

<2-3. Timing chart>
Next, FIG. 17 shows a timing chart in the case where the pixel portion 631 shown in FIG. 15 is operated by source line inversion. Specifically, in FIG. 17, the potential of the signal applied to the scanning line G1, the potential of the image signal applied from the signal line S1 to the signal line Sx, and the potential of the pixel electrode included in each pixel connected to the scanning line G1. The change of time is shown.

  First, the scanning line G1 is selected by inputting a signal having a pulse to the scanning line G1. In each of the plurality of pixels 631p connected to the selected scanning line G1, the transistor 634t is turned on. When the potential of the image signal is applied from the signal line S1 to the signal line Sx while the transistor 634t is on, the potential of the image signal is applied to the pixel electrode of the liquid crystal element 635LC through the on-transistor 634t. .

  In the timing chart shown in FIG. 17, in the period in which the scanning line G1 in the first frame period is selected, the odd-numbered signal lines S1, S3,. . . , Positive polarity image signals are sequentially input, and even-numbered signal lines S2, S4,. . . In the example, a negative polarity image signal is input to the signal line Sx. Therefore, the odd-numbered signal lines S1, S3,. . . , Pixel electrode (S1), pixel electrode (S3),. . . Is given a positive polarity image signal. The even-numbered signal line S2, signal line S4,. . . The pixel electrode (S2), pixel electrode (S4),... In the pixel 631p connected to the signal line Sx. . . A negative polarity image signal is applied to the pixel electrode (Sx).

  In the liquid crystal element 635LC, the orientation of liquid crystal molecules changes and the transmittance changes according to the value of the voltage applied between the pixel electrode and the common electrode. Therefore, the liquid crystal element 635LC can display gradation by controlling the transmittance according to the potential of the image signal.

  When the input of the image signal from the signal line S1 to the signal line Sx is completed, the selection of the scanning line G1 is completed. When selection of the scan line is completed, the transistor 634t is turned off in the pixel 631p including the scan line. Then, the liquid crystal element 635LC maintains gradation display by holding a voltage applied between the pixel electrode and the common electrode. Then, the scanning line G2 is sequentially selected from the scanning line G2, and the same operation as in the period in which the scanning line G1 is selected is performed in the pixels connected to the scanning lines.

  Next, the scanning line G1 is selected again in the second frame period. In the period in which the scanning line G1 in the second frame period is selected, unlike the period in which the scanning line G1 in the first frame period is selected, the odd-numbered signal lines S1, S3,. . . , Negative polarity image signals are sequentially input, and even-numbered signal lines S2, S4,. . . A positive polarity image signal is input to the signal line Sx. Therefore, the odd-numbered signal lines S1, S3,. . . , Pixel electrode (S1), pixel electrode (S3),. . . Is given a negative polarity image signal. The even-numbered signal line S2, signal line S4,. . . The pixel electrode (S2), pixel electrode (S4),... In the pixel 631p connected to the signal line Sx. . . A positive polarity image signal is applied to the pixel electrode (Sx).

  Also in the second frame period, when the input of the image signal from the signal line S1 to the signal line Sx is finished, the selection of the scanning line G1 is finished. Then, the scanning line G2 is sequentially selected from the scanning line G2, and the same operation as in the period in which the scanning line G1 is selected is performed in the pixels connected to the scanning lines.

  The above operation is similarly repeated in the third frame period and the fourth frame period.

  Note that the timing chart shown in FIG. 17 illustrates the case where image signals are sequentially input from the signal line S1 to the signal line Sx, but the present invention is not limited to this configuration. Image signals may be input simultaneously from the signal line S1 to the signal line Sx, or image signals may be input in order for each of a plurality of signal lines.

  In this embodiment, scanning line selection in the case of using the progressive method has been described. However, scanning line selection may be performed by using an interlace method.

  Note that by performing inversion driving in which the polarity of the potential of the image signal is inverted with respect to the reference potential of the common electrode, deterioration of the liquid crystal called burn-in can be prevented.

  However, when inversion driving is performed, a change in potential applied to the signal line when the polarity of the image signal changes increases, and thus a potential difference between the source electrode and the drain electrode of the transistor 634t functioning as a switching element increases. Therefore, the transistor 634t is likely to deteriorate in characteristics such as a shift in threshold voltage.

  In order to maintain the voltage held in the liquid crystal element 635LC, the off-state current is required to be low even if the potential difference between the source electrode and the drain electrode is large.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(Embodiment 6)

<Fade in fade out>
In this embodiment, a method for generating an image that can be displayed on a liquid crystal display device having a display function of one embodiment of the present invention will be described with reference to FIGS. In particular, an image switching method that is easy on the eyes of the user when switching images, an image switching method that reduces fatigue of the eyes of the user, and an image switching method that does not impose a burden on the eyes of the user will be described. .

  If the images are switched quickly and displayed, the eyes of the user may be induced. For example, a moving image in which a significantly different scene is switched or a case in which a different still image is switched is included.

  When switching and displaying different images, it is preferable not to switch the display instantaneously, but to switch the images slowly (quietly) and naturally.

  For example, when switching the display from a different first image to a second image, an image in which the first image fades out between the first image and the second image or / and an image in which the second image fades in Is preferably inserted. In addition, an image obtained by superimposing both images may be inserted so that the second image fades in (also referred to as a crossfade) at the same time as the first image fades out. A moving image (also referred to as morphing) that displays a gradually changing state may be inserted into the image.

  Specifically, the first still image is displayed at a low refresh rate, the image for image switching is displayed at a high refresh rate, and then the second still image is displayed at a low refresh rate.

<Fade in, fade out>
Hereinafter, an example of a method for switching between different images A and B will be described.

  FIG. 18A is a block diagram illustrating a structure of a display device that can perform an image switching operation. The display device illustrated in FIG. 18A includes an arithmetic device 671, a storage device 672, a graphic unit 673, and a display unit 674.

  In the first step, the arithmetic device 671 stores each data of the image A and the image B from the external storage device or the like in the storage device 672.

  In the second step, the arithmetic device 671 sequentially generates new image data based on the image data of the image A and the image B in accordance with a preset division number value.

  In the third step, the generated image data is output to the graphic unit 673. The graphic unit 673 causes the display unit 674 to display the input image data.

  FIG. 18B is a schematic diagram for explaining generated image data when the images are switched stepwise from image A to image B. FIG.

  FIG. 18B shows a case where N (N is a natural number) image data is generated from image A to image B, and each image data is displayed for f (f is a natural number) frame period. . Therefore, the period from the image A to the image B is f × N frames.

  Here, it is preferable that the user can freely set the parameters such as N and f described above. The arithmetic device 671 acquires these parameters in advance, and generates image data according to the parameters.

  The i-th image data (i is an integer between 1 and N) can be generated by weighting and adding the image data of image A and the image data of image B, respectively. For example, when the luminance (gradation) when the image A is displayed is a and the luminance (gradation) when the image B is displayed is b in a certain pixel, the i-th generated image data is displayed. The luminance (gradation) c of the pixel is a value shown in Expression (5).

  By switching from the image A to the image B using the image data generated by such a method, it is possible to switch a discontinuous image naturally (slowly).

  In Equation (5), the case where a = 0 for all pixels corresponds to a fade-in in which the black image is gradually switched to the image B. The case of b = 0 for all the pixels corresponds to a fade-out in which the image A is gradually switched to a black image.

  In the above description, the method of switching the images by temporarily overlapping the two images has been described. However, a method of not overlapping the images may be used.

  When the two images are not overlapped, when switching from the image A to the image B, a black image may be inserted between them. At this time, the image switching method as described above may be used when transitioning from the image A to the black image, or when transitioning from the black image to the image B, or both. The image inserted between the image A and the image B may be not only a black image but also a single color image such as a white image, or a multicolor image different from the image A and the image B may be used. May be.

  By inserting another image, particularly a single color image such as a black image, between the image A and the image B, the user can feel the switching of the image more naturally, and the user feels stress. Images can be switched without any change.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(Embodiment 7)
In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<Configuration example of semiconductor device>
FIG. 19A is a top view of a semiconductor device (hereinafter simply referred to as a semiconductor device) that can be used for a display device having a display function of one embodiment of the present invention. FIG. 19 (A) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash line A-B, between the alternate long and short dash line CD, and between the alternate long and short dash line EF. Note that in FIG. 19A, some components (such as a gate insulating film) of the semiconductor device are not illustrated in order to avoid complexity. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 19A.

  A dashed line AB in FIG. 19A indicates the channel length direction of the transistor 150. A one-dot chain line EF indicates the channel width direction of the transistor 150. Note that in this specification, the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode). In a horizontal plane, it means a direction perpendicular to the channel length direction.

  19A and 19B includes a transistor 150 including a first oxide semiconductor film 110 and a capacitor 160 including an insulating film between a pair of electrodes. Note that in the capacitor 160, one of the pair of electrodes is the second oxide semiconductor film 111, and the other of the pair of electrodes is the conductive film 120.

  The transistor 150 includes a gate electrode 104 over the substrate 102, an insulating film 108 functioning as a gate insulating film over the gate electrode 104, and a first oxide semiconductor film 110 at a position overlapping with the gate electrode 104 over the insulating film 108. And a source electrode 112a and a drain electrode 112b over the first oxide semiconductor film 110. In other words, the transistor 150 is provided in contact with the first oxide semiconductor film 110, the insulating film 108 serving as a gate insulating film provided in contact with the first oxide semiconductor film 110, and the insulating film 108. The gate electrode 104 is provided so as to overlap with the first oxide semiconductor film 110, and the source electrode 112 a and the drain electrode 112 b are electrically connected to the first oxide semiconductor film 110. Note that the transistor 150 illustrated in FIGS. 19A and 19B has a so-called bottom gate structure.

  In addition, insulating films 114, 116, and 118 are formed over the transistor 150, more specifically, over the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b. The insulating films 114, 116, and 118 function as protective insulating films for the transistor 150. In addition, an opening 142 reaching the drain electrode 112 b is formed in the insulating films 114, 116, and 118, and a conductive film 120 is formed on the insulating film 118 so as to cover the opening 142. The conductive film 120 functions as, for example, a pixel electrode.

  The capacitor 160 includes a second oxide semiconductor film 111 that functions as one of a pair of electrodes over the insulating film 116 and an insulating film that functions as a dielectric film over the second oxide semiconductor film 111. 118, and a conductive film 120 functioning as the other of the pair of electrodes at a position overlapping with the second oxide semiconductor film 111 with the insulating film 118 provided therebetween. In other words, the conductive film 120 functions as a pixel electrode and a capacitor element.

  Note that the first oxide semiconductor film 110 functions as a channel region of the transistor 150. In addition, the second oxide semiconductor film 111 functions as one electrode of the pair of electrodes of the capacitor 160. Therefore, the resistivity of the second oxide semiconductor film 111 is lower than that of the first oxide semiconductor film 110. In addition, the first oxide semiconductor film 110 and the second oxide semiconductor film 111 preferably include the same metal element. By using the same metal element for the first oxide semiconductor film 110 and the second oxide semiconductor film 111, a manufacturing apparatus (eg, a film formation apparatus or a processing apparatus) can be used in common. Therefore, the manufacturing cost can be suppressed.

  In addition, a wiring formed using a metal film or the like may be connected to the second oxide semiconductor film 111. For example, in the case where the semiconductor device illustrated in FIG. 1 is used for a transistor and a capacitor in a pixel portion of a display device, a lead wiring, a gate wiring, or the like is formed using a metal film, and the second oxide semiconductor film 111 is formed over the metal film. A configuration for connection may be used. By forming the lead wiring, the gate wiring, or the like with a metal film, the wiring resistance can be lowered, so that signal delay or the like can be suppressed.

  Further, the capacitor 160 has a light-transmitting property. That is, the second oxide semiconductor film 111, the conductive film 120, and the insulating film 118 included in the capacitor 160 are each formed using a light-transmitting material. In this manner, since the capacitor 160 has a light-transmitting property, it can be formed large (in a large area) in a region other than a portion where a transistor in a pixel is formed. An increased semiconductor device can be obtained. As a result, a semiconductor device having excellent display quality can be obtained.

  Note that as the insulating film 118 provided over the transistor 150 and used for the capacitor 160, an insulating film containing at least hydrogen is used. As the insulating film 107 used for the transistor 150 and the insulating films 114 and 116 provided over the transistor 150, an insulating film containing at least oxygen is used. As described above, the insulating film used for the transistor 150 and the capacitor 160 and the insulating film used for the transistor 150 and the capacitor 160 are formed using the insulating film having the above structure, whereby the first oxide semiconductor included in the transistor 150 is used. The resistivity of the second oxide semiconductor film 111 included in the film 110 and the capacitor 160 can be controlled.

  The insulating film used for the capacitor 160 and the insulating film used over the transistor 150 and the capacitor 160 have the following structure, whereby the flatness of the conductive film 120 can be improved. Specifically, the insulating films 114 and 116 are provided over the first oxide semiconductor film 110, and the second oxide semiconductor film 111 is sandwiched between the insulating film 116 and the insulating film 118. As described above, the resistance of the second oxide semiconductor film 111 without providing an opening in the insulating films 114 and 116 in a position overlapping with the second oxide semiconductor film 111 is provided over the second oxide semiconductor film 111. The rate can be controlled. With such a structure, for example, when the semiconductor device illustrated in FIG. 19 is used for a transistor and a capacitor in a pixel portion of a liquid crystal display device, the orientation of liquid crystal formed over the conductive film 120 is favorable. be able to.

  Note that the conductive film 120a formed at the same time as the conductive film 120 and etched at the same time may be provided so as to overlap with the channel region of the transistor. An example in that case is shown in FIG. For example, the conductive film 120a has the same material because it is formed at the same time as the conductive film 120, etched at the same time, and formed at the same time. Therefore, an increase in process steps can be suppressed. Note that one embodiment of the present invention is not limited to this. The conductive film 120a may be formed in a step different from that of the conductive film 120. The conductive film 120a has a region overlapping with the channel region of the transistor. Therefore, the conductive film 120a functions as the second gate electrode of the transistor. Therefore, the conductive film 120a may be connected to the gate electrode 104. Alternatively, the conductive film 120 a may be supplied with a different signal or a different potential from the gate electrode 104 without being connected to the gate electrode 104. With such a structure, the current driving capability of the transistor 150 can be further improved. At this time, the gate insulating films for the second gate electrode become the insulating films 114, 116, and 118.

  Alternatively, the second oxide semiconductor film 111a may be formed at the same time as the second oxide semiconductor film 111 and etched at the same time so that the second oxide semiconductor film 111a formed at the same time overlaps with a channel region of the transistor. An example in that case is shown in FIG. For example, the second oxide semiconductor film 111a is formed at the same time as the second oxide semiconductor film 111, etched at the same time, and formed at the same time, and thus has the same material. Therefore, an increase in process steps can be suppressed. Note that one embodiment of the present invention is not limited to this. The second oxide semiconductor film 111a may be formed in a step different from that of the second oxide semiconductor film 111. The second oxide semiconductor film 111 a has a region overlapping with the first oxide semiconductor film 110 which serves as a channel region of the transistor 150. Therefore, the second oxide semiconductor film 111a functions as the second gate electrode of the transistor 150. Therefore, the second oxide semiconductor film 111a may be connected to the gate electrode 104. Alternatively, the second oxide semiconductor film 111a may be supplied with a different signal or a different potential from the gate electrode 104 without being connected to the gate electrode 104. With such a structure, the gate insulating film with respect to the second gate electrode becomes the insulating films 114 and 116, so that the current driving capability of the transistor 150 is further improved as compared with the transistor illustrated in FIG. be able to.

  Note that in the transistor 150, since the first oxide semiconductor film 110 is used as a channel region, the resistivity is higher than that of the second oxide semiconductor film 111. On the other hand, the second oxide semiconductor film 111 has a function as an electrode, and thus has a lower resistivity than the first oxide semiconductor film 110.

  Here, a method for controlling the resistivity of the first oxide semiconductor film 110 and the second oxide semiconductor film 111 is described below.

<Method for controlling resistivity of oxide semiconductor>
The oxide semiconductor film that can be used for the first oxide semiconductor film 110 and the second oxide semiconductor film 111 has a resistivity depending on oxygen vacancies in the film and / or the concentration of impurities such as hydrogen and water in the film. It is a semiconductor material that can control. Therefore, by selecting a process for increasing oxygen vacancies and / or impurity concentration or a process for reducing oxygen vacancies and / or impurity concentration for the first oxide semiconductor film 110 and the second oxide semiconductor film 111, The resistivity of each oxide semiconductor film can be controlled.

  Specifically, plasma treatment is performed on the oxide semiconductor film used for the second oxide semiconductor film 111 functioning as an electrode of the capacitor 160 to increase oxygen vacancies in the oxide semiconductor film, and / or By increasing impurities such as hydrogen and water in the oxide semiconductor film, an oxide semiconductor film with high carrier density and low resistivity can be obtained. Further, an insulating film containing hydrogen is formed in contact with the oxide semiconductor film, and hydrogen is diffused from the insulating film containing hydrogen, for example, the insulating film 118 into the oxide semiconductor film, whereby the carrier density is high and the resistivity is high. A low oxide semiconductor film can be obtained. The second oxide semiconductor film 111 has a function as a semiconductor before the step of increasing oxygen vacancies in the film or diffusing hydrogen as described above, and a conductor after the step. As a function.

  On the other hand, the first oxide semiconductor film 110 functioning as a channel region of the transistor 150 is not in contact with the insulating films 106 and 118 containing hydrogen by providing the insulating films 107, 114, and 116. Oxygen is supplied to the first oxide semiconductor film 110 by applying an insulating film containing oxygen to at least one of the insulating films 107, 114, and 116, in other words, an insulating film capable of releasing oxygen. can do. The first oxide semiconductor film 110 to which oxygen is supplied becomes an oxide semiconductor film with high resistivity by filling oxygen vacancies in the film or at the interface. Note that as the insulating film from which oxygen can be released, for example, a silicon oxide film or a silicon oxynitride film can be used.

  In order to obtain an oxide semiconductor film with low resistivity, hydrogen, boron, phosphorus, or nitrogen is implanted into the oxide semiconductor film by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. May be.

  Further, in order to obtain an oxide semiconductor film with low resistivity, plasma treatment may be performed on the oxide semiconductor film. For example, the plasma treatment typically includes plasma treatment using a gas containing one or more selected from rare gases (He, Ne, Ar, Kr, Xe), hydrogen, and nitrogen. . More specifically, plasma treatment in an Ar atmosphere, plasma treatment in a mixed gas atmosphere of Ar and hydrogen, plasma treatment in an ammonia atmosphere, plasma treatment in a mixed gas atmosphere of Ar and ammonia, or nitrogen For example, plasma treatment in an atmosphere.

  Through the above plasma treatment, the oxide semiconductor film forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). The oxygen deficiency may be a factor that generates carriers. Further, when hydrogen is supplied from the vicinity of the oxide semiconductor film, more specifically, from an insulating film in contact with the lower side or the upper side of the oxide semiconductor film, the oxygen vacancies and hydrogen are combined to form carriers. It may generate electrons.

On the other hand, an oxide semiconductor film in which oxygen vacancies are filled and the hydrogen concentration is reduced can be said to be a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Here, the substantially intrinsic, the carrier density of the oxide semiconductor film, 8 × ^{10 11} pieces / cm less than ^3, preferably less than 1 × ¹⁰ 11 / cm ^3, more preferably 1 × ^{10 10} pieces / cm It means less than ³ . A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low defect level density; therefore, the trap level density can be reduced.

Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less. Therefore, the transistor 150 in which the first oxide semiconductor film 110a using the above-described high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is used for a channel region has little variation in electrical characteristics and high reliability. It becomes a transistor.

As the insulating film 118, for example, an insulating film containing hydrogen, in other words, an insulating film capable of releasing hydrogen, typically a silicon nitride film, is used, so that hydrogen is supplied to the second oxide semiconductor film 111. Can be supplied. As the insulating film capable of releasing hydrogen, the concentration of hydrogen contained in the film is preferably 1 × 10 ²² atoms / cm ³ or more. By forming such an insulating film in contact with the second oxide semiconductor film 111, hydrogen can be effectively contained in the second oxide semiconductor film 111. As described above, the resistivity of the oxide semiconductor film can be controlled by changing the structure of the insulating film in contact with the first oxide semiconductor film 110 and the second oxide semiconductor film 111. Note that the insulating film 106 may be formed using a material similar to that of the insulating film 118. By using silicon nitride as the insulating film 106, oxygen released from the insulating film 107 is supplied to the gate electrode 104 and can be prevented from being oxidized.

  Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to become water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, the second oxide semiconductor film 111 provided in contact with the insulating film containing hydrogen is an oxide semiconductor film having a carrier density higher than that of the first oxide semiconductor film 110.

In the first oxide semiconductor film 110 in which the channel region of the transistor 150 is formed, hydrogen is preferably reduced as much as possible. Specifically, in the first oxide semiconductor film 110, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

On the other hand, the second oxide semiconductor film 111 functioning as an electrode of the capacitor 160 is an oxide semiconductor film having a higher hydrogen concentration and / or oxygen deficiency and a lower resistivity than the first oxide semiconductor film 110. is there. The concentration of hydrogen contained in the second oxide semiconductor film 111 is 8 × 10 ¹⁹ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ or more. Further, the concentration of hydrogen contained in the second oxide semiconductor film 111 is twice or more, preferably 10 times or more, as compared to the first oxide semiconductor film 110. The resistivity of the second oxide semiconductor film 111 is preferably 1 × 10 ⁻⁸ times or more and less than 1 × 10 ⁻¹ times the resistivity of the first oxide semiconductor film 110, typically. Is 1 × 10 ⁻³ Ωcm or more and less than 1 × 10 ⁴ Ωcm, more preferably, the resistivity is 1 × 10 ⁻³ Ωcm or more and less than 1 × 10 ⁻¹ Ωcm.

  Here, details of other components of the semiconductor device illustrated in FIGS. 19A and 19B are described below.

<Board>
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. It is also possible to apply a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., and a semiconductor element provided on these substrates May be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. By using a large area substrate such as a generation (2950 mm × 3400 mm), a large display device can be manufactured. Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 150, the capacitor 160, and the like may be formed directly over the flexible substrate.

  In addition to these, a transistor can be formed using various substrates as the substrate 102. The kind of board | substrate is not limited to a specific thing. Examples of the substrate include a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded film, and a fibrous material. Or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

  Note that a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. As an example of the substrate on which the transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), There are synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

<First oxide semiconductor film and second oxide semiconductor film>
The first oxide semiconductor film 110 and the second oxide semiconductor film 111 include at least indium (In), zinc (Zn), and M (Al, Ti, Ga, Y, Zr, La, Ce, Sn, Hf, or the like. It is preferable to include a film represented by an In-M-Zn oxide containing a metal. In addition, in order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, a stabilizer is preferably included together with the transistor.

  Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like, including the metals described in M above. Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb). ), Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

  As an oxide semiconductor included in the first oxide semiconductor film 110 and the second oxide semiconductor film 111, for example, an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, or In—Sn—Zn is used. Oxide, In—Hf—Zn oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In -Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide Oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-S -Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide can be used In-Hf-Al-Zn-based oxide.

  Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

  In addition, the first oxide semiconductor film 110 and the second oxide semiconductor film 111 may include the same metal element among the above oxides. By using the same metal element for the first oxide semiconductor film 110 and the second oxide semiconductor film 111, manufacturing cost can be reduced. For example, manufacturing costs can be reduced by using metal oxide targets having the same metal composition. In addition, when a metal oxide target having the same metal composition is used, an etching gas or an etching solution for processing the oxide semiconductor film can be used in common. Note that the first oxide semiconductor film 110 and the second oxide semiconductor film 111 may have different compositions even if they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.

  Note that in the case where the first oxide semiconductor film 110 is an In-M-Zn oxide, the ratio of the number of In atoms to M atoms is preferably 25 atomic% when the sum of In and M is 100 atomic%. Higher, M is less than 75 atomic%, more preferably In is higher than 34 atomic%, and M is less than 66 atomic%.

  The first oxide semiconductor film 110 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of the transistor 52 can be reduced by using an oxide semiconductor with a wide energy gap.

  The thickness of the first oxide semiconductor film 110 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

  In the case where the first oxide semiconductor film 110 is an In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd), the In-M-Zn oxide is formed. The atomic ratio of the metal elements of the sputtering target used preferably satisfies In ≧ M and Zn ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, and the like. Note that the atomic ratio of the first oxide semiconductor film 110 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.

As the first oxide semiconductor film 110, an oxide semiconductor film with low carrier density is used. For example, the first oxide semiconductor film 110 has a carrier density of 1 × 10 ¹⁷ pieces / cm ³ or less, preferably 1 × 10 ¹⁵ pieces / cm ³ or less, more preferably 1 × 10 ¹³ pieces / cm ³ or less. More preferably, an oxide semiconductor film of 1 × 10 ¹¹ pieces / cm ³ or less is used.

  Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the first oxide semiconductor film 110 are appropriately set. Preferably.

In the first oxide semiconductor film 110, when silicon or carbon which is one of Group 14 elements is included, oxygen vacancies increase in the first oxide semiconductor film 110 and the n-type oxide semiconductor film 110 is formed. Therefore, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the first oxide semiconductor film 110 is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm 3. ³ or less.

In the first oxide semiconductor film 110, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm 2. Set to cm ³ or less. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the first oxide semiconductor film 110.

In addition, when nitrogen is contained in the first oxide semiconductor film 110, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less. .

  The first oxide semiconductor film 110 may have a non-single crystal structure, for example. The non-single-crystal structure is, for example, a CAAC-OS (c-axis-aligned crystal oxide semiconductor, which will be described later, or a c-axis aligned and a-b-plane-anchored crystal oxide semi-crystal structure, which will be described later, Or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  The first oxide semiconductor film 110 may have an amorphous structure, for example. An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

  Note that the first oxide semiconductor film 110 is a mixed film including an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure. May be. For example, the mixed film may include two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. For example, the mixed film has a stacked structure of two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. May have.

<Insulating film>
As the insulating films 106 and 107 functioning as the gate insulating film of the transistor 150, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film is formed by a plasma CVD (CVD: Chemical Vapor Deposition) method, a sputtering method, or the like. Insulating films including one or more of aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film are used. be able to. Note that a single-layer insulating film selected from the above materials may be used instead of the stacked structure of the insulating films 106 and 107.

  The insulating film 106 functions as a blocking film that suppresses permeation of oxygen. For example, in the case where excess oxygen is supplied into the insulating films 107, 114, and 116 and / or the first oxide semiconductor film 110, the insulating film 106 can suppress permeation of oxygen.

  Note that the insulating film 107 in contact with the first oxide semiconductor film 110 functioning as the channel region of the transistor 150 is preferably an oxide insulating film, and includes a region containing oxygen in excess of the stoichiometric composition ( More preferably, it has an oxygen-excess region. In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide the oxygen-excess region in the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 107 after film formation to form an oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

  In addition, when hafnium oxide is used as the insulating films 106 and 107, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, since the film thickness can be increased with respect to silicon oxide or silicon oxynitride, leakage current due to tunneling current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

  Note that in this embodiment, a silicon nitride film is formed as the insulating film 106 and a silicon oxide film is formed as the insulating film 107. Since the silicon nitride film has a higher relative dielectric constant than a silicon oxide film and a large film thickness necessary to obtain the same capacitance as the silicon oxide film, the insulating film functions as a gate insulating film of the transistor 150 By including a silicon nitride film as 108, the insulating film can be physically thickened. Therefore, a decrease in the withstand voltage of the transistor 150 can be suppressed, and further, the withstand voltage can be improved, so that electrostatic breakdown of the transistor 150 can be suppressed.

<Gate electrode, source electrode and drain electrode>
As a material that can be used for the gate electrode 104, the source electrode 112a, and the drain electrode 112b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or a main material thereof is used. The alloy as a component can be used as a single layer structure or a laminated structure. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a molybdenum film, or an alloy film containing molybdenum and tungsten Two-layer structure in which a copper film is laminated, two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and an aluminum film or copper layered on the titanium film or titanium nitride film A three-layer structure in which a film is stacked and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is stacked on the molybdenum film or the molybdenum nitride film, Further, there is a three-layer structure on which a molybdenum film or a molybdenum nitride film is formed. When the source electrode 112a and the drain electrode 112b have a three-layer structure, the first and third layers include titanium, titanium nitride, molybdenum, tungsten, an alloy containing molybdenum and tungsten, an alloy containing molybdenum and zirconium, Alternatively, a film made of molybdenum nitride is preferably formed, and a film made of a low resistance material such as copper, aluminum, gold or silver, or an alloy of copper and manganese is preferably formed as the second layer. Addition of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide Alternatively, a light-transmitting conductive material such as indium tin oxide may be used. A material that can be used for the gate electrode 104, the source electrode 112a, and the drain electrode 112b can be formed by a sputtering method, for example.

<Conductive film>
The conductive film 120 functions as a pixel electrode. For the conductive film 120, for example, a material having a light-transmitting property in visible light may be used. Specifically, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film 120, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO : Indium Tin Oxide), indium zinc oxide, conductive material having translucency such as indium tin oxide to which silicon oxide is added can be used. Further, the conductive film 120 can be formed by, for example, a sputtering method.

<Protective insulating film ALD>
As the insulating films 114, 116, and 118 that function as protective insulating films for the transistor 150, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a plasma CVD method, a sputtering method, and the like An insulating film containing at least one of a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.

  The insulating film 114 in contact with the first oxide semiconductor film 110 functioning as the channel region of the transistor 150 is preferably an oxide insulating film, and an insulating film capable of releasing oxygen is used. In other words, the insulating film capable of releasing oxygen is an insulating film having a region (oxygen-excess region) containing oxygen in excess of the stoichiometric composition. In order to provide the oxygen excess region in the insulating film 114, for example, the insulating film 114 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after film formation to form an oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

By using an insulating film capable of releasing oxygen as the insulating film 114, oxygen is transferred to the first oxide semiconductor film 110 functioning as a channel region of the transistor 150, so that the first oxide semiconductor film 110 It is possible to reduce the amount of oxygen deficiency. For example, the amount of released oxygen molecules in the range where the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower is measured by temperature programmed desorption gas analysis (hereinafter referred to as TDS analysis) By using an insulating film with 1.0 × 10 ¹⁸ molecules / cm ³ or more, the amount of oxygen vacancies contained in the first oxide semiconductor film 110 can be reduced.

The insulating film 114 preferably has a small amount of defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 3 × 10 ¹⁷ spins / It is preferable that it is cm ³ or less. This is because when the density of defects included in the insulating film 114 is high, oxygen is bonded to the defects and the amount of oxygen transmitted through the insulating film 114 is reduced. In addition, it is preferable that the amount of defects at the interface between the insulating film 114 and the first oxide semiconductor film 110 be small. Typically, the g value derived from the defects in the first oxide semiconductor film 110 is determined by ESR measurement. Is preferably 1.89 or more and 1.96 or less, and the spin density of the signal is 1 × 10 ¹⁷ spins / cm ³ or less, and more preferably the detection lower limit or less.

  Note that in the insulating film 114, all oxygen that enters the insulating film 114 from the outside may move to the outside of the insulating film 114. Alternatively, part of oxygen that enters the insulating film 114 from the outside may remain in the insulating film 114. In some cases, oxygen enters the insulating film 114 from the outside and oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, so that oxygen moves in the insulating film 114. When an oxide insulating film that can transmit oxygen is formed as the insulating film 114, oxygen released from the insulating film 216 provided over the insulating film 114 is transferred to the oxide semiconductor film 208 through the insulating film 114. Can be made.

The insulating film 114 can be formed using an oxide insulating film in which the level density of nitrogen oxides is low. Incidentally, state density of the nitrogen oxides, the energy of the top of the valence band of the oxide semiconductor film (E _{V_OS),} is formed between the energy conductor lower ends of the oxide semiconductor film (E _{C_OS)} You may get. As an oxide insulating film in which the level density of nitrogen oxide is low between _{EV_OS} and E _{C_OS,} a silicon oxynitride film with a low emission amount of nitrogen oxide, an aluminum oxynitride film with a low emission amount of nitrogen oxide, or the like Can be used.

Note that a silicon oxynitride film that emits less nitrogen oxide is a film that releases more ammonia than nitrogen oxide in a temperature programmed desorption gas analysis method, and typically releases ammonia molecules. The amount is 1 × 10 ¹⁸ molecules / cm ³ or more and 5 × 10 ¹⁹ molecules / cm ³ or less. Note that the amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50 ° C. to 650 ° C., preferably 50 ° C. to 550 ° C.

Nitrogen oxide (NO _x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO forms a level in the insulating film 114 or the like. The level is located in the energy gap of the oxide semiconductor film 208. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 114 and the oxide semiconductor film 208, the level may trap electrons on the insulating film 114 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 114 and the oxide semiconductor film 208, so that the threshold voltage of the transistor is shifted in the positive direction.

  Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 216 in the heat treatment, nitrogen oxide contained in the insulating film 114 is reduced. Therefore, electrons are not easily trapped at the interface between the insulating film 114 and the oxide semiconductor film 208.

  By using the oxide insulating film as the insulating film 114, a shift in threshold voltage of the transistor can be reduced, and variation in electric characteristics of the transistor can be reduced.

Note that the insulating film 114 is measured with an ESR of 100 K or less by heat treatment in a transistor manufacturing process, typically less than 400 ° C. or less than 375 ° C. (preferably, 340 ° C. to 360 ° C.). In the obtained spectrum, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a g value of 1.964 to 1.966 The following third signal is observed. The split width of the first signal and the second signal and the split width of the second signal and the third signal are about 5 mT in the X-band ESR measurement. In addition, a first signal having a g value of 2.037 or more and 2.039 or less, a second signal having a g value of 2.001 or more and 2.003 or less, and a first signal having a g value of 1.964 or more and 1.966 or less. The total density of the spins of the three signals is less than 1 × 10 ¹⁸ spins / cm ³ , typically 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ .

In the ESR spectrum of 100K or less, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a g value of 1.964 to 1 A third signal of .966 or less corresponds to a signal caused by nitrogen oxides (NO _x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a first signal having a g value of 1.964 to 1.966. It can be said that the smaller the total density of the signal spins of 3, the smaller the content of nitrogen oxide contained in the oxide insulating film.

The oxide insulating film has a nitrogen concentration measured by SIMS of 6 × 10 ²⁰ atoms / cm ³ or less.

  By forming the oxide insulating film using a PECVD method using silane and dinitrogen monoxide with a substrate temperature of 220 ° C. or higher and 350 ° C. or lower, a dense and high hardness film is formed. be able to.

The insulating film 116 formed so as to be in contact with the insulating film 114 is formed using an oxide insulating film containing oxygen in excess of the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition. An oxide insulating film containing oxygen in excess of oxygen that satisfies the stoichiometric composition has an oxygen release amount converted to oxygen atoms by thermal desorption gas spectroscopy (TDS). The oxide insulating film has a thickness of 1.0 × 10 ¹⁹ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film in the TDS is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

The insulating film 116 preferably has a small amount of defects. Typically, the ESR measurement shows that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 1.5 × 10 ^18. spins / cm less than ^3, and further preferably not larger than ^{1 × 10 18 spins / cm 3} . Note that the insulating film 116 is farther from the first oxide semiconductor film 110 than the insulating film 114, and thus has a higher defect density than the insulating film 114.

  The thickness of the insulating film 114 can be 5 nm to 150 nm, preferably 5 nm to 50 nm, preferably 10 nm to 30 nm. The thickness of the insulating film 116 can be greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 150 nm and less than or equal to 400 nm.

  In addition, since the insulating films 114 and 116 can be formed using the same kind of insulating film, the interface between the insulating film 114 and the insulating film 116 may not be clearly confirmed. Therefore, in this embodiment mode, the interface between the insulating film 114 and the insulating film 116 is indicated by a broken line. Note that although a two-layer structure of the insulating film 114 and the insulating film 116 is described in this embodiment mode, the present invention is not limited to this, and for example, a single-layer structure of the insulating film 114, a single-layer structure of the insulating film 116, or It is good also as a laminated structure of three or more layers.

  The insulating film 118 that functions as a dielectric film of the capacitor 160 is preferably a nitride insulating film. In particular, a silicon nitride film has a higher relative dielectric constant than a silicon oxide film and has a large film thickness necessary for obtaining a capacitance equivalent to that of a silicon oxide film, and thus functions as a dielectric film of the capacitor 160. By including a silicon nitride film as the insulating film 118, the insulating film can be physically thickened. Therefore, a decrease in the withstand voltage of the capacitor 160 can be suppressed, and further, the withstand voltage can be improved, and electrostatic breakdown of the capacitor 160 can be suppressed. Note that the insulating film 118 also has a function of reducing the resistivity of the second oxide semiconductor film 111 that functions as an electrode of the capacitor 160.

  The insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating film 118, diffusion of oxygen from the first oxide semiconductor film 110 to the outside, diffusion of oxygen contained in the insulating films 114 and 116, and the first oxide semiconductor from the outside Intrusion of hydrogen, water, or the like into the film 110 can be prevented. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

<Method for Manufacturing Semiconductor Device>
Next, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 19A and 19B will be described with reference to FIGS.

  First, the gate electrode 104 is formed over the substrate 102. After that, an insulating film 108 including insulating films 106 and 107 is formed over the substrate 102 and the gate electrode 104 (see FIG. 21A).

  Note that the substrate 102, the gate electrode 104, and the insulating films 106 and 107 can be formed by being selected from the above-described materials. Note that in this embodiment, a glass substrate is used as the substrate 102, a tungsten film is used as the conductive film as the gate electrode 104, and a silicon nitride film capable of releasing hydrogen is used as the insulating film 106. As the insulating film 107, a silicon oxynitride film capable of releasing oxygen is used.

  The gate electrode 104 can be formed by forming a conductive film over the substrate 102, patterning the conductive film so that a desired region remains, and then etching unnecessary regions.

  Next, a first oxide semiconductor film 110 is formed in a position overlapping with the gate electrode 104 over the insulating film 108 (see FIG. 21B).

  The first oxide semiconductor film 110 can be formed by selecting from the materials listed above. Note that in this embodiment, as the first oxide semiconductor film 110, an In—Ga—Zn oxide film (a metal oxide target of In: Ga: Zn = 1: 1: 1.2 is used). ) Is used.

  The first oxide semiconductor film 110 is formed by patterning an oxide semiconductor film over the insulating film 108 so that a desired region of the oxide semiconductor film remains, and then etching unnecessary regions. Can be formed.

  After the first oxide semiconductor film 110 is formed, heat treatment is preferably performed. The heat treatment is performed at a temperature of 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, more preferably 350 ° C. or higher and 450 ° C. or lower, an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or higher, or a reduced-pressure atmosphere. Just do it. The heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement oxygen desorbed from the first oxide semiconductor film 110 after the heat treatment in an inert gas atmosphere. By the heat treatment here, impurities such as hydrogen and water can be removed from at least one of the insulating films 106 and 107 and the first oxide semiconductor film 110. Note that the heat treatment may be performed before the first oxide semiconductor film 110 is processed into an island shape.

  Note that in order to impart stable electric characteristics to the transistor 150 including the first oxide semiconductor film 110 as a channel region, impurities in the first oxide semiconductor film 110 are reduced and the first oxide semiconductor film 110 is reduced. It is useful to make the film 110 intrinsic or substantially intrinsic.

  Next, a conductive film is formed over the insulating film 108 and the first oxide semiconductor film 110, patterned so that a desired region of the conductive film remains, and then an unnecessary region is etched, thereby insulating the conductive film. A source electrode 112a and a drain electrode 112b are formed over the film 108 and the first oxide semiconductor film 110 (see FIG. 21C).

  The source electrode 112a and the drain electrode 112b can be formed by selecting from the materials listed above. Note that in this embodiment, a three-layer structure of a tungsten film, an aluminum film, and a titanium film is used as the source electrode 112a and the drain electrode 112b.

  Further, the surface of the oxide semiconductor film 110 may be washed after the source electrode 112a and the drain electrode 112b are formed. Examples of the cleaning method include cleaning using a chemical solution such as phosphoric acid. By cleaning with a chemical solution such as phosphoric acid, impurities attached to the surface of the oxide semiconductor film 110 (eg, elements contained in the source electrode 112a and the drain electrode 112b) can be removed. Note that the cleaning is not necessarily performed, and in some cases, the cleaning may not be performed.

  The region exposed from the source electrode 112a and the drain electrode 112b of the oxide semiconductor film 110 is thinned in either or both of the step of forming the source electrode 112a and the drain electrode 112b and the cleaning step. There is.

  Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b. Then, patterning is performed so that desired regions of the insulating films 114 and 116 remain, and then unnecessary regions are etched to form openings 141 (see FIG. 21D).

  Note that after the insulating film 114 is formed, the insulating film 116 is preferably formed continuously without being exposed to the air. After forming the insulating film 114, the insulating film 114 and the insulating film are formed by continuously forming the insulating film 116 by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature of the source gas without opening to the atmosphere. The concentration of impurities derived from atmospheric components can be reduced at the interface with 116, and oxygen contained in the insulating films 114 and 116 can be moved to the first oxide semiconductor film 110, so that the first oxide It is possible to reduce the amount of oxygen vacancies in the semiconductor film 110.

  In the step of forming the insulating film 116, the insulating film 114 serves as a protective film for the first oxide semiconductor film 110. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while reducing damage to the first oxide semiconductor film 110.

  The insulating films 114 and 116 can be formed by selecting from the materials listed above. Note that in this embodiment, as the insulating films 114 and 116, a silicon oxynitride film capable of releasing oxygen is used.

  Further, it is preferable that heat treatment (hereinafter referred to as first heat treatment) be performed after the insulating films 114 and 116 are formed. By the first heat treatment, nitrogen oxides contained in the insulating films 114 and 116 can be reduced. Alternatively, part of oxygen contained in the insulating films 114 and 116 is moved to the first oxide semiconductor film 110 by the first heat treatment, so that the amount of oxygen vacancies contained in the first oxide semiconductor film 110 is reduced. can do.

  The temperature of the first heat treatment is typically less than 400 ° C, preferably less than 375 ° C, and more preferably 150 ° C to 350 ° C. The first heat treatment is performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (such as argon or helium). Just do it. Note that it is preferable that hydrogen, water, and the like be not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas. For the heat treatment, an electric furnace, RTA (Rapid Thermal Anneal), or the like can be used.

  The opening 141 is formed so that the drain electrode 112b is exposed. As a method for forming the opening 141, for example, a dry etching method can be used. However, the formation method of the opening 141 is not limited to this, and may be a wet etching method or a formation method in which a dry etching method and a wet etching method are combined. Note that the thickness of the drain electrode 112b may be reduced by an etching step for forming the opening 141.

  Next, an oxide semiconductor film to be the second oxide semiconductor film 111 is formed over the insulating film 116 so as to cover the opening 141 (see FIGS. 22A and 22B).

  Note that FIG. 22A is a schematic cross-sectional view of the inside of the deposition apparatus when an oxide semiconductor film is formed over the insulating film 116. In FIG. 22A, a sputtering apparatus is used as the film formation apparatus, and a target 165 installed inside the sputtering apparatus and a plasma 166 formed below the target 165 are schematically shown.

  First, when the oxide semiconductor film is formed, plasma is discharged in an atmosphere containing a third oxygen gas. At that time, oxygen is added into the insulating film 116 to be a formation surface of the oxide semiconductor film. In forming the oxide semiconductor film, an inert gas (eg, helium gas, argon gas, xenon gas, or the like) may be mixed in addition to the third oxygen gas. For example, it is preferable to use argon gas and third oxygen gas and increase the flow rate of the third oxygen gas more than the flow rate of the argon gas. By increasing the flow rate of the third oxygen gas, oxygen can be preferably added to the insulating film 116. For example, as a formation condition of the oxide semiconductor film, the ratio of the third oxygen gas in the entire deposition gas may be 50% to 100%, preferably 80% to 100%.

  Note that in FIG. 22A, oxygen or excess oxygen added to the insulating film 116 is schematically represented by a dashed arrow.

  The substrate temperature at the time of forming the oxide semiconductor film is room temperature to less than 340 ° C., preferably room temperature to 300 ° C., more preferably 100 ° C. to 250 ° C., and further preferably 100 ° C. to 200 ° C. It is. By forming the oxide semiconductor film by heating, the crystallinity of the oxide semiconductor film can be increased. On the other hand, when a large glass substrate (for example, the sixth generation to the tenth generation) is used as the substrate 102, the substrate temperature when the oxide semiconductor film is formed is 150 ° C. or higher and lower than 340 ° C. 102 may be deformed (distorted or warped). Therefore, in the case where a large glass substrate is used, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the oxide semiconductor film to 100 ° C. or higher and lower than 150 ° C.

  The oxide semiconductor film can be formed by selecting from the materials listed above. In this embodiment, an oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn metal oxide target (In: Ga: Zn = 1: 3: 6 [atomic ratio]).

  Next, the island-shaped second oxide semiconductor film 111 is formed by processing the oxide semiconductor into a desired shape (see FIG. 22C).

  The second oxide semiconductor film 111 is formed by forming an oxide semiconductor film over the insulating film 116, patterning the oxide semiconductor film so that a desired region remains, and then etching unnecessary regions. it can.

  Next, the insulating film 118 is formed over the insulating film 116 and the second oxide semiconductor film 111 (see FIG. 23A).

  The insulating film 118 includes one or both of hydrogen and nitrogen. As the insulating film 118, for example, a silicon nitride film is preferably used. The insulating film 118 can be formed using, for example, a sputtering method or a PECVD method. For example, in the case where the insulating film 118 is formed by a PECVD method, the substrate temperature is lower than 400 ° C., preferably lower than 375 ° C., more preferably 180 ° C. or higher and 350 ° C. or lower. It is preferable to set the substrate temperature in the case of forming the insulating film 118 within the above range because a dense film can be formed. In addition, by setting the substrate temperature in the case of forming the insulating film 118 within the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved to the oxide semiconductor film 110.

  Alternatively, after the insulating film 118 is formed, heat treatment equivalent to the first heat treatment described above (hereinafter referred to as second heat treatment) may be performed. As described above, in the formation of the oxide semiconductor film to be the second oxide semiconductor film 111, oxygen is added to the insulating film 116, and then less than 400 ° C., preferably less than 375 ° C., more preferably 180 ° C. By performing heat treatment at a temperature of 350 ° C. or lower, oxygen or excess oxygen in the insulating film 116 is moved into the first oxide semiconductor film 110, and oxygen vacancies in the first oxide semiconductor film 110 are transferred. Can be compensated.

  Here, oxygen that moves into the first oxide semiconductor film 110 is described with reference to FIGS. FIG. 24 shows the first temperature by the substrate temperature (typically less than 375 ° C.) at the time of forming the insulating film 118 or the second heat treatment (typically less than 375 ° C.) after the insulating film 118 is formed. FIG. 10 is a model diagram showing oxygen moving into the oxide semiconductor film 110. In FIG. 24, oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) shown in the first oxide semiconductor film 110 is represented by a dashed arrow. 24A and 24B are cross-sectional views corresponding to the dashed-dotted line AB and the dashed-dotted line EF shown in FIG. 1A, respectively, after the insulating film 118 is formed.

  The first oxide semiconductor film 110 illustrated in FIG. 24 fills oxygen vacancies by movement of oxygen from films in contact with the first oxide semiconductor film 110 (here, the insulating film 107 and the insulating film 114). Is done. In particular, in the semiconductor device of one embodiment of the present invention, when sputtering is performed on the oxide semiconductor film to be the first oxide semiconductor film 110, oxygen gas is used and oxygen is added to the insulating film 107. 107 has an excess oxygen region. In addition, since oxygen is used to add oxygen to the insulating film 116 when the oxide semiconductor film to be the second oxide semiconductor film 111 is formed by sputtering, the insulating film 116 has an excess oxygen region. Thus, the first oxide semiconductor film 110 sandwiched between the insulating films having the excess oxygen region is preferably filled with oxygen vacancies.

  In addition, an insulating film 106 is provided below the insulating film 107, and an insulating film 118 is provided above the insulating films 114 and 116. By forming the insulating films 106 and 118 using a material having low oxygen permeability, such as silicon nitride, oxygen contained in the insulating films 107, 114, and 116 can be confined to the first oxide semiconductor film 110 side. Thus, oxygen can be preferably transferred to the first oxide semiconductor film 110. Note that the insulating film 118 also has an effect of preventing impurities from the outside, for example, water, alkali metal, alkaline earth metal, and the like from diffusing into the first oxide semiconductor film 110 included in the transistor 150.

  The insulating film 118 includes one or both of hydrogen and nitrogen. Therefore, when the insulating film 118 is formed, the carrier density of the second oxide semiconductor film 111 in contact with the insulating film 118 is increased by adding one or both of hydrogen and nitrogen, and the oxide film It can function as a conductive film.

  Note that as the resistivity of the second oxide semiconductor film 111 is decreased, the hatching of the second oxide semiconductor film 111 illustrated in FIGS. 22C and 23A is changed.

The resistivity of the second oxide semiconductor film 111 is at least lower than that of the first oxide semiconductor film 110, preferably 1 × 10 ⁻³ Ωcm or more and less than 1 × 10 ⁴ Ωcm, more preferably 1 × 10. It is good that it is ⁻³ Ωcm or more and less than 1 × 10 ⁻¹ Ωcm.

  Next, patterning is performed so that a desired region of the insulating film 118 remains, and then an unnecessary region is etched to form an opening 142 (see FIG. 23B).

  The opening 142 is formed so that the drain electrode 112b is exposed. As a method for forming the opening 142, for example, a dry etching method can be used. However, the formation method of the opening 142 is not limited to this, and may be a wet etching method or a formation method in which a dry etching method and a wet etching method are combined. Note that the thickness of the drain electrode 112b may be reduced by an etching step for forming the opening 142.

  Note that the openings may be formed continuously in the insulating films 114, 116, and 118 in the step of forming the opening 142 without performing the step of forming the opening 141 described above. With such a process, a manufacturing process of the semiconductor device of one embodiment of the present invention can be reduced, so that manufacturing cost can be reduced.

  Next, a conductive film is formed over the insulating film 118 so as to cover the opening 142, and patterning and etching are performed so that a desired shape of the conductive film remains, so that the conductive film 120 is formed (FIG. 23C). reference).

  The conductive film 120 can be formed by selecting from the materials listed above. Note that an indium tin oxide film is used as the conductive film 120 in this embodiment.

  In addition, with the formation of the conductive film 120, the capacitor 160 is manufactured. The capacitor 160 has a structure in which a dielectric layer is sandwiched between a pair of electrodes. One of the pair of electrodes is the second oxide semiconductor film 111, and the other of the pair of electrodes is the conductive film 120. In addition, the insulating film 118 functions as a dielectric layer of the capacitor 160.

  Through the above steps, the transistor 150 and the capacitor 160 can be formed over the same substrate.

  As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 8)
In this embodiment, a modified example of the semiconductor device described in Embodiment 7 will be described with reference to FIGS. Note that portions similar to those shown in FIGS. 19 to 24 of Embodiment 7 or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

<Configuration Example of Semiconductor Device (Modification 1)>
FIG. 25A is a top view of the semiconductor device of one embodiment of the present invention, and FIG. 25B illustrates a single-dot chain line G-H, a single-dot chain line I-J, and a single point in FIG. This corresponds to a cross-sectional view of a cut surface between chain lines KL. Note that in FIG. 25A, some components (such as a gate insulating film) of the semiconductor device are omitted in order to avoid complexity.

  The semiconductor device illustrated in FIGS. 25A and 25B includes a transistor 151 including a first oxide semiconductor film 110 and a second oxide semiconductor film 111 and a gate wiring including a second oxide semiconductor film 111b. Contact portion 170. Note that the gate wiring contact portion 170 is a region where the gate wiring 105 and the wiring 112 are electrically connected.

  Note that a dashed-dotted line GH in FIG. 25A indicates the channel length direction of the transistor 151. A one-dot chain line KL indicates the channel width direction of the transistor 151.

  The transistor 151 includes a gate electrode 104 over the substrate 102, an insulating film 108 functioning as a first gate insulating film over the gate electrode 104, and a first oxide at a position overlapping with the gate electrode 104 over the insulating film 108. The semiconductor film 110, the source electrode 112a and the drain electrode 112b over the first oxide semiconductor film 110, and the second gate insulating film over the first oxide semiconductor film 110, the source electrode 112a and the drain electrode 112b And the second oxide semiconductor film 111a at a position overlapping with the first oxide semiconductor film 110 over the insulating film 116. The second oxide semiconductor film 111a functions as a second gate electrode in the transistor 151. That is, the transistor 151 illustrated in FIGS. 25A and 25B has a so-called double gate structure.

  In addition, an insulating film 118 is formed over the transistor 151, more specifically, over the insulating film 116 and the second oxide semiconductor film 111a. The insulating films 114 and 116 function as a second gate insulating film of the transistor 151 and also have a function as a protective insulating film of the transistor 151. The insulating film 118 functions as a protective insulating film of the transistor 151.

  In the gate wiring contact portion 170, the second oxide semiconductor film 111 b is formed over the gate wiring 105 and the wiring 112 so as to cover the opening 144 provided in the insulating film 108 and the opening 146 provided in the insulating films 114 and 116. Is formed.

  In the semiconductor device described in this embodiment, the gate wiring 105 and the wiring 112 are electrically connected to each other through the second oxide semiconductor film 111b in the gate wiring contact portion 170. With such a structure, the opening 144 and the opening 146 can be formed successively, so that the manufacturing process of the semiconductor device can be shortened.

  In addition, in the case where there is no protective film that blocks intrusion of oxygen over the second oxide semiconductor film 111b, the second oxide semiconductor film 111b may be altered and resistance may be increased in a high-temperature and high-humidity environment. In the semiconductor device described in this embodiment, since the second oxide semiconductor film 111b is covered with the insulating film 118, the high temperature and high humidity resistance of the semiconductor device can be improved without forming a new protective film. it can.

  Note that as the insulating film 118, an insulating film containing at least hydrogen is used. As the insulating films 107, 114, and 116, an insulating film containing at least oxygen is used. In this manner, the insulating film used for the transistor 151 and the gate wiring contact portion 170 or the insulating film in contact with the transistor 151 and the gate wiring contact portion 170 is the insulating film having the above structure, whereby the first oxide semiconductor film 110 is formed. In addition, the resistivity of the second oxide semiconductor films 111a and 111b can be controlled.

  Note that the resistivity of the first oxide semiconductor film 110 and the second oxide semiconductor films 111a and 111b can be controlled by referring to the description in Embodiment 7.

  A main difference between the semiconductor device shown in FIGS. 19A and 19B of the seventh embodiment and the semiconductor device shown in FIGS. 25A and 25B is that a gate wiring contact is used instead of the capacitor 161. The transistor 170 is provided, the transistor 151 is provided with the second oxide semiconductor film 111a having the function of the second gate electrode, and the conductive film 120 is not provided.

<Method for Manufacturing Display Device (Modification 1)>
Next, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 25A and 25B will be described with reference to FIGS.

  First, the gate electrode 104 and the gate wiring 105 are formed over the substrate 102. After that, an insulating film 108 including insulating films 106 and 107 is formed over the gate electrode 104 and the gate wiring 105 (see FIG. 26A). The gate wiring 105 can be formed at the same time using a material similar to that of the gate electrode 104.

  Next, the first oxide semiconductor film 110 is formed in a position overlapping with the gate electrode 104 over the insulating film 108 (see FIG. 26B).

  The first oxide semiconductor film 110 is formed by forming an oxide semiconductor film over the insulating film 108, patterning the oxide semiconductor film so that a desired region remains, and then etching unnecessary regions. it can.

  Note that in the etching process of the first oxide semiconductor film 110, part of the insulating film 107 (a region exposed from the first oxide semiconductor film 110) is etched by overetching, so that the film thickness decreases. is there.

  After the first oxide semiconductor film 110 is formed, heat treatment is preferably performed. This heat treatment can be performed in consideration of the heat treatment after the formation of the first oxide semiconductor film 110 in Embodiment 7.

  Next, a conductive film is formed over the insulating film 108 and the first oxide semiconductor film 110, patterned so that a desired region of the conductive film remains, and then an unnecessary region is etched, whereby a source electrode is formed. 112a, a drain electrode 112b, and a wiring 112 are formed (see FIG. 26C). The wiring 112 can be formed at the same time using a material similar to that of the source electrode 112a and the drain electrode 112b.

  Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110a, the source electrode 112a, the drain electrode 112b, and the wiring 112 (see FIG. 26D). After the insulating films 114 and 116 are formed, the first heat treatment described in Embodiment 7 is preferably performed.

  Next, patterning is performed so that desired regions of the insulating films 106, 107, 114, and 116 remain, and then unnecessary regions are etched to form openings 144 and 146 (see FIG. 27A).

  The opening 144 and the opening 146 are formed so that the wiring 112 and the gate wiring 105 are exposed. As a method for forming the opening 144 and the opening 146, for example, a dry etching method can be used. However, the formation method of the opening 144 and the opening 146 is not limited to this, and may be a wet etching method or a formation method in which a dry etching method and a wet etching method are combined.

  Since the opening 144 and the opening 146 can be formed at the same time by etching after patterning once, the manufacturing process can be shortened.

  Next, the second oxide semiconductor film 111a is formed in a position overlapping with the first oxide semiconductor film 110 over the insulating film 116, and at the same time, the second oxide semiconductor film 111a is formed over the insulating film 116 so as to cover the opening 144 and the opening 146. A second oxide semiconductor film 111b is formed (see FIG. 27B). The method for forming the second oxide semiconductor film 111a and the second oxide semiconductor film 111b can refer to the second oxide semiconductor film 111 described in Embodiment 7.

  The second oxide semiconductor films 111a and 111b are formed by forming an oxide semiconductor film over the insulating film 116, patterning the oxide semiconductor film so that a desired region remains, and then etching unnecessary regions. Can be formed.

  Note that at the time of etching the second oxide semiconductor films 111a and 111b, part of the insulating film 116 (region exposed from the second oxide semiconductor films 111a and 111b) is etched by overetching to have a film thickness. May decrease.

  Next, the insulating film 118 is formed over the insulating film 116 and the second oxide semiconductor films 111a and 111b (see FIG. 27C). When hydrogen contained in the insulating film 118 diffuses into the second oxide semiconductor films 111a and 111b, the resistivity of the second oxide semiconductor films 111a and 111b decreases. Note that the hatching of the second oxide semiconductor films 111a and 111b illustrated in FIGS. 27B and 27C is changed as the resistivity of the second oxide semiconductor films 111a and 111b is decreased. ing. Further, after the insulating film 118 is formed, the second heat treatment described in Embodiment 7 may be performed.

  Through the above steps, the transistor 151 and the gate wiring contact portion 170 can be formed over the same substrate.

  As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 9)
In this embodiment, a modified example of the semiconductor device described in Embodiment 7 will be described with reference to FIGS. Note that portions similar to those shown in FIGS. 19 to 24 of Embodiment 7 or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

<Configuration Example of Semiconductor Device (Modification 2)>
FIG. 28A is a top view of the semiconductor device of one embodiment of the present invention, and FIG. 28B illustrates a single-dot chain line MN, a single-dot chain line OP, and a single point in FIG. This corresponds to a cross-sectional view of a cut surface between chain lines Q-R. Note that in FIG. 28A, some components (such as a gate insulating film) of the semiconductor device are not illustrated in order to avoid complexity.

  28A and 28B includes a transistor 151 including a first oxide semiconductor film 110 and a second oxide semiconductor film 111, and a gate wiring contact portion 171. The semiconductor device illustrated in FIGS. Note that the gate wiring contact portion 171 refers to a region where the gate wiring 105 and the wiring 112 are electrically connected.

  Note that a dashed-dotted line MN in FIG. 28A indicates the channel length direction of the transistor 151. An alternate long and short dash line QR indicates a channel width direction of the transistor 151.

  The transistor 151 includes a gate electrode 104 over the substrate 102, an insulating film 108 functioning as a first gate insulating film over the gate electrode 104, and a first oxide at a position overlapping with the gate electrode 104 over the insulating film 108. The semiconductor film 110, the source electrode 112a and the drain electrode 112b over the first oxide semiconductor film 110, and the second gate insulating film over the first oxide semiconductor film 110, the source electrode 112a and the drain electrode 112b And the second oxide semiconductor film 111a at a position overlapping with the first oxide semiconductor film 110 over the insulating film 116. The second oxide semiconductor film 111a functions as a second gate electrode in the transistor 151. That is, the transistor 151 illustrated in FIGS. 28A and 28B has a so-called double gate structure.

  Further, the insulating film 118 and the insulating film 119 are formed over the transistor 151, more specifically, over the insulating film 116 and the second oxide semiconductor film 111a. The insulating films 114 and 116 function as a second gate insulating film of the transistor 151 and also have a function as a protective insulating film of the transistor 151. The insulating film 118 functions as a protective insulating film of the transistor 151. The insulating film 119 functions as a planarization film. In addition, an opening reaching the drain electrode 112b is formed in the insulating films 114, 116, 118, and 119, and a conductive film 120 is formed over the insulating film 119 so as to cover the opening. Among the openings, an opening provided in the insulating films 114 and 116 is an opening 146, and an opening provided in the insulating film 119 is an opening 148. The conductive film 120 functions as, for example, a pixel electrode.

  In the gate wiring contact portion 171, a wiring 112 is formed on the gate wiring 105 so as to cover the opening 144 provided in the insulating film 108.

  In the semiconductor device described in this embodiment, the end portion of the insulating film 118 and the end portion of the insulating film 119 substantially coincide with each other in the opening 148. By manufacturing the semiconductor device so as to have such a structure, the number of masks used for patterning can be reduced, and thus the manufacturing cost can be reduced.

  Note that as the insulating film 118, an insulating film containing at least hydrogen is used. As the insulating films 107, 114, and 116, an insulating film containing at least oxygen is used. In this manner, the insulating film used for the transistor 151 or the insulating film in contact with the transistor 151 is an insulating film having the above structure, whereby the first oxide semiconductor film 110 and the second oxide semiconductor film included in the transistor 151 are used. The resistivity of 111a can be controlled.

  Note that the resistivity of the first oxide semiconductor film 110 and the second oxide semiconductor film 111a can be controlled with reference to the description in Embodiment 7.

  A main difference between the semiconductor device shown in FIGS. 19A and 19B of the seventh embodiment and the semiconductor device shown in FIGS. 28A and 28B is that a gate wiring contact is used instead of the capacitor 161. A portion 171 is provided, a second oxide semiconductor film 111a having a function of a second gate electrode is provided in the transistor 151, and an insulating film 119 is provided.

<Method for Manufacturing Display Device (Modification 2)>
Next, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 28A and 28B will be described with reference to FIGS.

  First, the gate electrode 104 and the gate wiring 105 are formed over the substrate 102. After that, an insulating film 108 including insulating films 106 and 107 is formed over the gate electrode 104 and the gate wiring 105. The gate wiring 105 can be formed at the same time using a material similar to that of the gate electrode 104.

  Next, a first oxide semiconductor film 110 is formed in a position overlapping with the gate electrode 104 over the insulating film 108 (see FIG. 29A).

  The first oxide semiconductor film 110 is formed by forming an oxide semiconductor film over the insulating film 108, patterning the oxide semiconductor film so that a desired region remains, and then etching unnecessary regions. it can.

  Note that when the first oxide semiconductor film 110 is etched, part of the insulating film 108 (a region exposed from the first oxide semiconductor film 110) is etched by overetching, so that the film thickness is reduced. is there.

  After the first oxide semiconductor film 110 is formed, heat treatment is preferably performed. This heat treatment can be performed in consideration of the heat treatment after the formation of the first oxide semiconductor film 110 in Embodiment 7.

  Next, patterning is performed so that a desired region of the insulating films 106 and 107 remains, and then an unnecessary region is etched to form an opening 144 (see FIG. 29B).

  The opening 144 is formed so that the gate wiring 105 is exposed. As a method for forming the opening 144, for example, a dry etching method can be used. However, the formation method of the opening 144 is not limited to this, and may be a wet etching method or a formation method in which a dry etching method and a wet etching method are combined.

  Next, a conductive film is formed over the insulating film 108, the gate wiring 105, and the first oxide semiconductor film 110, patterned so that a desired region of the conductive film remains, and then unnecessary regions are etched. Thus, the source electrode 112a, the drain electrode 112b, and the wiring 112 are formed (see FIG. 17C). The wiring 112 can be formed at the same time using a material similar to that of the source electrode 112a and the drain electrode 112b.

  Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110 a, the source electrode 112 a, the drain electrode 112 b, and the wiring 112. After the insulating films 114 and 116 are formed, the first heat treatment described in Embodiment 7 is preferably performed.

  Next, patterning is performed so that desired regions of the insulating films 114 and 116 remain, and then unnecessary regions are etched to form openings 146 (see FIG. 29D).

  The opening 146 is formed so that the drain electrode 112b is exposed. As a method for forming the opening 146, for example, a dry etching method can be used. However, the method for forming the opening 146 is not limited to this, and a wet etching method or a formation method in which a dry etching method and a wet etching method are combined may be used.

  Next, the second oxide semiconductor film 111a is formed in a position overlapping with the first oxide semiconductor film 110 over the insulating film 116. For the formation method of the second oxide semiconductor film 111a, the second oxide semiconductor film 111 described in Embodiment 7 can be referred to.

  The second oxide semiconductor film 111a is formed by forming an oxide semiconductor film over the insulating film 116, patterning the oxide semiconductor film so that a desired region remains, and then etching unnecessary regions. it can.

  Note that when the second oxide semiconductor film 111a is etched, part of the insulating film 116 (a region exposed from the second oxide semiconductor film 111a) is etched by overetching, so that the film thickness decreases. is there.

  Next, the insulating film 118 is formed over the insulating film 116, the second oxide semiconductor film 111a, and the drain electrode 112b. When hydrogen contained in the insulating film 118 is diffused into the second oxide semiconductor film 111a, the resistivity of the second oxide semiconductor film 111a is decreased.

  Next, an insulating film 119 is formed over the insulating film 118 (see FIG. 30A). As the insulating film 119, for example, a heat-resistant organic material such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. An organic resin film is formed over the insulating film, patterned to leave a desired region, and then an unnecessary region is etched to form an opening at a position overlapping with the opening 146.

  Next, the opening 148 is formed by etching the insulating film 118 using the insulating film 119 having an opening as a mask (see FIG. 30B). Since the insulating film 119 can be used as a mask, a new mask for forming the opening 148 is unnecessary and patterning can be omitted. Therefore, the manufacturing cost of the semiconductor device can be reduced.

  Next, a conductive film is formed over the insulating film 119 so as to cover the opening 148, and patterning and etching are performed so that a desired shape of the conductive film remains, so that the conductive film 120 is formed (FIG. 30C). reference).

  Through the above steps, the transistor 151 and the gate wiring contact portion 171 can be formed over the same substrate.

  As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 10)
In this embodiment, an example of an oxide semiconductor that can be used for a transistor, a capacitor, and a gate wiring contact portion of the semiconductor device of one embodiment of the present invention will be described.

  Hereinafter, the structure of the oxide semiconductor is described.

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

<Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.

  An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor, or c-axis-aligned and a-b-plane anodized semiconductor oxide semiconductor, Examples thereof include a nanocrystalline oxide semiconductor (a-like OS), an amorphous-oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

  From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

  Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

  That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be described.

  A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS including an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even if 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) as illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 31E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 31E is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 31E is considered to be due to the (110) plane and the like.

  In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

  FIG. 32A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

  From FIG. 32A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (c-axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 32B and 32C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. 32D and 32E are images obtained by performing image processing on FIGS. 32B and 32C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

  In FIG. 32D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

  In FIG. 32E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding lattice points around the lattice points near the dotted line. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

  As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as CAA crystal (c-axis-aligned and a-b-plane-anchored crystal).

  The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

  Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

  In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8 × ^{10 11} atoms / cm ^3, preferably 1 × ¹⁰ 11 / cm less than ^3, more preferably less than 1 × ^{10 10} atoms / cm ^3, 1 × ^{10 -9} / cm ³ or An oxide semiconductor having the above carrier density can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

  A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 33B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 33B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

  Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

  FIG. 33D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a fine crystal oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

  Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 34 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 34A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 34B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . 34A and 34B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

  Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

  As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

  First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 35 is an example in which the average size of crystal parts (22 to 30 locations) of each sample was examined. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 35, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image and the like. From FIG. 35, the accumulated irradiation dose of electrons (e ⁻ ) of the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial observation by TEM is 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 35 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

  As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

  In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

  Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

<CAAC-OS Film Formation Method>
An example of a CAAC-OS film formation method is described below.

  FIG. 36 is a schematic diagram of a film formation chamber. The CAAC-OS can be formed by a sputtering method.

  As shown in FIG. 36, the substrate 5220 and the target 5230 are arranged to face each other. There is plasma 5240 between the substrate 5220 and the target 5230. A heating mechanism 5260 is provided below the substrate 5220. Although not shown, the target 5230 is bonded to the backing plate. A plurality of magnets are arranged at positions facing the target 5230 via the backing plate. A sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method.

A distance d (also referred to as a target-substrate distance (T-S distance)) between the substrate 5220 and the target 5230 is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled. Here, by applying a voltage of a certain level or higher to the target 5230, discharge starts and plasma 5240 is confirmed. Note that a high-density plasma region is formed in the vicinity of the target 5230 by a magnetic field. In the high-density plasma region, ions 5201 are generated by ionizing the deposition gas. The ion 5201 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar ⁺ ).

The target 5230 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane. As an example, FIG. 37 illustrates a crystal structure of InMZnO ₄ (the element M is, for example, Al, Ga, Y, or Sn) included in the target 5230. Note that FIG. 37A illustrates a crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. In the InMZnO ₄ crystal, a repulsive force is generated between two adjacent M—Zn—O layers because the oxygen atom has a negative charge. Therefore, the InMZnO ₄ crystal has a cleavage plane between two adjacent M—Zn—O layers.

  The ions 5201 generated in the high-density plasma region are accelerated toward the target 5230 by the electric field and eventually collide with the target 5230. At this time, the pellet 5200, which is flat or pellet-like sputtered particles, peels from the cleavage plane (see FIG. 36). The pellet 5200 is a portion sandwiched between two cleavage planes shown in FIG. Therefore, when only the pellet 5200 is extracted, the cross section becomes as shown in FIG. 37B and the upper surface becomes as shown in FIG. Note that the structure of the pellet 5200 may be distorted by the impact of the collision of the ions 5201.

  The pellet 5200 is a sputtered particle in the form of a flat plate or a pellet having a triangular plane, for example, a regular triangular plane. Alternatively, the pellet 5200 is a flat or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. However, the shape of the pellet 5200 is not limited to a triangle or a hexagon. For example, there are cases where a plurality of triangles are combined. For example, there may be a quadrangle (for example, a rhombus) in which two triangles (for example, regular triangles) are combined.

  The thickness of the pellet 5200 is determined according to the type of deposition gas. For example, the pellet 5200 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5200 has a width of 1 nm to 100 nm, preferably 2 nm to 50 nm, more preferably 3 nm to 30 nm. For example, the ion 5201 is caused to collide with the target 5230 including an In-M-Zn oxide. Then, the pellet 5200 having three layers of an M—Zn—O layer, an In—O layer, and an M—Zn—O layer is peeled off. Note that the particles 5203 are also ejected from the target 5230 as the pellet 5200 is peeled off. A particle 5203 has an aggregate of one atom or several atoms. Therefore, the particles 5203 can also be referred to as atomic particles.

When the pellet 5200 passes through the plasma 5240, the surface may be negatively or positively charged. For example, the pellet 5200 may receive a negative charge from O ^{2− in the} plasma 5240. As a result, oxygen atoms on the surface of the pellet 5200 may be negatively charged. In addition, the pellet 5200 may grow by being combined with indium, the element M, zinc, oxygen, or the like in the plasma 5240 when passing through the plasma 5240.

  The pellets 5200 and the particles 5203 that have passed through the plasma 5240 reach the surface of the substrate 5220. Note that part of the particles 5203 has a small mass and may be discharged to the outside by a vacuum pump or the like.

  Next, deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 will be described with reference to FIG.

  First, the first pellet 5200 is deposited on the substrate 5220. Since the pellet 5200 is plate-shaped, the pellet 5200 is deposited with the plane side facing the surface of the substrate 5220. At this time, the charge on the surface of the pellet 5200 on the substrate 5220 side is released through the substrate 5220.

  Next, the second pellet 5200 reaches the substrate 5220. At this time, since the surface of the pellet 5200 already deposited and the surface of the second pellet 5200 are charged, forces that repel each other are generated. As a result, the second pellet 5200 is deposited with the plane side facing slightly away from the surface of the substrate 5220, avoiding the pellet 5200 that has already been deposited. By repeating this, innumerable pellets 5200 are deposited on the surface of the substrate 5220 by a thickness corresponding to one layer. In addition, a region where the pellet 5200 is not deposited is generated between the pellets 5200 (see FIG. 38A).

  Next, the particles 5203 receiving energy from the plasma reach the surface of the substrate 5220. The particles 5203 cannot be deposited on an active region such as the surface of the pellet 5200. Therefore, the particle 5203 moves to a region where the pellet 5200 is not deposited and adheres to the side surface of the pellet 5200. The bond 520 is activated by energy received from plasma, so that the particle 5203 is chemically connected to the pellet 5200 to form a lateral growth portion 5202 (see FIG. 38B).

  Further, the horizontal growth portion 5202 grows in the horizontal direction (also referred to as lateral growth), thereby connecting the pellets 5200 (see FIG. 38C). In this manner, the lateral growth portion 5202 is formed until a region where the pellet 5200 is not deposited is filled. This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.

  Therefore, even when the pellets 5200 are deposited in different directions, since the particles 5203 fill the space between the pellets 5200 while laterally growing, no clear crystal grain boundary is formed. Further, since the particles 5203 are smoothly connected between the pellets 5200, a crystal structure different from single crystal and polycrystal is formed. In other words, a crystal structure having strain is formed between minute crystal regions (pellets 5200). As described above, since the region between the crystal regions is a distorted crystal region, it is considered inappropriate to refer to the region as an amorphous structure.

  Next, a new pellet 5200 is deposited with the plane side facing the surface (see FIG. 38D). Then, the horizontal growth portion 5202 is formed by depositing the particles 5203 so as to fill a region where the pellet 5200 is not deposited (see FIG. 38E). Thus, the particles 5203 are attached to the side surfaces of the pellet 5200 and the lateral growth portion 5202 is laterally grown, thereby connecting the pellets 5200 in the second layer (see FIG. 38F). Film formation continues until the m-th layer (m is an integer of 2 or more) is formed, resulting in a thin film structure having a laminate.

  Note that the manner in which the pellets 5200 are deposited also varies depending on the surface temperature of the substrate 5220 and the like. For example, when the surface temperature of the substrate 5220 is high, the pellet 5200 undergoes migration on the surface of the substrate 5220. As a result, the proportion of the pellets 5200 that are connected without the particle 5203 interposed therebetween increases, so that a CAAC-OS with higher orientation is obtained. The surface temperature of the substrate 5220 when the CAAC-OS is formed is from room temperature to less than 340 ° C., preferably from room temperature to 300 ° C., more preferably from 100 ° C. to 250 ° C., and still more preferably from 100 ° C. to 200 ° C. is there. Therefore, even when a large-area substrate of the eighth generation or higher is used as the substrate 5220, warping due to the formation of the CAAC-OS film hardly occurs.

  On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 is less likely to cause migration on the surface of the substrate 5220. As a result, the pellets 5200 are stacked to form an nc-OS with low orientation. In the nc-OS, since the pellet 5200 is negatively charged, the pellet 5200 may be deposited at a constant interval. Therefore, although the orientation is low, a slight regularity results in a dense structure as compared with an amorphous oxide semiconductor.

  In CAAC-OS, one large pellet may be formed when the gap between pellets is extremely small. The inside of one large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm when viewed from above.

  It is considered that the pellets are deposited on the surface of the substrate by the film formation model as described above. Since the CAAC-OS film can be formed even when the formation surface does not have a crystal structure, it can be seen that the above-described film formation model, which is a growth mechanism different from epitaxial growth, has high validity. Further, since the above-described film formation model is used, it can be seen that the CAAC-OS and the nc-OS can form a uniform film even on a large-area glass substrate or the like. For example, the CAAC-OS can be formed even when the surface (formation surface) of the substrate has an amorphous structure (eg, amorphous silicon oxide).

  Further, it can be seen that even when the surface of the substrate, which is the formation surface, is uneven, the pellets are arranged along the shape.

  Further, from the above-described film formation model, it can be seen that the following may be performed in order to form a highly crystalline CAAC-OS. First, in order to lengthen the mean free path, the film is formed in a higher vacuum state. Next, in order to reduce damage in the vicinity of the substrate, the plasma energy is weakened. Next, thermal energy is applied to the surface to be formed, and the plasma damage is cured each time the film is formed.

  In addition, the above-described deposition model has a polycrystalline structure of a complex oxide such as an In-M-Zn oxide in which the target has a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane. It is not limited to the case. For example, the present invention can be applied to a case where a target of a mixture including indium oxide, an oxide of element M, and zinc oxide is used.

  Since the target of the mixture does not have a cleavage plane, the atomic particles are peeled off from the target when sputtered. At the time of film formation, a strong electric field region of plasma is formed in the vicinity of the target. Therefore, the atomic particles separated from the target are connected and grown laterally by the action of the strong electric field region of the plasma. For example, first, indium as atomic particles are connected and laterally grown to form a nanocrystal composed of an In—O layer. Next, M-Zn-O layers are bonded to each other so as to complement the above. Thus, pellets may be formed even when a mixture target is used. Therefore, even when a mixture target is used, the above-described film formation model can be applied.

However, when a strong electric field region of plasma is not formed in the vicinity of the target, only atomic particles separated from the target are deposited on the substrate surface. In such a case as well, atomic particles may laterally grow on the substrate surface. However, since the orientation of the atomic particles is not uniform, the crystal orientation in the obtained thin film is not uniform. That is, the nc-OS or the like.
(Embodiment 11)
In this embodiment, the structure of a transistor having a structure different from that of the transistor described in Embodiment 7 will be described with reference to FIGS.

<Configuration Example 1 of Transistor>
FIG. 39A is a top view of the transistor 270, and FIG. 39B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 39A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG. Note that the direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction.

  The transistor 270 includes a conductive film 204 functioning as a first gate electrode over the substrate 202, an insulating film 206 over the substrate 202 and the conductive film 204, an insulating film 207 over the insulating film 206, and an oxide over the insulating film 207. A conductive semiconductor film 208; a conductive film 212a functioning as a source electrode electrically connected to the oxide semiconductor film 208; a conductive film 212b functioning as a drain electrode electrically connected to the oxide semiconductor film 208; The oxide semiconductor film 208, the insulating films 214 and 216 over the conductive film 212a and the conductive film 212b, and the oxide semiconductor film 211b over the insulating film 216 are included. An insulating film 218 is provided over the oxide semiconductor film 211b.

  In the transistor 270, the insulating film 214 and the insulating film 216 function as a second gate insulating film of the transistor 270. The oxide semiconductor film 211a is connected to the conductive film 212b through an opening 252c provided in the insulating film 214 and the insulating film 216. For example, the oxide semiconductor film 211a functions as a pixel electrode used in a display device. In the transistor 270, the oxide semiconductor film 211b functions as a second gate electrode (also referred to as a back gate electrode).

  As shown in FIG. 39C, the oxide semiconductor film 211b includes a conductive film functioning as a first gate electrode in the openings 252a and 252b provided in the insulating films 206 and 207, the insulating film 214, and the insulating film 216. 204. Therefore, the same potential is applied to the conductive film 220b and the oxide semiconductor film 211b.

  Note that although the structure in which the openings 252a and 252b are provided and the oxide semiconductor film 211b and the conductive film 204 are connected is described in this embodiment, the present invention is not limited to this. For example, a structure in which only one of the opening 252a and the opening 252b is formed and the oxide semiconductor film 211b and the conductive film 204 are connected, or the oxide semiconductor film 211b and the conductive film 204 are not provided without being provided with the opening 252a and the opening 252b. The film 204 may not be connected. Note that in the case where the oxide semiconductor film 211b and the conductive film 204 are not connected to each other, different potentials can be applied to the oxide semiconductor film 211b and the conductive film 204, respectively.

  As shown in FIG. 39B, the oxide semiconductor film 208 faces the conductive film 204 functioning as the first gate electrode and the oxide semiconductor film 211b functioning as the second gate electrode. And is sandwiched between conductive films functioning as two gate electrodes. The length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 211b functioning as the second gate electrode are larger than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 208, respectively. The entire oxide semiconductor film 208 is covered with the oxide semiconductor film 211b with the insulating film 214 and the insulating film 216 interposed therebetween. The oxide semiconductor film 211b functioning as the second gate electrode and the conductive film 204 functioning as the first gate electrode include openings 252a and 252b provided in the insulating films 206 and 207, the insulating film 214, and the insulating film 216, respectively. Therefore, the side surface in the channel width direction of the oxide semiconductor film 208 faces the oxide semiconductor film 211b functioning as the second gate electrode with the insulating film 214 and the insulating film 216 interposed therebetween.

  In other words, the conductive film 204 functioning as the first gate electrode and the oxide semiconductor film 211b functioning as the second gate electrode in the channel width direction of the transistor 270 are insulating films 206 and 207 functioning as gate insulating films. In addition, the insulating films 214 and 207 functioning as gate insulating films and the insulating films 214 functioning as the second gate insulating films are connected in the openings provided in the insulating films 214 and 216 functioning as the second gate insulating films. In addition, the oxide semiconductor film 208 is surrounded with the insulating film 216 interposed therebetween.

  With such a structure, the oxide semiconductor film 208 included in the transistor 270 is electrically converted by the electric field of the conductive film 204 functioning as the first gate electrode and the oxide semiconductor film 211b functioning as the second gate electrode. Can be enclosed. As in the transistor 270, a device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (s-channel) structure. Can be called.

  Since the transistor 270 has an s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 208 by the conductive film 204 functioning as the first gate electrode. Current driving capability is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 270 can be miniaturized. In addition, since the transistor 270 has a structure surrounded by the conductive film 204 functioning as the first gate electrode and the oxide semiconductor film 211b functioning as the second gate electrode, the mechanical strength of the transistor 270 can be increased. it can.

<Configuration Example 2 of Transistor>
Next, a structural example different from the transistor 270 illustrated in FIGS. 39A, 39B, and 39C is described with reference to FIGS. 40A, 40B, 40C, and 40D.

  40A and 40B are cross-sectional views of modifications of the transistor 270 illustrated in FIGS. 40B and 40C. 40C and 40D are cross-sectional views of modifications of the transistor 270 illustrated in FIGS. 27B and 27C.

  A transistor 270A illustrated in FIGS. 40A and 40B has a three-layer structure of the oxide semiconductor film 208 included in the transistor 270 illustrated in FIGS. More specifically, the oxide semiconductor film 208 included in the transistor 270A includes an oxide semiconductor film 208a, an oxide semiconductor film 208b, and an oxide semiconductor film 208c.

  A transistor 270B illustrated in FIGS. 40C and 40D has a two-layer structure of the oxide semiconductor film 208 included in the transistor 270 illustrated in FIGS. More specifically, the oxide semiconductor film 208 included in the transistor 270B includes an oxide semiconductor film 208b and an oxide semiconductor film 208c.

  For the structures of the transistors 270, 270A, and 270B described in this embodiment, the structure of the semiconductor device described in Embodiment 7 can be referred to. That is, the substrate 102 can be referred to for the material and manufacturing method of the substrate 202. For the material and the manufacturing method of the conductive film 204, the gate electrode 104 can be referred to. For the material and the manufacturing method of the insulating film 206 and the insulating film 207, the insulating film 106 and the insulating film 107 can be referred to, respectively. For the material and the manufacturing method of the oxide semiconductor film 208, the first oxide semiconductor film 110 can be referred to. The second oxide semiconductor film 111 can be referred to for materials and manufacturing methods of the oxide semiconductor film 211a and the oxide semiconductor film 211b. For the materials and manufacturing methods of the conductive films 21a and 21b, the source electrode 112a and the drain electrode 112b can be referred to, respectively. For the materials and manufacturing methods of the insulating film 214, the insulating film 216, and the insulating film 218, the insulating film 114, the insulating film 116, and the insulating film 118 can be referred to, respectively.

  Here, the band structure of the oxide semiconductor films 208a, 208b, and 208c and the insulating film in contact with the oxide semiconductor films 208b and 208c will be described with reference to FIGS.

  FIG. 41A illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 207, the oxide semiconductor films 208a, 208b, and 208c, and the insulating film 214. FIG. 41B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 207, the oxide semiconductor films 208b and 208c, and the insulating film 214. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 207, the oxide semiconductor films 208a, 208b, and 208c, and the insulating film 214 for easy understanding.

  In FIG. 41A, a silicon oxide film is used as the insulating films 207 and 214, and a metal oxide atomic ratio of In: Ga: Zn = 1: 1: 1.2 is used as the oxide semiconductor film 208a. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 208b is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. The oxide semiconductor film is formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 1: 1.2 as the oxide semiconductor film 208c. FIG.

  In FIG. 41B, a silicon oxide film is used as the insulating films 207 and 214, and an atomic ratio of metal elements is set to In: Ga: Zn = 4: 2: 4.1 as the oxide semiconductor film 208b. An oxide semiconductor film formed using an object target is used, and a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 1: 1.2 is formed as the oxide semiconductor film 208c. It is a band figure of the structure using the oxide semiconductor film made.

  As shown in FIGS. 41A and 41B, in the oxide semiconductor films 208a, 208b, and 208c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, trap centers and recombination centers can be formed at the interface between the oxide semiconductor film 208a and the oxide semiconductor film 208b or at the interface between the oxide semiconductor film 208b and the oxide semiconductor film 208c. It is assumed that there is no impurity that forms such a defect level.

  In order to form a continuous junction with the oxide semiconductor films 208a, 208b, and 208c, a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber is used so that each film is continuously exposed to the atmosphere. It is necessary to laminate them.

  41A and 41B, the oxide semiconductor film 208b becomes a well, and a channel region is formed in the oxide semiconductor film 208b in the transistor using the above stacked structure. Recognize.

  Note that by providing the oxide semiconductor films 208a and 208c, trap levels that can be formed in the oxide semiconductor film 208b can be separated from the oxide semiconductor film 208b.

  In addition, the trap level is farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 208b functioning as the channel region, and electrons may easily accumulate in the trap level. . Accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, a structure in which the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 208b is preferable. By doing so, electrons are unlikely to accumulate in the trap level, the on-state current of the transistor can be increased, and field effect mobility can be increased.

  In addition, the oxide semiconductor films 208a and 208c have a lower energy level at the bottom of the conduction band than the oxide semiconductor film 208b, and typically the energy level at the bottom of the conduction band of the oxide semiconductor film 208b. And the energy level at the lower end of the conduction band of the oxide semiconductor films 208a and 208c is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 208a and 208c and the electron affinity of the oxide semiconductor film 208b is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less.

  With such a structure, the oxide semiconductor film 208b serves as a main current path. That is, the oxide semiconductor film 208b functions as a channel region, and the oxide semiconductor films 208a and 208c function as an oxide insulating film. The oxide semiconductor films 208a and 208c are oxide semiconductor films formed of one or more metal elements included in the oxide semiconductor film 208b in which a channel region is formed; Interface scattering hardly occurs at the interface with the semiconductor film 208b or at the interface between the oxide semiconductor film 208b and the oxide semiconductor film 208c. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

  The oxide semiconductor films 208a and 208c are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 208a and 208c from functioning as part of the channel region. Therefore, the oxide semiconductor films 208a and 208c can also be referred to as oxide insulating films because of their physical properties and / or functions. The oxide semiconductor films 208a and 208c each have an electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) smaller than that of the oxide semiconductor film 208b, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the energy level at the lower end of the conduction band of the semiconductor film 208b is used. In order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 208a and 208c is reduced by the conduction of the oxide semiconductor film 208b. It is preferable to apply a material closer to the vacuum level by 0.2 eV than the energy level at the lower end of the band, preferably a material closer to the vacuum level by 0.5 eV or more.

  The oxide semiconductor films 208a and 208c preferably do not include a spinel crystal structure. In the case where the oxide semiconductor films 208a and 208c include a spinel crystal structure, the constituent elements of the conductive films 212a and 212b enter the oxide semiconductor film 208b at the interface between the spinel crystal structure and another region. May diffuse. Note that it is preferable that the oxide semiconductor films 208a and 208c be a CAAC-OS because a blocking property of a constituent element of the conductive films 212a and 212b, for example, a copper element is increased.

  The thickness of the oxide semiconductor films 208a and 208c is greater than or equal to a thickness that can prevent the constituent elements of the conductive films 212a and 212b from diffusing into the oxide semiconductor film 208b. The thickness is less than the thickness at which the supply of oxygen to the film 208b is suppressed. For example, when the thickness of the oxide semiconductor films 208a and 208c is 10 nm or more, the constituent elements of the conductive films 212a and 212b can be prevented from diffusing into the oxide semiconductor film 208b. In addition, when the thickness of the oxide semiconductor films 208a and 208c is 100 nm or less, oxygen can be effectively supplied from the insulating film 214 to the oxide semiconductor film 208b.

  In this embodiment, the oxide semiconductor films 208a and 208c are oxidized using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 1: 1.2. Although the structure using a physical semiconductor film has been illustrated, it is not limited to this. For example, as the oxide semiconductor films 208a and 208c, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 3: 2 [atomic ratio], In: Ga: Zn Alternatively, an oxide semiconductor film formed using a metal oxide target of 1: 3: 4 [atomic ratio] or In: Ga: Zn = 1: 3: 6 [atomic ratio] may be used.

  Note that in the case where a metal oxide target of In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 208a and 208c, the oxide semiconductor films 208a and 208c are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 3) in some cases. In the case where a metal oxide target of In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 208a and 208c, the oxide semiconductor films 208a and 208c are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target of In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 208a and 208c, the oxide semiconductor films 208a and 208c are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.

  In addition, in the drawing, the oxide semiconductor film 208 included in the transistor 270 and the oxide semiconductor film 208c included in the transistors 270A and 270B are thinner in a region that does not overlap with the conductive films 212a and 212b. Then, a shape in which part of the oxide semiconductor film has a recess is illustrated. Note that one embodiment of the present invention is not limited to this, and the oxide semiconductor film in a region which does not overlap with the conductive films 212a and 212b may not have a depression. An example of this case is shown in FIGS. 42A and 42B are cross-sectional views illustrating an example of a transistor. 42A and 42B illustrate a structure in which the oxide semiconductor film 208 of the transistor 270B described above does not have a depression.

  In the transistor according to this embodiment, each of the above structures can be freely combined.

  The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 12)
In this embodiment, an example of a display device including the transistor illustrated in the above embodiment will be described below with reference to FIGS.

<Overview>
FIG. 43 is a top view illustrating an example of the display device. A display device 700 illustrated in FIG. 43 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, The sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 43, a display element is provided between the first substrate 701 and the second substrate 705.

  In addition, the display device 700 is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC terminal portion 708 (FPC: Flexible Printed Circuit) to be connected is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A wiring 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the wiring 710.

  In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. . Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702 included in the display device 700 includes a plurality of transistors and a capacitor, and the semiconductor device described in Embodiment 7 can be used. The source driver circuit portion 704 and the gate driver circuit portion 706 each include a plurality of transistors and a wiring contact portion, and the semiconductor device described in Embodiment 8 can be used.

<Available light control member>
In addition, the display device 700 can have various modes or have various display elements. Display elements include, for example, liquid crystal elements, EL (electroluminescence) elements including LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) (EL elements including organic substances and inorganic substances, organic EL elements, inorganic EL elements). , Transistors (transistors that emit light in response to current), electron-emitting devices, electrophoretic devices, grating light valves (GLV), digital micromirror devices (DMD), DMS (digital micro shutter) devices, MIRASOL (registered trademark) Examples thereof include a display, an IMOD (interference modulation) element, a display element using a micro electro mechanical system (MEMS) such as a piezoelectric ceramic display, and an electrowetting element. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action may be included. Further, quantum dots may be used as the display element. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. An example of a display device using quantum dots is a quantum dot display. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

<Display method>
Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

<When using a light source>
In addition, a colored film (also referred to as a color filter) may be used to display a full color display device using white light (W) in a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. As the colored film, for example, red (R), green (G), blue (B), yellow (Y), or the like can be used in appropriate combination. By using the colored film, the color reproducibility can be increased as compared with the case where the colored film is not used. At this time, by arranging a region having a colored film and a region having no colored film, white light in the region having no colored film may be directly used for display. By arranging a region that does not have a colored film in part, in a bright display, a decrease in luminance due to the colored film can be reduced, and power consumption can be reduced by about 20% to 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having respective emission colors. . By using a self-luminous element, power consumption may be further reduced than when a colored film is used.

<Configuration>
In this embodiment mode, a structure of a display device using a liquid crystal element as a display element will be described with reference to FIG.

  44 is a cross sectional view taken along one-dot chain line U-V shown in FIG. A display device 700 illustrated in FIG. 44 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. In addition, the lead wiring portion 711 includes a wiring 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

  For example, the transistor 150 described in Embodiment 7 can be used as the transistor 750. As the transistor 752, the transistor 151 described in Embodiment 8 can be used.

  The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can reduce a current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

  As the capacitor 790, the capacitor 160 described in Embodiment 7 can be used. Since the capacitor 790 has a light-transmitting property, the capacitor 790 can be formed large (in a large area) in one pixel included in the pixel portion 702. Thus, a display device with an increased capacitance value while increasing an aperture ratio can be obtained.

  In FIG. 44, insulating films 764, 766, and 768 are provided over the transistor 750.

  The insulating films 764, 766, and 768 can be formed using a material and a manufacturing method similar to those of the insulating films 114, 116, and 118 described in Embodiment 7, respectively. Further, a planarization film may be provided over the insulating film 768. The planarization film can be formed using a material and a manufacturing method similar to those of the insulating film 119 described in Embodiment 9.

  The wiring 710 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. Note that the wiring 710 may be a conductive film formed in a step different from the source and drain electrodes of the transistors 750 and 752, for example, a conductive film functioning as a gate electrode. For example, when a material containing a copper element is used as the wiring 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

  The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

  In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. The first substrate 701 and the second substrate 705 can be formed using a material similar to that of the substrate 102 described in Embodiment 7.

  On the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.

  A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

  In this embodiment mode, the structure body 778 is provided on the first substrate 701 side; however, the present invention is not limited to this. For example, a structure in which the structure body 778 is provided on the second substrate 705 side or a structure in which the structure body 778 is provided on both the first substrate 701 and the second substrate 705 may be employed.

  The display device 700 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 according to voltages applied to the conductive films 772 and 774.

  The conductive film 772 is connected to a conductive film functioning as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the insulating film 768 and functions as a pixel electrode, that is, one electrode of the display element. The display device 700 is a so-called transmissive color liquid crystal display device in which a backlight, a sidelight, or the like is provided on the substrate 701 side and displays through a liquid crystal element 775 and a colored film 736.

  As the conductive films 772 and 774, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. The conductive film 772 and the conductive film 774 can be formed using a material similar to that of the conductive film 120 described in Embodiment 7.

  Note that the display device 700 illustrated in FIGS. 43 and 44 may be a transmissive color liquid crystal display device by using a conductive film that is transmissive to visible light as the conductive film 772, for example. Further, it may be a transflective color display in which a reflective film and a transmissive film are combined, and is not limited thereto.

  Although not shown in FIG. 44, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, a circularly polarizing plate obtained by combining a polarizing plate and a retardation plate may be used.

<External protective film>
Further, a protective film 717 may be formed outside the display device 700 as shown in FIG. As a method for forming the protective film 717, for example, it is desirable to form the protective film 717 by an atomic layer deposition method (hereinafter referred to as “ALD method”).

  The ALD method can form a film extremely uniformly on the film formation surface. By using the ALD method, for example, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide (ITO), tantalum oxide, silicon oxide, manganese oxide, nickel oxide, oxidation Erbium, cobalt oxide, tellurium oxide, barium titanate, titanium nitride, tantalum nitride, tantalum nitride, aluminum nitride, tungsten nitride, cobalt nitride, manganese nitride, hafnium nitride, or the like can be formed as a protective film. Further, the protective film is not limited to the insulating film, and a conductive film may be formed. For example, ruthenium, platinum, nickel, cobalt, manganese, copper, or the like can be formed.

  In addition, it is desirable to mask the portions that are electrically connected such as the FPC terminal portion 708 so as not to form a film. As a masking method, an organic film, an inorganic film, a metal, or the like can be used. For example, silicon oxide, silicon oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride oxide insulating film, silicon nitride, aluminum nitride nitride insulating film, photoresist, etc. Organic materials such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, and epoxy resin can be used. When these films are used as a mask, the protective film can be removed after the film formation.

  In addition, a region formed by the ALD method can be masked with a metal mask. The metal mask is a metal element selected from iron, chromium, nickel, cobalt, cobalt, tungsten, molybdenum, aluminum, copper, tantalum, titanium, or an alloy containing the above metal element as a component, or the above metal element. It can be formed using an alloy or the like in combination. The metal mask may be brought close to or in contact with the display panel.

  A film formed by the ALD method is extremely uniform, and a dense film can be formed. By forming the protective film 717 formed by the ALD method on the side surface portion of the display panel, intrusion of external components such as moisture can be suppressed. As a result, variation in transistor characteristics can be suppressed, and the operation of the peripheral circuit can be stabilized. Further, the frame can be narrowed, the pixel region can be enlarged, and the display device can be made high definition.

  As a liquid crystal used for the liquid crystal layer 776, the liquid crystal used for the liquid crystal element 51 described in Embodiment 1 can be referred to.

  As a driving method of a display device having a liquid crystal element, any of the various driving methods described in Embodiments 4 to 6 can be applied.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 13)
<Top gate>
In this embodiment, another structure example of a display device which can be used as the transmissive display device exemplified in the above embodiment is described.

  FIG. 46A is a schematic top view of the display device 300. FIG. 46B is a schematic cross-sectional view taken along the cutting line A1-A2 in FIG. 46A, between A3-A4, and between A5-A6. Note that in FIG. 46A, some components are not illustrated for clarity.

  The display device 300 includes a display portion 302, a signal line driver circuit 303, a scanning line driver circuit 304, and an external connection terminal 305 on the upper surface of the substrate 301.

  The display unit 302 includes a liquid crystal element 314. In the liquid crystal element 314, the alignment of liquid crystal is controlled by an electric field generated in a direction transverse to the substrate surface.

  The display device 300 includes an insulating layer 332, an insulating layer 334, an insulating layer 338, an insulating layer 341, an insulating layer 342, a transistor 311, a transistor 312, a liquid crystal element 314, an electrode 343, an electrode 352, an electrode 360, a liquid crystal layer 353, and a color filter. 327, a light shielding layer 328, and the like.

  Each pixel has a storage capacitor including at least one switching transistor 312, an electrode 343, and an electrode 360. An electrode 343 that is electrically connected to one of a source electrode and a drain electrode of the transistor 312 is provided.

  An electrode 352 is provided on the color filter 327.

  A reflective conductive material is used for the electrode 343. A part of the light-transmitting conductive material may be used.

  A light-transmitting conductive material is used for at least one of the electrode 343 and the second electrode 352. It is preferable to use a light-transmitting conductive material for both of these electrodes because the aperture ratio of the pixel can be increased.

  The color filter 327 is provided so as to overlap with the first electrode 343 and the second electrode 352. The light shielding layer 328 is provided so as to cover the side surface of the color filter 327. FIG. 46B illustrates a structure in which the color filter 327 is provided over the substrate 321, but the arrangement of the color filter is not limited to this position.

  A liquid crystal layer 353 is provided between the substrate 301 and the substrate 321. By applying a voltage between the electrode 343 and the electrode 352, an electric field is generated, and the alignment of the liquid crystal layer 353 is controlled by the electric field, and an image can be displayed by controlling the polarization of light in units of pixels. . If the electrode 343 is a reflective electrode, an image can be displayed by controlling the amount of light reflected from the outside.

  An alignment film for controlling the alignment of the liquid crystal layer 353 is preferably provided on a surface in contact with the liquid crystal layer 353. A light-transmitting material is used for the alignment film. Although not shown here, a polarizing plate is provided on the outer surface of the substrate 321 and the substrate 301 when viewed from the liquid crystal element 314.

  As the liquid crystal layer 353, a thermotropic liquid crystal, a low molecular liquid crystal, a high molecular liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. In addition, it is preferable to use a liquid crystal exhibiting a blue phase because an alignment film is unnecessary and a wide viewing angle can be obtained.

  Note that a material with high viscosity and low fluidity is preferably used for the liquid crystal layer 353.

  In this configuration example, the configuration of the liquid crystal element includes a TN (Twisted Nematic) mode, an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell Copied) mode. Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, etc. can be used.

  Transistors (the transistor 311, the transistor 312, and the like) provided in the display device 300 are top-gate transistors. Each transistor includes a semiconductor layer 335, an insulating layer 334 functioning as a gate insulating layer, and a gate electrode 333. In addition, an insulating layer 338 and an insulating layer 339 which cover the gate electrode 333 are stacked, and the semiconductor layer 335 includes a pair of electrodes 336 through openings provided in the insulating layer 334, the insulating layer 338, and the insulating layer 339.

  Here, an oxide semiconductor is preferably used for the semiconductor layer 335. As the oxide semiconductor, for example, the oxide semiconductor exemplified in the above embodiment can be used.

  The semiconductor layer 335 may include a source region or a region functioning as a drain region whose resistance is lower than that of a region functioning as a channel. For example, the source region and the drain region can be provided in a portion in contact with the pair of electrodes 336 or can be provided with a region functioning as a channel interposed therebetween. For example, a region whose resistivity is controlled by the method exemplified in the above embodiment may be used.

  By using an oxide semiconductor for the semiconductor layer 335, a transistor with less variation at a lower temperature than that of, for example, polycrystalline silicon can be manufactured with a large area.

  Alternatively, an oxide semiconductor may be used for the electrode 360.

  Note that in one embodiment of the present invention, an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

  In the active matrix system, not only transistors but also various active elements (active elements and nonlinear elements) can be used as active elements (active elements and nonlinear elements). For example, MIM (Metal Insulator Metal) or TFD (Thin Film Diode) can be used. Since these elements have few manufacturing steps, manufacturing cost can be reduced or yield can be improved. Alternatively, since these elements have small element sizes, the aperture ratio can be improved, and power consumption and luminance can be increased.

  As a method other than the active matrix method, a passive matrix type that does not use an active element (an active element or a non-linear element) can be used. Since no active element (active element or non-linear element) is used, the number of manufacturing steps is small, so that manufacturing costs can be reduced or yield can be improved. Alternatively, since an active element (an active element or a non-linear element) is not used, an aperture ratio can be improved, power consumption can be reduced, or luminance can be increased.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(Embodiment 14)
In this embodiment, a display device of one embodiment of the present invention and a method for driving the display device will be described with reference to FIGS.

  Note that the display device of one embodiment of the present invention may include an information processing portion, a calculation portion, a storage portion, a display portion, an input portion, and the like.

  In the display device of one embodiment of the present invention, in the case where the same image (still image) is continuously displayed, power consumption can be reduced by reducing the number of times the signal of the same image is written (also referred to as refreshing). Can be planned. Note that the frequency of refreshing is referred to as a refresh rate (also referred to as a scanning frequency or a vertical synchronization frequency). In the following, a display device with reduced refresh rate and less eye fatigue will be described.

  There are two types of eye fatigue: nervous system fatigue and muscular fatigue. The fatigue of the nervous system is that the brightness of the display device keeps on watching the light emission and blinking screen for a long time, and the brightness stimulates the eye's retina, nerves, and brain to cause fatigue. The fatigue of the muscular system is caused by overworking the ciliary muscle used for focus adjustment.

  FIG. 47A is a schematic diagram showing display on a conventional display device. As shown in FIG. 47A, the conventional display device rewrites an image 60 times per second. Continuing to watch such a screen for a long time may cause eye fatigue by stimulating the retina, nerves, and brain of the user's eyes.

  In the display device of one embodiment of the present invention, a transistor including an oxide semiconductor, for example, a transistor using CAAC-OS is applied to a pixel portion of the display device. The off-state current of the transistor is extremely small. Therefore, the luminance of the display device can be maintained even when the refresh rate of the display device is lowered.

  That is, as shown in FIG. 47B, for example, since the image can be rewritten once every 5 seconds, it is possible to view the same image for a long time as much as possible, and the screen flickers visible to the user Is reduced. This reduces irritation of the retina, nerves, and brain of the user's eyes and reduces nervous system fatigue.

  As shown in FIG. 48A, when the size of one pixel is large (for example, when the definition is less than 150 ppi), characters displayed on the display device are blurred. If you keep looking at the blurred characters displayed on the display device for a long time, the ciliary muscles will continue to focus, but it will be difficult to focus. There is a risk of burden.

  On the other hand, as shown in FIG. 48B, the display device according to one embodiment of the present invention has a small pixel size and high-definition display; it can. This makes it easier for the ciliary muscles to focus, thus reducing fatigue of the user's muscular system. By setting the resolution of the display device to 150 ppi or more, preferably 200 ppi or more, and more preferably 300 ppi or more, fatigue of the user's muscular system can be effectively reduced.

  A method for quantitatively measuring eye fatigue has been studied. For example, critical fusion frequency (CFF: Critical Flicker (Fusion) Frequency) is known as an evaluation index of fatigue of the nervous system. Further, as an evaluation index of muscular fatigue, adjustment time, adjustment near point distance, and the like are known.

  Other methods for evaluating eye fatigue include electroencephalography, thermography, measurement of the number of blinks, evaluation of tear volume, evaluation of the contraction response rate of the pupil, and a questionnaire for investigating subjective symptoms.

  For example, the driving method of the display device of one embodiment of the present invention can be evaluated by the above various methods.

<Driving method of display device>
Here, a method for driving the display device of one embodiment of the present invention is described with reference to FIGS.

[Display example of image information]
Hereinafter, an example in which an image including two different image information is moved and displayed will be described.

  FIG. 49A illustrates an example in which a window 451 and a first image 452a that is a still image displayed in the window 451 are displayed on the display portion 450.

At this time, it is preferable to display at the first refresh rate. The first refresh rate is 1.16 × 10 ⁻⁵ Hz (frequency about once a day) or more and 1 Hz or less, or 2.78 × 10 ⁻⁴ Hz (frequency about once per hour). ) 0.5 Hz or less, or 1.67 × 10 ⁻² Hz (frequency about once per minute) or more and 0.1 Hz or less.

  In this way, by setting the first refresh rate to an extremely small value and reducing the frequency of screen rewriting, it is possible to realize a display that does not substantially cause flickering, and more effectively, the user's eye fatigue. Can be reduced.

  The window 451 is displayed by executing image display application software, for example, and includes a display area for displaying an image.

  In addition, a button 453 for switching the display to different image information is provided at the bottom of the window 451. When the user performs an operation of selecting the button 453, a command for moving the image can be given to the information processing unit of the display device.

  In addition, what is necessary is just to set a user's operation method according to an input means. For example, when a touch panel provided over the display unit 450 is used as an input unit, the touch panel 453 can be operated by touching the button 453 with a finger, a stylus, or the like, or by performing gesture input such as sliding an image. . When gesture input or voice input is used, the button 453 is not necessarily displayed.

  When the information processing unit of the display device receives a command to move the image, the movement of the image displayed in the window 451 is started (FIG. 49B).

  Note that in the case where display is performed at the first refresh rate at the time of FIG. 49A, it is preferable to change the refresh rate to the second refresh rate before moving the image. The second refresh rate is a value necessary for displaying a moving image. For example, the second refresh rate can be 30 Hz to 960 Hz, preferably 60 Hz to 960 Hz, more preferably 75 Hz to 960 Hz, more preferably 120 Hz to 960 Hz, more preferably 240 Hz to 960 Hz.

  By setting the second refresh rate to a value higher than the first refresh rate, the moving image can be displayed more smoothly and naturally. Further, since flickering (also referred to as flicker) associated with rewriting is suppressed from being visually recognized by the user, it is possible to reduce eyestrain of the user.

  At this time, the image displayed in the window 451 is an image obtained by combining the first image 452a and the second image 452b to be displayed next. A part of the region is displayed in the window 451 so that the combined image moves in one direction (here, the left direction).

  Further, with the movement of the combined images, the luminance of the image displayed in the window 451 gradually decreases compared to the initial luminance (at the time of FIG. 49A).

  FIG. 49C shows a point in time when the image displayed in the window 451 reaches a predetermined coordinate. Therefore, the brightness of the image displayed in the window 451 at this time is the lowest.

  In FIG. 49C, as the predetermined coordinates, the coordinates where the first image 452a and the second image 452b are displayed in half are not limited to this, but the user can freely set the coordinates. Preferably it is possible.

  For example, a coordinate having a ratio of the distance from the initial coordinate to the distance from the initial coordinate to the final coordinate of the image that is greater than 0 and less than 1 may be set as the predetermined coordinate.

  Also, it is preferable that the user can freely set the luminance when the image reaches a predetermined coordinate. For example, the ratio of the luminance when the image reaches a predetermined coordinate to the initial luminance may be set to 0 or more and less than 1, preferably 0 or more and 0.8 or less, more preferably 0 or more and 0.5 or less.

  Subsequently, in the window 451, the combined image is displayed so that the luminance increases stepwise while moving (FIG. 49D).

  FIG. 49E shows a point in time when the coordinates of the combined images reach the final coordinates. In the window 451, only the second image 452b is displayed with a luminance equal to the initial luminance.

  Note that it is preferable to change the refresh rate from the second refresh rate to the first refresh rate after the movement of the image is completed.

  By performing such a display, even when the user follows the movement of the image with his / her eyes, the luminance of the image is reduced, so that the eyestrain of the user can be reduced. Therefore, by using such a driving method, an eye-friendly display can be realized.

[Example of document information display]
Next, an example of scrolling and displaying document information larger than the size of the display window will be described.

  FIG. 50A illustrates an example in which a window 455 and a part of document information 456 that is a still image displayed in the window 455 are displayed on the display portion 450.

  At this time, it is preferable to perform display at the first refresh rate.

  The window 455 is displayed by executing, for example, document display application software, document creation application software, and the like, and includes a display area for displaying document information.

  The document information 456 is larger in image size in the vertical direction than the display area of the window 455. Accordingly, only a part of the area is displayed in the window 455. As shown in FIG. 50A, the window 455 may include a scroll bar 457 indicating which area of the document information 456 is displayed.

  When a command for moving an image (also referred to as a scroll command here) is given to the display device by the input unit, the movement of the document information 456 is started (FIG. 50B). In addition, the brightness of the displayed image decreases stepwise.

  If the display is performed at the first refresh rate at the time of FIG. 50A, it is preferable to change the refresh rate to the second refresh rate before the document information 456 is moved.

  Here, not only the brightness of the image displayed in the window 455 but also the brightness of the entire image displayed on the display unit 450 is shown.

  FIG. 50C shows a point in time when the coordinates of the document information 456 reach predetermined coordinates. At this time, the luminance of the entire image displayed on the display unit 450 is the lowest.

  Subsequently, the document information 456 is displayed while moving in the window 455 (FIG. 50D). At this time, the luminance of the entire image displayed on the display unit 450 increases stepwise.

  FIG. 50E shows a point in time when the coordinates of the document information 456 reach the final coordinates. In the window 455, an area different from the initially displayed area of the document information 456 is displayed with a luminance equal to the initial luminance.

  Note that the refresh rate is preferably changed to the first refresh rate after the movement of the document information 456 is completed.

  By performing such a display, even when the user follows the movement of the image with his / her eyes, the luminance of the image is reduced, so that the eyestrain of the user can be reduced. Therefore, by using such a driving method, an eye-friendly display can be realized.

  In particular, display with high contrast such as document information causes more noticeable fatigue on the eyes of the user, so it is more preferable to apply such a driving method to display of document information.

  This embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 15)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  A display module 8000 shown in FIG. 51 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, a battery, between an upper cover 8001 and a lower cover 8002. 8011.

  The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

  The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

  As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

  The backlight 8007 has a light source 8008. Note that although FIG. 51 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

  The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

  The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

  The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

  52A to 52G are diagrams each illustrating an electronic device. These electronic devices include a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or operation switch), a connection terminal 5006, a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 5008, and the like.

  FIG. 52A illustrates a mobile computer which can include a switch 5009, an infrared port 5010, and the like in addition to the above components. FIG. 52B illustrates a portable image playback device (eg, a DVD playback device) provided with a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can. FIG. 52C illustrates a goggle type display which can include a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above components. FIG. 52D illustrates a portable game machine that can include the memory medium reading portion 5011 and the like in addition to the above objects. FIG. 52E illustrates a digital camera with a television receiving function, which can include an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like in addition to the above objects. FIG. 52F illustrates a portable game machine that can include the second display portion 5002, the recording medium reading portion 5011, and the like in addition to the above objects. FIG. 52G illustrates a portable television receiver that can include a charger 5017 and the like capable of transmitting and receiving signals in addition to the above components.

  The electronic devices illustrated in FIGS. 52A to 52G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying programs or data recorded on the recording medium It can have a function of displaying on the section. Further, in an electronic device having a plurality of display units, one display unit mainly displays image information and another one display unit mainly displays character information, or the plurality of display units consider parallax. It is possible to have a function of displaying a three-dimensional image, etc. by displaying the obtained image. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image, a function for capturing a moving image, a function for correcting a captured image automatically or manually, and a captured image on a recording medium (externally or incorporated in a camera) A function of saving, a function of displaying a photographed image on a display portion, and the like can be provided. Note that the functions of the electronic devices illustrated in FIGS. 52A to 52G are not limited to these, and can have various functions.

  An arm-mounted portable information terminal using the display device of one embodiment of the present invention will be described with reference to FIGS. Note that one embodiment of the present invention is not limited to an arm-mounted type that is mounted on a wrist, an upper arm, or the like, but can be applied to a portable information terminal that is mounted on a waist, an ankle, or the like.

  The wrist-worn type (or wristwatch type) portable information terminal exemplified in this embodiment may have a communication function and be capable of transmitting and receiving an e-mail or the like alone. The portable information terminal is preferably capable of executing various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

  Alternatively, e-mail transmission and reception may be performed by connecting wirelessly or wiredly to a mobile phone such as a smartphone or another portable information terminal. For example, the display unit of a wrist-worn type (or wristwatch type) portable information terminal may be used as a sub-display by being used together with a smartphone.

  In addition, the portable information terminal may be able to execute short-range wireless communication that is a communication standard. For example, hands-free communication may be possible by communicating with a headset capable of wireless communication.

  A wristwatch-type portable information terminal has at least one of a button, a switch, and a touch panel. The buttons and switches can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and cancellation, and power saving mode execution and cancellation. Moreover, these operations may be performed by operating the touch panel. The functions of buttons and switches may be freely set by an operating system incorporated in the portable information terminal.

  In addition, the wristwatch-type portable information terminal exemplified in this embodiment preferably includes a sensor that measures biological information of a user such as a heart rate, a respiratory rate, a pulse, a body temperature, or a blood pressure.

  For example, the heart rate can be measured from the contraction of capillaries such as arms using an optical sensor.

  Even if the mobile information terminal can be automatically turned on / off by using a sensor that grasps whether or not the mobile information terminal is worn on the user's arm from the electrical conductivity of the skin. Good.

  These sensors are preferably mounted, for example, on the surface side touched by the user's arm in the portable information terminal.

  Moreover, the data of use environment may be measurable. For example, you may have a ultraviolet sensor and an illumination intensity sensor. By knowing the amount of ultraviolet rays, it can be used to prevent sunburn. Further, the brightness of the display unit may be automatically adjusted depending on the illuminance of the usage environment. For example, these sensors are preferably mounted on the display surface side in a portable information terminal.

  The portable information terminal may be able to receive a GPS (Global positioning System) signal.

  Moreover, it is preferable that the portable information terminal can charge the secondary battery in a non-contact manner. The portable information terminal preferably includes a photoelectric conversion element, and the secondary battery can be charged using the photoelectric conversion element. For example, it is preferable that the secondary battery can be charged by solar power generation.

  A wristwatch-type portable information terminal 370 illustrated in FIG. 53A includes a display portion 371, a battery 373, a fastener 375, a housing 377, and the like. The display portion 371, the battery 373, and the housing 377 each have flexibility. Therefore, it is easy to bend portable information terminal 370 into a desired shape. For example, a flexible display panel can be used for the display portion 371, and a flexible light-emitting panel may be combined. As the battery 373, a flexible secondary battery can be used. Therefore, even if bending stress is applied, the bending stress can be dispersed throughout without concentrating the bent portions, so that damage due to excessive bending of the display portion 371 and the battery 373 can be suppressed. As a result, the reliability of the portable information terminal 370 can be improved.

  FIG. 53A illustrates an example in which two batteries 373 are provided in the housing 377, but the number of batteries is not particularly limited as long as the number is one or more. In addition, a battery 373 may be disposed over the display portion 371.

  For the housing 377, for example, one or more of metals, resins, natural materials, and the like can be used. As the metal, stainless steel, aluminum, titanium alloy, or the like can be used. As the resin, acrylic resin, polyimide resin, or the like can be used. Natural materials that can be used include wood, stone, bone, leather, paper, and cloth.

  FIG. 53B shows a perspective view of a state where the portable information terminal 380 is bent in an annular shape, and FIG. 53C shows a top view of a state where the portable information terminal 380 is expanded (also referred to as expansion). 53D and 53E are cross-sectional views taken along dashed-dotted line Z1-Z2 in FIG.

  The wristwatch-type portable information terminal 380 includes a display portion 371, housings 372 a and 372 b, and a battery 373. The housing 372b and the battery 373 each have flexibility. Therefore, it is easy to curve the portable information terminal 380 into a desired shape. Further, the display portion 371 and the housing 372a may each have flexibility. Note that as illustrated in FIG. 53C, the portable information terminal 380 may include an operation button 379.

  As shown in FIG. 53D, the battery 373 includes the secondary battery 20 and a member 40 having rubber elasticity. In addition, the display device of one embodiment of the present invention is preferably applied to the display portion 371. The display unit 371 includes the display device 10 and a member 40 having rubber elasticity. The member 40 may have a concavo-convex structure 40a in order to bend more easily and to improve the reliability with respect to repeated bending and stretching.

  As shown in FIG. 53E, the portable information terminal 380 may further include a sensor 70. As the sensor 70, various sensors such as the above-described sensor for detecting biological information can be used. The flexibility of the sensor 70 does not matter. The sensor 70 may be provided inside or outside the member 40 having rubber elasticity. FIG. 53E illustrates an example in which one embodiment of the present invention is applied to a battery 373 and the display portion 371, the housing 372a, and the sensor 70 do not have flexibility.

  The electronic device described in this embodiment includes a display portion for displaying some information. The display device described in any of the other embodiments can be applied to the display portion.

DESCRIPTION OF SYMBOLS 10 Display apparatus 21a Conductive film 21b Conductive film 40 Member 40a Uneven structure 51 Liquid crystal element 52 Transistor 70 Sensor 102 Substrate 104 Gate electrode 105 Gate wiring 106 Insulating film 107 Insulating film 108 Insulating film 110 Oxide semiconductor film 110a Oxide semiconductor film 111 Oxidation Oxide semiconductor film 111b oxide semiconductor film 112 wiring 112a source electrode 112b drain electrode 114 insulating film 116 insulating film 118 insulating film 119 insulating film 119a insulating film 119b insulating film 119c insulating film 120 conductive film 120a conductive film 133 scanning Line 134 Transistor 136 Capacitance electrode 141 Opening 142 Opening 144 Opening 146 Opening 148 Opening 148a Opening 148b Opening 148c Opening 150 Transistor 151 Transistor 152 Semiconductor device 160 Capacitor Element 161 Capacitance element 165 Target 166 Plasma 170 Gate wiring contact part 171 Gate wiring contact part 181 Transmission axis 183 Orientation direction 185 Orientation direction 187 Orientation angle 189 Twist angle 202 Substrate 204 Conductive film 206 Insulating film 207 Insulating film 208 Oxide semiconductor film 208a Oxide semiconductor film 208b oxide semiconductor film 208c oxide semiconductor film 211a oxide semiconductor film 211b oxide semiconductor film 212a conductive film 212b conductive film 214 insulating film 216 insulating film 218 insulating film 220b conductive film 252a opening 252b opening 252c opening 270 transistor 270A Transistor 270B Transistor 300 Display device 301 Substrate 302 Display unit 305 External connection terminal 311 Transistor 312 Transistor 314 Liquid crystal element 321 Substrate 327 Lar filter 332 Insulating layer 333 Gate electrode 334 Insulating layer 336 Electrode 338 Insulating layer 339 Insulating layer 341 Insulating layer 342 Insulating layer 343 Electrode 352 Electrode 353 Liquid crystal layer 360 Electrode 370 Portable information terminal 371 Display unit 372a Housing 372b Housing 373 Battery 375 Fastener 377 Case 379 Operation button 380 Portable information terminal 402 Dotted line 404 Line 406 Line 450 Display unit 451 Window 452a Image 452b Image 453 Button 455 Window 456 Document information 457 Scroll bar 500 Input means 500_C Signal 600 Liquid crystal display device 610 Control unit 615_C Secondary control signal 615_V Secondary image signal 620 Arithmetic device 625_C Primary control signal 625_V Primary image signal 630 Display portion 631 Pixel portion 631a Region 631b Region 631c Region 631p Pixel 632 G drive circuit 632_G G signal 633 S drive circuit 633_S S signal 634 Pixel circuit 634c Capacitance element 634c (i) Parasitic capacitance 634c (i + 1) Parasitic capacitance 634t Transistor 635 Display element 635_1 Pixel electrode 635LC Liquid crystal element 650 Light supply unit 671 Arithmetic device 672 Storage device 673 Graphic unit 674 Display means 700 Display device 701 Substrate 702 Pixel portion 704 Source driver circuit portion 705 Substrate 706 Gate driver circuit portion 708 FPC terminal portion 710 Wiring 711 Wiring portion 712 Seal material 716 FPC
734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulating film 766 Insulating film 768 Insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 790 Capacitor element 1000a Pixel part 1000b Pixel part 1010 Substrate 1011 Pixel 1011a Pixel electrode 1011b Pixel electrode 1011c Pixel electrode 1012a Insulating layer 1012b Insulating layer 1012c Insulating layer 1012d Insulating layer 1012e Insulating layer 1012f Insulating layer 1014 Alignment film 1020 Substrate 1021a Color filter 1021b Color filter 1021c Color filter 1023 Counter electrode 1025 Spacer 1027 Alignment film 1030 Liquid crystal layer 1040 Polarizing element 1042 Phase plate 1044 Scattering plate 1050 Reflection 1060 Sealant 1062 Spacer 1064 Filler 1066 Semi-permeable membrane 5000 Case 5001 Display unit 5002 Display unit 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support Part 5013 Earphone 5014 Antenna 5015 Shutter button 5016 Image receiving part 5017 Charger 5200 Pellet 5201 Ion 5202 Horizontal growth part 5203 Particle 5220 Substrate 5230 Target 5240 Plasma 5260 Heating mechanism 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Back light 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery S Signal line G Scan line S1 Signal line S2 Signal line S3 Signal line S4 Signal line Sx Signal line G1 Scan line G2 Scan line Gy Scan line Si Signal line Si + 1 Signal line

Claims (7)

A display device in which a liquid crystal material is sandwiched between a first substrate and a second substrate,
The first substrate has a plurality of pixels;
The pixel has first to third pixel electrodes,
The first to third pixel electrodes have light reflectivity and conductivity,
The second pixel electrode has a region overlapping with the first pixel electrode through an insulating film,
The third pixel electrode has a region overlapping with the second pixel electrode via an insulating film,
A third pixel electrode of one of the adjacent pixels has a region overlapping with a first pixel electrode of the other pixel through an insulating film;
The second substrate has a color filter showing first to third hues;
The display device, wherein the color filters of the first to third hues are disposed so as to face the first to third pixel electrodes. The display device according to claim 1, further comprising a conductive film on a surface of the color filter facing the liquid crystal material. 3. The display device according to claim 2, further comprising a film having a property of transmitting part of the light incident on the surface of the color filter facing the liquid crystal material and reflecting the rest. 4. The maximum transmission wavelength of the color filters of the first to third hues is λ _x (x = 1, 2, 3), the refractive index of the liquid crystal is n, and the first Or when the distance between the surface of the third pixel electrode and the surface of the conductive film is L _x , the optical resonance condition mλ _x = 2 · n · L _x (m is a positive integer)
A display device characterized by satisfying the relationship: 5. The display device according to claim 1, wherein the pixel includes a switching element. 6. The display device according to claim 5, wherein the switching element is a field effect transistor. 7. The display device according to claim 5, wherein the switching element includes an oxide semiconductor.