JP2016134394A - Group iii-v compound semiconductor epitaxial wafer and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable attainment of a sufficient etching selection ratio even when a stopper layer between an HEMT structure layer and an HBT structure layer is thinned.SOLUTION: A group III-V compound semiconductor epitaxial wafer comprises: a single crystal substrate 11; a high electron mobility transistor structure layer 2 which is formed on the single crystal substrate 11 and in which a Schottky layer 18 composed of GaAs is formed in a top layer; a heterobipolar transistor structure layer 3 formed on the high electron mobility transistor structure layer 2; and a first stopper layer 19 formed between the high electron mobility transistor structure layer 2 and the heterobipolar transistor structure layer 3, in which a second stopper layer 22 which is formed closer to the high electron mobility transistor structure layer 2 than a base layer 24 of the heterobipolar transistor structure layer 3, and has a higher etching selection ratio against an etchant for etching the heterobipolar transistor structure layer 3 than GaAs or is not to be etched.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a group III-V compound semiconductor epitaxial wafer in which a high electron mobility transistor structure layer and a heterobipolar transistor structure layer are sequentially laminated on a single crystal substrate, and a method for manufacturing the same.

  In order to reduce power consumption, a high electron mobility transistor (HEMT) structure layer and a hetero bipolar transistor (HBT) structure layer are sequentially formed on a GaAs single crystal substrate. A laminated BiFET structure III-V compound semiconductor epitaxial wafer is known.

  A transistor element fabricated using a III-V compound semiconductor epitaxial wafer having a BiFET structure is a combination of a HEMT having a switching function and an HBT having a power amplifier function. It can be used for an amplifier module or the like.

  By the way, in a III-V compound semiconductor epitaxial wafer having a BiFET structure, in order to separate the HEMT structure layer and the HBT structure layer, it is necessary to remove a part of the HBT structure layer by wet etching to expose the HEMT structure layer. is there. At this time, a stopper layer for stopping the etching is provided between the HEMT structure layer and the HBT structure layer so that only the HBT structure layer can be removed by etching.

  As the stopper layer, a stopper layer having a higher etching selection ratio (also referred to simply as a selection ratio) than GaAs with respect to an etching solution for etching the HBT structure layer is used. Specifically, a stopper layer made of InGaP or AlAs is generally used.

  By providing a stopper layer, it becomes possible to stop etching at the stopper layer on the HEMT structure layer when etching the HBT structure layer, and then remove the stopper layer with an etchant that etches only the stopper layer. The HEMT structure layer can be exposed.

  However, if the performance of the stopper layer (performance for stopping etching) is not sufficient, etching may not be stopped.

  Optimize the stopper layer performance by increasing the stopper layer purity (high V / III ratio), increasing the stopper layer thickness, or optimizing the interval sequence before and after the stopper layer A method for performing the above has been proposed.

  In addition, there exists patent document 1 as prior art document information relevant to invention of this application.

JP 2011-192734 A

  However, in the method for improving the performance of the stopper layer as described above, it may be difficult to remove the stopper layer itself.

  In particular, when the stopper layer is thickened, the stopper layer may become a resistance layer, causing a problem. Furthermore, when InGaP is used as the stopper layer, if the stopper layer is thickened, an interface charge is generated at the stopper layer interface, and the vicinity of the interface also becomes a resistance layer. Furthermore, when the stopper layer is thickened, foreign matter is likely to be generated, and this foreign matter also becomes a resistance component. Therefore, it is preferable that the stopper layer is thin.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, and even if the stopper layer between the HEMT structure layer and the HBT structure layer is thinned, a III-V group compound semiconductor capable of obtaining a sufficient etching selectivity. An epitaxial wafer and a manufacturing method thereof are provided.

  The present invention was devised to achieve the above object, and has a high electron mobility transistor structure in which a single crystal substrate and a Schottky layer made of GaAs are formed on the uppermost layer are formed on the single crystal substrate. A heterobipolar transistor structure layer formed on the high electron mobility transistor structure layer, and the heterobipolar transistor structure layer formed between the high electron mobility transistor structure layer and the heterobipolar transistor structure layer. And a first stopper layer for stopping the etching when etching the substrate, in the III-V compound semiconductor epitaxial wafer, the higher electron mobility transistor structure layer side than the base layer of the heterobipolar transistor structure layer And etching the heterobipolar transistor structure layer. Relative quenching liquid, high etching selection ratio than GaAs, or a III-V group compound semiconductor epitaxial wafer formed a second stopper layer which is not etched.

  The etching solution may be an aqueous ammonia-water solution, and the second stopper layer may have an etching selectivity higher than that of GaAs or not etched with respect to the aqueous ammonia-water solution.

  The second stopper layer may be made of InGaP or AlAs, and the thickness of the second stopper layer may be 2 nm or more.

  The thickness of the second stopper layer may be 50 nm or more and 200 nm or less.

The second stopper layer may be made of InGaP, and the As concentration of the second stopper layer may be 2 × 10 ²⁰ cm ⁻³ or less.

  The heterobipolar transistor structure layer may have a surface roughness (RMS) of 1 nm or less.

  The heterobipolar transistor structure layer may have a surface roughness (RMS) of 0.4 nm or less.

  The carrier concentration of the second stopper layer may be equal to or lower than the carrier concentration of the epitaxial layer formed immediately above the second stopper layer.

  The etching selectivity of the second stopper layer to the etching solution may be 5 times or more that of GaAs.

  The present invention also provides a single crystal substrate, a high electron mobility transistor structure layer formed on the single crystal substrate and having a Schottky layer made of GaAs as the uppermost layer, and the high electron mobility transistor structure layer A heterobipolar transistor structure layer formed thereon, and formed between the high electron mobility transistor structure layer and the heterobipolar transistor structure layer, for stopping etching when the heterobipolar transistor structure layer is etched. And a sub-collector layer formed on the high electron mobility transistor structure layer side of the base layer of the heterobipolar transistor structure layer. And etching the heterobipolar transistor structure layer. A III-V group compound semiconductor in which a second stopper layer having an etching selectivity higher than that of GaAs or not etched with respect to the etching solution is formed, and the second stopper layer is formed below the growth temperature of the subcollector layer It is a manufacturing method of an epitaxial wafer.

  According to the present invention, it is possible to obtain a sufficient etching selectivity even when the stopper layer between the HEMT structure layer and the HBT structure layer is thinned.

It is a lamination structure figure of a III-V compound semiconductor epitaxial wafer concerning one embodiment of the present invention. In the Example of this invention, it is a graph which shows the relationship between an etching selectivity and the standard value of the resistance value after an etching.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a stacked structure diagram of a III-V group compound semiconductor epitaxial wafer according to the present embodiment.

  As shown in FIG. 1, a group III-V compound semiconductor epitaxial wafer (hereinafter simply referred to as a wafer) 1 includes a single crystal substrate 11 made of semi-insulating GaAs and a high electron mobility formed on the single crystal substrate 11. A BiFET structure wafer including a transistor structure layer (hereinafter referred to as a HEMT structure layer) 2 and a heterobipolar transistor structure layer (hereinafter referred to as an HBT structure layer) 3 formed on the HEMT structure layer.

  The HEMT structure layer 2 is formed on a single crystal substrate 11 by sequentially stacking a buffer layer 12, a supply layer 13, a spacer layer 14, a channel layer 15, a spacer layer 16, a supply layer 17, and a Schottky layer 18.

  The buffer layer 12 is made of, for example, an undoped AlGaAs layer, the supply layer 13 is, for example, an n-type AlGaAs layer, the spacer layer 14 is, for example, an undoped AlGaAs layer, the channel layer 15 is, for example, an InGaAs layer, the spacer layer 16 is, for example, an undoped AlGaAs layer, or a supply layer 17 For example, the n-type InGaP layer and the Schottky layer 18 are made of, for example, an undoped GaAs layer.

  The supply layers 13 and 17 are made of, for example, a Si δ-doped layer. The δ-doped layer is a region where a dopant (Si in this case) is locally contained at a high concentration, and does not exist as a layer having a reduced scale as shown in FIG. That is, in FIG. 1, the scale of each layer is changed for convenience, and the laminated structure of the wafer 1 is schematically shown.

  On the HEMT structure layer 2 (between the HEMT structure layer 2 and the HBT structure layer 3), a first stopper layer 19 for stopping the etching when the HBT structure layer 3 is etched and a cap layer 20 are sequentially laminated. Is done.

  In the present embodiment, the first stopper layer 19 made of InGaP is formed. Although details will be described later, since the second stopper layer 22 is formed in this embodiment, the thickness of the first stopper layer 19 can be as thin as 5 nm or less.

  When forming the first stopper layer 19, it is desirable to set the growth temperature to be equal to or lower than the growth temperature of the HEMT structure layer 2 in order to suppress the characteristic deterioration of the HEMT structure layer 2 due to heat during the growth of the first stopper layer 19. . In the present specification, the growth temperature means the substrate temperature of the single crystal substrate 11 during growth.

  The HBT structure layer 3 is basically formed by sequentially laminating a sub-collector layer 21, a collector layer 23, a base layer 24, an emitter layer 25, an emitter contact layer 26, and a non-alloy layer 27 on the cap layer 20.

  The subcollector layer 21 is made of, for example, an n-type GaAs layer, the collector layer 23 is made of, for example, an n-type GaAs layer, the base layer 24 is made of, for example, a p-type GaAs layer, the emitter layer 25 is made of, for example, an n-type InGaP layer, and the emitter contact layer 26 is made of, for example, n The type GaAs layer and the non-alloy layer 27 are made of, for example, an n-type InGaAs layer.

  In the wafer 1, the layers 12 to 27 are formed by a vapor phase growth method (MOVPE (Metal Organic Vapor Phase Epitaxy) method).

  Now, in the wafer 1 according to the present embodiment, the etching selectivity is higher than that of GaAs with respect to the etching solution for etching the HBT structure layer 3 on the HEMT structure layer 2 side of the base layer 24 of the HBT structure layer 3. Alternatively, the second stopper layer 22 that is not etched is formed.

  In this embodiment, since an aqueous solution of ammonia perwater is used as an etchant for etching the HBT structure layer 3, the second stopper layer 22 has an etching selectivity higher than that of GaAs with respect to the aqueous solution of ammonia overwater, or What was not etched was used.

  Specifically, the second stopper layer 22 may be made of InGaP or AlAs. In the present embodiment, the second stopper layer 22 made of InGaP is used.

  In the present embodiment, the second stopper layer 22 is formed on the subcollector layer 21, that is, between the subcollector layer 21 and the collector layer 23. However, the present invention is not limited to this, and the second stopper layer 22 may be formed below the subcollector layer 21, that is, between the cap layer 20 and the subcollector layer 21. In addition, the collector layer 23 may be formed of InGaP and serve as the second stopper layer 22.

  The thickness of the second stopper layer 22 is preferably 2 nm or more. This is because if the thickness of the second stopper layer 22 is less than 2 nm, the effect of stopping the etching cannot be sufficiently obtained. The thicker the second stopper layer 22 is, the easier it is to stop the etching. However, if the thickness is too large, foreign substances serving as a resistance component are likely to be generated. Therefore, the thickness of the second stopper layer 22 is preferably 200 nm or less. More preferably, the thickness of the second stopper layer 22 is not less than 50 nm and not more than 200 nm.

When the second stopper layer 22 made of InGaP is used, the As concentration of the second stopper layer 22 is preferably 2 × 10 ²⁰ cm ⁻³ or less. The second stopper layer 22 is removed with a hydrochloric acid-based etchant after the HBT structure layer 3 is etched. However, when the As concentration in InGaP increases, the second stopper layer 22 is etched with the hydrochloric acid-based etchant. This is because it becomes difficult and the surface becomes very rough after etching. As a result of studies by the present inventors, it has been confirmed that if the As concentration is 2 × 10 ²⁰ cm ⁻³ or less, etching can be easily performed using an etching solution with hydrochloric acid: water = 1: 1.

  Also, the carrier concentration of the second stopper layer 22 is preferably less than or equal to the carrier concentration of the epitaxial layer (here, the collector layer 23) formed immediately above the second stopper layer 22. Here, the second stopper layer 22 was formed undoped (no doping).

  The selection ratio of the second stopper layer 22 to the etching solution for etching the HBT structure layer 3 is preferably 5 times or more that of GaAs. When the present inventors examined, when only 5 nm of 1st stopper layers 19 were formed, the selection ratio was less than 5. As a whole, the selection ratio is desirably 10 or more. In this embodiment, the selection ratio of the second stopper layer 22 is 5 times or more that of GaAs.

  By the way, when the stopper layers 19 and 22 are thin as in the present embodiment, if the surface roughness is 1 nm or more, etching may be lost at the thinned portion, and etching may not be stopped. Therefore, it can be said that the smaller the surface roughness is, the better in order to stop etching uniformly within the wafer surface.

  Therefore, the surface roughness (RMS) of the wafer 1, that is, the surface roughness (RMS) of the HBT structure layer 3 may be 1 nm or less, and more preferably 0.4 nm or less. The surface roughness (RMS) of the HBT structure layer 3 was measured when the surface roughness (RMS) of the wafer 1 obtained by the present inventors was sufficiently effective to stop etching. By setting the thickness to 0.4 nm or less, it is considered that the etching can be surely stopped uniformly within the wafer surface.

  In the present embodiment, since the second stopper layer 22 is formed on the subcollector layer 21, when the second stopper layer 22 is formed, a temperature change interval is not generated with the same growth temperature as the subcollector layer 21. It is desirable to suppress the characteristic deterioration of the HEMT structure layer 2 by growing the substrate at a temperature lower than the sub-collector layer growth temperature. In other words, the second stopper layer 22 is desirably formed at a temperature lower than the growth temperature of the subcollector layer 21.

  When the second stopper layer 22 made of InGaP is used, the band gap of the second stopper layer 22 increases as the growth temperature when forming the second stopper layer 22 is lower than the growth temperature of the subcollector layer 21. When the growth temperature is lowered until the band gap of the second stopper layer 22 reaches about 1.89 eV, the temperature change interval becomes longer, the heat load on the HEMT structure layer 2 becomes larger, and the mobility of the HEMT structure layer 2 decreases. There is a risk of deterioration of characteristics. Therefore, it is desirable that the growth temperature of the second stopper layer 22 is a growth temperature at which the band gap of the second stopper layer 22 is 1.89 eV or less, more preferably 1.84 to 1.89 eV.

  As described above, in the wafer 1 according to this embodiment, the etching solution for etching the HBT structure layer 3 on the side of the HEMT structure layer 2 with respect to the base layer 24 of the HBT structure layer 3 is more selective than GaAs. The second stopper layer 22 having a high ratio or not etched is formed.

  By forming the second stopper layer 22, even when the first stopper layer 19 is thinned to a thickness of 5 nm or less, for example, the stopper layers 19 and 22 as a whole have a large selection ratio, and the HBT structure layer 3 is formed. When etching, the stopper layers 19 and 22 can sufficiently stop the etching.

  In this embodiment, since it becomes possible to make each stopper layer 19 and 22 thin, it can suppress that the stopper layers 19 and 22 become a resistance layer and a problem arises, and InGaP was used for the stopper layers 19 and 22. Even in this case, the generation of the resistance layer due to the generation of the interface charge can be suppressed. Further, by making the stopper layers 19 and 22 thinner, it is possible to suppress the generation of foreign substances as resistance components, and the stopper layers 19 and 22 can be easily removed.

  In the present embodiment, since the second stopper layer 22 is formed at a temperature lower than the growth temperature of the subcollector layer 21, an increase in the thermal load on the HEMT structure layer 2 when the second stopper layer 22 is grown is suppressed. It is possible to suppress deterioration of the characteristics of the HEMT structure layer 2.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

  In FIG. 1, the wafer 1 of Example 1 in which the 20 nm-thick second stopper layer 22 made of undoped InGaP was formed. InGaP was used for the first stopper layer 19 and the thickness was 5 nm.

  Further, in FIG. 1, the wafer 1 of Example 2 in which the second stopper layer 22 made of undoped InGaP and having a thickness of 100 nm was formed. InGaP was used for the first stopper layer 19 and the thickness was 5 nm.

  Moreover, in FIG. 1, the wafer 1 of Example 3 in which the 2 nm-thick second stopper layer 22 made of undoped AlAs was formed. InGaP was used for the first stopper layer 19 and the thickness was 5 nm.

  For comparison, a conventional wafer having the same structure as in Examples 1 to 3 was prepared except that the second stopper layer 22 was omitted.

  Using the created wafers of Examples 1 to 3 and the conventional example, the relationship between the etching selectivity when etching with an aqueous ammonia-water solution and the standard value of the resistance value after etching was obtained by experiments. The results are shown in FIG. The value on the vertical axis in FIG. 2 is a standard value obtained by dividing the resistance value after etching by the resistance value at the time when the first stopper layer 19 is exposed. This indicates that the etching stop effect in the stopper layer 19 is lost, and the HEMT structure layer 2 below the Schottky layer 18 has been etched.

  As shown in FIG. 2, in the conventional wafer, it was difficult to stop the etching with the first stopper layer 19, and the selection ratio was less than 5.

  In contrast, in the wafers 1 of Examples 1 and 2, the selectivity is 20 or more, and it can be seen that the effect of stopping the etching by the first stopper layer 19 is sufficiently obtained. In the wafer 1 of Example 3, although the standard value of the vertical axis slightly exceeds 1, it can be seen that the effect of stopping the etching is sufficiently obtained as compared with the conventional example.

  From the above results, it was confirmed that by forming the second stopper layer 22, the selectivity can be improved and the effect of stopping the etching at the first stopper layer 19 can be improved.

1 III-V compound semiconductor epitaxial wafer (wafer)
2 High electron mobility transistor structure layer (HEMT structure layer)
3 Hetero bipolar transistor structure layer (HBT structure layer)
18 Schottky layer 19 First stopper layer 22 Second stopper layer 24 Base layer

Claims (10)

A single crystal substrate;
A high electron mobility transistor structure layer formed on the single crystal substrate and having a Schottky layer made of GaAs as the uppermost layer;
A heterobipolar transistor structure layer formed on the high electron mobility transistor structure layer;
A first stopper layer formed between the high electron mobility transistor structure layer and the heterobipolar transistor structure layer for stopping etching when the heterobipolar transistor structure layer is etched;
In III-V compound semiconductor epitaxial wafers with
The etching selectivity for etching the heterobipolar transistor structure layer on the high electron mobility transistor structure layer side of the base layer of the heterobipolar transistor structure layer is higher than that of GaAs or not etched. 2. A III-V compound semiconductor epitaxial wafer characterized by forming a stopper layer. The etchant is an aqueous ammonia-water solution;
The III-V group compound semiconductor epitaxial wafer according to claim 1, wherein the second stopper layer is one having an etching selectivity higher than that of GaAs or not etched with respect to an aqueous solution of ammonia-peroxide. The second stopper layer is made of InGaP or AlAs;
The III-V group compound semiconductor epitaxial wafer according to claim 1 or 2, wherein the thickness of the second stopper layer is 2 nm or more. The III-V group compound semiconductor epitaxial wafer according to claim 3 whose thickness of said 2nd stopper layer is 50 nm or more and 200 nm or less. The second stopper layer is made of InGaP;
5. The III-V group compound semiconductor epitaxial wafer according to claim 1, wherein an As concentration of the second stopper layer is 2 × 10 ²⁰ cm ⁻³ or less. The III-V compound semiconductor epitaxial wafer according to any one of claims 1 to 5, wherein the heterobipolar transistor structure layer has a surface roughness (RMS) of 1 nm or less. The III-V group compound semiconductor epitaxial wafer according to claim 6 whose surface roughness (RMS) of said heterobipolar transistor structure layer is 0.4 nm or less. The III-V group compound semiconductor epitaxial wafer according to any one of claims 1 to 7, wherein a carrier concentration of the second stopper layer is equal to or less than a carrier concentration of an epitaxial layer formed immediately above the second stopper layer. The III-V group compound semiconductor epitaxial wafer according to any one of claims 1 to 8, wherein an etching selection ratio of the second stopper layer to the etching solution is 5 times or more that of GaAs. A single crystal substrate;
A high electron mobility transistor structure layer formed on the single crystal substrate and having a Schottky layer made of GaAs as the uppermost layer;
A heterobipolar transistor structure layer formed on the high electron mobility transistor structure layer;
A first stopper layer formed between the high electron mobility transistor structure layer and the heterobipolar transistor structure layer for stopping etching when the heterobipolar transistor structure layer is etched;
In a method for producing a III-V compound semiconductor epitaxial wafer comprising:
On the subcollector layer formed on the high electron mobility transistor structure layer side of the base layer of the heterobipolar transistor structure layer, the etching solution for etching the heterobipolar transistor structure layer is more selective than GaAs. Forming a second stopper layer having a high ratio or not etched;
The method for producing a group III-V compound semiconductor epitaxial wafer, wherein the second stopper layer is formed below the growth temperature of the subcollector layer.

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