JP2016131291A - Reception circuit, transmission / reception circuit, and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception circuit with a simple configuration capable of automatically setting a strobe point to an optimum phase.SOLUTION: The circuit includes: a decision feedback type equalization circuit (DFE) 42 for acquiring at a strobe point; a controlling part (controller 4)6 for replaying clock data and controlling an acquisition voltage level at DFE at the same time; and a phase shifter PI43 for changing a phase of the strobe point. The controlling part detects both extreme phases of a phase range that can be correctly acquired at a first voltage level, calculates an intermediate phase, detects a margin voltage level, which is one of both extreme phases, calculates an inclination of a linear line connecting the other of both extreme phases and the margin voltage level, detects an intermediate voltage level within a voltage range in the intermediate phase, calculates a phase difference between the intermediate phase and a phase which is at the same voltage level as the intermediate voltage level on a linear line that passes through the intermediate phase and has the calculated inclination in an eye pattern, and sets a strobe point to a phase shifted from the intermediate phase by an amount of the phase difference.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a reception circuit, a transmission / reception circuit, and an integrated circuit.

  Receiver circuits (receivers) such as SERializer / DESerializer (SERDES) circuits that transmit high-speed data (Data) signals are equipped with filters called equalizers, and inter-signal interference (InterSymbol after transmission) The signal waveform distorted by Interference (ISI) is corrected. The equalizer is realized by a linear equalizer (Linear Equalizer: LE) or a decision feedback equalizer (Decision-Feedback Equalizer: DFE), or by combining LE and DFE.

  On the other hand, the receiving circuit is equipped with a logic circuit called a clock data recovery (CDR) circuit for detecting the boundary phase corresponding to the changing edge of the received data signal and tracking the boundary. In general, the intermediate phase between two adjacent boundaries is near the peak of the received data signal.

  In a receiving circuit using DFE, the height in the voltage direction is automatically adjusted. On the other hand, the strobe point at which the received data signal is captured is set to a phase intermediate between the two boundaries of the clock reproduced by the CDR. Therefore, even if the voltage direction is adjusted to an optimum value, the strobe point is fixed at the intermediate phase.

  As described above, the phase between the two adjacent boundaries is generally near the peak of the received data signal. When the data rate is relatively low, the phase of the strobe point is large even if it is fixed. It doesn't matter. However, as the data rate increases, the waveform deformation becomes relatively large, and even if the strobe point slightly deviates from the optimum phase, correct reception cannot be performed and the bit error rate (BER) is high. Become.

JP 2012-124593 A JP-A-2005-303607 International Publication No. 2008/117441

  According to the embodiment, the receiving circuit that sets the strobe point to the optimum phase is realized by simple processing.

  The receiving circuit according to the first aspect includes a decision feedback equalization circuit, a control unit, and a phase shifter. The decision feedback equalization circuit performs a decision feedback equalization process on the received data signal and captures it at the strobe point. The control unit regenerates the clock data from the output of the decision feedback equalization circuit and controls the voltage level of the received data signal in the decision feedback equalization circuit. The phase shifter changes the phase of the strobe point. The control unit executes a strobe point setting process. In the strobe point setting process, the control unit controls the phase shifter to detect the both-end phase of the phase range in which the received data signal can be correctly captured at the first voltage level, calculates the intermediate phase between the both-end phases, On the other hand, a limit voltage level at which the received data signal can be correctly captured is detected. The control unit further calculates a slope of a straight line connecting the two positions from the other position of the both end phases and the position of the limit voltage level in the eye pattern, and sets the voltage range in which the received data signal can be correctly captured in the intermediate phase. Detect intermediate voltage level. The control unit further calculates a phase difference between the phase having the same voltage level as the intermediate voltage level and the intermediate phase on a straight line having an inclination calculated through the intermediate phase in the eye pattern. The control unit further executes a strobe point setting process for setting a strobe point to a phase obtained by shifting the intermediate phase by the phase difference.

  The transmission / reception circuit according to the second aspect includes a transmission unit and a reception unit. The receiving unit includes a decision feedback equalization circuit, a control unit, and a phase shifter. The decision feedback equalization circuit performs a decision feedback equalization process on the received data signal and captures it at the strobe point. The control unit regenerates the clock data from the output of the decision feedback equalization circuit and controls the voltage level of the received data signal in the decision feedback equalization circuit. The phase shifter changes the phase of the strobe point. The control unit executes a strobe point setting process. In the strobe point setting process, the control unit controls the phase shifter to detect the both-end phase of the phase range in which the received data signal can be correctly captured at the first voltage level, calculates the intermediate phase between the both-end phases, On the other hand, a limit voltage level at which the received data signal can be correctly captured is detected. The control unit further calculates a slope of a straight line connecting the two positions from the other position of the both end phases and the position of the limit voltage level in the eye pattern, and sets the voltage range in which the received data signal can be correctly captured in the intermediate phase. Detect intermediate voltage level. The control unit further calculates a phase difference between the phase having the same voltage level as the intermediate voltage level and the intermediate phase on a straight line having an inclination calculated through the intermediate phase in the eye pattern. The control unit further executes a strobe point setting process for setting a strobe point to a phase obtained by shifting the intermediate phase by the phase difference.

  According to the embodiment, the receiving circuit that automatically sets the strobe point to the optimum phase is realized with a simple configuration.

FIG. 1 is a diagram illustrating a configuration of a communication system that transmits and receives a plurality of serial data signals (Serial signals) in parallel between chips. FIG. 2 is a diagram illustrating a waveform example of a received data signal in a high-speed data communication system, where (A) illustrates an actual waveform example and (B) schematically illustrates an eye opening. FIG. 3 is a diagram illustrating a configuration of a decision-feedback equalizer (DFE). FIG. 4 is a flowchart showing processing for setting the strobe point to the optimum phase in the embodiment. FIG. 5 is a diagram illustrating a configuration of the SERDES circuit of the chip according to the embodiment. FIG. 6 is a diagram illustrating a more detailed configuration of the SERDES circuit according to the embodiment. FIG. 7 is a flowchart showing the processes in steps S11, S12 and S14 excluding the calculation process in the flowchart of FIG. FIG. 8 is a diagram illustrating a configuration example of a DFE having a 2-tap configuration.

  Before describing the receiving circuit of the embodiment, a general communication system will be described.

  In a communication system that performs high-speed data communication, parallel data generated on the transmission side is converted into serial data and then output to a transmission path, and the received serial data is converted into parallel data. Therefore, a chip that performs such communication has a SERializer / DESerializer (SERDES) circuit. The receiving side has a clock data recovery (CDR) circuit that recovers a communication clock from the received data signal, and receives received data with the recovered clock. Furthermore, in order to improve the data communication speed between chips, the serial data communication is performed in parallel.

FIG. 1 is a diagram illustrating a configuration of a communication system that transmits and receives a plurality of serial data signals (Serial signals) in parallel between chips.
Chips 10 </ b> A and 10 </ b> B each have a SERDES circuit 11. The SERDES circuit 11 includes a plurality (four in this case) of input / output (IO) circuits 12A-12D. The SERDES circuit 11 converts parallel data generated in the chip into serial data and outputs it from the IO circuit at the time of transmission, and converts the received serial data into parallel data and supplies it to the chip at the time of reception. . With the configuration of FIG. 1, for example, 32-bit parallel data is converted into 4 × 8-bit serial data and output. Chips 10A and 10B are both on the transmission side and the reception side, and the direction of the data signal in the transmission path is determined depending on which side is the transmission side.

  The data signal to be communicated deteriorates due to the driver slew rate on the transmission side, noise generated in the transmission path, the characteristics of the amplification circuit on the reception side, etc., and the waveform of the received data signal increases as the data communication speed increases. The effect of deterioration is increased. If the waveform deterioration of the received data signal increases, correct communication cannot be performed.

  FIG. 2 is a diagram illustrating a waveform example of a received data signal in a high-speed data communication system, where (A) illustrates an actual waveform example and (B) schematically illustrates an eye opening.

  In FIG. 2A, the solid line shows the waveform when the data one cycle before is “1” and changes to “0”, and the broken line shows the data when the data before one cycle changes to “0” and “1”. The waveforms are shown respectively. FIG. 2B schematically shows a solid line waveform in FIG. FIG. 2B is used for the later description.

  The waveform shown in FIG. 2A cannot be accurately received. Therefore, in order to reduce the influence of waveform deterioration, the receiver circuit (receiver) that transmits high-speed data signals is equipped with a filter called an equalizer, and inter-signal interference after being transmitted on the transmission line. Correct the signal waveform distorted by (InterSymbol Interference: ISI). The equalizer is realized by a linear equalizer (LE), a decision-feedback equalizer (DFE), or a combination of LE and DFE. The DFE has a function of estimating and correcting waveform deterioration information from past data strings. On the other hand, the linear equalizer is also called a forward equalizer (Feed-Forward Equalizer: FFE).

FIG. 3 is a diagram illustrating a configuration of a decision-feedback equalizer (DFE).
The DFE includes two addition circuits 21A and 21B, a selection circuit (selector) 22, and a latch circuit (Latch) 23. Assuming that the data before one data cycle (1 Unit Interval: 1UI) is “1”, the adder circuit 21A adds a voltage (+ V1) that eliminates the influence of the data before 1 UI, and adds DFE Data A Is generated. The adder circuit 21B assumes that the data before 1 UI is “0”, and adds the voltage (−V1) that removes the influence of the data before 1 UI to generate DFE Data B.

  The selector 22 selects one of DFE Data A and DFE Data B according to the output of the latch circuit 23, that is, the data before 1 UI. The latch circuit 23 latches the output of the selector 22 in response to the rise of the clock CLK, and holds the latched data until the next rise of CLK.

  The DFE in FIG. 3 performs correction when the data before 1 UI is “1” and “0” in advance, and after the data before 1 UI is determined, selects the appropriate correction. . Such a DFE is called a speculative type, and performs two kinds of correction. One of them is wasted, but the time required for the correction can be shortened, so it is widely used in a high-speed receiving circuit. Since DFE is widely known, further explanation is omitted.

  On the other hand, the receiving circuit is equipped with a logic circuit called a clock data recovery (CDR) circuit that detects the boundary phase corresponding to the changing edge of the received data signal and tracks the boundary (Boundary). ing. The CDR circuit may have a PLL circuit that oscillates at a frequency corresponding to a reception clock, or may have an oscillation circuit that generates a clock having a frequency similar to that of other chips. In the former case, a clock having a predetermined phase of the PLL circuit is extracted and used as a reception data clock. In the latter case, since the frequencies do not match completely, a phase interpolator (PI) circuit is provided, and the received data clock of a predetermined phase is generated from the boundary that follows the changing edge of the received data signal and the changing edge. Generate. In the former case, a reception data clock having a desired phase may be generated from the output of the PLL circuit by the PI circuit. Here, the rising edge of the reception data clock CLK is referred to as a strobe point. In general, since the intermediate phase between two adjacent boundaries is near the peak of the received data signal, the strobe point is the intermediate phase of the boundary.

  In a receiving circuit using DFE, the height in the voltage direction is automatically adjusted. Therefore, even if the voltage direction is adjusted to an optimum value, the strobe point is fixed at the intermediate phase.

  As described above, the phase between the two adjacent boundaries is generally near the peak of the received data signal. When the data rate is relatively low, the phase of the strobe point is large even if it is fixed. It doesn't matter. However, the higher the data rate, the greater the effect of waveform degradation, and even if the strobe point deviates slightly from the optimal phase with a wide eye opening, correct reception cannot be performed, and the bit error rate ( Bit Error Rate: BER) is reduced.

  For this reason, it is required to adjust the strobe point to an optimum phase, but for this purpose, it is necessary to grasp the shape of the eye opening. The circuit for detecting the shape of the eye opening has a problem that the circuit scale is large and the time required for detection is long.

  According to the chip (integrated circuit) including the SERDES circuit of the embodiment described below, a receiving circuit that sets the strobe point to the optimum phase can be realized by simple processing.

  The receiving circuit having the DFE can detect a voltage range in which data can be correctly received at the strobe point. Further, as described above, the strobe point can be changed by a phase interpolator (PI) circuit, and the PI circuit functions as a phase shifter for the strobe point. The receiving circuit of the embodiment uses these existing functions.

  By using an existing function, the circuit scale to be added can be reduced, but detection of the shape of the eye opening increases the detection time and is difficult to put into practical use. Therefore, the receiving circuit of the embodiment sets the strobe point to the optimum phase with simple processing.

FIG. 4 is a flowchart showing processing for setting the strobe point to the optimum phase in the embodiment.
An algorithm for setting the strobe point to the optimum phase will be described with reference to FIGS. 4 and 2B.

  As described above, FIG. 2B is a diagram schematically showing a waveform when the data before 1 UI changes from “1” to “0”, and the hatched portion corresponds to the eye opening. It is desirable to set the strobe point at the position where the vertical width is maximum in the shaded portion.

In step S11 of FIG. 4, the initial state is set.
In FIG. 2B, the cross marks are points where the voltage level is 0V and the phase is the initial value of the strobe point, for example, the phase between the adjacent boundaries. As is apparent from the figure, the position indicated by the cross is not the position where the amplitude of the eye opening is maximized.

In step S12, while maintaining the state where the voltage level is 0V from the position indicated by the cross mark, the phase is shifted to the left and right to detect the positions of the two black triangle marks that are the limits of whether or not there is an error. To do.
In step S13, the position (circle) of the intermediate phase between the two black triangles is obtained.

In step S14, the voltage of the DFE is changed at the phase of one of the two black triangles (here, the left side) to detect a limit voltage that becomes the limit with or without an error (Error).
In step S15, in the eye pattern coordinates, the slope of a straight line connecting the point at the left black triangle mark phase and the limit voltage and the other of the two black triangle marks (here, the right side) is calculated.

In step S16, the optimum voltage at the intermediate phase of the circle is detected. The optimum voltage is, for example, an intermediate voltage between an upper limit and a lower limit obtained by changing the voltage up and down. In FIG. 2B, the position of the optimum voltage is indicated by a white triangle.
In step S17, the shift phase is calculated by dividing the difference between the optimum voltage and the circled voltage (0V) by the slope calculated in step S15.

In step S18, the optimum phase shifted from the intermediate phase by the shift phase is calculated. In FIG. 2 (B), the position of the optimum phase is indicated by a square mark on the straight line having the above inclination passing through the intermediate phase of the circle mark. The voltage at the position of the square mark is the same as the optimum voltage in the intermediate phase.
The optimum phase calculated as described above is set as the strobe point.

  The process of setting the strobe point described above to the optimum phase is performed when the receiving chip receives a data signal in a predetermined known pattern. Therefore, the transmitting chip transmits a data signal in this pattern. If two chips forming the communication system are determined in advance and both chips store a predetermined pattern, transmission / reception can be performed with the predetermined pattern. In that case, the above processing is started by exchanging command signals when the system is started, when a certain time elapses, or when an environmental change is detected.

  However, the communication partner may not store a predetermined pattern. The chip including the SERDES circuit of the embodiment performs processing for setting the strobe point to the optimum phase in the SERDES circuit, assuming such a situation.

FIG. 5 is a diagram illustrating a configuration of the SERDES circuit of the chip according to the embodiment.
The SERDES circuit according to the embodiment includes a transmission unit (Tx) 31, a reception unit (Rx) 32, a jitter generation circuit (Jitter gen) 33, a data pattern generation unit 34, an error determination unit 35, and a control unit 36. Have. The Tx 31 includes a multiplexer (MUX) that converts parallel data into serial data, a driver, and the like. The Rx 32 includes an amplifier circuit, an equalizer, a demultiplexer (DEMUX) that converts serial data into parallel data, a CDR circuit, and the like. Tx31 and Rx32 are portions normally provided in the SERDES circuit, and the description thereof is omitted.

  The jitter generation circuit 33 adds jitter corresponding to signal degradation generated in the transmission path to the data signal output from the Tx 31, and then outputs it to the reception end of the Rx32. In general, the transmission data signal output from Tx31 is switched so as not to be received by Rx32. However, in the embodiment, when performing the optimum phase setting process, Rx32 receives the signal from the jitter generation circuit 33. Can be switched to.

  The jitter generation circuit 33 is realized by, for example, a wiring in a chip having the same length as the transmission path, and generates a waveform deterioration equivalent to that when the transmission path is transmitted. However, the present invention is not limited to this, and the wiring may be realized by adding a resistor, a capacitor, an inductor, and the like. Further, the jitter generation circuit 33 may have a plurality of paths having different path lengths, and the control circuit 36 may select one of them.

  The data pattern generation unit 34 generates a data pattern for performing the optimum phase setting process and supplies the data pattern to the Tx 31. The Tx 31 outputs a signal corresponding to the data pattern, and this signal is input to the Rx 32 via the jitter generation circuit 33. The error determination unit 35 determines normality / abnormality (error) of the data received by the Rx 32 and outputs a determination result (result) to the control unit 36. The control unit 36 controls each unit to execute the optimum phase setting process, and executes a calculation process.

  The data pattern when performing the optimum phase setting process generated by the data pattern generation unit 34 is not limited to one type, and may have a plurality of patterns.

FIG. 6 is a diagram illustrating a more detailed configuration of the SERDES circuit according to the embodiment. In FIG. 6, the same parts as those in FIG.
In FIG. 6, the pattern generation / determination unit 37 is a part that combines the functions of the data pattern generation unit 34 and the error determination unit 35 of FIG. 5. The receiving unit (Rx) 32 includes an equalizer 41, a DFE 42, a phase interpolation circuit (PI) 43, and a controller 46. The controller 46 has a DEMUX 44 and a CDR 45, and also has a register and the like (not shown). A part of the equalizer 41, the PI 43, and the DFE 42 is realized by an analog circuit. The equalizer 41 is, for example, a linear equalizer (Linear Equalizer: LE), and the linear equalizer is also called a forward equalizer (Feed-Forward Equalizer: FFE). The controller 46, the remaining part of the DFE 42, and the pattern generation / determination unit 37 are realized by a logic circuit, and a part thereof is realized by a program or the like. In FIG. 6, the control unit 36 of FIG. 5 is realized by a program using the existing logic circuit of the reception unit 32. The DFE 42, the PI 43, the DEMUX 44, and the CDR 45 are widely known and the existing ones can be used, and thus detailed description thereof is omitted.

  The controller 46 forming the control unit 36 controls each unit to execute the optimum phase setting process according to the flowchart shown in FIG. The optimum phase setting process is automatically performed at any time when a predetermined time elapses or when a large environmental change such as a large temperature change occurs as an initialization process when starting up the apparatus.

  FIG. 7 is a flowchart showing the processes in steps S11, S12 and S14 excluding the calculation process in the flowchart of FIG. The process of step S16 is performed similarly to S14.

Step S21 corresponds to S11 and performs processing for setting to an initial state.
Steps S22 and S23 correspond to the process of detecting the black triangle on the right side of S12. In S22, the phase is shifted to the right by the unit amount, and it is determined whether an error has occurred in S23. S22 and S23 are repeated, and when it is determined that an error has occurred in S23, the phase of the right black triangle is determined. The unit amount for shifting the phase is determined according to the accuracy of phase adjustment. The same applies to other detection processes.

In step S24, the detected black triangle phase on the right side is stored in a register in the controller 46, and the initial phase is restored.
Steps S25 and S26 correspond to processing for detecting the phase of the black triangle on the left side of S12. Since the processing from S25 to S27 is similar to the processing from S22 to S24, description thereof will be omitted.

  Steps S28 and S29 correspond to the process of detecting the limit voltage at the black triangle phase on the left side of S14. In S28, the DFE voltage is increased by a unit amount, and it is determined in S29 whether an error has occurred. S28 and S29 are repeated, and the limit voltage is determined when it is determined that an error has occurred in S29.

In step S30, the detected limit voltage is stored in a register in the controller 46.
In FIG. 7, in order to detect an optimum phase corresponding to a plurality of inter-symbol interferences (Inter-Symbol Interference: ISI), the pattern generation / determination unit 37 can generate a plurality of ISI patterns, and according to each ISI pattern. Determine the optimal phase.

  In step S31, when the ISI attached only by the pattern (Pattern) is insufficient, the jitter generation circuit 33 in FIG. 5 adds the ISI. As a result, it is possible to detect the optimum phase assuming that the transmission loss (Loss) is large. It should be noted that step S31 need not be performed when the ISI attached by the pattern alone is sufficient.

  Although the SER / DES circuit of the chip according to the embodiment has been described above, it goes without saying that various modifications are possible. For example, the DFE in FIG. 3 has a 1-tap configuration in which data is binary and the data value to be fed back is 0 or 1, but the data is quaternary and the data value to be fed back is any one of 0 to 3. A certain 2-tap configuration may be used.

  FIG. 8 is a diagram illustrating a configuration example of a DFE having a 2-tap configuration. As shown in FIG. 3, DFE Data A-D indicates a data signal to which four different voltages are added in advance. In the DFE of FIG. 8, two stages of selection are performed using the rising and falling edges of CLK. Specifically, selection is performed in a two-stage latch circuit (Latch) by a rising edge of CLK and a rising edge of CLKX obtained by inverting CLK. The CLK speed used at this time is half the data rate (Data Rate), and 1: 2 demultiplexing can be performed in this portion.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

1A, 10B chip (integrated circuit)
11 SERDES
31 Transmitter circuit (Tx)
32 Receiver circuit (Rx)
33 Jitter generation circuit 34 Data pattern generation unit 35 Error determination unit 36 Control unit 37 Pattern generation / determination unit 41 Equalizer 42 DFE
43 Phase interpolation circuit (PI)
44 Demultiplexer (DEMUX)
45 CDR
46 controller

Claims (5)

A decision feedback equalization circuit that performs decision feedback equalization on the received data signal and captures it at the strobe point; and
Regenerating clock data from the output of the decision feedback equalization circuit, and controlling a fetch voltage level of the received data signal in the decision feedback equalization circuit;
A phase shifter that changes the phase of the strobe point;
The controller is
Controlling the phase shifter to detect both end phases of a phase range in which the received data signal can be correctly captured at the first voltage level;
Calculate the intermediate phase of the both end phases,
In one of the two end phases, a limit voltage level at which the received data signal can be correctly captured is detected,
From the other position of the both-end phase in the eye pattern and the position of the limit voltage level, calculate the slope of a straight line connecting the two positions,
Detecting an intermediate voltage level in a voltage range in which the received data signal can be correctly captured in the intermediate phase;
In the eye pattern, on a straight line passing through the intermediate phase and having the slope, a phase that is the same voltage level as the intermediate voltage level and a phase difference between the intermediate phase are calculated,
A reception circuit that executes a strobe point setting process for setting the strobe point to a phase shifted from the intermediate phase by the phase difference. A transmission / reception circuit having a transmission unit and a reception unit,
The receiver is
A decision feedback equalization circuit that performs decision feedback equalization on the received data signal and captures it at the strobe point; and
Regenerating clock data from the output of the decision feedback equalization circuit, and controlling a fetch voltage level of the received data signal in the decision feedback equalization circuit;
A phase shifter that changes the phase of the strobe point;
The controller is
Controlling the phase shifter to detect both end phases of a phase range in which the received data signal can be correctly captured at the first voltage level;
Calculate the intermediate phase of the both end phases,
In one of the two end phases, a limit voltage level at which the received data signal can be correctly captured is detected,
From the other position of the both-end phase in the eye pattern and the position of the limit voltage level, calculate the slope of a straight line connecting the two positions,
Detecting an intermediate voltage level in a voltage range in which the received data signal can be correctly captured in the intermediate phase;
In the eye pattern, on a straight line passing through the intermediate phase and having the slope, a phase that is the same voltage level as the intermediate voltage level and a phase difference between the intermediate phase are calculated,
A transmission / reception circuit that executes a strobe point setting process for setting the strobe point to a phase shifted from the intermediate phase by the phase difference. A transmission path from the transmitter to the receiver;
A data pattern generation unit that generates a data signal pattern received by the reception unit in the strobe point setting process,
The transmitter transmits a transmission data signal corresponding to the data signal pattern generated by the data pattern generator to the receiver;
The transmission / reception circuit according to claim 2, wherein the control unit determines whether a reception data signal is correctly received corresponding to the data signal pattern.   An integrated circuit comprising the receiving circuit according to claim 1.   An integrated circuit comprising the transmission / reception circuit according to claim 2.

Images