JP2016111027A - Intermediate substrate, semiconductor substrate, and manufacturing method of semiconductor substrate - Google Patents

Abstract

A technique for appropriately removing a region of a semiconductor crystal layer having a high concentration of mixed impurity atoms is provided. An intermediate substrate for transferring a semiconductor crystal layer onto an insulating layer, the semiconductor crystal layer forming substrate, a first semiconductor crystal layer, a second semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal These layers are arranged in the order of the semiconductor crystal layer forming substrate, the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer, and the first semiconductor crystal layer is Alx1Ga1 −x1As (0 <x1 ≦ 1), the second semiconductor crystal layer is made of Six2Ge1-x2 (0 ≦ x2 <x3), and the third semiconductor crystal layer is made of Six3Ge1-x3 (0.2 ≦ x3 ≦ 1). ), And the fourth semiconductor crystal layer provides an intermediate substrate made of Six4Ge1-x4 (0 ≦ x4 <x3). [Selection] Figure 3

Description

  The present invention relates to an intermediate substrate, a semiconductor substrate, and a method for manufacturing a semiconductor substrate.

  Since Group IV semiconductors such as Ge and SiGe have high hole mobility, application to the active layer (channel layer) of high-performance P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is expected. ing. High-performance P-channel MOSFETs are expected to form CMOSFETs (Complementary MOSFETs) together with high-performance N-channel MOSFETs, and such CMOSFETs exhibit performance only when they are formed on a single substrate. Therefore, a technique for forming a semiconductor crystal layer on a different substrate is required. Non-Patent Document 1 discloses a CMOSFET structure in which an N-channel MOSFET using a III-V group compound semiconductor as a channel and a P-channel MOSFET using Ge as a channel are formed on a single substrate. .

  As a technique for forming different materials such as a III-V compound semiconductor layer and a group IV semiconductor crystal layer on a single substrate (for example, a silicon substrate), a semiconductor crystal layer formed on a crystal growth substrate is formed as a single substrate. The technique of transferring to is known. For example, Non-Patent Document 2 discloses a technique in which an AlAs layer is formed as a sacrificial layer on a GaAs substrate, and the Ge layer formed on the sacrificial layer (AlAs layer) is transferred to a silicon substrate.

S. Takagi, et al., SSE, vol. 51, pp. 526-536, 2007. Y. Bai and E. A. Fitzgerald, ECS Transactions, 33 (6) 927-932 (2010)

  An N-channel MISFET (Metal-Insulator-Semiconductor Field Effect Transistor, which may be simply referred to as “nMISFET” in this specification) having a group III-V compound semiconductor as a channel, and a P-channel having a group IV semiconductor as a channel In order to form a type MISFET (sometimes simply referred to as “pMISFET” in this specification) on one substrate, a group III-V compound semiconductor for nMISFET and a group IV semiconductor for pMISFET are formed. A technique for forming on a single substrate is required. In consideration of manufacturing a single substrate as an LSI (Large Scale Integration), a III-V group compound semiconductor crystal layer for nMISFET and a pMISFET on a silicon substrate capable of utilizing existing manufacturing equipment and existing processes. It is preferable to form a group IV semiconductor crystal layer.

  A III-V group compound single crystal substrate such as GaAs is used as the semiconductor crystal layer formation substrate, and a III-V group compound semiconductor crystal such as AlAs is used as a sacrificial layer when the semiconductor crystal layer is peeled off from the semiconductor crystal layer formation substrate by etching. A semiconductor crystal layer for transfer may be formed by epitaxially growing a group IV semiconductor such as Ge using a layer. A group III atom such as Ga and a group V atom such as As may function as a donor or acceptor inside a group IV semiconductor such as Ge. Therefore, when the semiconductor crystal layer is formed by epitaxial growth, it is necessary to avoid contamination of unintended impurity atoms from the semiconductor crystal layer forming substrate or the sacrificial layer as much as possible.

  However, since it is unavoidable that a certain amount of impurity atoms are mixed, a technique for reducing the influence of the mixed impurity atoms is important. For example, when the contamination of impurity atoms is mainly contamination from the semiconductor crystal layer formation substrate, the concentration of impurity atoms inside the semiconductor crystal layer is higher as it is closer to the semiconductor crystal layer formation substrate and lower as it is farther away. . Therefore, after transferring the semiconductor crystal layer to the transfer destination substrate, a portion containing a large amount of impurity atoms is removed by etching or the like, and a portion of the semiconductor crystal layer having a low concentration of impurity atoms is used as a channel layer, thereby achieving high performance. A pMISFET can be formed.

  However, in the semiconductor crystal layer on the transfer destination substrate, it is difficult to appropriately remove only the portion containing a large amount of impurity atoms, resulting in a variation in the thickness of the semiconductor crystal layer.

  An object of the present invention is to provide a technique for reducing the influence of impurity atoms mixed in a semiconductor crystal layer on a transfer destination substrate. In particular, it is an object to provide a technique for appropriately removing a region of a semiconductor crystal layer having a high concentration of mixed impurity atoms.

In order to solve the above problems, in a first aspect of the present invention, there is provided an intermediate substrate for transferring a semiconductor crystal layer onto an insulating layer, the semiconductor crystal layer forming substrate, the first semiconductor crystal layer, the second A semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal layer, the semiconductor crystal layer forming substrate; the first semiconductor crystal layer; the second semiconductor crystal layer; the third semiconductor crystal layer; A semiconductor crystal layer is disposed in the order of the semiconductor crystal layer forming substrate, the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer, and the first semiconductor crystal layer Is made of Al _x1 Ga _1-x1 As (0 <x1 ≦ 1), the second semiconductor crystal layer is made of Si _x2 Ge _1-x2 (0 ≦ x2 <x3), and the third semiconductor crystal layer is made of _{, Si x3 Ge 1-x3 (} 0 Consists 2 ≦ x3 ≦ 1), said fourth semiconductor crystal _layer, providing an intermediate substrate made of _{Si x4 Ge 1-x4 (0} ≦ x4 <x3).

When HCl is used as the etchant, the etching rate of the first semiconductor crystal layer is any one of the semiconductor crystal layers selected from the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer. Can be larger. The etching rate of the second semiconductor crystal layer in the case of using a mixed liquid in which HCl, H ₂ O ₂ and H ₂ O are mixed at a molar ratio of 4: 1: 95 as the etchant is the etching rate of the third semiconductor crystal layer. It can be greater than the speed. The etching rate of the third semiconductor crystal layer when HF is used as the etchant may be higher than the etching rate of the fourth semiconductor crystal layer. The fourth semiconductor crystal layer may have a surface roughness of 1 nm or less. When the fourth semiconductor crystal layer is a Ge layer, the Si composition x3 of the third semiconductor crystal layer and the thickness t (nm) of the third semiconductor crystal layer are 0 <t <2.5 · x3 ^{−1. .25} relationship can be satisfied.

In the second aspect of the present invention, the semiconductor device includes a substrate, an insulating layer on the substrate, and a fourth semiconductor crystal layer on the insulating layer, and the fourth semiconductor crystal layer is Si _x4 Ge. _1-x4 (0 ≦ x4 <1), containing one or more atoms selected from As and Ga in a range of 1 × 10 ¹⁶ [cm ⁻³ ] to 5 × 10 ¹⁸ [cm ⁻³ ] A semiconductor substrate is provided.

  The concentration of one or more atoms selected from As and Ga contained in the fourth semiconductor crystal layer is reduced or increased as it proceeds from the surface side of the fourth semiconductor crystal layer to the substrate side. can do.

  In a third aspect of the present invention, a step of sequentially growing a first semiconductor crystal layer, a second semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal layer on a semiconductor crystal layer formation substrate; Facing the surface of the fourth semiconductor crystal layer and the surface of the transfer destination substrate or the surface of the layer formed on the transfer destination substrate, and bonding the semiconductor crystal layer forming substrate and the transfer destination substrate; The first semiconductor crystal layer is removed by etching, and the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer are left on the transfer destination substrate, and the semiconductor crystal layer forming substrate and the There is provided a method of manufacturing a semiconductor substrate, comprising: separating a transfer destination substrate; and etching the second semiconductor crystal layer.

  The etching rate of the second semiconductor crystal layer in the step of etching the second semiconductor crystal layer may be higher than the etching rate of the third semiconductor crystal layer. The method may further include a step of etching the third semiconductor crystal layer. In this case, the etching rate of the third semiconductor crystal layer in the step may be higher than the etching rate of the fourth semiconductor crystal layer. it can.

A cross section of a semiconductor substrate 100 is shown. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps, and also shows a cross section of the intermediate substrate 200. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor substrate 100 in the order of steps. It is the graph which showed the depth profile of As atom concentration. It is the graph which showed the relationship between the etching depth when changing the silicon composition and thickness of a 3rd semiconductor crystal layer, and etching time. It is the table | surface which showed the photograph which microscopically observed the substrate surface when changing the silicon composition and thickness of a 3rd semiconductor crystal layer. It is the table | surface which showed the result of having measured the roughness of the substrate surface when changing the silicon composition and thickness of a 3rd semiconductor crystal layer.

  FIG. 1 shows a cross section of a semiconductor substrate 100. The semiconductor substrate 100 includes a substrate (transfer destination substrate) 114, an insulating layer 112, and a fourth semiconductor crystal layer 110.

  The substrate (transfer destination substrate) 114 is, for example, a Si substrate, and is a transfer destination substrate in a bonding method, as will be described later. The insulating layer 112 is a silicon oxide layer, for example, and electrically insulates between the fourth semiconductor crystal layer 110 and the substrate 114. The insulating layer 112 can reduce the stray capacitance of an electronic device such as a MISFET formed in the fourth semiconductor crystal layer 110 and improve the device performance.

The fourth semiconductor crystal layer 110 is, for example, a Ge layer, and an electronic element such as a MISFET is formed and functions as an active layer of the electronic element. In the fourth semiconductor crystal layer 110, as will be described later, impurity atoms are reduced, and the performance of an electronic element formed there is improved. The fourth semiconductor crystal layer 110 is made of Si _x4 Ge _1-x4 (0 ≦ x4 <1), and one or more atoms selected from As and Ga are 1 × 10 ¹⁶ [cm ⁻³ ] or more and 5 × 10. ¹⁸ [cm ⁻³ ] It is contained in the following range.

  The upper limit of the Si composition x4 of the fourth semiconductor crystal layer 110 varies depending on the relationship with the thickness of the fourth semiconductor crystal layer 110. When the fourth semiconductor crystal layer 110 may be thin, the upper limit of x4 can be increased. However, when the fourth semiconductor crystal layer 110 needs to be thicker, the upper limit of x4 cannot be increased too much. That is, the Si composition x4 of the fourth semiconductor crystal layer 110 can be appropriately selected within a limit range derived from the thickness of the fourth semiconductor crystal layer 110.

  The fourth semiconductor crystal layer 110 contains one or more atoms selected from As and Ga. The concentration of the atoms decreases or increases as it proceeds from the surface side of the fourth semiconductor crystal layer 110 to the substrate side. The depth direction profile of the concentration of As atoms will be described in detail later.

  2 to 8 are cross-sectional views showing the method of manufacturing the semiconductor substrate 100 in the order of steps.

  As shown in FIG. 2, the first semiconductor crystal layer 104 is formed on the semiconductor crystal layer formation substrate 102.

  The semiconductor crystal layer forming substrate 102 is a substrate for forming the high-quality fourth semiconductor crystal layer 110. A preferable material of the semiconductor crystal layer forming substrate 102 depends on a material, a forming method, and the like of the fourth semiconductor crystal layer 110. In general, the semiconductor crystal layer forming substrate 102 is preferably made of a material that lattice matches or pseudo-lattice matches with the fourth semiconductor crystal layer 110 to be formed. For example, when a Ge layer is formed as the fourth semiconductor crystal layer 110 by an epitaxial growth method, the semiconductor crystal layer formation substrate 102 is preferably a GaAs single crystal substrate, and a single crystal substrate of InP, sapphire, Ge, or SiC can be selected. It is. When the semiconductor crystal layer forming substrate 102 is a GaAs single crystal substrate, the plane orientation on which the fourth semiconductor crystal layer 110 is formed includes the (100) plane or the (111) plane.

The first semiconductor crystal layer 104 is made of Al _x1 Ga _1-x1 As (0 <x1 ≦ 1). For example, the first semiconductor crystal layer 104 may be any semiconductor crystal layer selected from the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 at an etching rate when HCl is used as the etchant. The etching rate may be greater than For etching, wet etching using an aqueous hydrochloric acid solution as an etchant (etching solution), dry etching using an etching gas, or the like can be applied.

By setting the first semiconductor crystal layer 104 to Al _x1 Ga _1-x1 As (0 <x1 ≦ 1), the first semiconductor crystal layer 104 is changed to the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 104. The semiconductor crystal layer 110 can function as a sacrificial layer for transferring to the transfer destination substrate.

  The first semiconductor crystal layer 104 includes the semiconductor crystal layer formation substrate 102, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 (hereinafter simply referred to as “fourth semiconductor crystal layer 110 etc.”). It is a layer for separating. By removing the first semiconductor crystal layer 104 by etching, the semiconductor crystal layer formation substrate 102 and the fourth semiconductor crystal layer 110 and the like are separated.

  When the first semiconductor crystal layer 104 is etched, it is necessary that at least a part of the semiconductor crystal layer formation substrate 102, the fourth semiconductor crystal layer 110, and the like remain without being etched. For this reason, the etching rate of the first semiconductor crystal layer 104 needs to be higher than the etching rates of the semiconductor crystal layer forming substrate 102, the fourth semiconductor crystal layer 110, and the like, and is preferably several times higher. When a GaAs single crystal substrate is selected as the semiconductor crystal layer forming substrate 102 and a Ge layer is selected as the fourth semiconductor crystal layer 110 or the like, the first semiconductor crystal layer 104 is preferably an AlAs layer. When the thickness of the first semiconductor crystal layer 104 increases, the crystallinity of the fourth semiconductor crystal layer 110 and the like tends to decrease. Therefore, the thickness of the first semiconductor crystal layer 104 can ensure the function as a sacrificial layer. It is preferable to be as thin as possible. The thickness of the first semiconductor crystal layer 104 can be selected in the range of 0.1 nm to 10 μm.

The first semiconductor crystal layer 104 can be formed by an epitaxial growth method, a CVD (Chemical Vapor Deposition) method, a sputtering method, or an ALD (Atomic Layer Deposition) method. As the epitaxial growth method, a MOCVD (Metal Organic Chemical Vapor Deposition) method or an MBE (Molecular Beam Epitaxy) method can be used. When the first semiconductor crystal layer 104 is formed by MOCVD, TMGa (trimethyl gallium), TEGa (triethyl gallium), TMA (trimethyl aluminum), TMIn (trimethyl indium), AsH ₃ (arsine), PH _{3 are used} as source gases. (Phosphine) or the like can be used. Hydrogen can be used as the carrier gas. A compound in which a part of a plurality of hydrogen atom groups of the source gas is substituted with a chlorine atom or a hydrocarbon group can also be used. The growth temperature (also referred to as reaction temperature) can be appropriately selected in the range of 300 ° C to 900 ° C, preferably in the range of 400 to 800 ° C. The thickness of the first semiconductor crystal layer 104 can be controlled by appropriately selecting the source gas supply amount and the reaction time.

  As shown in FIG. 3, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are sequentially epitaxially grown on the first semiconductor crystal layer 104.

The second semiconductor crystal layer 106 is made of Si _x2 Ge _1-x2 (0 ≦ x2 <x3). The second semiconductor crystal layer 106 has an etching rate of, for example, the third semiconductor crystal layer when using a mixed liquid in which HCl, H ₂ O _2, and H ₂ O are mixed in a molar ratio of 4: 1: 95 as an etchant. It can be greater than 108 etch rates. For etching, wet etching using a mixed solution of hydrochloric acid, hydrogen peroxide, and water as an etchant (etching solution), dry etching using an etching gas, or the like can be applied.

The third semiconductor crystal layer 108 is made of Si _x3 Ge _1-x3 (0.2 ≦ x3 ≦ 1). For example, the third semiconductor crystal layer 108 may have an etching rate higher than that of the fourth semiconductor crystal layer 110 when HF is used as an etchant. Note that wet etching using a hydrofluoric acid aqueous solution as an etchant (etching solution), dry etching using an etching gas, or the like can be applied to the etching.

By setting the second semiconductor crystal layer 106 to Si _x2 Ge _1-x2 (0 ≦ x2 <x3) and the third semiconductor crystal layer 108 to Si _x3 Ge _1-x3 (0.2 ≦ x3 ≦ 1), The third semiconductor crystal layer 108 can function as an etching stopper when the second semiconductor crystal layer 106 is etched.

The fourth semiconductor crystal layer 110 is made of Si _x4 Ge _1-x4 (0 ≦ x4 <x3). By setting the fourth semiconductor crystal layer 110 to Si _x4 Ge _1-x4 (0 ≦ x4 <x3), the etching resistance of the fourth semiconductor crystal layer 110 is increased when the third semiconductor crystal layer 108 is etched, 4 Disappearance due to etching of the semiconductor crystal layer 110 can be suppressed.

The surface roughness of the fourth semiconductor crystal layer 110 is 1 nm or less. When the fourth semiconductor crystal layer 110 is a Ge layer, the Si composition x3 of the third semiconductor crystal layer 108 and the thickness t (nm) of the third semiconductor crystal layer 108 are 0 <t <2.5 · x3. ^-1.25 can be satisfied. By satisfying such a relationship, the surface roughness of the fourth semiconductor crystal layer 110 can be kept low.

  The second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 (the fourth semiconductor crystal layer 110 and the like) are transfer target layers to be transferred to a transfer destination substrate described later. The fourth semiconductor crystal layer 110 and the like are formed on the semiconductor crystal layer formation substrate 102 by an epitaxial growth method or the like, whereby the crystallinity of the fourth semiconductor crystal layer 110 is realized with high quality. Furthermore, by transferring the fourth semiconductor crystal layer 110 or the like to the transfer destination substrate, the high-quality fourth semiconductor crystal layer 110 can be placed on any transfer destination substrate without considering lattice matching with the transfer destination substrate. Can be formed.

Examples of the fourth semiconductor crystal layer 110 include Si _x Ge _1-x (0 ≦ x <1). More specifically, the case of x = 0 can be mentioned. That is, Ge is mentioned. When the fourth semiconductor crystal layer 110 is Si _x Ge _1-x (0 <x <1), the Si composition ratio x of Si _x Ge _1-x is preferably 0.1 or less. By setting the Si composition ratio to 0.1 or less, semiconductor characteristics close to Ge can be obtained.

  The thickness of the fourth semiconductor crystal layer 110 can be appropriately selected within the range of 0.1 nm to 500 μm. The thickness of the fourth semiconductor crystal layer 110 is preferably not less than 0.1 nm and less than 1 μm. By setting the thickness of the fourth semiconductor crystal layer 110 to less than 1 μm, it can be used for a composite substrate suitable for manufacturing a high-performance transistor such as an ultra-thin body MISFET.

The second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 can be formed by an epitaxial growth method or an ALD method. As the epitaxial growth method, a CVD method or an MBE method can be used. When the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are made of a group IV compound semiconductor and are formed by a CVD method, GeH ₄ (germane), SiH ₄ (silane) are used as source gases. Alternatively, Si ₂ H ₆ (disilane) or the like can be used. Hydrogen can be used as the carrier gas. A compound in which a part of a plurality of hydrogen atom groups of the source gas is substituted with a chlorine atom or a hydrocarbon group can also be used. The growth temperature can be appropriately selected in the range of 300 ° C to 900 ° C, preferably in the range of 400 to 800 ° C. The thicknesses of the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 can be controlled by appropriately selecting the source gas supply amount and the reaction time.

  Note that a substrate having the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 on the semiconductor crystal layer formation substrate 102 is used for forming the semiconductor substrate 100. It can be grasped as the intermediate substrate 200. The intermediate substrate 200 includes a semiconductor crystal layer forming substrate 102, a first semiconductor crystal layer 104, a second semiconductor crystal layer 106, a third semiconductor crystal layer 108, and a fourth semiconductor crystal layer 110. The semiconductor crystal layer formation substrate 102, the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are composed of the semiconductor crystal layer formation substrate 102, the first semiconductor crystal layer 104, The second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are arranged in this order.

  As shown in FIG. 4, the surface of the fourth semiconductor crystal layer 110 and the surface of the transfer destination substrate 114 face each other, and the semiconductor crystal layer forming substrate 102 and the transfer destination substrate 114 are bonded together as shown in FIG. . Note that the insulating layer 112 may be formed on the surface of the transfer destination substrate 114 or the surface of the fourth semiconductor crystal layer 110. FIG. 4 shows an example in which the insulating layer 112 is formed on the surface of the fourth semiconductor crystal layer 110, but the present invention is not limited to this, and the insulating layer 112 may be formed on the surface of the transfer destination substrate 114.

  The transfer destination substrate 114 is a substrate to which the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are transferred. The transfer destination substrate 114 may be a target substrate on which an electronic device that uses the fourth semiconductor crystal layer 110 as an active layer is finally disposed. Until the fourth semiconductor crystal layer 110 is transferred to the target substrate. It may be a temporary placement substrate in an intermediate state. That is, the fourth semiconductor crystal layer 110 may be further transferred from the transfer destination substrate 114 to another substrate. The transfer destination substrate 114 may be made of either an organic material or an inorganic material. Examples of the transfer destination substrate 114 include a silicon substrate, an SOI (Silicon on Insulator) substrate, a glass substrate, a sapphire substrate, an SiC substrate, and an AlN substrate. In addition, the transfer destination substrate 114 may be an insulating substrate such as a ceramic substrate or a plastic substrate, or a conductive substrate such as a metal. When a silicon substrate or an SOI substrate is used as the transfer destination substrate 114, a manufacturing apparatus used in an existing silicon process can be used, and knowledge of the known silicon process can be used to improve research and development and manufacturing efficiency.

  When the transfer destination substrate 114 is a hard substrate that is not easily bent, such as a silicon substrate, the fourth semiconductor crystal layer 110 to be transferred is protected from mechanical vibration and the like, and the crystal quality of the fourth semiconductor crystal layer 110 is increased. Can keep. When the transfer destination substrate 114 is a flexible substrate such as plastic, the flexible substrate is bent away from the semiconductor crystal layer forming substrate 102 in the etching process of the first semiconductor crystal layer 104 described later. The etching solution can be supplied quickly, and the transfer destination substrate 114 and the semiconductor crystal layer forming substrate 102 can be quickly separated.

  As shown in FIG. 6, the first semiconductor crystal layer 104 is removed by etching, and the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 110 are left on the transfer destination substrate 114. The semiconductor crystal layer forming substrate 102 and the transfer destination substrate 114 are separated. The separated semiconductor crystal layer forming substrate 102 can be reused after appropriate processing.

  As shown in FIG. 7, the second semiconductor crystal layer 106 is removed by etching. Here, the etching rate of the second semiconductor crystal layer 106 is higher than the etching rate of the third semiconductor crystal layer 108. As a result, the third semiconductor crystal layer 108 functions as an etching stopper as described above.

  As shown in FIG. 8, the third semiconductor crystal layer 108 is removed by etching, and the semiconductor substrate 100 shown in FIG. 1 is obtained. Here, the etching rate of the third semiconductor crystal layer 108 is higher than the etching rate of the fourth semiconductor crystal layer 110. Thereby, etching until the fourth semiconductor crystal layer 110 is exposed can be performed with good controllability, and variation in the thickness of the fourth semiconductor crystal layer 110 can be suppressed to a low level.

  According to the semiconductor substrate manufacturing method described above, since the semiconductor substrate is formed at a position distant from the semiconductor crystal layer forming substrate 102, only the fourth semiconductor crystal layer 110 with little impurity atom mixing is left, leaving the third semiconductor crystal layer. 108 and the second semiconductor crystal layer 106 can be etched with good controllability. As a result, variation in the thickness of the fourth semiconductor crystal layer 110 having a low impurity concentration can be reduced.

(Example)
As the semiconductor crystal layer forming substrate 102, a GaAs substrate having a crystal growth surface with a plane orientation of (100) and an off angle of 2 ° was used. On the GaAs substrate, as a first semiconductor crystal layer 104, a second semiconductor crystal layer 106, a third semiconductor crystal layer 108, and a fourth semiconductor crystal layer 110, an AlAs layer having a thickness of 20 nm and a Ge layer having a thickness of 570 nm, respectively. Then, an SiGe layer having a thickness of 6.5 nm, an Si composition of 0.29, and a Ge layer having a thickness of 550 nm were sequentially formed by an epitaxial growth method to produce an intermediate substrate.

In the epitaxial growth of the AlAs layer, TMA (trimethylaluminum), AsH ₃ (arsine) and hydrogen were used as source gases, and the substrate temperature was set to 600 ° C. In the epitaxial growth of the Ge layer, GeH ₄ (german) and hydrogen were used as source gases, and the substrate temperature was set to 650 ° C. In the epitaxial growth of the SiGe layer, SiH ₄ (silane), GeH ₄ and hydrogen were used as source gases, and the substrate temperature was 600 ° C.

  As a comparative example, the thickness of the SiGe layer was 11 nm, the Si composition was 0.18, and the others were the same as above, the thickness of the SiGe layer was 11 nm, the Si composition was 0.29, and the others were the same as above, A SiGe layer having a thickness of 22 nm and a Si composition of 0.18 was otherwise prepared, and a SiGe layer having a thickness of 22 nm and a Si composition of 0.29 was prepared.

  FIG. 9 is a graph showing a depth profile of As atom concentration. It can be seen that the As concentration is higher near the GaAs substrate. That is, by using the intermediate substrate of this embodiment and extracting only the Ge layer far from the GaAs substrate, the quality of the Ge layer can be improved and a high-performance p-type MISFET can be produced.

  FIG. 10 is a graph showing the relationship between the etching depth and the etching time when the silicon composition and thickness of the third semiconductor crystal layer are changed. From the figure, it is considered that the etching is not stopped and the function as an etching stopper is not sufficient for the Si composition of 0.18. On the other hand, for the Si composition of 0.29, the etching is stopped and the function as an etching stopper is considered to be sufficient.

  FIG. 11 is a table showing a microscopic observation of the substrate surface when the silicon composition and thickness of the third semiconductor crystal layer are changed. FIG. 12 is a table showing the results of measuring the roughness of the substrate surface when the silicon composition and thickness of the third semiconductor crystal layer were changed. From the figure, dislocation occurs when the thickness of the SiGe layer as the third semiconductor crystal layer reaches 22 nm, and when the thickness decreases to 11 nm, dislocation is not observed at Si composition of 0.18. In the case of 0.29, dislocations are still observed. As the thickness decreases to 6.5 nm, dislocations are not observed even when the Si composition is 0.29. Further, FIG. 12 shows that the surface roughness decreases as the dislocation is reduced.

  In summary, under the conditions of this example, when the thickness of the SiGe layer is 6.5 nm and the Si composition is 0.29, it functions as an etching stopper, has no dislocations, and has a sufficiently flat surface roughness. It can be said that an intermediate substrate was obtained. As the Si composition decreases, the function as an etching stopper decreases, and as the thickness of the third semiconductor crystal layer increases, dislocation increases and surface roughness deteriorates. That is, it can be said that there is an optimum region for the combination of the thickness of the SiGe layer and the Si composition.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 102 ... Semiconductor crystal layer formation substrate, 104 ... 1st semiconductor crystal layer, 106 ... 2nd semiconductor crystal layer, 108 ... 3rd semiconductor crystal layer, 110 ... 4th semiconductor crystal layer, 112 ... Insulating layer, 114: Transfer destination substrate.

Claims (11)

An intermediate substrate for transferring a semiconductor crystal layer onto an insulating layer,
A semiconductor crystal layer forming substrate, a first semiconductor crystal layer, a second semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal layer;
The semiconductor crystal layer formation substrate, the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer are the semiconductor crystal layer formation substrate, the first semiconductor crystal layer, The second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer are arranged in this order,
The first semiconductor crystal layer is made of Al _x1 Ga _1-x1 As (0 <x1 ≦ 1),
The second semiconductor crystal layer is made of Si _x2 Ge _1-x2 (0 ≦ x2 <x3);
The third semiconductor crystal layer is made of Si _x3 Ge _1-x3 (0.2 ≦ x3 ≦ 1);
The intermediate substrate, wherein the fourth semiconductor crystal layer is made of Si _x4 Ge _1-x4 (0 ≦ x4 <x3). When HCl is used as the etchant, the etching rate of the first semiconductor crystal layer is any one of the semiconductor crystal layers selected from the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer. The intermediate substrate according to claim 1. The etching rate of the second semiconductor crystal layer in the case of using a mixed liquid in which HCl, H ₂ O ₂ and H ₂ O are mixed at a molar ratio of 4: 1: 95 as the etchant is the etching rate of the third semiconductor crystal layer. The intermediate substrate according to claim 1 or 2, wherein the intermediate substrate is larger than a speed. The intermediate substrate according to any one of claims 1 to 3, wherein an etching rate of the third semiconductor crystal layer when HF is used as an etchant is higher than an etching rate of the fourth semiconductor crystal layer. The intermediate substrate according to any one of claims 1 to 4, wherein a surface roughness of the fourth semiconductor crystal layer is 1 nm or less. The fourth semiconductor crystal layer is a Ge layer;
The Si composition x3 of the third semiconductor crystal layer and the thickness t (nm) of the third semiconductor crystal layer are:
(Equation 1)
0 <t <2.5 · x3 ^−1.25
The intermediate substrate according to any one of claims 1 to 5, wherein the relationship is satisfied. A substrate, an insulating layer on the substrate, and a fourth semiconductor crystal layer on the insulating layer,
The fourth semiconductor crystal layer is made of Si _x4 Ge _1-x4 (0 ≦ x4 <1), and one or more atoms selected from As and Ga are 1 × 10 ¹⁶ [cm ⁻³ ] or more and 5 × 10. ¹⁸ [cm ⁻³ ] A semiconductor substrate contained in the following range. The concentration of one or more atoms selected from As and Ga contained in the fourth semiconductor crystal layer is decreased or increased as the concentration proceeds from the surface side of the fourth semiconductor crystal layer to the substrate side. 8. The semiconductor substrate according to 7. Sequentially epitaxially growing a first semiconductor crystal layer, a second semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal layer on a semiconductor crystal layer forming substrate;
Facing the surface of the fourth semiconductor crystal layer and the surface of the transfer destination substrate or the surface of the layer formed on the transfer destination substrate, and bonding the semiconductor crystal layer forming substrate and the transfer destination substrate;
The first semiconductor crystal layer is removed by etching, and the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer are left on the transfer destination substrate. Separating the transfer destination substrate;
Etching the second semiconductor crystal layer;
The manufacturing method of the semiconductor substrate which has this. The method for manufacturing a semiconductor substrate according to claim 9, wherein an etching rate of the second semiconductor crystal layer in the step of etching the second semiconductor crystal layer is higher than an etching rate of the third semiconductor crystal layer. Etching the third semiconductor crystal layer;
11. The method of manufacturing a semiconductor substrate according to claim 9, wherein an etching rate of the third semiconductor crystal layer in the step is higher than an etching rate of the fourth semiconductor crystal layer.