JP2016100748A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of reducing sharp changes in oscillation signal.SOLUTION: The oscillation circuit has a discrimination part (16; 116; 216) that determines which of a first timer and a second timer (27, 28;127, 128;227, 228) does not perform time measurement. The oscillation is circuit configured so that the object timer (27 or 28;127 or 128;227 or 228) in the first timer and the second timer, which is determined as no-time measurement operation by the discrimination part, the characteristics of which can be adjusted by an adjusting section (4 or 16;104 or 116; 204 or 216) during the non-time measurement.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an oscillation circuit.

  This type of oscillation circuit is used, for example, to generate a clock signal (see, for example, Patent Document 1). According to the technique described in Patent Document 1, switching between charge and discharge of a capacitor is performed using a logic circuit including two comparators and a flip-flop circuit.

JP 2003-101389 A

In the case of dynamically adjusting the frequency / duty ratio of the oscillation circuit using the circuit described in Patent Document 1, for example, there is a method of adjusting the reference voltage or the charging current of the capacitor. Then, when the glitch is generated in the oscillation signal or the duty ratio is abruptly changed, the oscillation signal may be abruptly changed, and a circuit for inputting the oscillation signal may be erroneously operated.
An object of the present invention is to provide an oscillation circuit capable of suppressing a steep fluctuation of an oscillation signal.

  According to the first aspect of the present invention, the charging unit charges the output current of the current output unit, and the comparison unit compares the charging voltage of the charging unit with a predetermined voltage. The first time measuring unit measures the time until the charging voltage of the charging unit reaches a predetermined voltage by the comparison unit. Further, the second time measuring unit measures the time until the charging voltage of the charging unit reaches a predetermined voltage by the comparing unit when the time measuring operation is not performed by the first time measuring unit. The output unit outputs an oscillation signal according to the time measurement results of the first and second time measurement units. The determination circuit determines which of the first and second time measurement units is not measuring time. Then, the adjustment unit adjusts the characteristic of the target time measurement unit that is determined not to measure time by the determination circuit during the non-time measurement.

  For example, since the adjustment unit adjusts the characteristics of the second time measurement unit while the first time measurement unit is performing the time measurement operation, the second time measurement unit is in a period that does not affect the output of the oscillation signal. Can be adjusted. Thereby, a steep fluctuation of the oscillation signal can be suppressed. On the contrary, since the adjustment unit adjusts the characteristics of the first time measurement unit while the second time measurement unit is performing the time measurement operation, the first time measurement is performed during a period that does not affect the output of the oscillation signal. The characteristics of the part can be adjusted. Thereby, a steep fluctuation of the oscillation signal can be suppressed.

Electrical configuration diagram schematically showing an example of the system of the first embodiment Electrical configuration diagram schematically showing an internal configuration example of an oscillation circuit Electrical configuration diagram schematically showing a configuration example of the first and second capacitors Timing chart schematically showing the relationship between the sync pulse signal and the oscillation signal of the oscillation circuit Timing chart schematically showing frequency / duty ratio adjustment example Electrical configuration diagram schematically showing an internal configuration example of the oscillation circuit in the second embodiment Circuit diagram schematically showing the configuration for adjusting the mirror ratio between the input and output transistors Timing chart schematically showing frequency / duty ratio adjustment example Electrical configuration diagram schematically showing an internal configuration example of the oscillation circuit in the third embodiment A circuit diagram schematically showing a configuration for adjusting a predetermined voltage to be compared by the comparison unit Timing chart schematically showing frequency / duty ratio adjustment example Timing chart schematically showing an example of frequency / duty ratio adjustment in the fourth embodiment

  Hereinafter, some embodiments of the oscillation circuit will be described with reference to the drawings. In the embodiments, the same or similar components are denoted by the same or similar reference numerals, and the description of the second and subsequent embodiments is omitted as necessary.

(First embodiment)
In each embodiment described below, as shown in FIG. 1, a mode applied to an oscillation circuit 3 in a slave 2 connected to a vehicle master ECU (Electronic Control Unit) 1 will be described. The slave 2 includes an oscillation circuit 3, a CPU 4, a receiver 5, and a transmitter 6, part or all of which are integrated into an integrated circuit. The CPU 4 is based on a sync pulse signal supplied from the external ECU 1. The frequency of the clock signal (equivalent to the oscillation signal) output from the oscillation circuit 3 can be controlled to be changed.

  As shown in FIG. 2, the oscillation circuit 3 includes a reference voltage output unit 7, a voltage / current conversion unit 8, a current mirror circuit 9, first and second variable capacitors (equivalent to first and second capacitors) 10 and 11, First and second comparators 12 and 13, first and second valid / invalid switching circuits 14, a flip-flop circuit 15 as an output unit, and a discrimination circuit (equivalent to an adjustment unit and a discrimination unit) 16 are provided. The reference voltage output unit 7 is configured by connecting a plurality of resistors 19 and 20 in series between a power supply terminal 17 and a ground (corresponding to a first power supply line) 18, and is output by, for example, a band gap reference circuit (not shown). A highly accurate bandgap reference voltage is divided by a plurality of resistors 19 and 20 and output as a reference voltage.

  The voltage-current converter 8 is configured by combining, for example, an operational amplifier 21, an N-channel MOS transistor 22, and a resistor 23 in the illustrated form. The voltage-current conversion unit 8 inputs the output reference voltage of the reference voltage output unit 7 to the non-inverting input terminal of the operational amplifier 21, connects the gate of the MOS transistor 22 to the output of the operational amplifier 21, and resistance from the source of the MOS transistor 22 to the resistor The ground 18 is energized via the power supply 23, and the terminal voltage of the resistor 23 is connected to the inverting input terminal of the operational amplifier 21 for feedback. Thereby, the voltage-current converter 8 can output a current corresponding to the reference voltage of the reference voltage output unit 7.

  The output of the voltage / current converter 8 is input to the current mirror circuit 9. The current mirror circuit 9 includes, for example, an input transistor 24 and first and second output transistors 25 and 26 as current output units connected to the input transistor 24 as a current mirror. The mirror ratio between the input transistor 24 and the first output transistor 25 is set to a predetermined first value, and the mirror ratio between the input transistor 24 and the second output transistor 26 is set to a predetermined second value. These first value and second value may be set to the same value or different values.

  The output current of the first output transistor 25 is input to the first variable capacitor 10 serving as a charging unit. The first variable capacitor 10 is configured to be capable of changing a capacitance value according to a control signal supplied from the determination circuit 16 and charges the output current of the first output transistor 25. The first comparator 12 compares the band gap reference voltage VBGR (corresponding to the first voltage) with the charging voltage of the first variable capacitor 10 and outputs the comparison result to the first input terminal of the flip-flop circuit 15.

  The output current of the second output transistor 26 is input to the second variable capacitor 11 serving as a charging unit. The second variable capacitor 11 is configured to be capable of changing the capacitance value in accordance with a control signal given from the determination circuit 16 and charges the output current of the second output transistor 26. The second comparator 13 compares the band gap reference voltage VBGR (corresponding to the first voltage) with the charging voltage of the second variable capacitor 11 and outputs the comparison result to the second input terminal of the flip-flop circuit 15.

The flip-flop circuit 15 is configured by, for example, an inverting input type RS flip-flop, and continues to output the first level “H” to the output terminal OUT when the “L” pulse is input to the first input terminal (set terminal). When the “L” pulse is input to the second input terminal (reset terminal), the second level “L” is continuously output to the output terminal OUT. As a result, the flip-flop circuit 15 functions as an output unit that outputs a clock signal corresponding to the time measurement results of the first time measurement unit 27 and the second time measurement unit 28.
The first output transistor 25, the first variable capacitor 10, and the first comparator 12 operate as the first time measurement unit 27. The second output transistor 26, the second variable capacitor 11, and the second comparator 13 operate as the second time measuring unit 28.

  The valid / invalid switching circuit 14 is configured by combining, for example, N-channel type MOS transistors 29 and 30, a NOT gate 31, and the like, and the first and second variable capacitors 10, 11 according to the output level of the output terminal OUT. Open / short circuit the terminal. As a result, the inverting input terminals of the first and second comparators 12 and 13 are opened / short-circuited, and the first and second time measuring units 27 and 28 are switched between valid / invalid. For example, when the output level of the output terminal OUT is the first level “H”, the MOS transistor 29 is turned on, whereby the charging voltage of the first variable capacitor 10 is discharged and the voltage of the inverting input terminal of the first comparator 12 is discharged. Is fixed at 0V. As a result, the operation of the first time measuring unit 27 is invalidated. At the same time, when the MOS transistor 30 is turned off, the inverting input terminal of the second comparator 13 is opened by opening the terminals of the second variable capacitor 11, and the operation of the second time measuring unit 28 is activated. Is done.

  On the contrary, when the output level of the output terminal OUT is the second level “L”, the MOS transistor 30 is turned on, so that the charging voltage of the second variable capacitor 11 is discharged, and the operation of the second time measuring unit 28 is performed. It is invalidated. At the same time, when the MOS transistor 29 is turned off, the terminal of the first variable capacitor 10 is opened, and the operation of the first time measuring unit 27 is validated.

The determination circuit 16 determines whether the first time measurement unit 27 is operating or the second time measurement unit 28 is operating according to the output result of the flip-flop circuit 15, for example.
Further, the CPU 4 is connected to the output terminal OUT. The CPU 4 has a built-in counter and can count pulses of the clock signal output from the oscillation circuit 3. The CPU 4 determines whether the frequency / duty ratio of the clock signal output from the oscillation circuit 3 is within a predetermined range according to the output period of the level “H” or “L” of the output clock signal from the output terminal OUT. If it is not within the predetermined range, an adjustment signal is output to the discrimination circuit 16.

  When the adjustment signal is input from the CPU 4, the determination circuit 16 adjusts the characteristics of the first time measurement unit 27 and the second time measurement unit 28 according to the operation determination results of the first and second time measurement units 27 and 28. The timing is determined, and the characteristics of the target time measurement unit (27 or 28) are adjusted.

  The discrimination circuit 16 can individually adjust the characteristics of the first time measurement unit 27 and the second time measurement unit 28. For example, in the first embodiment, as a characteristic of the first time measuring unit 27 and the second time measuring unit 28, a mode in which the capacitance value of the first variable capacitor 10 and the capacitance value of the second variable capacitor 11 are changed is shown. .

  As shown in FIG. 3A, the first and second variable capacitors 10 and 11 are configured by connecting in series a series circuit of unit switches 29a, 29b,... 29c and unit capacitors 30a, 30b,. As shown in FIG. 3B, the first and second variable capacitors 10 and 11 are formed by connecting in parallel a parallel circuit of unit switches 31a, 31b,... 31c and unit capacitors 32a, 32b,. May be configured. The determination circuit 16 can change the capacitance values of the first and second variable capacitors 10 and 11 by turning on / off some or all of the unit switches 29a to 29c.

  The operation of the above configuration will be described. FIG. 4 schematically shows the relationship between the sync pulse signal transmitted from the master ECU 1 to the slave 2 and the output clock signal of the oscillation circuit 3 in a timing chart. The master ECU 1 transmits various commands to the slave 2, and the slave 2 executes processing according to the command. When the ECU 1 transmits this command, the sync pulse signal shown in FIG. (E.g., 500 [μs]).

  When the CPU 4 receives a sync pulse signal a predetermined number of times (for example, 8 times) while counting the pulses of the clock signal by the built-in counter, the command input from the master ECU 1 is blocked until the next sync pulse is received. Until the next sync pulse is received, the OSC training period T2 is set.

  The OSC training period T2 is a period provided for confirming whether the clock signal of the oscillation circuit 3 is generated at a desired frequency. The CPU 4 uses the sync pulse interval input from the ECU 1 and the count number of the clock signal pulses, and compares the theoretical count value based on the sync pulse interval with the actual count number, thereby obtaining the desired clock signal. It is determined whether or not it occurs in the frequency range (period T3 in FIG. 4).

  At this time, if the calculated frequency is within the predetermined range, the CPU 4 proceeds to the communication processing between the next master ECU 1 and the slave 2 as it is, but if the calculated frequency is out of the predetermined range, Before shifting to the communication processing between the master ECU 1 and the slave 2, the frequency of the clock signal is adjusted with higher accuracy by adjusting the oscillation frequency of the oscillation circuit 3. For example, before the OSC training, if the clock signal has a frequency error of about ± 5 [%] with respect to the target frequency, it can be adjusted to a frequency error of about ± 1 [%] with respect to the target frequency after the OSC training.

  A specific example of the normal operation of the oscillation circuit 3 and the OSC training process will be described below with reference to FIG. In the normal state, the level of the output terminal OUT is either the first level “H” or the second level “L”. Therefore, the valid / invalid switching circuit 14 turns on one of the MOS transistors 29 and 30 and turns off the other. Here, at a certain time t0, the output terminal OUT is set to the second level “L” level, the MOS transistor 30 in the valid / invalid switching circuit 14 is turned on, and the MOS transistor 29 is turned off. An explanation will be given assuming this. At this time, the 1st time measurement part 27 is validated, and the 2nd time measurement part 28 is invalidated.

  The reference voltage output unit 7 shown in FIG. 2 outputs a reference voltage, and this reference voltage is input to the voltage-current converter 8. The voltage / current converter 8 converts the input reference voltage into a voltage / current, and outputs a current signal to the current mirror circuit 9. The current mirror circuit 9 outputs a constant current corresponding to the mirror ratio between the input / output transistors 24 and 25 to the first variable capacitor 10 through the first output transistor 25. Since the MOS transistor 29 is off, the first variable capacitor 10 is charged with a constant current. Since the output current of the first output transistor 25 is constant, the charging voltage of the first variable capacitor 10 increases linearly with, for example, the first gradient A1 with time (see TA1 period in FIG. 5).

  The current mirror circuit 9 outputs a current corresponding to the mirror ratio between the input / output transistors 24 and 26 to the second variable capacitor 11 through the second output transistor 26, but the MOS transistor 30 is on. The current flows through the MOS transistor 30 and the second variable capacitor 11 is not charged.

  During this period TA1, the charging voltage of the first variable capacitor 10 rises, but when this charging voltage reaches the band gap reference voltage VBGR, the output of the first comparator 12 is inverted. When the inverted output level “L” of the first comparator 12 is input, the flip-flop circuit 15 inverts the level of the output terminal OUT by inverting the output. Here, the output terminal OUT transitions from the second level “L” to the first level “H” (see t1 in FIG. 5).

  When the level of the output terminal OUT changes to the first level “H”, the MOS transistor 29 is turned on and the MOS transistor 30 is turned off. Then, the charging voltage of the first variable capacitor 10 is discharged through the MOS transistor 29, and the output of the first comparator 12 changes to “H” again. Since the charging voltage of the first variable capacitor 10 sharply decreases and is fixed at 0V, the operation of the first time measuring unit 27 is invalidated. At the same time, since the terminal of the second variable capacitor 11 is opened, the second variable capacitor 11 starts charging through the second output transistor 26 of the current mirror circuit 9. Since the output current of the second output transistor 26 is constant, the charging voltage of the second variable capacitor 11 rises, for example, linearly with time (see TA2 period in FIG. 5).

  During this period TA2, the charging voltage of the second variable capacitor 11 rises. When this charging voltage reaches the band gap reference voltage VBGR, the output of the second comparator 13 is inverted. When the inverted output level “L” of the second comparator 13 is input, the flip-flop circuit 15 inverts the level of the output terminal OUT by inverting the output. Here, the output terminal OUT transits from the first level “H” to the second level “L” (see t2 in FIG. 5).

  When the level of the output terminal OUT changes to the second level “L”, the MOS transistor 29 is turned off and the MOS transistor 30 is turned on. Then, the charging voltage of the second variable capacitor 11 is discharged through the MOS transistor 30, and the output of the second comparator 13 changes to “H” again. Since the charging voltage of the second variable capacitor 11 sharply decreases and is fixed at 0V, the operation of the second time measuring unit 28 is invalidated. At the same time, since the terminal of the first variable capacitor 10 is opened, the first variable capacitor 10 starts charging through the first output transistor 25 of the current mirror circuit 9. This operation is the same as the operation during the period TA1, and thereafter, the first time measurement units 27 and 28 alternately repeat the time measurement operation during the periods TA1 and TA2. In the steady state, it operates in this way.

  Next, the OSC training processing operation will be described. The oscillation circuit 3 outputs a clock signal from the output terminal OUT in a steady state, and also outputs a clock signal to the determination circuit 16, but as shown in FIGS. When the training period T2 is reached, it is determined whether or not the clock signal is generated in a predetermined frequency range by comparing the theoretical count value based on the sync pulse interval with the actual count number (FIGS. 4 and 5). Period T3), if it does not occur in the predetermined frequency range, an adjustment signal for adjusting the frequency / duty ratio of the clock signal is output to the discrimination circuit 16 (timing t3 in FIG. 5).

  When adjusting the frequency / duty ratio of the clock signal, only the frequency of the clock signal may be adjusted or only the duty ratio may be adjusted. In the example shown in FIG. The example which changes both is shown. Note that the output waveform of the clock signal shown in the rightmost column of FIG. 5 is a schematic one, and the waveform (frequency and duty ratio) is greatly changed for easy understanding of the features of the present embodiment. Note that this is different from the actual output waveform.

  For example, when the CPU 4 determines that the frequency of the clock signal is out of a predetermined frequency range and the frequency is low, the CPU 4 outputs an adjustment signal to the determination circuit 16, and the determination circuit 16 receives the adjustment signal. A time measuring unit that determines which one of the first and second time measuring units 27 and 28 is operating and is determined not to be operating among the first and second time measuring units 27 and 28 The target time measuring unit (27 or 28) is used to adjust the characteristics during non-time measurement.

  That is, when one of the MOS transistors 29 and 30 is turned on, one of the charging voltages of the first and second variable capacitors 10 and 11 is discharged, but the CPU 4 performs non-time measurement during this discharging period. The characteristics of the first or second time measuring unit 27 or 28 are adjusted during this non-time measurement.

  When the determination circuit 16 adjusts the characteristics of the first or second time measurement unit 27 or 28, the capacitance value of the first or second variable capacitor 10 or 11 in the target time measurement unit is adjusted. At this time, the discrimination circuit 16 turns on or off some or all of the unit switches 29a to 29c or 31a to 31c shown in FIG. 3A or 3B to thereby unit capacitors 30a to 30c or 32a. Adjust the combined capacitance value of ~ 32c.

  For example, the second time measuring unit 28 is operating during the period TA2 within the period T3 shown in FIG. 5, and the first time measuring unit 27 stops the time measuring operation during this operation. Therefore, the determination circuit 16 adjusts the capacitance value of the first variable capacitor 10 constituting the first time measuring unit 27 during this period TA2. As a result, the rising gradient A3 of the charging voltage of the first variable capacitor 10 can be changed in the subsequent period TA3.

  Even if the determination circuit 16 changes and controls the capacitance value of the first variable capacitor 10 during the period TA2, since the MOS transistor 29 is on, the terminal voltage of the first variable capacitor 10 does not vary. Therefore, it is possible to suppress the possibility that the clock signal (oscillation signal) output from the output terminal OUT is adversely affected.

  Further, during the subsequent period TA3, the first time measuring unit 27 is operating, and during this operation, the second time measuring unit 28 stops the time measuring operation. For this reason, the determination circuit 16 adjusts the capacitance value of the second variable capacitor 11 constituting the second time measuring unit 28 during the period TA3. As a result, the rising gradient A4 of the charging voltage of the second variable capacitor 11 can be changed in the subsequent period TA4.

  Even if the determination circuit 16 changes and controls the capacitance value of the second variable capacitor 11 during the period TA3, the terminal voltage of the second variable capacitor 11 does not vary because the MOS transistor 30 is on. Therefore, it is possible to minimize the possibility that the clock signal (oscillation signal) output from the output terminal OUT will be adversely affected.

  As described above, according to the present embodiment, as described above, while the first time measurement unit 27 performs the time measurement operation, the determination circuit 16 sets the capacitance value of the second variable capacitor 11 of the second time measurement unit 28. Therefore, the characteristics of the second time measuring unit 28 can be adjusted during a period that does not affect the output of the clock signal. While the second time measurement unit 28 is performing the time measurement operation, the determination circuit 16 adjusts the capacitance value of the first variable capacitor 10 of the first time measurement unit 27, so that it does not affect the output of the clock signal. In addition, the characteristics of the first time measuring unit 27 can be adjusted. Thereby, it is possible to suppress a steep fluctuation of the clock signal.

  The determination circuit 16 can change the frequency of the clock signal by changing both the capacitance values of the first and second variable capacitors 10 and 11 so that the gradient ratio A1: A2 and the gradient ratio A3: A4 are constant. . In addition, the determination circuit 16 changes at least one of the capacitance values of the first and second variable capacitors 10 and 11 so that the gradient ratio A1: A2 and the gradient ratio A3: A4 are different from each other. The duty ratio can be changed.

(Second Embodiment)
6 to 8 show additional explanatory views of the second embodiment. The second embodiment shows a mode in which the mirror ratio between the input transistor and the output transistor is adjusted when adjusting the characteristics of the target time measurement unit.

  In FIG. 6 describing the second embodiment, reference numerals 104 to 131 are added to the components having the same or similar functions corresponding to the components 4 to 31 described in the first embodiment, respectively. A description will be omitted if necessary.

  As shown in FIG. 6, the oscillation circuit 103 includes a first fixed capacitor 110 instead of the first variable capacitor 10 and a second fixed capacitor 111 instead of the second variable capacitor 11. Yes. The current mirror circuit 109 is configured such that the output currents of the first and second output transistors 125 and 126 can be adjusted by the determination circuit 116, respectively.

  As shown in FIG. 7, the first output transistor 125 connects, for example, a plurality of P-channel type cell MOS transistors 133a... 133b in parallel, and switches 134a, 135a... 134b are connected to the gates of these cell MOS transistors 133a. , 135b are connected. Therefore, the determination circuit 116 can adjust the output current amount of the first output transistor 125 by controlling the switches 134a, 135a,. Since the configuration of the second output transistor 126 is the same as the configuration of the first output transistor 125, the description thereof is omitted, but the determination circuit 116 can adjust the amount of output current of the second output transistor 126.

  For example, the second time measuring unit 128 is operating during the period TA2 within the period T3 shown in FIG. 8, and the first time measuring unit 127 stops the time measuring operation during this operation. Therefore, when receiving an adjustment signal from the CPU 104, the determination circuit 116 adjusts the amount of output current of the first output transistor 125 constituting the first time measurement unit 127 during this period TA2. As a result, in the subsequent period TA3, the rising gradient A3 of the charging voltage of the first variable capacitor 110 can be changed.

  Even if the determination circuit 116 changes the output current amount of the first output transistor 125 during the period TA2, the terminal voltage of the first variable capacitor 110 does not change because the MOS transistor 129 is on. Therefore, there is no adverse effect on the clock signal (oscillation signal) output from the output terminal OUT.

  Further, during the subsequent period TA3, the first time measuring unit 127 is operating, and during this operation, the second time measuring unit 128 stops the time measuring operation. Therefore, when receiving the adjustment signal from the CPU 104, the determination circuit 116 adjusts the output current amount of the second output transistor 126 constituting the second time measuring unit 128 during this period TA3. As a result, in the subsequent period TA4, the rising gradient A4 of the charging voltage of the second fixed capacitor 111 can be changed.

  Even if the determination circuit 116 changes the output current amount of the second output transistor 126 during the period TA3, the MOS transistor 130 is on, so that the terminal voltage of the second fixed capacitor 111 does not vary. Therefore, there is no adverse effect on the clock signal (oscillation signal) output from the output terminal OUT. As described above, the same effects can be obtained in the second embodiment.

(Third embodiment)
9 to 11 show additional explanatory views of the third embodiment. In 3rd Embodiment, when adjusting the characteristic of a target time measurement part, the form which adjusts the predetermined voltage which a comparison part makes as a comparison object is shown.
In FIG. 9, reference numerals 204 to 231 added with 200 are added to the constituent elements having the same or similar functions corresponding to the constituent elements 4 to 31 described in the first embodiment, respectively. Description is omitted.

  In the third embodiment, as shown in FIG. 9, in the first comparator 212, the voltage input to the non-inverting input terminal is changed to the variable voltage V1 (corresponding to the first voltage) instead of the bandgap reference voltage VBGR. The voltage V1 can be variably controlled by the determination circuit 216. The voltage input to the non-inverting input terminal of the second comparator 213 is a variable voltage V2 (corresponding to the first voltage) instead of the bandgap reference voltage VBGR, and the voltage V2 can be variably controlled by the determination circuit 216. It has become.

  In the example shown in FIG. 9, a resistor 232 is connected in series between the supply node of the fixed voltage source V3 and the non-inverting input terminal of the first comparator 212, and the non-inverting input terminal of the first comparator 212 and the ground 218 are connected. The first variable current source 218 is connected between the two. Further, a resistor 234 is connected in series between the supply node of the fixed voltage source V3 and the non-inverting input terminal of the second comparator 213, and the second is connected between the non-inverting input terminal of the second comparator 213 and the ground 218. A variable current source 235 is connected.

  The first variable current source 233 and the second variable current source 235 can adjust the DC current amount from the determination circuit 216. The first variable current source 233 illustrated in FIG. 10 includes, for example, an input transistor 237 that inputs a reference current from the current source 236, and a plurality of output transistors 238a, 238b,. . The switches 239a, 239b,... 239c are connected to the current output paths of the output transistors 238a, 238b,. The determination circuit 216 switches on / off the switches 239a, 239b,... 239c, thereby switching the output transistors 238a, 238b,. Since the second variable current source 235 has the same configuration as the first variable current source 233, the description thereof is omitted.

  As a result, as shown in FIG. 9, the determination circuit 116 can adjust the amount of current flowing from the fixed voltage source V3 to the resistor 232, and the voltage to the non-inverting input terminal of the first comparator 212 can be adjusted according to the voltage drop of the resistor 232. The input voltage V1 can be adjusted. The determination circuit 116 can adjust the amount of current flowing from the fixed voltage source V3 to the resistor 234, and can adjust the input voltage V2 to the non-inverting input terminal of the second comparator 213 according to the voltage drop of the resistor 234.

  Now, during the period TA2 in the period T3 shown in FIG. 11, the second time measuring unit 228 is operating, and during this operation, the first time measuring unit 227 stops the time measuring operation. Therefore, the determination circuit 216 adjusts the voltage V1 that is the comparison target voltage of the first comparator 212 of the first time measurement unit 227 during the period TA2. As a result, the threshold voltage of the first comparator 212 can be changed in the subsequent period TA3. In this case, the first slope (upward slope) A1 of the charging voltage of the first fixed capacitor 210 does not change.

  Even if the determination circuit 216 controls to change the voltage V1 during the period TA2, the terminal voltage of the first fixed capacitor 210 does not vary because the MOS transistor 229 is on. Therefore, the possibility that the clock signal (oscillation signal) output from the output terminal OUT is adversely affected can be suppressed as much as possible.

  Further, during the subsequent period TA3, the first time measuring unit 227 is operating, and during this operation, the second time measuring unit 228 stops the time measuring operation. Therefore, the determination circuit 216 adjusts the voltage V2 that is the comparison target voltage of the second comparator 213 of the second time measurement unit 228 during the period TA3. As a result, the threshold voltage of the second comparator 213 can be changed in the subsequent period TA4. In this case, the second gradient (rising gradient) A2 of the charging voltage of the second fixed capacitor 211 does not change.

  Even if the determination circuit 216 changes the voltage V2 during the period TA3, since the MOS transistor 230 is on, the terminal voltage of the second fixed capacitor 211 does not vary. Therefore, the possibility that the clock signal (oscillation signal) output from the output terminal OUT is adversely affected can be suppressed as much as possible. As described above, the same effects can be obtained in the third embodiment.

(Fourth embodiment)
FIG. 12 shows an additional explanatory diagram of the fourth embodiment. In the third embodiment, the discrimination circuit 216 has changed the voltages V1 and V2 to be compared. However, only one of the voltages V1 and V2 to be compared may be changed. FIG. 12 shows an example in which the voltage V2 is not changed. In this case, the duty ratio can be adjusted.

(Other embodiments)
For example, the following modifications or expansions are possible. In the first embodiment, the adjustment unit may adjust the capacitance values of the variable capacitors 10 and 11 mainly by either the determination circuit 16 or the CPU 4. In the second embodiment, the adjustment unit may adjust the output current amounts of the output transistors 125 and 126 mainly by either the determination circuit 116 or the CPU 104. In the third embodiment, the adjustment unit may adjust the output current amount of the variable current sources 233 and 235 mainly by either the CPU 204 or the determination circuit 216.

  The charging unit is not limited to the capacitors 10, 11, 110, 111, 210, and 211. The current output unit is not limited to the output transistors 25, 26, 125, 126, 225, and 226. The comparison unit is not limited to the comparators 12, 13, 112, 113, 212, and 213. The oscillation signal is not limited to the clock signal, and various rectangular signals can be applied.

The components (for example, the adjustment unit and the determination circuit (determination unit)) of each embodiment may be configured by hardware or software (program) as long as it can be functionally realized. The configurations of the embodiments can be applied in appropriate combinations.
The constituent elements described in the claims are assigned with the reference numerals in order to make it easier to understand the correspondence between the constituent elements in the claims and the configuration examples described in the specification. The invention according to the claims is not limited to this component.

  In the drawing, 3, 103 and 203 are oscillation circuits, 4, 104 and 204 are CPUs (adjusting units), 25, 26, 125, 126, 225 and 226 are output transistors (current output units) 10, 11, 110, Reference numerals 111, 210, and 211 denote capacitors (charging units), and 16, 116, and 216 denote discrimination circuits (discrimination units and adjustment units).

Claims (6)

A current output unit (25, 26; 125, 126; 225, 226), a charging unit (10, 11; 110, 111; 210, 211) for charging the current output by the current output unit, and the charging unit Comparison units (12, 13; 112, 113; 212, 213) for comparing the charging voltage of the charging unit with the first voltage (VBGR; V1, V2), respectively. First and second time measuring units (27, 28; 127, 128; 227, 228) for measuring time to voltage and alternately performing time measuring operations;
An output unit (15; 115; 215) for outputting an oscillation signal according to the time measurement results of the first and second time measurement units;
A discriminating unit (16; 116; 216) for discriminating which of the first and second time measuring units is not measuring time,
Of the first and second time measurement units, the target time measurement unit (27 or 28; 127 or 128; 227 or 228) that has been determined not to measure time by the determination unit has a non-time measurement characteristic. An oscillation circuit characterized by being configured to be adjustable by an adjustment unit (4 or 16; 104 or 116; 204 or 216). The charging unit includes a capacitor (10; 110; 210) for charging the current output by the current output unit,
The oscillation circuit according to claim 1, wherein the adjustment unit adjusts a capacitance value of the capacitor when adjusting a characteristic of the target time measurement unit. The current output unit includes an input transistor (24; 124; 224) that inputs a reference current, and an output transistor (25, 26; 125, 126; that outputs a current mirrored from the current input to the input transistor). 225, 226),
The oscillation circuit according to claim 1, wherein the adjustment unit adjusts a mirror ratio between the input transistor and the output transistor when adjusting characteristics of the target time measurement unit.   The adjustment unit (204 or 216) adjusts the first voltage (V1 or V2) to be compared by the comparison unit when adjusting the characteristics of the target time measurement unit (227 or 228). The oscillation circuit according to any one of claims 1 to 3, wherein the oscillation circuit is characterized in that:   5. The oscillation circuit according to claim 1, wherein the adjustment unit is configured to be able to individually adjust characteristics of the first and second time measurement units.   The adjustment unit controls to change the frequency of the oscillation signal based on a sync pulse signal supplied from the outside, and performs OSC training by adjusting the frequency during non-time measurement of the characteristics of the target time measurement unit. The oscillation circuit according to any one of claims 1 to 5, wherein

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