JP2016192694A - Stream processing apparatus - Google Patents

Abstract

Provided is a stream processing apparatus capable of reducing a load on a data processing unit and a necessary memory capacity in a configuration for processing using stream data received by a plurality of channels. A stream processing apparatus according to an embodiment performs data processing using a plurality of stream buffers provided for each channel that receives stream data, and stream data read from the plurality of stream buffers at the same timing. And a data processing unit 10 for performing the above. Each stream buffer 11 includes a FIFO 12 (FIFO memory) that stores received stream data by a first-in first-out method, and a synchronization circuit 21 that synchronizes the stream data of each channel by adjusting the timing of writing the received stream data to the FIFO 12. It is constituted by. [Selection] Figure 5

Description

  The present invention relates to a stream processing apparatus that processes continuously received stream data.

  2. Description of the Related Art Conventionally, there are stream processing apparatuses that process continuously received stream data such as music data, video data, or data output from a sensor. Since such a stream processing apparatus continuously receives stream data, the stream data is temporarily stored in a buffer constituted by a FIFO memory that stores the received stream data by, for example, a first-in first-out method. The stream is read and processed by the data processing unit (see, for example, Patent Document 1).

JP 2011-23799 A

  However, when processing using stream data received on multiple channels, there may be a difference in the timing of receiving stream data between channels, and it is necessary to synchronize the stream data to be processed by the data processing unit. was there. As a result, there is a problem that the load on the data processing unit increases and the required memory capacity increases.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the load on the data processing unit and the required memory capacity in a configuration in which processing is performed using stream data received on a plurality of channels. An object of the present invention is to provide a stream processing apparatus that can

  According to the first aspect of the present invention, the stream processing device uses a plurality of stream buffers provided for each channel that receives stream data, and stream data read from the plurality of stream buffers at the same timing. And a data processing unit that performs processing. Each stream buffer includes a FIFO memory that stores the received stream data in a first-in first-out manner, and a synchronization circuit that synchronizes the stream data of each channel by adjusting the timing of writing the received stream data to the FIFO memory. Has been.

  As a result, the data processing unit does not need to perform software synchronization processing for synchronizing each stream data. Since there is no need to perform software-like synchronization processing, the load on the data processing unit does not increase, and it is not necessary to secure a memory capacity for synchronization processing. Therefore, in a configuration in which processing is performed using stream data received through a plurality of channels, the load on the data processing unit and the required memory capacity can be reduced.

The figure which shows typically the structure of the data processing system to which the stream processing apparatus by 1st Embodiment is applied. The figure which shows the example of the detection point of a sensor typically The figure which shows the gap which occurs in the stream data typically The figure which shows typically the electric constitution of the conventional stream processing apparatus as a comparative example The figure which shows typically the electric constitution of a stream processing apparatus The figure which shows the electric constitution of the stream buffer typically The figure which shows the operation mode of the stream buffer typically The figure which shows the operation | movement aspect of the stream buffer of another channel typically The figure which shows the operation | movement aspect of a stream processing apparatus typically The figure which shows typically the deviation which arises in the stream data by 2nd Embodiment The figure which shows the electric constitution of the stream buffer typically The figure which shows the operation mode of the stream buffer typically The figure which shows the operation | movement aspect of a stream processing apparatus typically The figure which shows typically the electric constitution of the stream buffer by 3rd Embodiment. The figure which shows typically the operation | movement aspect of the stream buffer in 4th Embodiment. Diagram showing the electrical configuration of the stream buffer The figure which shows typically the operation | movement aspect of the stream buffer in 5th Embodiment. Diagram showing the electrical configuration of the stream buffer The figure which shows typically the operation | movement aspect of the stream buffer in 6th Embodiment. Diagram showing the electrical configuration of the stream buffer

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the site | part substantially common in each embodiment, and the detailed description is abbreviate | omitted.
(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 9.

  As shown in FIG. 1, the stream processing apparatus 1 according to the present embodiment receives and processes stream data output from the sensor unit 2. The sensor unit 2 includes a plurality of, for example, four sensors 2A to 2D in this embodiment, and stream data is output from each of the sensors 2A to 2D. Hereinafter, for convenience, the stream data output from the sensor 2A is referred to as channel 0 (CH [0]) stream data, and similarly, the stream data output from the sensors 2B to 2D is referred to as channels 1 to 3 (CH [1] to CH [3]) will also be described as stream data.

  Each of the sensors 2A to 2D assumes a so-called laser distance meter in the present embodiment. As shown in FIG. 2, the sensor unit 2A has a 360 ° range in the scanning direction indicated by the arrow R with the sensor unit 2 as the center. Scan horizontally. And each sensor 2A-2D measures the distance to the target object (illustration omitted) in each measurement point P0-Pk (k is arbitrary integers), and outputs the measurement result as stream data. That is, the sensors 2A to 2D sequentially output the measurement results of the measurement points P0 to Pk in time series. The sensor unit 2 is not necessarily required to measure the entire circumference of 360 °, and the number (k) of the measurement points P0 to Pk to be measured can be arbitrarily set.

The stream processing apparatus 1 performs data processing for detecting, for example, an object such as an obstacle based on the stream data output from each of the sensors 2A to 2D, that is, the measurement result of each height in the present embodiment.
Now, since the stream processing apparatus 1 needs to detect an object at each of the measurement points P0 to Pk, basically, the data processing is performed using the detection result for the same measurement point. However, since the sensors 2A to 2D are provided at different positions, due to an installation error at the time of installation, individual differences in activation time from when the power is turned on until stream data is output, etc. Deviation may occur.

  Specifically, as shown in FIG. 3, for example, when “3” (meaning data of the measurement point P3) of the stream data of CH [1] is used as the reference data for convenience, the data of CH [0] The stream data has a deviation of 2 data (2 measurement points) from the reference data. Further, the stream data of CH [2] has a deviation of three data (three measurement points) from the reference data. Further, the stream data of CH [4] has a shift of one data (one measurement point) from the reference data, and the data itself is shifted by the time td.

  As described above, when stream data is received from a plurality of channels, for example, the measurement position shift (hereinafter also referred to as a spatial shift for convenience) such as the shift of three data as described above, or the time td. There may be a minute shift (hereinafter also referred to as a time shift for convenience).

  A conventional apparatus (hereinafter referred to as a conventional stream processing apparatus 100 for the sake of convenience) as shown in FIG. 4 as a comparative example temporarily stores the stream data and a conventional data processing unit 101 that performs data processing. A FIFO memory (indicated as FIFO 102 in FIG. 4) is provided. In the conventional stream processing apparatus 100, stream data is sequentially stored in the FIFO 102 in time series every time it is received. Note that the numerical values such as 0, 1,... 5 enclosed in a square frame shown in FIG. 4 are data corresponding to the positions of the measurement points described above (P0, P1,... P5, etc.). It is shown that.

  In this case, although the time lag described above is absorbed by the FIFO 102, the conventional data processing unit 101 receives the stream data of each channel received at the same timing, for example, “1”, “3”, “0”, “ In the case of “2”, the stream data read from the FIFO 102 is also “1”, “3”, “0”, and “2”. That is, the above-described spatial deviation cannot be absorbed by the FIFO 102. As a result, in order to process stream data in which a spatial deviation occurs, first, synchronization for synchronizing the stream data is performed. Since it is necessary to perform processing in software, and the memory capacity is required for the synchronization process and the synchronization process, the load and the memory capacity are increased. Therefore, the stream processing apparatus 1 according to the present embodiment reduces the load and the required memory capacity as follows.

As shown in FIG. 5, the stream processing apparatus 1 of the present embodiment includes a data processing unit 10 and a plurality (n) of stream buffers 11 provided corresponding to each channel. The number of stream buffers 11 may be set arbitrarily.
The data processing unit 10 is configured by a microcomputer having a CPU, a ROM, a RAM, and the like (not shown), and controls the stream processing device 1 by executing a program stored in the ROM or the like.

  Each stream buffer 11 includes a FIFO 12 (corresponding to a FIFO memory) that stores received stream data in a first-in first-out manner, and a synchronization circuit 13 that synchronizes the stream data of each channel by adjusting the timing of writing the received stream data to the FIFO 12. It has.

  As shown in FIG. 6, the synchronization circuit 13 includes an offset register 14, a subtracter 15, and a gate circuit 16. That is, the synchronization circuit 13 is basically realized by hardware such as a logic circuit and the operation is performed independently from the data processing unit 10.

  The offset register 14 is set with an offset value corresponding to a deviation from the stream data of other channels. This offset value is set at the time of calibration work (calibration work) when the stream processing apparatus 1 is installed. Specifically, when the sensors 2A to 2D are inspected, the spatial deviation is measured, and a value indicating the deviation is set as an offset value. In the present embodiment, when a certain channel is used as a reference, an offset value is set based on how late the stream data of another channel is received.

  For this reason, for example, when the spatial deviation as illustrated in FIG. 3 is measured, 2 is set as the offset value in the offset register 14 of the stream buffer 11 corresponding to CH [0]. Similarly, 0 is set as the offset value in the case of CH [1], 3 is set as the offset value in the case of CH [2], and 1 is set as the offset value in the case of CH [3]. The Each offset value may be stored in the synchronization circuit, or may be provided from the data processing unit 10 or the like every time the stream processing apparatus 1 is activated.

  The subtracter 15 subtracts the offset value set in the offset register 14 in accordance with the timing of receiving the stream data. Specifically, for example, in the case of CH [0], the subtracter 15 subtracts the offset value by 1 such as 2 → 1 → 0. Although not shown, a clock signal corresponding to the stream data cycle is input to the offset register 14 and the subtraction by the subtracter 15 is enabled, that is, the subtraction is performed according to the clock. Will be done.

  When the offset value of the offset register 14 does not match a predetermined reference value (0 in this embodiment), the gate circuit 16 validates and receives the subtraction of the offset value by the subtracter 15. The writing of the stream data to the FIFO 12 is restricted. On the other hand, when the offset value of the offset register 14 matches the reference value (0), the gate circuit 16 invalidates the subtraction of the offset value by the subtractor 15 and writes the received stream data to the FIFO 12. To give permission. The synchronization circuit 13 includes a comparator 17 and two AND gates 18 and 19.

Next, the operation of the above configuration will be described together with details of the synchronization circuit 13.
First, the data format of stream data targeted in this embodiment will be described. As for the stream data, a data body (indicated as S_DATA in FIG. 6) and a data valid signal (indicated as S_EN in FIG. 6) indicating that the data exists are received. The data valid signal is a signal that indicates that valid data exists when it is at the H level, and that there is no valid data when it is at the L level.

Of the received stream data, the data body (S_DATA) is connected to the data input (indicated as DATA_IN in FIG. 6) of the FIFO 12. The data valid signal (S_EN) is connected to one input terminal of the AND gate 19 of the gate circuit 16.
The other input terminal of the AND gate 19 is connected to the comparator 17. The comparator 17 compares the current offset value of the offset register 14 with the reference value (0), and outputs an H level if they match, and an L level if they do not match. On the other hand, AND gate 19 outputs H level when both the output of comparator 17 and the data valid signal are at H level.

  At this time, the FIFO 12 is permitted to write when a write permission signal (indicated as WR_EN in FIG. 6) is turned on, that is, when the output of the AND gate 19 becomes H level. Further, when the write permission signal is turned off, that is, when the output of the AND gate 19 becomes L level, the FIFO 12 is restricted from being written. In this manner, the AND gate 19 controls the writing of the stream data to the FIFO 12 by turning on / off the write permission signal of the FIFO 12.

  The other AND gate 18 of the gate circuit 16 receives the data valid signal (S_EN) and the inverted output of the comparator 17. Therefore, the AND gate 18 outputs the H level when the current offset value of the offset register 14 does not match the reference value (0) and the data valid signal (S_EN) is at the H level. The output of the AND gate 18 functions as an update valid signal (denoted as EN in FIG. 6) of the offset register 14. For this reason, when the output of the AND gate 18 is at the H level, updating of the offset value is permitted. More specifically, at the timing when the offset value is not 0 and stream data is received, subtraction by the subtractor 15 is validated, and the offset value is updated.

  On the other hand, once the offset value is subtracted to 0, the AND gate 18 outputs L level regardless of reception of stream data thereafter. That is, in the present embodiment, the offset value is subtracted in the initial period when the reception of the stream data is started.

Next, details of the operation mode of the stream buffer 11 having such a synchronization circuit 13 will be described. Since the synchronization circuit 13 of each channel performs substantially the same operation, here, the details will be described using CH [0] as an example as shown in FIG.
The stream data shown in FIG. 7 corresponds to the stream data of CH [0] among the four stream data shown in FIG. 3, and is the reference data (data “3” of the stream data of CH [1]). On the other hand, there is a shift of two data. For simplification of explanation, it is assumed that data is not read from the FIFO 12 by the data processing unit 10 from time T1 to time T6 shown in FIG.

  The stream buffer 11 that receives the stream data of CH [0] is ready for reception at time T0, and 2 indicating a spatial deviation is set as the offset value (see FIG. 3). Note that the reception mode of the stream data of CH [0] is that data at the measurement point P1 (shown as 1 in FIG. 7) is received at time T1 after the time T0, and data at the measurement point P2 (FIG. 7 is indicated as 1), data at measurement point P3 (indicated as 2 in FIG. 7) is received at time T3, and data at measurement point P4 (indicated as 3 in FIG. 7) is received at time T4. Assume that data at a measurement point P5 (shown as 4 in FIG. 7) is received at time T5, and data at a measurement point P6 (shown as 5 in FIG. 7) is received at time T6. Hereinafter, the data of the measurement point P1 is also referred to as “1” data for convenience.

  In this case, when the data “1” is received at time T1, the synchronization circuit 13 does not match the offset value (2) and the reference value (0), so the output of the comparator 17 becomes L level. The subtraction by the subtracter 15 is validated when the output of the AND gate 18 becomes H level. As a result, the offset value set in the offset register 14 is subtracted and updated from 2 to 1. At this time, since the output of the AND gate 19 is at the L level, writing to the FIFO 12 is restricted. In other words, the data “1” received at time T1 is not written to the FIFO 12.

  Next, when data “2” is received at time T2, the synchronization circuit 13 does not match the offset value (1) and the reference value (0) at the time of reception. When enabled, the offset value is updated from 1 to 0, and writing of data “2” into the FIFO 12 is restricted. For this reason, the data “2” received at time T 2 is not written into the FIFO 12.

  When the data “3” is received at time T3, the synchronization circuit 13 matches the offset value (0) and the reference value (0) at the time of reception, so that the output of the AND gate 18 is L Level, and the subtraction by the subtractor 15 is invalidated. Therefore, thereafter, the offset value is not updated. On the other hand, since the output of the AND gate 19 becomes the H level, writing to the FIFO 12 is permitted. Therefore, the data “3” received at time T 3 is stored in the FIFO 12.

  Similarly, from time T4 to time T6, the offset value (0) and the reference value (0) coincide with each other, so that writing to the FIFO 12 is permitted. As a result, as the storage mode of the FIFO 12 at time T6, the data “3” is stored as the data that is written at the beginning, that is, the earliest on the reading side (the data processing unit 10 side) and that is read out first. Next, the data “4”, the data “5”, and the data “6” are sequentially stored in time series.

Thereby, the channels are synchronized in the state stored in the FIFO 12, and the data read by the data processing unit 10 at the same timing becomes data indicating the same measurement point (see FIG. 2).
In this way, when the reception preparation is completed, the stream buffer 11 cancels the number of data corresponding to the offset value (2 at this time) (two data “1” and “2”) and stores the data in the FIFO 12. The timing at which the stream data is written is adjusted and synchronized so that the data to be written first is “3”, that is, data at the same measurement point as the reference data.

  The same applies to the stream buffers 11 of other channels. Specifically, as shown in FIG. 8, in the CH [1] stream buffer 11, since its own channel is the reference data, the offset value is set to 0 (see FIG. 3) and received at time T0. If the preparation is completed, writing to the FIFO 12 from the first received data (data “3” in FIG. 8) is permitted. Therefore, data “3” is stored in the FIFO 12 at the head, and then data is sequentially stored in time series so that the data becomes “4”.

  Further, in the stream buffer 11 of CH [2], since the offset value is set to 3 (see FIG. 3), “3” shifted by 3 data from the first received data (“0” data). Are stored at the head of the FIFO 12. Similarly, in the CH [3] stream buffer 11, since the offset value is set to 1 (see FIG. 3), “1” shifted by 1 data from the first received data (data “2”). Is stored at the head of the FIFO 12.

  As described above, in the stream processing apparatus 1 of the present embodiment, as shown in FIG. 9, the first received data after completion of reception preparation is “1” data in CH [0], and in CH [1]. Even if there is a shift in each channel, such as “3” data, “0” data in CH [2], and “2” data in CH [3], the channel in each stream buffer 11 Are synchronized. As a result, data without spatial deviation is stored in the FIFO 12, and the data processing unit 10 can perform data processing using data without deviation without performing synchronization processing.

According to the embodiment described above, the following effects can be obtained.
The stream processing apparatus 1 includes a plurality of stream buffers 11 provided for each channel that receives stream data, and a data processing unit 10 that performs data processing using the stream data read from the plurality of stream buffers 11 at the same timing; It is equipped with. Each stream buffer 11 has a FIFO 12 (FIFO memory) that stores received stream data in a first-in first-out manner, and a synchronization circuit that synchronizes the stream data of each channel by adjusting the timing of writing the received stream data to the FIFO 12. 13.

  Therefore, the data processing unit 10 does not need to perform software synchronization processing for synchronizing each stream data. Since there is no need to perform software synchronization processing, the load on the data processing unit 10 does not increase, and it is not necessary to secure a memory capacity for synchronization processing. Therefore, in a configuration in which processing is performed using stream data received through a plurality of channels, the load on the data processing unit 10 and the required memory capacity can be reduced.

In the case of the present embodiment, the synchronization circuit 13 sets the offset register 14 in which an offset value corresponding to a deviation from the stream data of other channels is set, and the offset register 14 in accordance with the timing of receiving the stream data. If the offset value of the offset register 14 and the offset value of the offset register 14 do not match a predetermined reference value, the subtraction of the offset value by the subtractor 15 is enabled and the received stream data When the offset value of the offset register 14 matches the reference value, the subtraction of the offset value by the subtractor 15 is invalidated and the received stream data is allowed to be written to the FIFO 12. And a gate circuit 16 to be configured It has been.
As a result, the synchronization circuit 13 can be realized with a simple configuration and is realized by hardware that operates independently from the data processing unit 10, so that the processing and the memory capacity are not increased.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 10 to 15.
In the case of the first embodiment, the offset value is set based on how late the stream data of other channels are received with respect to the reference data. On the other hand, in the case of the present embodiment, the offset value is set based on how far stream data of other channels is received with respect to the reference data.

As shown in FIG. 10, in this embodiment, the stream data of CH [2] is adopted as reference data. The reception mode shown in FIG. 10 is the same as the reception mode (see FIG. 3) of the first embodiment.
In FIG. 10, when data “3” of CH [2] is used as reference data, data “3” of CH [0] is received one data ahead of the reference data. Similarly, the data “3” of CH [1] is received by three data ahead of the reference data, and the data “3” of CH [3] is two data ahead of the reference data. Has been received.

For this reason, in the case of the conventional stream processing apparatus 100 as shown in FIG. 4, if the preparation for reception is completed at time T10, the data of each channel is “1” at the beginning of the reading side in the FIFO 12. Deviations such as “3”, “0”, and “2” occur.
Therefore, in the present embodiment, the channels are synchronized by setting the number of data received ahead of the reference data as an offset value, and a period of non-synchronization is compensated with dummy data.

  As shown in FIG. 11, the stream buffer 20 of this embodiment includes a synchronization circuit 21. The synchronization circuit 21 includes an offset register 14, an adder 22, a gate circuit 23, and a dummy data buffer 24. That is, the synchronization circuit 21 is basically realized by hardware such as a logic circuit and the operation is performed independently from the data processing unit 10.

  In the offset register 14, an offset value corresponding to a deviation from the stream data of other channels is set, for example, during calibration work. The offset value is a value indicating a deviation from the reference data. In the case of the reception mode illustrated in FIG. 10, the offset value of CH [0] is −1, the offset value of CH [1] is −3, and CH [ The offset value of 2] is set to 0, and the offset value of CH [3] is set to -2.

The adder 22 adds the offset value set in the offset register 14. Specifically, for example, in the case of CH [0], the offset value is incremented by 1 such as −1 → 0.
When the offset value of the offset register 14 does not match a predetermined reference value (0 in the present embodiment), the gate circuit 23 enables addition of the offset value by the adder 22 and writes it to the FIFO 12. When the data is switched to the dummy data stored in the dummy data buffer 24 and the offset value of the offset register 14 matches the reference value, the addition of the offset value by the adder 22 is invalidated and written to the FIFO 12. Switch data to stream data. The synchronization circuit 21 includes a comparator 17, a selector 25, an OR gate 26, and a NOT gate 27.

  The dummy data buffer 24 stores dummy data (value = X) to be written to the FIFO 12 instead of stream data in a period in which the channels are not synchronized. In the present embodiment, one type of dummy data is stored. The dummy data buffer 24 may be configured by a nonvolatile storage unit, but may be configured by a volatile storage unit so that dummy data is set from the data processing unit 10 or the like at the time of startup or the like. . Further, the value (X) of the dummy data may be set to a value that can be identified as dummy data.

Next, the operation of the above configuration will be described together with details of the synchronization circuit 21. FIG.
The data body (S_DATA) of the received stream data is connected to the H input side (indicated as H in FIG. 11) of the selector 25. A dummy data buffer 24 is connected to the L input side of the selector 25. The output of the selector 25 is connected to the data input (DATA_IN) of the FIFO 12. The selector 25 is switched by the comparator 17.

  The comparator 17 outputs an H level when the offset value of the offset register 14 matches the reference value (0 in this embodiment), and outputs an L level when the offset value does not match the reference value. . For this reason, the data written in the FIFO 12 is switched to either stream data or dummy data depending on whether or not the offset value matches the reference value.

  At this time, the write enable signal (WR_EN) of the FIFO 12 is generated by the OR gate 26. Since the data valid signal (S_EN) and the inverted output of the comparator 17 are input to the OR gate 26, even if the OR gate 26 is switched to the dummy data side, that is, the comparator 17 is at the L level. Even in the case of outputting, writing to the FIFO 12 is permitted if the data valid signal (S_EN) becomes H level.

Further, when the data is switched to the dummy data side, that is, when the comparator 17 outputs the L level and the NOT gate 27 outputs the H level, the update valid signal ( Since EN) is at the H level, updating of the offset value by the adder 22 is validated.
Next, details of the operation mode of the stream buffer 20 having such a synchronization circuit 21 will be described with reference to FIG. Since the synchronization circuit 21 of each channel performs substantially the same operation, description will be given here by taking CH [0] as an example.

  The stream data shown in FIG. 12 corresponds to the stream data of CH [0] among the four stream data shown in FIG. 10, and the reference data (data “3” of the stream data of CH [2]) On the other hand, a shift of one data has occurred. For simplification of explanation, it is assumed that the data processing unit 10 does not read data from the FIFO 12 between time T10 and time T16 shown in FIG.

  When the stream buffer 11 that receives the stream data of CH [0] is ready for reception at time T10, the data is received by one data ahead of the reference data, and thus shows a spatial deviation as an offset value. -1 is set. Note that the reception mode of the stream data on CH [0] is that data “1” is received at time T11 after time T10, data “2” is received at time T12, and “3” is received at time T13. The data “4” is received at time T14, the data “5” is received at time T15, and the data “6” is received at time T16.

  As an operation mode of the synchronization circuit 21, when the offset value is set, the set offset value (−1) and the reference value (0) do not match, so the output of the comparator 17 becomes L level, The output of the NOT gate 27 becomes H level, and the addition by the adder 22 is validated. At this time, since the output of the comparator 17 is inverted and input to the OR gate 26, the write enable signal (WR_EN) of the FIFO 12 becomes H level. That is, the synchronization circuit 21 permits writing of dummy data. At this time, since the selector 25 is on the dummy data side, the synchronization circuit 21 writes the dummy data (X) in the FIFO 12.

  Then, the synchronization circuit 21 repeats addition of the offset value and writing of dummy data until the offset value becomes the reference value. At this time, dummy data is written each time the offset value is added (updated). In the case of CH [0], since the offset value set first is −1, the synchronization circuit 21 writes one dummy data in the FIFO 12. Further, since the addition is invalidated after the offset value becomes the reference value, the synchronization circuit 21 does not write any more dummy data.

  Thereafter, when data “1” is received at time T11, the synchronization circuit 21 is on the stream data side received by the selector 25 because the offset value has already become the reference value, and the stream data is It is written in the FIFO 12. Similarly, when data is received at times T12 to T16, the synchronization circuit 13 permits writing to the FIFO 12 at each time because the offset value is a reference value.

  As a result, for example, as the storage mode of the FIFO 12 at time T16, the dummy data (X), the data “1”, the data “2”, the data “3”, the data “4”, in order from the head on the reading side, Dummy data and data received in time series, such as “5” data and “6” data, are stored.

  Similarly, in the case of CH [1] in which −3 is set as the offset value, from the data “3” (see FIG. 10) received at time T11 after three dummy data (X) are stored in the FIFO 12. Stream data is stored in time series. Further, in the case of CH [2] in which 0 is set as the offset value, dummy data is not stored, stream data is stored in time series in order from the data “0” received at time T11, and −2 as the offset value. In the case of CH [3] in which is set, after the two dummy data (X) are stored in the FIFO 12, the stream data is stored in chronological order from the data “2” received at time T11.

As a result, as shown in FIG. 13, each channel can be synchronized in the state stored in the FIFO 12, and the data read by the data processing unit 10 at the same timing is the data indicating the same measurement point (see FIG. 2). Become.
Thus, in the present embodiment, as shown in FIG. 10, the first received data after completion of reception preparation is “1” data for CH [0], and “3” data for CH [1]. , CH [2] is “0” data, and CH [3] is “2” data, even when there is a shift in each channel, the channels are synchronized when stored in the FIFO 12. be able to. For this reason, it is not necessary to perform a synchronization process for synchronizing each channel in the data processing unit 10.

According to the embodiment described above, the following effects can be obtained.
Since the stream processing apparatus 1 can synchronize each channel by the stream buffer 20, the FIFO 12 stores data having no spatial deviation, and the data processing unit 10 can perform the deviation without performing the synchronization process. Data processing can be performed using data with no data. Therefore, as in the first embodiment described above, the load on the data processing unit 10 and the required memory capacity can be reduced in a configuration in which processing is performed using stream data received on a plurality of channels.

  The synchronization circuit 21 of the stream processing apparatus 1 according to the present embodiment includes an offset register 14, an adder 22 that adds the offset value set in the offset register 14, a dummy data buffer 24 that stores dummy data, and an offset When the offset value of the register 14 does not match a predetermined reference value, the addition of the offset value by the adder 22 is validated and the data to be written to the FIFO 12 is stored in the dummy data buffer 24. On the other hand, when the offset value of the offset register 14 matches the reference value, the addition of the offset value by the adder 22 is invalidated and the gate circuit 23 that switches the data to be written to the FIFO 12 to the received stream data is provided. I have.

  As a result, the synchronization circuit 21 can be realized with a simple configuration and is realized by hardware that operates independently from the data processing unit 10, so that an increase in processing and memory capacity is not caused.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to FIG. In the third embodiment, the first embodiment is substantially combined with the second embodiment.
As shown in FIG. 14, the synchronization circuit 31 of the stream buffer 30 of the stream processing apparatus 1 of the present embodiment includes an offset register 14, a down counter synchronization circuit 32, an up counter synchronization circuit 33, a selector 34, and a comparator 35. It has.

  The down counter type synchronization circuit 32 substantially corresponds to the synchronization circuit 13 of the first embodiment, and subtracts the offset value set first, and controls writing to the FIFO 12 according to the offset value. Thus, each channel is synchronized. That is, the down counter type synchronization circuit 32 has an element deletion type configuration in which each channel is synchronized by deleting an element for deleting an element corresponding to the offset value. In this embodiment, the element to be deleted is received stream data as will be described later.

  On the other hand, the up-counter type synchronization circuit 33 substantially corresponds to the synchronization circuit 21 of the second embodiment, adds the offset value set first, and writes to the FIFO 12 according to the offset value. By controlling, each channel is synchronized. That is, the up-counter type synchronization circuit 33 has an element addition type configuration in which each channel is synchronized by deleting an element for adding an element corresponding to an offset value. In this embodiment, the element to be inserted is dummy data as will be described later. In the fifth embodiment to be described later, the received stream data data is adopted as an element to be inserted.

  The synchronization circuit 31 switches which one of the down counter type synchronization circuit 32 and the up counter type synchronization circuit 33 is used for synchronization by a selector 34 that switches according to the output from the comparator 35 that compares the offset values. In other words, the synchronization circuit 31 switches the path for writing stream data to the FIFO 12 to either the down-counter synchronization circuit 32 or the up-counter synchronization circuit 33 according to the sign of the offset value initially set.

  A comparator 35 that switches the selector 34 compares the offset value of the offset register 14 with 0, and outputs an L level if the offset value is smaller than 0, and outputs an H level if the offset value is 0 or more. The selector 34 switches the circuit to be used to the up-counter type synchronization circuit 33 side when the comparator 35 outputs an L level, that is, when the initially set offset value is a negative value. . On the other hand, when the comparator 35 outputs the H level, that is, when the offset value set first is a positive value, the selector 34 switches the circuit to be used to the down counter type synchronization circuit 32 side. .

  For this reason, when a negative offset value is set, as in the second embodiment described above, addition of the offset value and dummy operation to the FIFO 12 until the offset value reaches the reference value (0 in the present embodiment). On the other hand, when the data is written, when the offset value becomes the reference value, the stream data is written to the FIFO 12. As a result, dummy data and stream data are stored in the FIFO 12 in the manner shown in FIGS. 12 and 13 described above, and the channels can be synchronized.

  On the other hand, when a positive offset value is set, the offset value is subtracted to the FIFO 12 until the offset value reaches the reference value (0 in the present embodiment), as in the first embodiment. When the offset value reaches the reference value, writing to the FIFO 12 is permitted. As a result, the stream data is stored in the FIFO 12 in the manner shown in FIGS. 7 to 9 and the channels can be synchronized.

As described above, even in the configuration of the present embodiment, the load on the data processing unit 10 and the necessary memory capacity can be reduced in the configuration in which processing is performed using stream data received through a plurality of channels. Further, similar to the first embodiment and the second embodiment described above, the synchronization circuit 31 can be realized with a simple configuration and realized with hardware that operates independently from the data processing unit 10. Therefore, processing and memory capacity are not increased.
Moreover, versatility can be improved by providing the down counter type synchronizing circuit 32 and the up counter type synchronizing circuit 33 as in the present embodiment, and automatically switching the circuit to be used depending on whether the offset value is positive or negative. .

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIGS. 15 and 16. Note that the present embodiment has a configuration obtained by extending the second embodiment described above.

  First, the reception mode of stream data will be described. In this embodiment, the stream data is received with an index value (hereinafter referred to as an INDEX value) indicating the order of the data. Therefore, if stream data is received, it can be determined whether or not the data is transmitted correctly in time series. As the INDEX value, for example, a value indicating time (a value indicating a temporal position), a serial number, or a measurement point (a value indicating a spatial position) shown in FIG. 1 can be adopted. In the present embodiment, the measurement point is adopted as the INDEX value.

  As shown in FIG. 15, data “1” (data with INDEX value = 1) is received at time T30, and data “2” (data with INDEX value = 2) is received at time T31. At T32, data “3” (INDEX value = 3) is received, data “5” (INDEX value = 5) is received at time T33, and data “6” (INDEX value) is received at time T34. = 6) is received, and data “7” (data of INDEX value = 7) is received at time T35.

That is, in this reception mode, stream data is received in a state where there is no data with the INDEX value = 4 due to a failure in the reception path, noise, or a failure on the output side (for example, the sensor unit 2 side). .
In this case, even if each channel is first synchronized as in the second embodiment described above, there is a factor that causes synchronization to be lost during operation (lost data with INDEX value = 4). If the stream data is written in the FIFO 12 as it is, it cannot be synchronized with other channels. Therefore, in this embodiment, when a situation where the INDEX value becomes discontinuous due to data loss or the like occurs, the channels are synchronized as follows.

  As shown in FIG. 16, the stream buffer 40 of the stream processing apparatus 1 of this embodiment includes a synchronization circuit 41 and a FIFO 12. The synchronization circuit 41 has substantially the same configuration as the synchronization circuit 21 of the second embodiment (hereinafter also referred to as a write control block for convenience), an index buffer 42 (42a, 42b), and an arithmetic unit 43. It has.

  The index buffer 42 stores index values of at least two or more stream data received successively. In the case of the present embodiment, the INDEX value of the received stream data is written to one index buffer 42a, and the previous INDEX value written to the index buffer 42a is written to the index buffer 42b. For this reason, by comparing the INDEX values written in the index buffer 42a and the index buffer 42b, it can be determined whether or not the INDEX values are continuous.

  The computing unit 43 computes an offset value to be set in the offset register 14 based on the INDEX value of the index buffer 42 (42a, 42b) storing the INDEX values of the two most recent stream data. In the case of the present embodiment, the computing unit 43 includes an INDEX value written in the index buffer 42a (hereinafter referred to as the Nth INDEX value for convenience) and an INDEX value written in the index buffer 42b (hereinafter referred to as “the INDEX value”). For the sake of convenience, the difference value + 1 is calculated as an offset value based on the (N−1th INDEX value).

  Specifically, for example, when the Nth INDEX value is “5” and the N−1th INDEX value is “4”, the calculator 43 calculates 4-5 + 1 = 0 as an offset value. . Further, as will be described later, when the Nth INDEX value is “5” and the N−1th INDEX value is “3”, the arithmetic unit 43 sets 3-5 + 1 = −1 as an offset value. Calculate as Then, the synchronization circuit 41 sets the offset value calculated by the calculator 43 in the offset register 14.

Next, the operation of the above configuration will be described.
As shown in FIG. 15, when data “1” is received at time T30 and data “2” is received at time T31, the offset value calculated by the calculator 43 is 0-1 + 1 = 0. In this case, the operation mode of the synchronization circuit 41 is that the offset value matches the reference value (0 in this embodiment), so that the writing of the stream data received in the write control block to the FIFO 12 is permitted. Also, when the data “3” is received at time T32, the calculated offset value is 0, and thus the received stream data is written in the FIFO 12.

  When the data “5” is received at time T33, the offset value is calculated as 3-5 + 1 = −1. Then, by setting the offset value of −1 in the offset register 14, the data input of the FIFO 12 is switched to the dummy data buffer 24 side by the selector 25, as in the second embodiment described above, and the family data (X) Is written into the FIFO 12. At this time, the offset value is added to zero. For this reason, the received data “5” is subsequently written to the FIFO 12.

  Thereafter, when the data “6” is received at time T34, the calculated offset value becomes 0, and thus the received stream data is written into the FIFO 12. Also, when the data “7” is received at time T 35, the calculated offset value is 0, and thus the received stream data is written into the FIFO 12.

  By such an operation of the synchronization circuit 41, for example, at time T35, the storage mode of the FIFO 12 is “1” data, “2” data, “3” data, dummy data, in order from the head on the reading side. Data “5”, data “6”, and data “7” are stored. That is, for example, if “4” data is missing, the missing data is compensated by dummy data.

As a result, it is possible to prevent a shift between the channel in which data is lost and another channel. That is, the channels can be synchronized. Although FIG. 15 illustrates CH [0], the same applies to other channels.
As described above, even in the configuration of the present embodiment, as in the second embodiment described above, in the configuration in which processing is performed using stream data received by a plurality of channels, the load on the data processing unit 10 and necessary Memory capacity can be reduced.

  In the case of the present embodiment, the lack of data is detected based on the INDEX value. When data is missing, dummy data for the missing data is stored in the FIFO 12. Thereby, even during the operation of receiving stream data continuously, it is possible to prevent the data from being shifted between the channels and to synchronize the channels.

(Fifth embodiment)
Hereinafter, the fifth embodiment will be described with reference to FIGS. 17 and 18. In addition, since this embodiment becomes a structure which expanded above-described 4th Embodiment, detailed description of the overlapping part is abbreviate | omitted.

  As shown in FIG. 17, the stream data reception mode of this embodiment is substantially the same as that of the fourth embodiment. Data “1” is received at time T40 and “2” is received at time T41. Data is received, data “3” is received at time T42, data “5” is received at time T43, data “6” is received at time T44, and data “7” is received at time T45. It shall be received. Further, it is assumed that the INDEX value is attached to the stream data. In the present embodiment, the measurement points are assigned as INDEX values.

  In this case, the data “4” is missing, but the data “3” is a measurement result (see FIG. 2) in the vicinity of the data “4”. It is presumed that the data “4” is approximate data. Whether or not the data approximates depends on the type of stream data. For example, data output from a temperature sensor or the like is considered to be approximately approximate.

  Now, even if each channel is first synchronized as in the second embodiment described above, there is a cause of loss of synchronization during operation (data loss of INDEX value = 4). If stream data is written in the FIFO 12 as it is, synchronization with other channels cannot be achieved. That is, in the present embodiment, data of different measurement points is processed as data of the same measurement point.

  Therefore, in the present embodiment, when a situation in which the INDEX value becomes discontinuous due to data loss or the like occurs, the channels are synchronized as follows. More specifically, when the difference value between the index values of at least two or more stream data received continuously is 2 or more, the stream data of each channel is synchronized by inserting an element corresponding to the difference value. ing. In the present embodiment, the received stream data is adopted as an element.

  As shown in FIG. 17, the stream buffer 50 of the stream processing apparatus 1 of this embodiment includes a synchronization circuit 51 and a FIFO 12. The synchronization circuit 51 has substantially the same configuration as the synchronization circuit 41 of the fourth embodiment (hereinafter referred to as a write control block for convenience), two data buffers 52 (52a and 52b), and a selector 53. , And a comparator 54.

  The data buffer 52 stores at least two or more stream data received successively. In the case of this embodiment, the received stream data is written in one data buffer 52a, and the previous data written in the data buffer 52a is written in the data buffer 52b. For this reason, two data received successively are stored in the data buffer 52a and the data buffer 52b. Hereinafter, the data written to the data buffer 52a is also referred to as D [N] for convenience, and the data written to the data buffer 52b is also referred to as D [N-1] for convenience.

  The selector 53 switches the data input of the FIFO 12 between the write control block side and the data buffer 52 side. This switching is performed by the comparator 54. The comparator 54 compares the INDEX values of the index buffers 42a and 42b and switches to the data buffer 52 side when the difference between the INDEX values is 2 or more.

Next, the operation of the above configuration will be described.
As shown in FIG. 17, the stream data reception mode of this embodiment is the same as that of the fourth embodiment described above. Therefore, although detailed description is omitted, since the offset value calculated by the calculator 43 is 0 during the period from time T40 to time T42, the received stream data is written in the FIFO 12.

  When the data “5” is received at time T43, the offset value is calculated as 3-5 + 1 = −1. Therefore, the selector 25 switches the path to the dummy data buffer 24 side.

  However, since the difference between the INDEX values is 2 or more, that is, there is missing data, the selector 53 switches the data input of the FIFO 12 to the data buffer 52 side. At time T43, data “5” received at time T43 is stored in the data buffer 52a, and data “3” received at time T42 is stored in the data buffer 52b. Therefore, the data “3” stored in the data buffer 52 b is written into the FIFO 12. Since the offset value becomes 0 when the data “3” is written, the received data “5” is subsequently written to the FIFO 12.

After that, at time T44 and time T45, the calculated offset value is 0 and the difference between the INDEX values is 1. Therefore, the received “6” data and “7” data are written in the FIFO 12 as they are. .
By such an operation of the synchronizing circuit 51, for example, at the time T45, the storage mode of the FIFO 12 is “1” data, “2” data, “3” data, “3” in order from the head on the reading side. Data, “5” data, “6” data, and “7” data are stored. That is, for example, if the data “4” is missing, the missing data is compensated for by the data “3” that is received most recently and the INDEX difference is 1.

As a result, it is possible to prevent a shift between the channel in which data is lost and another channel. That is, the channels can be synchronized. Although FIG. 17 illustrates CH [0], the same applies to other channels.
As described above, even in the configuration of the present embodiment, in the configuration in which processing is performed using stream data received through a plurality of channels, as in the fourth embodiment described above, the load on the data processing unit 10 and necessary Memory capacity can be reduced. In addition, since the data loss is detected based on the INDEX value, it is possible to prevent the data from being shifted between the channels even during the operation of continuously receiving the stream data.
In the case of the present embodiment, for example, when the data “4” is missing, it is compensated with the data “3” that is estimated to approximate it. Depending on the type of stream data, it can be used as it is for data processing. it can.

(Sixth embodiment)
Hereinafter, the sixth embodiment will be described with reference to FIGS. 19 and 20. In the following, an example of combination with a down-counter type synchronization circuit as in the first embodiment is shown, but it may be combined with an up-counter type synchronization circuit as in the second to fifth embodiments.

  As shown in FIG. 19, in the stream data reception mode of this embodiment, data “1” is received at time T50, data “2” is received at time T51, and data “3” is received at time T52. "4" data is received at time T54, "4" data is received again at time T54, "5" data is received at time T55, and "6" data is received at time T56. It shall be received. Further, it is assumed that the INDEX value is attached to the stream data. In the present embodiment, the measurement points are assigned as INDEX values.

In this case, since the data “4” is received in duplicate, if it is written to the FIFO 12 as it is, it cannot be synchronized with other channels. That is, in the present embodiment, data of different measurement points is processed as data of the same measurement point.
Therefore, in the present embodiment, when a situation occurs in which the INDEX value becomes discontinuous due to data duplication, the channels are synchronized as follows.
As shown in FIG. 20, the stream buffer 60 of the stream processing apparatus 1 according to the present embodiment includes a synchronization circuit 61 and a FIFO 12. The synchronization circuit 51 has two index buffers 42 (42a, 42b) in addition to the configuration substantially the same as the down counter type synchronization circuit 13 of the first embodiment (hereinafter referred to as a write control block for convenience). ), A comparator 62, and an AND gate 63.

The index buffer 42 operates substantially the same as in the third embodiment, and stores index values of at least two or more stream data received successively. The INDEX value of the received stream data is written into one index buffer 42a, and the previous INDEX value written in the index buffer 42a is written in the index buffer 42b.
The comparator 62 compares the INDEX value written in the index buffer 42a with the INDEX value written in the index buffer 42b, and outputs an H level when the two match, while the two do not match. Outputs an L level.

  The output of the comparator 62 is inverted and input to the AND gate 63. Further, the output of the AND gate 19 of the write control block is input to the AND gate 63. The output of the AND gate 19 has been described in the first embodiment and will not be described in detail. However, if the offset value matches the reference value (0 in this embodiment), the data valid signal (S_EN) is used. If the offset value and the reference value do not coincide with each other, the signal level becomes the L level even if the data valid signal (S_EN) is input. The output of the AND gate 63 is connected to the write enable signal (WR_EN) of the FIFO 12.

Therefore, in the synchronization circuit 61, when the same INDEX value is stored in the index buffers 42a and 42b, the write permission signal (WR_EN) of the FIFO 12 becomes L level, and writing to the FIFO 12 is restricted.
Next, the operation of the above configuration will be described.
In the case of the reception mode shown in FIG. 19, the synchronization circuit 61 has received the INDEX values (measurement points in the present embodiment) of the stream data continuously received during the period from time T50 to time T53. Stream data is written to the FIFO 12.

On the other hand, when the data of “4” is received at time T54, the synchronization circuit 61 receives data of “4” having the same INDEX value at the previous time T53. The writing of the data “4” received at time T54 is restricted.
After that, when the data of “5” is received at time T55, the synchronization circuit 61 permits writing to the FIFO 12 because the INDEX values are not the same. Also, when data “6” is received at time T56, since the INDEX values are not the same, writing to the FIFO 12 is permitted.

  By such an operation of the synchronizing circuit 61, for example, at the time T56, the storage mode of the FIFO 12 is “1” data, “2” data, “3” data, “4” in order from the head on the reading side. Data, “5” data, and “6” data are stored. That is, for example, when the data “4” is duplicated, writing of the duplicated data is restricted, and the data is canceled (discarded).

As a result, in the case where data overlaps, it is possible to prevent a deviation from occurring with other channels. That is, the channels can be synchronized. Although FIG. 19 illustrates CH [0], the same applies to other channels.
As described above, even in the configuration of the present embodiment, as in the second embodiment described above, in the configuration in which processing is performed using stream data received by a plurality of channels, the load on the data processing unit 10 and necessary Memory capacity can be reduced.

  In addition, the synchronization circuit 61 of the present embodiment has two index buffers 42 (42a and 42b), and when the index value of the received stream data matches the index value of the stream data received immediately before it. The writing of the stream data received this time to the FIFO 12 is restricted. Thereby, even if the data is duplicated during the operation of continuously receiving the stream data, it is possible to prevent the data order from being shifted between the channels. Therefore, the channels can be synchronized.

(Other embodiments)
The present invention is not limited to those exemplified in the above-described embodiments, and can be arbitrarily modified or expanded without departing from the gist thereof.
The hardware configuration exemplified in the embodiment is a functional view of the main part, and is not limited to this. For example, detailed timing control for writing to the FIFO 12 is also performed. That is, each synchronization circuit shown in each embodiment may be realized by different logic circuits as long as substantially the same processing can be performed. Further, the output level of each signal and its polarity are not limited to those exemplified in the embodiment. For example, the signal level for switching between valid / invalid may have the opposite polarity to the embodiment. Of course, when the polarities are different, a logic circuit corresponding to the polarities may be used.

The numbers of the index buffers 42 and the data buffers 52 exemplified in each embodiment are examples, and are not limited to this as long as two or more pieces of data can be stored.
The stream data only needs to be continuously received, and may be video data, music data, or the like.

  In the drawing, 1 is a stream processing device, 11, 20, 30, 40, 50, 60 are stream buffers, 13, 21, 31, 41, 51, 61 are synchronization circuits, 12 is a FIFO, 14 is an offset register, 15 is Subtractors 16 and 23 are gate circuits, 22 is an adder, 24 is a dummy data buffer, 32 is a down counter type synchronization circuit, 33 is an up counter type synchronization circuit, 42, 42a and 42b are index buffers, and 43 is an arithmetic unit 52, 52a and 52b are data buffers, and 54 is a comparator.

Claims (9)

A plurality of stream buffers (11, 20, 30, 40, 50, 60) provided for each channel for receiving stream data;
A data processing unit (10) that performs data processing using stream data read from the plurality of stream buffers (11, 20, 30, 40, 50, 60) at the same timing,
Each of the stream buffers (11, 20, 30, 40, 50, 60)
A FIFO memory (12) for storing received stream data in a first-in first-out manner;
And a synchronization circuit (13, 21, 31, 32, 33, 41, 51, 61) that synchronizes the stream data of each channel by adjusting the timing of writing the received stream data to the FIFO memory (12). A stream processing apparatus. The synchronization circuit (13)
An offset register (14) in which an offset value corresponding to a deviation from the stream data of other channels is set;
A subtractor (15) for subtracting the offset value set in the offset register (14);
When the offset value of the offset register (14) does not match a predetermined reference value, the subtraction of the offset value by the subtracter (15) is enabled and the FIFO memory (12) is written. On the other hand, when the offset value of the offset register (14) matches the reference value, the subtraction of the offset value by the subtracter (15) is invalidated and the FIFO memory (12) is written. An enabling gate circuit (16);
The stream processing apparatus according to claim 1, comprising: The synchronization circuit (13, 21)
An offset register (14) in which an offset value corresponding to the deviation of the stream data between the channels is set;
An adder (22) for adding the offset value set in the offset register (14);
A dummy data buffer (24) for storing dummy data;
When the offset value of the offset register (14) does not match a predetermined reference value, the addition of the offset value by the adder (22) is validated and the data to be written to the FIFO memory (12) Is switched to the dummy data stored in the dummy data buffer (24), while the offset value of the offset register (14) matches the reference value, the addition of the offset value by the adder (22) And a gate circuit (23) for switching the data to be written to the FIFO memory (12) to the received stream data,
The stream processing apparatus according to claim 1, comprising: The synchronization circuit (31)
An offset register (14) in which an offset value corresponding to the deviation of the stream data between the channels is set;
A down counter type synchronization circuit (32) for synchronizing each channel by deleting elements corresponding to the offset value set in the offset register (14);
An up-counter type synchronization circuit (33) for synchronizing each channel by inserting elements corresponding to the offset value set in the offset register (14);
A circuit used when writing data into the FIFO memory (12) according to the sign of the offset value set in the offset register (14) is the down counter type synchronizing circuit (32) or the up counter type synchronizing circuit. A switch (34) for switching to any of (33);
The stream processing apparatus according to claim 1, comprising: The down counter type synchronization circuit (32) validates the subtraction of the offset value by the subtracter (15) when the offset value of the offset register (14) does not match a predetermined reference value. At the same time, the stream data received as the element is deleted by restricting the writing of the received stream data to the FIFO memory (12), while the offset value of the offset register (14) matches the reference value. In this case, the subtraction of the offset value by the subtracter (15) is invalidated, and the received stream data is allowed to be written to the FIFO memory (12).
The up-counter synchronization circuit (33) validates the addition of the offset value by the adder (22) when the offset value of the offset register (14) does not match a predetermined reference value. At the same time, dummy data as the element is inserted by writing dummy data stored in the dummy data buffer (24) in the FIFO memory (12) instead of the received stream data, while the offset register (14) Is equal to the reference value, the addition of the offset value by the adder (22) is invalidated and the received stream data is allowed to be written to the FIFO memory (12). The stream processing apparatus according to claim 4. The stream data includes an index value indicating the order of data,
The synchronization circuit (21, 31, 41) includes an index buffer (42) for storing index values of at least two or more stream data received in succession, and an index value stored in the index buffer (42). A calculation unit (43) for calculating an offset value to be set in the offset register (14) based on the offset value, and setting the offset value calculated by the calculation unit (43) in the offset register (14). The stream processing apparatus according to claim 3, wherein the stream processing apparatus is characterized in that: The stream data includes an index value indicating the order of data,
The synchronization circuit (21, 31, 41, 51) inserts an element corresponding to the difference value when the difference value of the index values of at least two or more stream data received successively is 2 or more. The stream processing apparatus according to claim 3, wherein the stream data of each channel is synchronized.   The synchronization circuit (21, 31, 41, 51) includes an index buffer (42) for storing index values of at least two or more stream data continuously received, and at least two or more streams received continuously. A data buffer (52) for storing data and a comparator (54) for comparing the index values stored in the index buffer (42) to detect a difference are stored in the index buffer (42). If the difference between the index values is 2 or more, the latest stream data having a difference of 1 among the stream data stored in the data buffer (52) as the element is the FIFO memory (12). The stream processing apparatus according to claim 7, wherein the stream processing apparatus writes data to the stream. The stream data includes an index value indicating the order of data,
The synchronization circuit (13, 21, 31, 32, 33, 41, 51, 61) includes an index buffer (42) for storing an index value of at least two or more stream data received in succession. When the index value of the stream data received matches the index value of the stream data received immediately before, the writing of the stream data received this time to the FIFO memory (12) is restricted. The stream processing apparatus according to any one of 1 to 8.

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