JP2016174089A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can sufficiently inhibit pad separation and poor connection.SOLUTION: A semiconductor device of the present embodiment includes: first wiring 15 located on a first insulation film 11; a second insulation film 16 located on the first wiring and the first insulation film; second wiring 20 located on the second insulation film; a third insulation film 21 located on the second wiring and the second insulation film; a barrier layer 24 located on the third insulation film; a pad 30 located on the barrier layer and the third insulation film; a fourth insulation film 28 located on the pad and the third insulation film; and an opening 28a which is formed in the fourth insulation film and located on the pad, in which there are no barrier layer and no second wiring but there is the first wiring under the pad located under the opening.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  A conventional semiconductor device has an I / O pad which is a terminal used for input / output of the external signal, and the structure of the pad is as follows. A barrier metal layer is formed on the interlayer insulating film, an Al alloy film is formed on the barrier metal layer, a passivation film is formed on the Al alloy film, and a pad opening is formed in the passivation film. The Al alloy film exposed through the pad opening becomes a pad.

  By bonding a metal such as wire bonding to the pad, an external component and the semiconductor device are electrically connected. When this connection is made or after the connection is made, there is a problem that a crack occurs in the interlayer insulating film under the pad, or that the pad is peeled off or a connection failure occurs due to insufficient adhesion of the pad.

  As a countermeasure against the above-mentioned problem, Patent Document 1 discloses that a barrier metal layer located under a pad opening is removed to suppress pad cracking, pad peeling, or poor connection.

  However, by simply removing the barrier metal layer located under the pad opening, it is not possible to sufficiently suppress pad cracking, pad peeling or connection failure.

Japanese Patent Laying-Open No. 2004-282034 (FIG. 7)

  Some embodiments of the present invention relate to a semiconductor device capable of sufficiently suppressing pad peeling and connection failure.

  One embodiment of the present invention includes a first wiring located on a first insulating film, a second insulating film located on the first wiring and the first insulating film, and the second insulating film. A second wiring positioned on the film; a third insulating film positioned on the second wiring and the second insulating film; a barrier layer positioned on the third insulating film; and the barrier A layer located on the layer and the third insulating film; a fourth insulating film located on the pad and the third insulating film; and a fourth insulating film formed on the fourth insulating film and located on the pad. And under the pad located under the opening does not have the barrier layer and the second wiring, but has the first wiring. This is a featured semiconductor device.

  According to one embodiment of the present invention, the lower portion of the pad located under the opening does not include the barrier layer and the second wiring, but includes the first wiring. Adhesion between the insulating film and the pad can be improved. As a result, the occurrence of cracks in the third insulating film under the pad due to various impacts applied to the pad can be sufficiently suppressed, and pad peeling and poor connection can be sufficiently suppressed.

  Another embodiment of the present invention is the semiconductor device according to the above embodiment of the present invention, wherein the first wiring is a wiring made of metal or polysilicon. Thereby, the demerit by the restrictions of arrangement | positioning of the wiring which consists of a metal or a polysilicon can be reduced.

  One embodiment of the present invention includes a first wiring including an impurity region located on a semiconductor substrate, a second insulating film located on the first wiring and the semiconductor substrate, and the second insulating film. A second wiring located; a third insulating film located on the second wiring and the second insulating film; a barrier layer located on the third insulating film; the barrier layer; A pad positioned on the third insulating film; a fourth insulating film positioned on the pad and the third insulating film; and an opening formed on the pad and formed on the fourth insulating film. And under the pad located under the opening, the barrier layer and the second wiring are not provided, but the first wiring is provided. It is a semiconductor device.

  According to one embodiment of the present invention, the pad located under the opening does not include the barrier layer and the second wiring, but includes the first wiring including the impurity region. The adhesion between the insulating film and the pad can be improved. As a result, the occurrence of cracks in the third insulating film under the pad due to various impacts applied to the pad can be sufficiently suppressed, and pad peeling and poor connection can be sufficiently suppressed.

  According to one embodiment of the present invention, a first wiring including a silicide region located on a semiconductor substrate or a semiconductor film, a second insulating film located on the first wiring and the semiconductor substrate, and the second insulation A second wiring positioned on the film; a third insulating film positioned on the second wiring and the second insulating film; a barrier layer positioned on the third insulating film; and the barrier A layer located on the layer and the third insulating film; a fourth insulating film located on the pad and the third insulating film; and a fourth insulating film formed on the fourth insulating film and located on the pad. And under the pad located under the opening does not have the barrier layer and the second wiring, but has the first wiring. This is a featured semiconductor device.

  According to the above embodiment of the present invention, the pad located under the opening does not have the barrier layer and the second wiring, but has the first wiring made of the silicide region. The adhesion between the insulating film and the pad can be improved. As a result, the occurrence of cracks in the third insulating film under the pad due to various impacts applied to the pad can be sufficiently suppressed, and pad peeling and poor connection can be sufficiently suppressed.

8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

[Embodiment 1]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

  First, a semiconductor element is formed on a semiconductor substrate (not shown) such as a silicon substrate, and a first interlayer insulating film 11 is formed on the semiconductor substrate. Next, a barrier metal layer 12 is formed on the first interlayer insulating film 11, and an aluminum alloy film 13 is formed on the barrier metal layer 12. Next, a metal layer 14 such as an antireflection film is formed on the aluminum alloy film 13.

  Next, the first wiring 15 is formed on the first interlayer insulating film 11 by patterning the metal layer 14, the aluminum alloy film 13, and the barrier metal layer 12. Next, a second interlayer insulating film (also referred to as a second insulating film) 16 is formed over the first wiring 15 and the first interlayer insulating film 11. Next, a barrier metal layer 17 is formed on the second interlayer insulating film 16, and an aluminum alloy film 18 is formed on the barrier metal layer 17. Next, a metal layer 19 is formed on the aluminum alloy film 18.

  Next, the second wiring 20 is formed on the second interlayer insulating film 16 by patterning the metal layer 19, the aluminum alloy film 18 and the barrier metal layer 17. Next, a third interlayer insulating film (also referred to as a third insulating film) 21 is formed over the second wiring 20 and the second interlayer insulating film 16. Next, a via hole located on the second wiring 20 is formed in the third interlayer insulating film 21, and a barrier metal layer 22 is formed on the inner surface of the via hole and on the third interlayer insulating film 21.

  Next, a W film is formed in the via hole and on the barrier metal layer 22. Next, the W film located on the third interlayer insulating film 21 is removed by CMP to bury a W plug 23 made of the W film in the via hole.

  Next, a barrier metal layer (also referred to as a barrier layer) 24 is formed on the W plug 23 and the third interlayer insulating film 21. For this barrier metal layer 24, for example, a laminated film of a Ti film and a TiN film or a TiN film can be used. Next, an opening 24a is formed in the barrier metal layer 24 by a photolithography technique and an etching technique. The opening 24a is located under a pad opening 28a described later. Next, an aluminum alloy film 25 is formed on the barrier metal layer 24, and a metal layer 26 is formed on the aluminum alloy film 25. For the metal layer 26, for example, a laminated film of a Ti film and a TiN film or a TiN film can be used.

  Next, by patterning the metal layer 26, the aluminum alloy film 25, and the barrier metal layer 24, a third wiring 27 having a pad 30 is formed on the third interlayer insulating film 21. Next, a passivation film (also referred to as a fourth insulating film) 28 is formed over the third wiring 27 and the third interlayer insulating film 21. Next, a pad opening 28a located on the pad 30 is formed in the passivation film 28 by a photolithography technique and an etching technique.

  Under the pad 30 located under the pad opening 28a in the semiconductor device manufactured as described above, the barrier metal layer 24 and the second wiring 20 are not provided, and the first wiring 15 is provided. (See FIG. 1). That is, under the pad 30 located under the pad opening 28a, the opening 24a is provided but the barrier metal layer 24 is not provided, the second wiring 20 is not provided, and the first wiring 15 is provided. have.

  According to the present embodiment, the third interlayer insulating film 21 is formed by removing the barrier metal layer 24 and the second wiring 20 located under the pad opening 28 a and disposing the first wiring 15. And the pad 30 can be improved in adhesion. As a result, it is possible to sufficiently suppress the occurrence of cracks in the interlayer insulating film below the pad 30 when bonding a metal such as wire bonding to the pad 30 or after bonding. It is possible to sufficiently suppress the occurrence of connection failure.

  Further, in the present embodiment, since the first wiring 15 below the wiring immediately below the pad opening 28a can be disposed under the pad opening 28a, the demerit due to the wiring layout restriction is reduced. it can.

  In the present embodiment, the pad 30 is used as a bonding pad for bonding to a metal such as wire bonding, but various uses are possible as long as the pad is used as an impact. It is also possible to use the pad 30 of the present embodiment as a pad to which a probe needle is applied, for example, during probe inspection of a semiconductor device.

  In the present embodiment, the first to third wirings 15, 20, and 27 made of an aluminum alloy film are used. However, first to third wirings made of other metal films may be used.

[Embodiment 2]
FIG. 2 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to one embodiment of the present invention. The same portions as those in FIG.

  An insulating film (also referred to as a first insulating film) 32 is formed over the semiconductor substrate. Next, a polysilicon layer is formed on the insulating film 32, and this polysilicon layer is patterned to form a polysilicon wiring 31 on the insulating film 32.

  Next, the steps after forming a second interlayer insulating film (also referred to as a second insulating film) 16 on the polysilicon wiring 31 and the insulating film 32 are the same as those in the first embodiment.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained.

[Embodiment 3]
3 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. The same portions as those in FIG. 1 are denoted by the same reference numerals, and only different portions will be described.

  The semiconductor device of FIG. 3 has a semiconductor element (not shown) formed on a silicon substrate 33 as a semiconductor substrate, and has a first wiring 34 made of an impurity region located on the silicon substrate 33. A second interlayer insulating film (also referred to as a second insulating film) 16 similar to that shown in FIG. 1 is formed on the first wiring 34 and the silicon substrate 33. A first wiring 34 is formed under the pad 30 located under the pad opening 28a.

  Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

  First, a semiconductor element (not shown) is formed on the silicon substrate 33. Next, impurity ions are implanted into the silicon substrate 33 and heat treatment is performed, whereby the first wiring 34 that is a diffusion layer made of impurity regions is formed in the silicon substrate 33.

  Next, the steps after the step of forming the second interlayer insulating film 16 on the first wiring 34 and the silicon substrate 33 are the same as those in the first embodiment.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained.

[Embodiment 4]
4 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. The same portions as those in FIG. 1 are denoted by the same reference numerals, and only different portions will be described.

  The semiconductor device of FIG. 4 includes a semiconductor element (not shown) formed on a silicon substrate 33 as a semiconductor substrate, and includes a first wiring 35 made of a silicide region located on the silicon substrate. A second interlayer insulating film (also referred to as a second insulating film) 16 similar to that shown in FIG. 1 is formed on the first wiring 35 and the silicon substrate 33. A first wiring 35 is formed under the pad 30 located under the pad opening 28a.

  Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

  First, a semiconductor element (not shown) is formed on the silicon substrate 33. Next, a metal layer is formed on the silicon substrate 33, and the metal layer and the silicon substrate 33 are subjected to heat treatment, whereby the first wiring 35 made of a metal silicide region is formed on the silicon substrate 33.

  Next, the steps after forming the second interlayer insulating film (also referred to as second insulating film) 16 on the first wiring 35 and the silicon substrate 33 are the same as those in the first embodiment.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained.

  In the present embodiment, the first wiring 35 made of the metal silicide region is formed on the silicon substrate 33. However, the first wiring made of the metal silicide region can be formed on various silicon layers. For example, it may be formed on a polysilicon layer.

In one embodiment of the present invention, when a specific B (hereinafter referred to as “B”) is formed above (or below) a specific A (hereinafter referred to as “A”) (when B is formed), It is not limited to the case where B is formed directly (or below) (B is formed). It includes the case where B is formed (otherwise B) is formed on the upper side (or the lower side) of A through other things as long as the effects of the present invention are not inhibited.
Further, the structure expressed by the expression above (or below) is not necessarily limited to one direction. For example, when B is formed above (or below) A (B is formed), the semiconductor device When used upside down, it includes the case where B is formed below (or above) A (B is formed).

  DESCRIPTION OF SYMBOLS 11 ... 1st interlayer insulation film (it is also called 1st insulation film), 12 ... Barrier metal layer, 13 ... Aluminum alloy film, 14 ... Metal layer, 15 ... 1st wiring, 16 ... 2nd interlayer insulation film (Also referred to as second insulating film), 17 ... barrier metal layer, 18 ... aluminum alloy film, 19 ... metal layer, 20 ... second wiring, 21 ... third interlayer insulating film (also called third insulating film) ), 22 ... barrier metal layer, 23 ... W plug, 24 ... barrier metal layer (also referred to as barrier layer), 24a ... opening, 25 ... aluminum alloy film, 26 ... metal layer, 27 ... third wiring, 28 ... Passivation film, 28a... Pad opening (also referred to as opening), 30... Pad, 31... Polysilicon wiring, 32 .. insulating film (also referred to as first insulating film), 33. Wiring.

Claims (4)

A first wiring located on the first insulating film;
A second insulating film located on the first wiring and the first insulating film;
A second wiring located on the second insulating film;
A third insulating film located on the second wiring and the second insulating film;
A barrier layer located on the third insulating film;
A pad located on the barrier layer and the third insulating film;
A fourth insulating film located on the pad and the third insulating film;
An opening formed in the fourth insulating film and positioned on the pad,
The semiconductor device according to claim 1, wherein the first wiring is provided below the pad located below the opening, not the barrier layer and the second wiring. In claim 1,
The semiconductor device, wherein the first wiring is a wiring made of metal or polysilicon. A first wiring composed of an impurity region located on a semiconductor substrate;
A second insulating film located on the first wiring and the semiconductor substrate;
A second wiring located on the second insulating film;
A third insulating film located on the second wiring and the second insulating film;
A barrier layer located on the third insulating film;
A pad located on the barrier layer and the third insulating film;
A fourth insulating film located on the pad and the third insulating film;
An opening formed in the fourth insulating film and positioned on the pad,
The semiconductor device according to claim 1, wherein the first wiring is provided below the pad located below the opening, not the barrier layer and the second wiring. A first wiring composed of a silicide region located in a semiconductor substrate or semiconductor film;
A second insulating film located on the first wiring and the semiconductor substrate;
A second wiring located on the second insulating film;
A third insulating film located on the second wiring and the second insulating film;
A barrier layer located on the third insulating film;
A pad located on the barrier layer and the third insulating film;
A fourth insulating film located on the pad and the third insulating film;
An opening formed in the fourth insulating film and positioned on the pad,
The semiconductor device according to claim 1, wherein the first wiring is provided below the pad located below the opening, not the barrier layer and the second wiring.

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