JP2016172393A - Liquid ejection device and liquid ejection method - Google Patents

Abstract

A liquid discharge apparatus and a liquid discharge method capable of suppressing erroneous discharge due to noise are provided. Data for selecting a waveform from a drive signal is selection data SP, and print data SI defining the size of a liquid dot formed by driving a drive element, and at least part of the selection data SP. A control data generation unit that generates verification data CP including the same logical array, a drive signal generation unit, and a control data generation unit. The print data SI includes the print data SI and the verification data CP, and the print data SI is a predetermined value. Printing control data based on comparison between the controller for outputting the printing control data arranged at the bit positions and the drive signal, the comparison data CD including the verification data CP in the printing control data inputted from the controller, and the selection data SP And an error check unit that detects the number of shifts of the logical array in the data. [Selection] Figure 11

Description

  The present invention relates to a liquid discharge apparatus and a liquid discharge method for discharging a liquid.

  An ink jet printing apparatus, which is an example of the liquid ejection apparatus described above, includes, for example, a controller provided in a printing apparatus main body and a print head that ejects liquid such as ink, as disclosed in Patent Document 1. And a head unit. Various data and signals output from the controller are input to the head unit through a flexible cable. The signal output from the controller is, for example, a drive signal that drives a plurality of ejection units. The data output by the controller is, for example, print data for controlling application and non-application of the drive signal to each ejection unit, and selection that specifies which drive pulse is selected from among a plurality of drive pulses included in the drive signal. It is data.

  By the way, in the printing apparatus, as the medium to be printed becomes larger, the distance that the head unit is scanned becomes longer. As a result, various disturbances caused by the head unit being scanned over a long distance are generated for various processes. As a technique for suppressing the influence of such disturbance, for example, as described in Patent Document 2, a technique is known in which a disturbance with respect to the movement of the carriage is estimated and the estimation result is fed back to the driving amount of the carriage motor.

JP 2007-112149 A JP 2007-283561 A

  On the other hand, the longer the distance that the head unit is scanned, the longer the wiring for transferring data to the head unit. When such a wiring length becomes long, the transfer of data from the controller to the head unit is likely to be affected by disturbance. For example, as the wiring length increases, the frequency of deformation of the flexible cable increases, and further, the frequency of contact between the deformed flexible cable and other parts of the apparatus main body increases. Such an increase in frequency changes the amount of electrostatic charge in the flexible cable and promotes the generation of noise due to a change in static electricity. This type of noise on the wiring is input to the head unit together with the data to be transferred, and causes a data shift that shifts the logical arrangement of the data to be transferred by the noise in the data input to the head unit. Let Such a data shift causes an erroneous ejection in which ink is not ejected from nozzles that should eject ink or ink is ejected from nozzles that should not eject ink, and is an obstacle to improving the quality of printing results. ing. In addition to the ink jet printing apparatus, even in other liquid ejection apparatuses, noise is generated due to various causes in the configuration in which the controller on the main body side and the head unit communicate through a transmission path such as a flexible cable. Therefore, the situation described above is generally common.

  An object of the present invention is to provide a liquid ejection apparatus and a liquid ejection method that can suppress erroneous ejection due to noise.

Hereinafter, means for solving the above-described problems and the effects thereof will be described.
A liquid ejection apparatus that solves the above problems includes a plurality of drive elements for ejecting liquid, a drive signal generation unit that generates a drive signal including a plurality of waveforms for driving the drive elements, and a waveform from the drive signals. The data for selection is selection data, and includes control data that defines the size of a liquid dot formed by driving the driving element, and verification data that includes the same logical array as at least a part of the selection data. Integrated control data including a control data generation unit to be generated, the drive signal generation unit, and the control data generation unit, including the control data and the verification data, and the control data arranged at predetermined bit positions A control unit that outputs the drive signal, comparison data including the verification data in the integrated control data input from the control unit, and the selection An error check unit that detects the number of shifts of the logical array in the integrated control data based on comparison with data, and a bit position shifted by the shift number from the predetermined bit position in the input integrated control data. A correction unit that outputs data as the control data after correction; the discharge control unit that drives the plurality of drive elements based on the control data after correction; and the selection data; the drive elements; A head unit having an error check unit, the correction unit, and the ejection control unit; a flexible cable that electrically connects the control unit and the head unit in the transmission path of the integrated control data; Is provided.

  According to the above configuration, even when a data shift caused by noise occurs, the number of data shifts in the integrated control data is detected, and the drive element is controlled based on the control data corrected according to the detected number of shifts. Driven to discharge liquid. Therefore, erroneous ejection due to noise can be suppressed.

In the liquid ejecting apparatus, it is preferable that the selection data is transferred from the control unit to the head unit before the integrated control data.
According to the above configuration, since the selection data to be compared with the comparison data is transferred to the head unit before the comparison data, the detection processing of the data shift number in the integrated control data smoothly proceeds.

  In the liquid ejecting apparatus, the error check unit includes a first holding unit that holds the comparison data and a second holding unit that holds the selection data. The storage capacity of the first holding unit is: It is preferable that the storage capacity of the second holding unit is larger.

  According to the above configuration, the data length of the comparison data can be made larger than the data length of the selection data. Therefore, it is easier to detect the number of shifts in the logical array than in the comparison mode in which data having the same data length as the selected data is extracted as comparison data for each comparison.

  In the liquid ejection apparatus, the verification data area in the comparison data when there is no data shift is a comparison target area, and the error check unit includes the selection data and the comparison target area in the comparison data. Comparing these data, when these data do not match, shifting the comparison target area bit by bit in the comparison data, and repeatedly comparing the selection data and the data of the comparison target area, When the selection data and the data in the comparison target area match, the number of shifts of the comparison target area until these data match is detected as the shift number in the input integrated control data It is preferable.

  According to the above configuration, since the shift number of the logical array can be detected by the bit shift of the comparison target region, the time required to detect the shift number of the logical array can be shortened.

In the liquid ejection apparatus, it is preferable that the selection data is transferred from the control unit to the head unit before the ejection of the liquid is started.
According to the above configuration, the correction process for the data shift can be performed from the start of the liquid discharge, and thus erroneous discharge due to noise can be appropriately suppressed.

In the liquid ejecting apparatus, it is preferable that the verification data is transferred after the control data when the integrated control data is transferred.
According to the above configuration, when data corresponding to noise is inserted below the integrated control data, data corresponding to noise continues below the verification data. Therefore, data corresponding to noise can be included in the comparison data. Since the data corresponding to noise is characteristic data followed by data of the same logic level, according to such a configuration, the accuracy of determination of coincidence or mismatch between the selection data and the comparison data is improved. As a result, the detection accuracy of the data shift number is improved.

  A liquid discharge method that solves the above problem is a liquid discharge method in which a head drive circuit controls a plurality of drive elements based on a drive signal and integrated control data transmitted by a control unit via a flexible cable and discharges liquid. The drive signal is a signal including a plurality of waveforms for driving the drive element, and the integrated control data is control data that defines the size of a liquid dot formed by driving the drive element; Verification data including the same logical arrangement as at least a part of selection data for selecting a waveform from the driving signal, the control data is transmitted arranged in a predetermined bit position, and the head driving circuit includes A step of acquiring selection data, and the head drive circuit includes the verification data in the selection data and the integrated control data. Comparing the comparison data, which is data, and detecting the number of shifts of the logical array in the integrated control data; and the head driving circuit is configured to detect the shift number from the predetermined bit position in the integrated control data. The shifted bit position data is handled as the corrected control data, and the plurality of driving elements are applied by applying the driving signal to the driving elements based on the corrected control data and the selection data. Driving.

  According to the above method, even when a data shift due to noise occurs, the number of shifts of data in the integrated control data is detected, and the drive element is controlled based on the control data corrected according to the detected number of shifts. Driven to discharge liquid. Therefore, erroneous ejection due to noise can be suppressed.

FIG. 2 is a perspective view illustrating an overview configuration of a printer that is an embodiment of a liquid ejection apparatus. The block diagram which shows the connection form of a head unit and a circuit board. FIG. 6 is a plan view showing the relationship between the arrangement of nozzles and drive elements in the ejection head. (A) is a data block diagram which shows the data structure of selection data, (b) is a data block diagram which shows the data structure of printing control data. 6 is a timing chart showing transitions of various signal outputs and transitions of print control data transfer. FIG. 3 is a block diagram illustrating an electrical configuration of the printer. FIG. 2 is a block diagram showing a part of an electrical configuration of a discharge control system in a head drive circuit. A truth table showing correspondence between print data and pulse selection information. FIG. 3 is a block diagram illustrating an electrical configuration of an erroneous ejection determination system and an ejection control system in a head drive circuit. (A) shows the voltage waveform in the wiring when print control data is normally transferred, and (b) shows the voltage waveform in the wiring when noise occurs. (A) is a data configuration diagram showing a logical array in comparison data and selection data at normal time, and (b-1) to (b-3) are logical arrays in comparison data at abnormal time in order with respect to the selection data. The data block diagram which shows the result of the comparison of a logical value when making it shift. (A) is a schematic diagram which shows the data stored in a 1st register at the time of normality, (b) is a schematic diagram which shows the data stored in a 1st register at the time of abnormality. The flowchart which shows the signal output sequence in a controller. 6 is a flowchart showing a signal input sequence in the head drive circuit.

Hereinafter, an embodiment embodying a liquid ejection apparatus and a liquid ejection method will be described with reference to the drawings.
A printer 11 that is an example of the liquid ejection apparatus illustrated in FIG. 1 is, for example, an ink jet printer. The printer 11 includes a bottomed box-shaped frame 12 that is partially open including the upper part, and a support base 13 that supports paper P, which is an example of a medium, is disposed at the bottom of the frame 12. A guide member 14 extending in parallel with the longitudinal direction of the support base 13 is installed above the support base 13 with both ends supported by the frame 12. The carriage 15 is supported by the guide member 14 so as to be capable of reciprocating in the scanning direction X. The discharge head 16 is supported by the carriage 15 so as to face the support base 13. A liquid container 17 containing ink, which is an example of a liquid, is detachably attached to the carriage 15.

  Note that the number of the liquid containers 17 in the present embodiment is four, and each of the four liquid containers 17 stores inks of different colors. As an example of the ink, black (K), cyan ( C), magenta (M) and yellow (Y) inks are separately stored in these liquid containers 17. The ink supplied from each liquid container 17 is discharged toward the paper P from the discharge head 16 moving in the scanning direction X together with the carriage 15. As a result, a color image or character is printed on the paper P.

  In the scanning direction X, a driving pulley 18 is disposed at one of both ends of the frame 12, and a driven pulley 19 is disposed at the other of the both ends. The driving pulley 18 and the driven pulley 19 are supported by the frame 12 in a rotatable state. An output shaft of a carriage motor 20 that is a power source of the carriage 15 is connected to the drive pulley 18. An endless timing belt 21 is hung on the pair of pulleys 18 and 19. When the driving force of the carriage motor 20 is transmitted to the carriage 15 through the timing belt 21, the carriage 15 guided by the guide member 14 reciprocates in the scanning direction X.

  The printer 11 is provided with a transport motor 22 and various rollers that are rotated by the driving force output by the transport motor 22. The rollers are rotated by driving the transport motor 22, and the rollers are rotated to rotate the rollers in a direction intersecting the scanning direction X, for example, a transport direction Y that is a direction orthogonal to the scanning direction X. The upper sheet P is conveyed.

  In the frame 12, a maintenance device 23 for performing maintenance of the ejection head 16 is provided in a non-printing region that is one end of the moving region of the carriage 15. The maintenance device 23 performs flushing for discharging ink from the discharge head 16 into the cap 24, cleaning for discharging ink of the ink supply system from the discharge head 16, and the like.

Next, a configuration for inputting a signal and transferring data to the head unit 60 including the ejection head 16 will be described with reference to FIG.
As shown in FIG. 2, the printer 11 includes a circuit board 30 fixed to the frame 12 and a head drive circuit 61 provided in the head unit 60. The head drive circuit 61 controls the drive of the drive element 62 provided for each nozzle. The head drive circuit 61 constitutes a head unit 60 together with the ejection head 16. The drive element 62 is, for example, a piezoelectric vibrator or an electrostatic drive element.

  The circuit board 30 is electrically connected to the head drive circuit 61 via a flexible cable 65 which is a transmission path for various data and signals. The flexible cable 65 has a length that does not hinder the movement of the carriage 15. When the flexible cable 65 is deformed as the carriage 15 moves, the flexible cable 65 may come into contact with the frame 12 or other components in the frame 12. Deformation of the flexible cable 65 or contact between the flexible cable 65 and other components may cause a change in the amount of electrostatic charge in the flexible cable 65, which may add noise to data transferred by the flexible cable 65. The deformation of the flexible cable 65 and the contact between the deformed flexible cable 65 and another member are examples of noise sources.

  The circuit board 30 includes a controller 31 that is an example of a control unit that controls driving of the printer 11. The controller 31 has a microcomputer 32 and an ASIC 33. ASIC is an abbreviation for “Application Specific IC”. The controller 31 generates various data and various signals for controlling driving of the driving element 62. Various data generated by the controller 31 is transmitted to the head drive circuit 61 through the data line DL constituting the flexible cable 65. Various signals generated by the controller 31 are output to the head drive circuit 61 through the signal lines SL for each signal constituting the flexible cable 65. The head drive circuit 61 receives various data and signals from the controller 31, and applies or does not apply a plurality of drive pulses included in the received signal for each drive element 62 based on the received various data. The selected drive pulse is input to the drive element 62. Ink is ejected from the nozzle corresponding to the drive element 62 to which the drive pulse is input, and printing of images, characters, and the like based on various data is performed on the paper P. Among the plurality of drive pulses, a drive pulse that vibrates the drive element 62 to such an extent that ink is not ejected is included. No ink is ejected from the nozzle corresponding to the drive element 62 to which such a drive pulse is applied, The ink interface in the nozzle vibrates slightly.

  The data transferred to the head drive circuit 61 includes print data SI which is an example of control data, selection data SP, and verification data CP. The data line DL transfers these data SI, SP, and CP from the controller 31 to the head drive circuit 61. The signals input to the head drive circuit 61 include a drive signal COM, a latch signal LAT, a channel signal CH, a clock signal SCK, and a transfer completion signal TS. Details of these various data and various signals will be described later. In FIG. 2, only one data line DL is shown, but the number of data lines DL is the same as the number of ink colors, and in this embodiment, there are four. The data SI, SP, CP for each color are serially transferred through the data line DL associated with each color, and the data SI, SP, CP for all colors are transferred in parallel through all the data lines DL.

  Next, the discharge head 16 will be described with reference to FIG. As shown in FIG. 3, a nozzle opening surface 161 that is the bottom surface of the ejection head 16 includes a plurality of nozzles 162 that are arranged in a line at a constant nozzle pitch in the transport direction Y that is the vertical direction in the drawing. A column is formed. One nozzle row is formed for each ink, and four nozzle rows are formed on the nozzle opening surface 161 of the present embodiment. One nozzle row is composed of, for example, a total of 360 nozzles 162 indicated by # 1 to # 360. In the example of FIG. 3, four nozzle rows are provided that can eject four colors of ink of black (K), cyan (C), magenta (M), and yellow (Y), respectively. The arrangement pattern of the nozzles constituting the nozzle row is not limited to the one-row arrangement, and may be a zigzag arrangement in which the two rows of nozzles are shifted by a half pitch in the row direction. If the number of nozzles per row is plural, the number may be changed as appropriate.

  The ejection head 16 includes the same number of drive elements 62 as the nozzles 162. The drive element 62 is disposed at a position facing the nozzle 162, and the element arrangement of the drive element 62 has the same arrangement pattern as the nozzle row. In FIG. 3, for convenience of explaining the relationship between the arrangement of the nozzles 162 and the arrangement of the drive elements 62, the drive elements 62 are schematically shown outside the ejection head 16. One discharge portion 63 is configured by the nozzle 162 and the drive element 62 forming one pair. In the ejection head 16, for example, one ejection section group 64 including 360 ejection sections 63 corresponding to each of 360 nozzles 162 is provided for each nozzle row.

Next, various signals used for driving the drive element 62, that is, the drive signal COM, the latch signal LAT, and the channel signal CH will be described with reference to FIG.
As shown in FIG. 5, the controller 31 determines the printing cycle TA as a repeated period in which the drive signal COM is applied once. The printing cycle TA is a period determined by the latch signal LAT, and the controller 31 outputs the latch signal LAT once for each printing cycle TA.

  The drive signal COM is composed of drive pulses having a plurality of waveforms. The drive signal COM in the present embodiment is composed of four drive pulses for each printing cycle TA. The four drive pulses are the first drive pulse DP1, the second drive pulse DP2, the third drive pulse DP3, and the fourth drive pulse DP4. The controller 31 outputs the drive pulses in this order in time series. The first drive pulse DP1 has a large amplitude among the four drive pulses and is output during the first period T1. The second drive pulse DP2 has a small amplitude among the four drive pulses and is output in the second period T2 following the first period T1. The second drive pulse DP2 is a pulse for vibrating the drive element 62 to such an extent that ink is not ejected, and slightly vibrates the ink in the nozzle. The third drive pulse DP3 has a large amplitude among the four drive pulses, and is output in a third period T3 following the second period T2. The fourth drive pulse DP4 has a medium amplitude among the four drive pulses, and is output in a fourth period T4 following the third period.

  The latch signal LAT is a signal for determining various data received from the controller 31 by the head driving circuit 61. The latch signal LAT defines the timing when the output of the drive signal COM is started, that is, the timing when the first drive pulse DP1 is output.

  The channel signal CH defines the timing at which the four driving pulses included in the driving signal COM are switched from the previously output driving pulse to the next driving pulse output subsequent thereto. That is, the channel signal CH is output at a timing when the first driving pulse DP1 is switched to the second driving pulse DP2, is output at a timing when the second driving pulse DP2 is switched to the third driving pulse DP3, and is output from the third driving pulse DP3. It is output at the timing of switching to the 4 drive pulse DP4.

  The controller 31 generates a black print control data SIn (K), a cyan print control data SIn (C), a magenta print control data SIn (M), and a yellow print control data SIn (Y). The signal is transferred to the head drive circuit 61 through the flexible cable 65 in synchronization with the signal SCK. In the following description, when the colors are not particularly distinguished, they are simply referred to as print control data SIn. In the present embodiment, the print control data SIn corresponds to an example of integrated control data.

  The print control data SIn transmitted from the controller 31 is composed of print data SI and verification data CP. The print data SI is generated for each nozzle row, and discharge or non-discharge is determined once for all the discharge units 63 included in the nozzle row. The verification data CP is used to verify the presence / absence of a data shift error. Details of the data shift error will be described later.

  The controller 31 transfers the selection data SP to the head drive circuit 61 in synchronization with the clock signal SCK, and also transfers the print control data SIn for each color in synchronization with the clock signal SCK.

  For example, the controller 31 first transfers the selection data SP when printing is started, that is, before the first ejection of ink by each ejection unit 63 is performed. In other words, the controller 31 transfers the selection data SP before the application of the drive pulse to the drive element 62 is started. The controller 31 transfers new selection data SP at least when a print job is started every time the selection data SP needs to be changed. Next, the controller 31 repeats the transfer of the print control data SIn every print cycle TA. The controller 31 synchronizes the black print data SI (K) and the black verification data CP with the cyan print data SI (C) and the cyan verification data CP in synchronization with the clock signal SCK within the print cycle TA. Transfer one by one. In addition, the controller 31 synchronizes the magenta print data SI (M) and the magenta verification data CP, and the yellow print data SI (Y) and the yellow verification data CP with the clock signal SCK within the print cycle TA. Transfer one by one. The print control data SIn transferred in one printing cycle TA is used for ejection control in the printing cycle TA next to the printing cycle TA.

Next, the selection data SP, print data SI, and verification data CP will be described with reference to FIG.
The selection data SP shown in FIG. 4A is data for selecting the driving mode of each driving element 62, and is data for selecting a waveform from the driving signal COM. There are four types of drive modes of the drive element 62 in the present embodiment, and the selection data SP includes 4-bit data indicating selection of the fourth drive pulse DP4 for each drive mode. The selection data SP includes 4-bit data indicating selection of the third driving pulse DP3 for each driving mode, 4-bit data indicating selection of the second driving pulse DP2 for each driving mode, and first data for each driving mode. It includes 4-bit data indicating selection of drive pulse DP1.

  The print data SI shown in FIG. 4B defines ink ejection and non-ejection for each nozzle 162. Further, the print data SI of the present embodiment defines the size of the ink dots formed on the paper P by the drive of the drive element 62 as the drive mode of the drive element 62. The print data SI is, for example, four-gradation data in which 2 bits are assigned to each nozzle 162, and represents the dot size of any one of no dots, small dots, medium dots, and large dots for each nozzle 162. The print data SI includes upper bit data SIH consisting of only the upper bits of the two bits assigned to each nozzle 162, and lower bit data SIL consisting of only the lower bits of the two bits assigned to each nozzle 162. including. The number of bits included in the high-order bit data SIH is 360 bits in which 360 bits are associated with each nozzle 162 by one bit. The number of bits included in the lower-order bit data SIL is also 360 bits, in which one bit is associated with each nozzle 162 for 360 nozzles 162.

  The verification data CP shown in FIG. 4B has the same data configuration as the selection data SP. In other words, the verification data CP and the selection data SP have the same logical array. When the verification data CP and the selection data SP are serially transferred in synchronization with the clock signal SCK, the transition of the logic level in the verification data CP is the same as the transition of the logic level in the selection data SP. The print control data SIn at the time of transmission includes such verification data CP below the print data SI.

  Next, the electrical configuration of the printer 11 will be described with reference to FIG. As shown in FIG. 6, the controller 31 of the printer 11 includes an external interface (hereinafter also referred to as “external I / F”) 34 in addition to the microcomputer 32 (hereinafter also simply referred to as “computer 32”) and the ASIC 33. And an internal interface (hereinafter also referred to as “internal I / F”) 35. The external I / F 34 is an interface for receiving print job data (hereinafter also simply referred to as “print job”) from a host device such as a personal computer, and the internal I / F 35 communicates with the head drive circuit 61. It is an interface for doing.

  The computer 32 includes a main control unit 41 composed of a CPU, a RAM 42 that temporarily stores various data, and a nonvolatile memory 43 that stores various programs. The computer 32 is electrically connected to an operation unit 25 that is operated to give various instructions and inputs to the printer 11 and a display unit 26 including, for example, a liquid crystal display panel. The main control unit 41 performs processing for receiving an instruction, setting content, and the like based on a signal from the operation unit 25 and display processing for displaying a menu screen, various messages, and the like on the display unit 26. The main control unit 41 controls driving of the carriage motor 20 and the transport motor 22 via the motor drive circuits 51 and 52.

  The ASIC 33 outputs an oscillation circuit 45 that generates a clock signal SCK, a drive signal generation circuit 46 that is an example of a drive signal generation unit that generates the drive signal COM, and data such as print data SI and selection data SP. And a data output control unit 47.

  The RAM 42 has an input buffer 42A, a work memory 42B, and an output buffer 42C. The input buffer 42A temporarily stores print data in a print job received by the external I / F 34 from the host device. The work memory 42B temporarily stores data being processed. In the output buffer 42C, which is also an image buffer, print data SI as image data for printing that is serially transferred to the head drive circuit 61 is developed.

  The main control unit 41 includes a discharge control signal generation unit 411. The ejection control signal generation unit 411 reads out and analyzes the print data in the input buffer 42A, and develops it into multi-bit print data SI with reference to font data, a graphic function, etc. in the nonvolatile memory 43. The developed print data SI is stored in the output buffer 42C, and when the print data SI corresponding to one scan of the ejection head 16 is obtained, the print data SI for one scan is used as a data output control. Is output to the unit 47. In the present embodiment, the ejection control signal generation unit 411 and the data output control unit 47 correspond to an example of a control data generation unit.

  The main control unit 41 instructs the drive signal generation circuit 46 to output the drive signal COM, the latch signal LAT, and the channel signal CH to the head drive circuit 61. The drive signal generation circuit 46 generates a drive signal COM, a latch signal LAT, and a channel signal CH based on an instruction from the main control unit 41, and outputs the signals COM, LAT, and CH to the head drive circuit through the internal I / F 35. Input to 61. That is, the drive signal generation circuit 46 repeats the drive signal COM in which the first drive pulse DP1, the second drive pulse DP2, the third drive pulse DP3, and the fourth drive pulse DP4 are arranged in time series in units of the printing cycle TA. Generate. The drive signal generation circuit 46 synchronizes the timing when the output of the drive signal COM is started and the timing when the output of the latch signal LAT is started. The drive signal generation circuit 46 synchronizes the timing at which the previous drive pulse is switched to the next drive pulse in the drive signal COM and the timing at which the channel signal CH is output. These signals COM, LAT, and CH are input from the internal I / F 35 to the head drive circuit 61 via the flexible cable 65. Further, the drive signal generation circuit 46 inputs a data trigger DT for starting transfer of various data to the data output control unit 47 when the latch signal LAT is output.

  The main control unit 41 instructs the data output control unit 47 to transfer the print control data SIn. The data output control unit 47 obtains permission from the main control unit 41 to directly access the nonvolatile memory 43, and reads the selection data SP from the nonvolatile memory 43. Further, the data output control unit 47 obtains permission from the main control unit 41 to directly access the RAM 42. The data output control unit 47 reads the selection data SP from the nonvolatile memory 43, reads the print data SI from the output buffer 42C, and generates verification data CP having the same data configuration as the selection data SP by reading the selection data SP. All of these are transmitted in synchronization with the clock signal SCK from the oscillation circuit 45.

  Prior to outputting the print data SI, the data output control unit 47 transmits the selection data SP only once at the start of printing. For example, since the logical arrangement corresponding to the printing mode is set in the selection data SP, the selection data SP having the logical arrangement corresponding to the next printing mode is output once at least at the timing when the printing mode changes. At the start of the print job, selection data SP corresponding to the print mode specified in the print job is transmitted from the data output control unit 47 to the head drive circuit 61 through the flexible cable 65.

  Note that the printer 11 of the present embodiment includes, for example, a high-quality print mode such as a photo print mode that gives priority to print quality over the print speed, and a high-speed print mode such as draft print mode that gives priority to print speed over print quality. A plurality of printing modes including are prepared. The nonvolatile memory 43 stores a plurality of selection data SP for each print mode. The controller 31 reads one selection data SP corresponding to the designated print mode from the nonvolatile memory 43 at the start of printing, and outputs the read selection data SP to the head drive circuit 61 prior to the output of the print control data SIn. . In the case of flushing for ejecting ink that is not related to printing, if a driving pulse dedicated for maintenance that is different from the driving pulse at the time of printing is used, the selection data SP for flushing is output at the start of flushing and the flushing is completed. Later, selection data SP before flushing is output.

  The data output control unit 47 serially transfers the print data SI to the head drive circuit 61 through the flexible cable 65 for each nozzle row. Further, when the data trigger DT is input from the drive signal generation circuit 46, the data output control unit 47 receives the verification data CP for the current transfer through the flexible cable 65 after the print data SI for one nozzle row. Serial transfer to the drive circuit 61 is performed. That is, the data output control unit 47 outputs the selection data SP before the print control data SIn in synchronization with the clock signal SCK. Further, the data output control unit 47 displays the print control data SIn composed of the print data SI and the verification data CP in a mode in which the print data SI is arranged at a predetermined bit position, and the verification data CP is converted into the print data SI. Output later.

  The data output control unit 47 has a built-in counter that counts the transfer clock, for example, counts the number of pulses of the clock signal SCK at the time of data output, and outputs data when the counted value reaches the number of bits for each data type. finish. Further, the data output control unit 47 inputs a transfer completion signal TS to the head drive circuit 61 when the transmission of the print data SI and the verification data CP for one nozzle row is completed. The transfer completion signal TS indicates that the transmission of the print data SI and the verification data CP to the head drive circuit 61 is completed.

  The transfer completion signal TS is, for example, temporarily at an H level that is a high logic level while the print control data SIn for one nozzle row is being transferred, and at an L timing that is a low logic level at other timings. Is set. The period required to transfer the print control data SIn for one nozzle row is the transfer period, and the timing when this transfer period has elapsed from the start of the transfer of the print control data SIn is the transfer completion time. The transfer completion signal TS causes the head drive circuit 61 to recognize the period from the completion of the transfer to the start of the next printing cycle TA. In the period from the completion of the transfer to the start of the next printing cycle TA, the head drive circuit 61 performs a process for detecting the number of data shifts due to a data shift error and a process for correcting the print data SI. In other words, the controller 31 sets the print cycle TA so that the transfer period of the print control data SIn, the period required for the shift number detection process, and the period required for the correction process of the print data SI are included in the print period TA. Determine.

  As shown in FIG. 6, one head driving circuit 61 is provided for each type of ink, that is, for each nozzle row. Each head drive circuit 61 includes a control circuit 70, a reception unit 71, an oscillation circuit 72, a data division unit 73, an error check unit 74, and a discharge control unit 75.

  The control circuit 70 controls the operation of each unit included in the head drive circuit 61 based on various signals input from the controller 31. For example, the control circuit 70 starts detection processing for the number of data shifts due to a data shift error at a timing specified by the transfer completion signal TS, and causes each unit to execute correction processing for print data SI thereafter.

  The oscillation circuit 72 generates a clock signal SCKh used for synchronizing the operation of each circuit in the head drive circuit 61. One head unit 60 may be provided with one oscillation circuit 72, and the clock signal SCKh generated by the oscillation circuit 72 may be shared by each head drive circuit 61 provided in one head unit 60.

  The discharge controller 75 controls the driving of each drive element 62 based on various signals input from the controller 31 and corrected print data SI input from the control circuit 70.

  The receiving unit 71 sequentially receives the selection data SP and the print control data SIn for one nozzle row from the data output control unit 47 in synchronization with the clock signal SCK. The receiving unit 71 inputs the selection data SP and the print control data SIn to the data sorting unit 73.

  For example, the selection data SP is input to the data sorting unit 73 at the start of a print job, and the received print control data SIn for one nozzle row is input in the first communication that is subsequent communication. The data sorting unit 73 outputs the selection data SP input at the start of printing or the like to the error check unit 74. The data sorting unit 73 extracts the pre-correction print data EI from the received print control data SIn. Further, the data sorting unit 73 extracts the comparison data CD from the received print control data SIn.

  The print data EI before correction is data including at least the print data SI in the received print control data SIn, and has a data length larger than the data length of the print data SI. The comparison data CD is data including at least the verification data CP in the print control data SIn, and has a data length larger than the verification data CP. The data sorting unit 73 outputs the extracted comparison data CD to the error check unit 74 and outputs the extracted pre-correction print data EI to the discharge control unit 75.

The error check unit 74 includes a first storage unit 741 that is an example of a first holding unit, a second storage unit 742 that is an example of a second holding unit, and a comparison detection unit 743.
The error check unit 74 performs an error check on the print control data SIn input from the controller 31 to the head drive circuit 61. Specifically, the error check unit 74 controls the printing of the selection data SP input from the data sorting unit 73 at the start of printing and the data in the comparison target area in the comparison data CD acquired in the first and subsequent communications. Comparison is made for each communication of data SIn. The error check unit 74 detects the number of data shifts caused by a data shift error with respect to the print control data SIn acquired in each communication.

  The first storage unit 741 stores the comparison data CD received in the first and subsequent communications. The first storage unit 741 updates the comparison data CD stored in the first storage unit 741 every time new verification data CP is input.

  The second storage unit 742 stores the selection data SP received at the start of printing. The second storage unit 742 holds the current selection data SP until new selection data SP is input, for example, until it is changed due to a change in print mode or the like. The storage capacity of the first storage unit 741 is larger than the storage capacity of the second storage unit 742.

  The comparison detection unit 743 compares the comparison area data in the comparison data CD stored in the first storage unit 741 with the selection data SP stored in the second storage unit 742. For example, the comparison detection unit 743 measures the number of bits shifted in the upper direction from the least significant bit in the comparison data CD as the number of data shifts in the selection data SP, and outputs the measurement result to the control circuit 70. To do.

  The control circuit 70 controls the output of the print data storage unit 751 included in the discharge control unit 75 based on the measurement result input from the comparison detection unit 743, that is, the detected data shift number. The control circuit 70 bit-shifts the pre-correction print data EI stored in the print data storage unit 751 based on the detected data shift number. The control circuit 70 stores the pre-correction print data EI after the bit shift in the print data storage unit 751 as the corrected print data SI.

The discharge control unit 75 includes a print data storage unit 751, a selection information generation unit 752, and a gate driver circuit 753.
The print data storage unit 751 generates corrected print data SI from the pre-correction print data EI according to the shift number detected by the control circuit 70. A latch signal LAT is input from the controller 31 to the print data storage unit 751. When the latch signal LAT is input to the print data storage unit 751, the print data storage unit 751 latches the corrected print data SI as the discharge print data SI. The print data storage unit 751 outputs the latched corrected print data SI to the gate driver circuit 753.

  The selection information generation unit 752 receives the selection data SP from the second storage unit 742 and the latch signal LAT and the channel signal CH from the controller 31. The selection information generation unit 752 generates decode data based on the input selection data SP, latch signal LAT, and channel signal CH. The decoded data is data for causing the gate driver circuit 753 to generate the pulse selection information PS. The pulse selection information PS is, for example, a 4-bit logical array that selects at least one of the four drive pulses. The pulse selection information PS associates a drive pulse or a combination of drive pulses with each dot size assigned to each nozzle 162 in the print data SI. That is, in the print data SI, any one of the dot sizes of no dots, small dots, medium dots, and large dots is associated with each nozzle 162, and the pulse selection information PS includes a drive pulse and a drive for each dot size. Correlate combinations of pulses.

  The gate driver circuit 753 receives print data SI from the print data storage unit 751, decode data from the selection information generation unit 752, and drive signal COM from the controller 31. The gate driver circuit 753 drives the drive element 62 based on these various data and various signals. Specifically, the gate driver circuit 753 specifies the dot size selected by the print data SI for each drive element 62, selects the drive pulse associated with the dot size by the pulse selection information PS, and selects the selected drive pulse. A drive pulse is applied to the drive element 62.

  Next, an example of specific configurations of the print data storage unit 751, the selection information generation unit 752, and the gate driver circuit 753 of the ejection control unit 75 will be described with reference to FIG. In FIG. 7, only the configuration provided corresponding to each of the two nozzle drive elements 62A and 62B constituting one nozzle row is shown.

  As shown in FIG. 7, the print data storage unit 751 includes a print data storage unit 751A corresponding to the drive element 62A and a print data storage unit 751B corresponding to the drive element 62B. Each of the print data storage units 751A and 751B has a first shift register 81, a second shift register 82, a first latch circuit 83, and a second latch circuit provided one for each drive element 62. 84.

  In the print data storage unit 751A, the first shift register 81 stores the upper bit data SIH of the print data SI, and the second shift register 82 stores the lower bit data SIL of the print data SI. Similarly, in the print data storage unit 751B, the first shift register 81 stores the upper bit data SIH of the print data SI, and the second shift register 82 stores the lower bit data SIL of the print data SI. To do.

  The input terminal of the first latch circuit 83 is electrically connected to the output terminal of the first shift register 81. The input terminal of the second latch circuit 84 is electrically connected to the output terminal of the second shift register 82. When the latch signal LAT is input to each of the latch circuits 83 and 84, the first latch circuit 83 latches the upper bit data SIH stored in the first shift register 81. The second latch circuit 84 latches the lower bit data SIL stored in the second shift register 82.

  The selection information generation unit 752 includes a third shift register 85 and a logic circuit 86. The third shift register 85 stores selection data SP. The logic circuit 86 receives the selection data SP from the third shift register 85 and the latch signal LAT and the channel signal CH from the controller 31. The logic circuit 86 generates decode data used by the decoder 87 for the decoding process from the selection data SP, and outputs the decode data to each decoder 87 at a timing based on the latch signal LAT and the channel signal CH.

  The gate driver circuit 753 includes a gate driver circuit 753A corresponding to the drive element 62A and a gate driver circuit 753B corresponding to the drive element 62B. Each of the gate driver circuits 753A and 753B includes a decoder 87, a level shifter 88, and a switch circuit 89. The output terminal of the first latch circuit 83 is electrically connected to the input terminal of the decoder 87, and the upper bit data SIH latched by the first latch circuit 83 is input from the first latch circuit 83 to the decoder 87. Is done. The input terminal of the decoder 87 is electrically connected to the output terminal of the second latch circuit 84, and the lower bit data SIL latched by the second latch circuit 84 is input from the second latch circuit 84 to the decoder 87. Is done. The output terminal of the logic circuit 86 is connected to the input terminal of the decoder 87, and the decoded data output from the logic circuit 86 is input from the logic circuit 86 to the decoder 87. The decoder 87 generates pulse selection information PS based on the various types of input data, and outputs the pulse selection information PS to the level shifter 88.

  The level shifter 88 is supplied with the pulse selection information PS from the decoder 87 in order from the higher-order bit data in the pulse selection information PS for each input of the latch signal LAT and the channel signal CH. For example, the logical value of the most significant bit in the logic array of the pulse selection information PS is input at the start of the period T1 that is the first timing, and the pulse selection information PS is input at the start of the period T2 that is the second timing. The logical value of the second bit is input. The level shifter 88 functions as a voltage amplifier. When the logical value of the pulse selection information PS input this time is “1”, the level shifter 88 outputs an ON signal boosted to a voltage that can drive the switch circuit 89, for example, a voltage of about several tens of volts. Further, the level shifter 88 outputs an off signal that does not drive the switch circuit 89 when the logical value of the pulse selection information PS input this time is “0”. The on signal and the off signal generated by the level shifter 88 are input from the level shifter 88 to the switch circuit 89. For example, when the logical value of the most significant bit in the logic array of the pulse selection information PS is “1” at the start of the period T 1, the level shifter 88 inputs an ON signal to the switch circuit 89. Next, when the logical value of the second bit in the pulse selection information PS is “0” at the start of the period T 2, the level shifter 88 inputs an OFF signal to the switch circuit 89.

  A drive signal COM is input from the controller 31 to the input terminal of the switch circuit 89. The drive element 62A or the drive element 62B is connected to the output terminal of the switch circuit 89. An output terminal of the level shifter 88 is connected to the control terminal of the switch circuit 89, and an ON signal and an OFF signal are input from the level shifter 88. When an ON signal is input to the switch circuit 89, any one of the first to fourth drive pulses DP1 to DP4 is applied to each of the drive elements 62A and 62B. For example, when the logical value of the pulse selection information PS input this time to the level shifter 88 is “1”, the switch circuit 89 transitions to the ON state, and the drive pulse at that time is applied to the drive elements 62A and 62B. . On the other hand, when the logical value of the pulse selection information PS input this time to the level shifter 88 is “0”, the switch circuit 89 transits to the OFF state, and the drive pulse at that time is not applied to the drive elements 62A and 62B.

  Next, the relationship between the print data SI and the pulse selection information PS will be described with reference to FIG. FIG. 8 shows print data SI ([00], [01], [10], [11]) for each nozzle and pulse selection information PS ([0100], [0010], [1001], [1010]). It is a truth table showing the correspondence relationship.

  As shown in FIG. 8, the decoder 87 uses the 2-bit print data SI for each drive element 62 and the decode data to select four types of pulses that are 4-bit data (D1, D2, D3, D4). Information PS is generated. Data D1 indicates whether to select the first drive pulse DP1. Data D2 indicates whether or not to select the second drive pulse DP2. Data D3 indicates whether to select the third drive pulse DP3. Data D4 indicates whether to select the fourth drive pulse DP4. The 4-bit pulse selection information PS is input to the switch circuit 89 connected to each drive element 62.

  The logical arrangement of the data D4 in each pulse selection information PS is [0100] in order from the bottom of the truth table, and is the same as the logical arrangement (see FIG. 4) of the selection data SP associated with the fourth drive pulse DP4. is there. The logical arrangement of the data D3 in each pulse selection information PS is [1010] in order from the bottom of the truth table, and is the same as the logical arrangement (see FIG. 4) of the selection data SP associated with the third drive pulse DP3. is there. The logical arrangement of the data D2 in each pulse selection information PS is [0001] from the bottom of the truth table, and is the same as the logical arrangement of the selection data SP (see FIG. 4) associated with the second drive pulse DP2. is there. The logical arrangement of the data D1 in each pulse selection information PS is [1100] in order from the bottom of the truth table, and is the same as the logical arrangement (see FIG. 4) of the selection data SP associated with the first drive pulse DP1. is there.

  That is, in the processing performed by the logic circuit 86 and the decoder 87, the selection data SP, which is 16-bit serial data, is converted into 4-bit parallel data for each drive pulse. For example, the logical array [1010], which is the arrangement of the most significant bits in the parallel data for each drive pulse, is associated with the print data SI of [11]. Further, for example, the logical arrangement of the least significant bits in the parallel data for each drive pulse is associated with the print data SI of [00].

  Specifically, when the logical arrangement in the print data SI for each nozzle is [00], [0100] is generated as the pulse selection information PS. Then, the second drive pulse DP2 is applied in the second period T2 in the current printing cycle TA, and no drive pulse is applied except in the second period T2. As a result, in the current printing cycle TA, the ink is not ejected, and the ink in the nozzle is slightly vibrated to suppress the increase in the viscosity of the ink.

  When the logical arrangement in the print data SI for each nozzle is [01], [0010] is generated as the pulse selection information PS. Then, in the current printing cycle TA, the third drive pulse DP3 is applied in the third period T3, and no drive pulse is applied except in the third period T3. As a result, in the current printing cycle TA, one large ink droplet is ejected and a small dot is formed on the paper P.

  When the logical arrangement in the print data SI for each nozzle is [10], [1001] is generated as the pulse selection information PS. Then, in the current printing cycle TA, the first drive pulse DP1 is applied in the first period T1, and further, the fourth drive pulse DP4 is applied in the fourth period T4. As a result, in the current printing cycle TA, one large ink droplet and one small ink droplet are ejected, and medium dots are formed on the paper P.

  When the logical arrangement in the print data SI for each nozzle is [11], [1010] is generated as the pulse selection information PS. Then, in the current printing cycle TA, the first drive pulse DP1 is applied in the first period T1, and further, the third drive pulse DP3 is applied in the third period T3. As a result, in the current printing cycle TA, two large ink droplets are ejected and large dots are formed on the paper P.

  Next, a specific configuration of the head drive circuit 61 will be described with reference to FIG. As shown in FIG. 9, the error check unit 74 includes a first register 91 having the first storage unit 741, a second register 92 having the second storage unit 742, and the comparison detection unit 743. Yes.

  The first register 91 has a storage capacity capable of storing data of a number of bits obtained by adding a predetermined number of bits as an additional capacity to the number of bits of the print control data SIn for one nozzle row. The additional capacity is a capacity for temporarily storing noise included in the transferred data in the first register 91 together with the print control data SIn when the print control data SIn for one nozzle row is transferred. The additional capacity is set in consideration of the number of data shifts assumed to occur in the print control data SIn due to a data shift error caused by noise. The additional capacity is set in consideration of the time that can be allocated to the shift number detection process in the comparison detection unit 743 in one printing cycle TA. For example, when the additional capacity is 4 bits, the first register 91 sets the bit number of the print control data SIn for one nozzle row, that is, the bit number of the verification data CP to 720 bits that is the bit number of the print data SI. It has a storage capacity of 740 bits, which is a total of 736 bits including 16 bits and 4 bits of the additional capacity.

  The first storage unit 741 is composed of a partial storage area of the first register 91, and has a storage capacity capable of storing data of the number of bits obtained by adding the number of bits of the additional capacity to the number of bits of the verification data CP. ing. For example, the first storage unit 741 has a storage capacity of 20 bits that combines 16 bits of the verification data CP and 4 bits of the additional capacity. Of the data stored in the first register 91, the data transferred from the first storage unit 741 to the comparison detection unit 743 is the comparison data CD. The number of bits of the comparison data CD is the sum of the number of bits of the verification data CP and the number of bits of the additional capacity. The comparison data CD includes data at the lowest address determined in the first storage unit 741, and is transferred from the first storage unit 741 to the comparison detection unit 743 while maintaining a logical arrangement.

  For example, when the additional capacity is 4 bits, the comparison data CD is data from the least significant bit to 20 bits among the data stored in the first register 91. When there is no data shift in the print control data SIn stored in the first register 91, the comparison data CD includes all of the verification data CP and the print data with the least significant bit data of the verification data CP as the lowest order. It consists of a part of SI. That is, the comparison data CD is data including verification data CP in the received print control data SIn.

  The second storage unit 742 has a storage capacity capable of storing the selection data SP, and the second register 92 only needs to be composed of the second storage unit 742 only. The storage capacity of the second storage unit 742 is smaller than the storage capacity of the first storage unit 741.

  The control circuit 70 receives a clock signal SCK, a transfer completion signal TS, and the like from the controller 31. The control circuit 70 generates a control signal AS for controlling the output of the first register 91. The control signal AS is a signal for determining data stored in the first register 91 and transferring the determined data to the second storage unit 742 or the comparison detection unit 743. In addition, the control circuit 70 generates a control signal BS for controlling the output of the second register 92. The control signal BS is a signal for determining the data stored in the second register 92 and transferring the determined data to the comparison detection unit 743.

  For example, when the selection data SP is transferred at the start of printing, the control circuit 70 generates a control signal AS for transferring the data stored in the first register 91 to the second storage unit 742. The control circuit 70 transfers the selection data SP stored in the first register 91 to the second storage unit 742 in response to the output of the control signal AS. In addition, the control circuit 70 transfers the data stored in the first register 91 to the comparison detection unit 743 at the timing specified by the transfer completion signal TS, that is, the timing at which the transfer of the print control data SIn is recognized. A control signal AS for transfer is generated. The control circuit 70 transfers the comparison data CD, which is the data stored in the first storage unit 741, to the comparison detection unit 743 by the output of the control signal AS.

  The print control data SIn received in the first and subsequent communications is stored in the first register 91. At this time, the first register 91 stores the print control data SIn received by the receiving unit 71. The print control data SIn at the time of reception has the same logical arrangement as the print control data SIn at the time of transmission, or has a logical arrangement including the print control data SIn at the time of transmission and noise. For example, when the additional capacity is 4 bits and the print control data SIn at the time of reception does not include noise, the print control data at the time of reception from the fifth address to the lowest address in the first register 91 is received. SIn is stored. On the other hand, when the print control data SIn at the time of reception includes noise, the print control data SIn at the time of transmission and the noise are stored between the highest address and the lowest address of the first register 91. At this time, the address in which the print control data SIn at the time of reception is stored in the first register 91 is shifted upward by the number of bits of noise.

  The comparison detection unit 743 includes a shift register, a comparator, a counter, and the like. The comparison detection unit 743 receives the clock signal SCKh generated by the oscillation circuit 72 of the head drive circuit 61.

  The comparison detection unit 743 compares the data in the comparison target area, which is a part of the comparison data CD, with the selection data SP. The comparison detection unit 743 sets the number of bits of the comparison target area to the number of bits of the selection data SP, and shifts the comparison target area bit by bit in the comparison data CD. In the comparison by the comparison detection unit 743, when the data in the comparison target area matches the selection data SP, the comparison detection unit 743 outputs the number of times shifted so far as the signal NS.

  Specifically, the comparison detection unit 743 first stores, in the comparison data CD transferred from the first storage unit 741, the storage area corresponding to the number of bits of the verification data CP in order from the lowest in the first storage unit 741. That is, the 16-bit storage area from the lowest is set as the comparison target area, and the selection data SP output from the second storage unit 742 is compared with the data in the comparison target area. If these data do not match, the comparison detection unit 743 shifts the comparison target area bit by bit in the comparison data CD using the clock signal SCKh as a shift clock, and the comparison target area data The comparison with the selection data SP is repeated. The number of shifts, which is the number of regions to be compared, is measured by a counter. If the data matches by the comparison, the counter measurement is stopped and a signal NS indicating the count value n at that time is compared and detected. The signal is output from the unit 743 to the control circuit 70.

  The first register 91 is connected to the third register 94 via the selector 93 in a state where data can be transmitted. The selector 93 switches the transfer source for transferring data to the third register 94 between the first register 91 and the second register 92. The third register 94 has a storage capacity capable of storing print control data SIn for one column. The third register 94 has a print data storage unit 751 for storing the corrected print data SI and a third storage unit 754 for storing the selection data SP. Note that the data sorting unit 73 described above includes a first register 91 and a selector 93. The print data storage unit 751 includes the first shift register 81 and the second shift register 82 described above. In the present embodiment, the control circuit 70 corresponds to an example of a correction unit.

  The control circuit 70 transfers the corrected print data SI, which is a part of the data stored in the first register 91, to the third register 94. The control circuit 70 sets a transfer reference address in the address of the first register 91. The transfer reference address is an address in which the most significant data of the print control data SIn is stored if no data shift occurs. The control circuit 70 sets an address that is higher by the number of bits corresponding to the count value n from the transfer reference address as the corrected reference address. Then, the control circuit 70 transfers the data having the highest data stored in the corrected reference address to the third register 94 as corrected print data SI.

  Specifically, when the signal NS indicating the count value n is input from the comparison detection unit 743, the control circuit 70 generates a control signal CS that controls input and output of the selector 93. The control circuit 70 inputs the control signal CS to the selector 93 and transfers the corrected print data SI to the third register 94. For example, the control circuit 70 uses the number obtained by subtracting the count value n from the number of bits obtained by adding the number of bits of the print data SI and the number of bits of the additional capacity as the number of clocks, and uses the shift clock of such number of clocks as the control signal CS. Then, the data stored in the first register 91, that is, the print data EI before correction is transferred to the third register 94. The clock signal SCKh is used as the shift clock.

  When the transfer of the corrected print data SI to the third register 94 is completed, the control circuit 70 switches the input of the selector 93 from the first register 91 to the second storage unit 742 and is stored in the second storage unit 742. The selection data SP is transferred to the third register 94. Through such data transfer, the corrected print data SI and selection data SP are stored in the third register 94. The corrected print data SI is stored in the print data storage unit 751 included in the third register 94, and the selection data SP is stored in the third storage unit 754 included in the third register 94.

  Thereafter, the control circuit 70 generates a control signal DS that controls the output of the third register 94. The control circuit 70 inputs selection data SP stored in the third storage unit 754 from the third storage unit 754 to the selection information generation unit 752 by inputting the control signal DS to the third register 94, and also performs printing. The corrected print data SI stored in the data storage unit 751 is input from the print data storage unit 751 to each decoder 87. The selection information generation unit 752 generates decode data based on the input selection data SP. Next, the selection information generation unit 752 inputs the generated decoded data to each decoder 87. On the other hand, each decoder 87 decodes the input print data SI based on the decode data to generate the pulse selection information PS. Next, each decoder 87 outputs the generated pulse selection information PS to the level shifter 88 in synchronization with the latch signal LAT and the channel signal CH.

  Next, with reference to FIG. 10 and FIG. 11, a process for detecting the number of data shifts due to a data shift error will be described. First, the data shift error will be described with reference to FIG.

  As shown in FIG. 10A, the print control data SIn is transferred in parallel from the controller 31 to the head drive circuit 61 through the flexible cable 65 in synchronization with the clock signal SCK. That is, the print control data SIn is output from the controller 31 as a pulse signal whose logic level transitions between “1” and “0”, and at the timing when the clock signal SCK is input to the head drive circuit 61, the head drive circuit 61. Received at. In the example of FIG. 10A, the logical arrangement of the print control data SIn received by the head drive circuit 61 is “... 10101”.

  By the way, in the process in which the print control data SIn and the clock signal SCK are transferred by the flexible cable 65, the flexible cable 65 is relatively long, and the movement at the time of scanning is also relatively fast. Cheap. As a result, noise is easily applied to the transferred data during the transfer of the print control data SIn and the clock signal SCK and before and after the transfer. As shown in FIG. 10B, when noise N is applied after the transfer of the print control data SIn and the clock signal SCK, the head drive circuit 61 receives the noise N as a logical array “11”, and print control after the transfer. The logical array of the data SIn is handled as “... As a result, the print control data SIn at the time of transmission is shifted by the number of bits of the logical array “11” that is noise N (2 bits in the example in the figure) in the print control data SIn after transfer. That is, a logical array due to noise N is inserted below the correct print control data SIn, and data shift occurs.

  With reference to FIG. 11, the data shift number detection processing will be described. In FIG. 11, a normal time when no data shift error has occurred and an abnormal time when a data shift error has occurred will be described. In the case of an abnormality, a case where a 2-bit logical array due to noise is inserted in the lower order than the verification data CP in the received print control data SIn and a 2-bit data shift occurs in the received print control data SIn. This will be described as an example.

  Further, in FIG. 11, in order to facilitate understanding of the shift number detection process, the addresses where the comparison data CD and the selection data SP are stored are arranged in order from the lowest order from the left to the right in the figure. A logical arrangement of the comparison data CD and a logical arrangement of the selection data SP are shown. That is, the comparison data CD and the selection data SP are shown such that the least significant bit when stored in the first storage unit 741 and the second storage unit 742 is arranged on the leftmost side of the drawing. The higher rank of the comparison data CD indicates the higher rank in the state stored in the first storage section 741, and the lower rank of the comparison data CD indicates the position stored in the first storage section 741. Indicates lower order.

  As shown in FIG. 11A, during normal operation without noise, the data stored in the lower 16-bit storage area in the first storage unit 741 of the comparison data CD is the verification data CP. Further, of the comparison data CD, the data stored in the upper 4 bits storage area in the first storage unit 741 is a part of the print data SI. In this case, the lower 16 bits of the comparison data CD match the selection data SP. Therefore, the signal NS indicating the count value n = 0 is output from the comparison detection unit 743 to the control circuit 70.

  On the other hand, as shown in FIG. 11 (b-1), at the time of abnormality with noise, the lower 2 bits of the comparison data CD are noise, and the first storage of the comparison data CD is the first storage. The data stored in the storage area of 16 bits from the lower 3 bits in the part 741 is the verification data CP. For this reason, when the count value n = 0, the lower 16-bit data of the comparison data CD, that is, the data in the comparison target area does not match the selection data SP.

  If the data does not match at the count value n = 0, the comparison detection unit 743 shifts the logical array of the comparison data CD by 1 bit in the lower direction with respect to the address where the data is stored. Accordingly, the comparison detection unit 743 shifts the comparison target region by 1 bit in the upper direction, and increases the count value n by 1. As a result, as shown in FIG. 11B-2, the lower 1 bit data of the comparison data CD is noise, and the 16 bit data from the lower 2 bits of the comparison data CD is the verification data CP. . For this reason, even when the count value n = 1, the lower 16 bits of the comparison data CD do not match the selection data SP.

  When the count value n = 1 and the data do not match, the comparison detection unit 743 shifts the logical array of the comparison data CD by 1 bit further downward with respect to the stored address. As a result, the comparison detection unit 743 further shifts the comparison target region by 1 bit in the upper direction, and increases the count value n by 1. As a result, as shown in FIG. 11 (b-3), the lower 16 bits of the comparison data CD become the verification data CP. For this reason, when the count value n = 2, the lower 16 bits of the comparison data CD match the selection data SP. When the data matches at the count value n = 2, the comparison detection unit 743 outputs a signal NS indicating the count value n = 2 to the control circuit 70.

  In this way, the shift of the comparison data CD and the comparison with the selection data SP are repeated until the lower 16 bits of the comparison data CD match the selection data SP. Then, the count value n when the lower 16 bits of the comparison data CD coincides with the selection data SP is detected as the data shift number, and the number is output to the control circuit 70.

  Next, the print data SI correction process based on the detected shift number will be described with reference to FIG. In FIG. 12, the additional capacity is 4 bits, and a normal time when no data shift error occurs and an abnormal time when a data shift error occurs are described. In the case of an abnormality, a case where a 2-bit logical array due to noise is inserted in the lower order than the verification data CP in the received print control data SIn and a 2-bit data shift occurs in the received print control data SIn. This will be described as an example. In FIG. 12, the data stored in the first register 91 is shown with the upper right side on the paper.

  As shown in FIG. 12A, the shift number is detected as 0 when noise is normal, and when the shift number is detected as 0, the first register 91 moves in the lower direction from the most significant address of the first register 91. An additional capacity is secured for the additional capacity, and dummy data DD is stored in the additional capacity. The dummy data DD is held in the first register 91 before the print control data SIn is input. The control circuit 70 transfers data from the fifth most significant address to the address corresponding to the number of bits of the print data SI, that is, 720 bits of data stored in the first register 91, that is, the third register 94. . As described above, during normal operation, the above processing removes the dummy data DD from the pre-correction print data EI stored from the highest address of the first register 91, that is, the data including the dummy data DD and the print data SI. Accordingly, the correct print data SI is stored in the third register 94.

  As shown in FIG. 12 (b), when there is an abnormal noise, that is, when the detected number of shifts is 1 or more, in the first register 91, the uppermost address of the first register 91 is directed in the lower direction. Thus, an additional capacity is secured, and print data SI is stored in at least a part of the additional capacity. A part of the print data SI is stored in an area corresponding to the number of shifts from the lowest address in the additional capacity. The control circuit 70 converts the data stored in the first register 91 to the uppermost data by the number of bits corresponding to the detected number of shifts from the data obtained by removing the number of bits of the additional capacity from the highest level. Then, data corresponding to the number of bits of the print data SI is transferred to the third register 94. That is, the control circuit 70 removes the data of the number of bits obtained by subtracting the number of shifts from the number of bits of the additional capacity from the most significant data stored in the first register 91, and sets the number of bits of the print data SI. Corresponding data is transferred from the first register 91 to the third register 94 as corrected print data SI.

  For example, when the additional capacity is 4 bits and the shift number is detected as 2, the number of bits of the print data SI from the third most significant address among the data held in the first register 91. 720-bit data up to the address corresponding to is stored in the third register 94.

  When the shift number is detected as 2, the print control data SIn has a 2-bit data shift, and the start of the print data SI is shifted by 2 bits in the upper direction. That is, the first register 91 holds the 2-bit dummy data DD from the most significant, and stores the print data SI from the third address. Accordingly, by the above processing, the pre-correction print data EI held in the first register 91 from the top, that is, the dummy data DD is removed from the data including the dummy data DD and the print data SI, and the correct print data is obtained. SI is stored in the third register 94.

  In other words, the data stored in the third register 94 is stored in the storage area in which the print data SI is stored if the first register 91 has completed the input of the print control data SIn and no data shift has occurred. This is data stored in the planned storage area when the number of shift clocks is returned by the detected number of shifts.

Next, the operation of the printer 11 will be described with reference to FIGS. 13 and 14.
When a print job is input and printing is started, signals such as a drive signal COM and print control data SIn are transmitted from the controller 31 to the head drive circuit 61 through the flexible cable 65. At this time, the controller 31 executes the signal output sequence shown in FIG. 13, and the head drive circuit 61 executes the signal input sequence shown in FIG. First, a signal output sequence executed by the controller 31 will be described with reference to FIG.

  First, in step S11, it is determined whether it is time to start printing. If it is time to start printing (Yes in step S11), the process proceeds to step S12. On the other hand, for example, if printing is in progress and it is not time to start printing (No determination in step S11), the process proceeds to step S13.

  In step S12, the controller 31 outputs selection data SP. The controller 31 reads the selection data SP corresponding to the print mode designated in the received print job from the nonvolatile memory 43 and transmits it to the head unit 60. Further, the controller 31 writes the selection data SP in a memory such as the RAM 42. When the process of step S12 is completed, the process proceeds to step S13.

  In step S13, the controller 31 outputs print data SI. The controller 31 generates print data SI that can be used by the head drive circuit 61 from print data in the print job, and transmits the print data SI to the head unit 60 in synchronization with the clock signal SCK. When the process of step S13 is completed, the process proceeds to step S14.

  In step S14, the controller 31 outputs verification data CP. The controller 31 reads the selection data SP from the memory and outputs it to the head drive circuit 61 as verification data CP. At this time, the verification data CP is output in synchronization with the clock signal SCK. When the process of step S14 is completed, the process proceeds to step S15.

  In step S15, it is determined whether or not the output of the data SI and CP for one discharge is completed. For example, the controller 31 counts the number of pulses of the clock signal SCK synchronized with the data SI and CP with a counter (not shown) at the time of output, and the count value is a predetermined value corresponding to the data length of the data SI and CP. It is determined that the output has been completed when the value reaches. If the output is not completed (No at Step S15), the process returns to Step S13, and the output of the print data SI (Step S13) or the output of the verification data CP (Step S14) is continued, and the data SI, CP for one discharge Is completed (Yes in step S15), the process proceeds to step S16. In step S <b> 16, the controller 31 outputs a transfer completion signal TS to the head unit 60. In this way, the controller 31 performs printing instructed by the print job by repeatedly executing the signal output sequence shown in FIG. 13 for each printing cycle TA.

On the other hand, in the head unit 60, the following signal input sequence shown in FIG.
First, in step S21, selection data SP is input to the head drive circuit 61. The selection data SP input by the receiving unit 71 is stored in the second storage unit 742 in the error check unit 74. In step S <b> 22, print data SI is input to the head drive circuit 61. The print data SI input by the receiving unit 71 is stored in the first register 91 in the error check unit 74.

  In step S23, verification data CP is input. The verification data CP input by the receiving unit 71 is stored in the first storage unit 741 in the first register 91 in the error check unit 74. In this way, the head drive circuit 61 ends the input of the selection data SP sent at the start of printing and the first print control data SIn (print data SI and verification data CP) sent subsequently.

  In the next step S24, the selection data SP and the comparison data CD are compared. That is, the comparison detection unit 743 compares whether the comparison data CD including the verification data CP input from the first storage unit 741 matches the selection data SP input from the second storage unit 742.

  In step S25, it is determined whether or not the selection data SP matches the data in the planned area that is the verification data CP in the comparison data CD, that is, the data in the comparison target area. If the data do not match (negative determination in step S25), the process proceeds to step S26, and if the data matches (positive determination in step S25), the process proceeds to step S27.

  In step S26, the comparison target area of the comparison data CD is shifted by 1 bit in the register in the comparison detection unit 743, and the count value n is set to n + 1. Then, returning to step S24, the selection data SP and the comparison data CD are compared again.

  In step S27, the count value n, that is, the number obtained by shifting the comparison target area until the selection data SP and the data of the comparison target area of the comparison data CD match is output. In step S28, the pre-correction print data EI stored in the first register 91 is shifted by the number of bits corresponding to the count value n and stored in the print data storage unit 751 as corrected print data SI.

  In step S29, ejection control based on the print data SI stored in the print data storage unit 751 is performed. That is, the gate driver circuit 753 drives the drive element 62 based on the current print data SI input from the print data storage unit 751 and ejects ink droplets from the nozzles 162. Thus, printing for one printing cycle TA is performed by the ejection head 16.

  Thereafter, by repeatedly executing the processing of steps S22 to S29, the head driving circuit 61 sequentially inputs the second and subsequent print control data SIn, and compares the selection data SP with the comparison data CD including the verification data CP. The ejection control based on the print data SI is performed while performing the correction based on.

  As a result, even when a data shift error due to noise occurs, the data shift in the print control data SIn is corrected, and printing based on the correct print data SI is performed. Therefore, erroneous ejection due to noise can be suppressed, thereby improving the quality of the printing result.

  In the present embodiment, the same data as the selection data SP, which is data for selecting the drive pulse applied to the drive element 62, is used as verification data CP for detecting the number of data shifts due to a data shift error. Yes. The selection data SP is essential data for driving the ejection unit 63 to eject ink from the ejection head 16. By using such data as data for detecting data shift errors, it is possible to detect data shift errors with a simple configuration compared to a configuration in which data used only for detecting data shift errors is prepared separately. In addition, the correction is possible.

  Since the selection data SP and the verification data CP are predetermined data that does not depend on each print data SI, for example, for error check of the print data SI, the data calculated from the print data SI is changed to the print data SI. In addition, the data to be transmitted to the head drive circuit 61 can be easily generated as compared with the configuration for transmitting to the head drive circuit 61. Furthermore, the present embodiment is compared with a configuration in which only an error check is performed, such as a configuration in which an error in the print data SI is checked using the print data SI and data calculated from the print data SI. The effect obtained is high in that the number of data shifts is detected and corrected by comparing the selection data SP, which is predetermined data, with the comparison data CD including the verification data CP.

According to the printer 11 of the present embodiment described in detail above, the following effects can be obtained.
(1) The data shift number in the print control data SIn is detected, and the drive element 62 is driven and ink is ejected based on the print data SI corrected according to the detected shift number. Therefore, erroneous ejection due to noise can be suppressed.

  (2) Specifically, the selection data SP is compared with the data in the comparison target area in the comparison data CD. When these data do not match, the comparison target area in the comparison data CD is shifted bit by bit. Thus, the comparison of the selection data SP and the data in the comparison target area is repeated. When the selection data SP matches the data in the comparison target area, the number of shifts of the comparison target area until these data match is detected as the data shift number in the print control data SIn. According to such a configuration, since the shift number of the logical array in the print control data SIn can be detected by the bit shift of the comparison target area, the time required to detect the shift number of the logical array can be shortened. is there.

  (3) The selection data SP is transferred from the controller 31 to the head unit 60 before the print control data SIn. According to such a configuration, since the selection data SP to be compared with the comparison data CD is transferred to the head unit 60 before the comparison data CD, the detection processing of the data shift number in the print control data SIn is performed. Go smoothly.

  (4) The selection data SP is transferred from the controller 31 to the head unit 60 before the ejection of ink from the ejection head 16 is started. According to such a configuration, correction processing for data shift can be performed from the start of ink ejection, that is, from the beginning of printing, so that erroneous ejection due to noise can be appropriately suppressed.

In addition, the said embodiment can also be changed into the following forms.
In the above embodiment, when the print control data SIn is transferred, the verification data CP is transferred after the print data SI. However, the verification data CP may be transferred before the print data SI. Even in such a configuration, the data having the number of bits obtained by adding the number of bits of the verification data CP and the number of bits of the additional capacity is the comparison data with the data that should be the least significant bit of the verification data CP in the print control data SIn CD. Then, while shifting the comparison target area of the comparison data CD, the selection data SP is compared with the data of the comparison target area of the comparison data CD, that is, the data of the planned area that is the verification data CP. The number by which the comparison target area is shifted until the data matches is detected as the data shift number in the print control data SIn.

  However, from the viewpoint of increasing the detection accuracy of the shift number, it is preferable that the verification data CP is transferred after the print data SI. In the configuration in which the verification data CP follows the print data SI, when data corresponding to noise is inserted below the correct print control data SIn, if the data shift does not occur, the verification data CP is scheduled to be entered. The data is data corresponding to noise. That is, the data in the vicinity of the least significant bit of the comparison data CD is data corresponding to noise. As described above, data corresponding to noise is basically H-level data and continuous data having a logical value “1”. Therefore, when comparing the selection data SP with the comparison data CD, the selection data SP is compared with the data that continues at the H level, and therefore, the match or mismatch between the selection data SP and the comparison data CD is accurately determined. Cheap.

  On the other hand, in the configuration in which the print data SI follows the verification data CP, if data corresponding to noise is inserted below the correct print control data SIn, the region that is the verification data CP is expected if no data shift occurs. The data entering is a part of the print data SI. That is, data near the least significant bit of the comparison data CD is a part of the print data SI. Therefore, when the selection data SP and the comparison data CD are compared, the selection data SP and a part of the print data SI are compared, so that the accuracy of determining whether the selection data SP matches the comparison data CD or not. Depends on the logical arrangement in the print data SI.

Therefore, the shift number detection accuracy is improved in the configuration in which the verification data CP is transferred after the print data SI.
In the above embodiment, the entire verification data CP and the entire selection data SP have the same logical array, but the verification data CP may be data including the same logical array as at least a part of the selection data. For example, the verification data CP may be 8-bit data that is the same as the lower 8 bits of the selection data SP. In such a case, a part of the selection data SP, that is, the same part as the verification data CP is used for comparison with the comparison data CD.

  For the verification data CP, the maximum data shift number assumed when a data shift error due to noise occurs, or a predetermined margin (for example, a predetermined value within a range of 1 to 3 bits) is added to the maximum data shift number. It is preferable that the number of bits be a certain number. If the verification data CP having a bit number smaller than the bit number of the selection data SP is used as described above, the print control data SIn can be transferred at a high speed by the amount of the data amount of the print control data SIn, and the error check unit. The check processing load at 74 can be reduced, and the time required for the check processing can be reduced.

  As described above, when the number of bits of the verification data CP is smaller than the number of bits of the selection data SP and a part of the selection data SP is used for comparison with the comparison data CD, the comparison data CD is more than the selection data SP. The storage capacity of the first storage unit 741 may not be larger than the storage capacity of the second storage unit 742. In short, the comparison data CD may be data having a number of bits larger than the number of bits of the verification data CP. With such a configuration, the comparison data CD is compared with the selection data SP while shifting the comparison target area of the comparison data CD. Thus, the number of data shifts can be detected.

  However, if the storage capacity of the first storage unit 741 is larger than the storage capacity of the second storage unit 742, the number of bits of the comparison data CD is larger than the number of bits of the selection data SP, and the verification data CP is selected. As the same data as the data SP, the entire selection data SP can be compared with the comparison data CD. Therefore, since the number of bits of data to be compared increases, the accuracy of determining whether these data match or not match is increased, and the detection accuracy of the number of data shifts is increased.

  In the above embodiment, 16-bit data from the least significant bit of the comparison data CD is compared with the selection data SP. That is, the least significant bit in the comparison data CD is set as a reference position for comparison. The comparison reference position in the comparison data CD is not limited to this, as long as the comparison target area in the comparison data CD, that is, the data in the area scheduled to be the verification data CP is compared with the selection data SP. It is not limited to the lower bits.

  In the above embodiment, the case where data corresponding to noise is inserted below the verification data CP in the print control data SIn and a data shift occurs has been described. When all of the data recognized as print control data SIn including noise is input to a shift register having a storage capacity corresponding to the number of bits of the print control data SIn, correct print control is performed according to the data corresponding to the lower noise. There arises a problem that upper data in the data SIn is pushed out of the shift register. On the other hand, in the above-described embodiment, since the first register 91 has an additional capacity, the correct print control data SIn is stored in the first register 91 without being pushed out, and is corrected based on the detection of the shift number. SI is output from the first register 91. This can solve the above problem.

  Here, in the configuration in which the data recognized as the print control data SIn including noise is counted from the most significant bit and only the data corresponding to the number of bits of the print control data SIn is stored in the shift register, the print data SI is used. However, when data corresponding to noise is inserted in the upper part, there is a problem that lower-order data in the correct print control data SIn is not input to the shift register. In this case, the data near the top of the data stored in the shift register is data corresponding to noise.

  To deal with such a problem, the data stored in the shift register of the number of bits of the print control data SIn is compared with the selection data SP while shifting the comparison target area, which is the verification data CP, one bit at a time in the lower direction. By doing so, the number of data shifts can be detected. Then, the data having the bit number corresponding to the shift number is removed from the most significant data stored in the shift register, and the bit number data of the print data SI is transferred to the print data storage unit 751 to correct the data. The printed data SI is stored in the print data storage unit 751. The shift register does not store the lower-order data in the correct print control data SIn for the data corresponding to the noise, but since this portion is the verification data CP, the print data SI and the selection data SP are stored. It does not affect the discharge control that is used. This can solve the above problem.

  As described above, the configuration in which the comparison target area of the comparison data CD is shifted bit by bit and compared with the selection data SP to detect the shift number of the data and correct the print data SI according to the shift number is the print The present invention can also be applied to the case where it is assumed that data corresponding to noise is inserted above the print data SI in the control data SIn.

  In the above embodiment, the selection data SP is transferred from the controller 31 to the head unit 60 before the print control data SIn for each print job, that is, every time one print data is processed. For example, when there is no change in the print mode, the selection data SP transferred to the head unit 60 in one print job may be used in subsequent print jobs.

  If there is a margin in the printing cycle TA, the selection data SP may be transferred after the print control data SIn. In this case, the selection data SP does not pass through the first register 91 but the second register 92. Should be stored in.

  The head drive circuit 61 may have a nonvolatile memory, and the selection data SP may be stored in the head drive circuit 61 in advance. In this case, it is not necessary to transfer the selection data SP from the controller 31 to the head unit 60. When there are a plurality of print modes, a plurality of selection data SP is stored in the head drive circuit 61, and the selection data SP to be used is transferred from the controller 31 to the head unit 60 according to the set print mode. It suffices if a signal to be specified is sent.

  In the above embodiment, the discharge control unit 75 performs discharge control using the selection data SP stored in the second storage unit 742. However, the discharge control unit 75 performs discharge control using the verification data CP as the selection data SP. You may go. According to this configuration, the verification data CP may be transferred to the third register 94 as it is after the print data SI of the first register 91, and the process of reading the selection data SP from the second storage unit 742, for example, the control circuit 70 selects the selector Since the process of reading the selection data SP by controlling 93 can be made unnecessary, the discharge control can be simplified correspondingly.

  A printer (printing apparatus) as an example of a liquid ejection apparatus is not limited to a serial printer, and may be a line printer or a page printer. For example, the liquid ejecting apparatus may be a line printer including a line head. The line printer is configured by connecting a controller as an example of a control unit in the apparatus main body and a head unit including a line head through a flexible cable. For example, the line head may be a multi-head type head in which a plurality of ejection heads are arranged in a line or zigzag. In the case of this type of multi-head type, the controller is connected to each of a plurality of ejection heads constituting the line head via a flexible cable, or the controller is connected to at least one of the plurality of ejection heads via a flexible cable. Further, a configuration in which the connection destination discharge head is sequentially connected to the adjacent discharge head may be employed. Furthermore, the line head may be configured to be movable up and down during cleaning.

  In the above embodiment, the controller 31 that is an example of the control unit is realized by the cooperation of software by a computer that executes a program and hardware by an electronic circuit such as an ASIC, but the controller 31 is configured only by software. It may be configured only by hardware.

  -A flexible cable is not limited to a flexible flat cable, What is necessary is just a flexible cable. For example, the controller 31 and the head unit 60 may be connected via a plurality of flexible cables. Note that the flexible cable may be configured to have at least one signal line, but a configuration including a plurality of signal lines is preferable for the purpose of reducing the number of cables.

  -The liquid ejection device is not limited to an ink jet printer (printing device), but is a liquid other than ink, for example, a liquid material in which particles of a functional material are dispersed or mixed in a liquid, a fluid such as a gel A liquid discharge apparatus that discharges water may also be used. For example, a liquid ejection device ejects a liquid material that contains materials such as electrode materials and color materials (pixel materials) used in the manufacture of liquid crystal displays, EL (electroluminescence) displays, and surface-emitting displays in a dispersed or dissolved state. It may be a liquid ejection device. Furthermore, the liquid ejection device may be a liquid ejection device that ejects biological organic materials used in biochip manufacturing, or a liquid ejection device that ejects a liquid that is used as a precision pipette as a sample. Furthermore, the liquid ejecting device is an ultraviolet curable resin for forming liquid ejecting devices that pinpoint lubricant oil to precision machines such as watches and cameras, and micro hemispherical lenses (optical lenses) used for optical communication elements. A liquid discharge apparatus that discharges a transparent resin liquid such as a liquid onto the substrate, or a liquid discharge apparatus that discharges an etching liquid such as acid or alkali to etch the substrate or the like may be used. Moreover, the liquid discharge apparatus which discharges a liquid and manufactures a three-dimensional structure may be sufficient.

  DESCRIPTION OF SYMBOLS 11 ... Printer as an example of a liquid discharge apparatus, 16 ... Discharge head, 162 ... Nozzle, 25 ... Operation part, 26 ... Display part, 31 ... Controller which is an example of a control part, 41 ... Main control part, 411 ... Control data An ejection control signal generation unit that is an example of a generation unit, 46 ... a drive signal generation circuit that is an example of a drive signal generation unit, 47 ... a data output control unit, 60 ... a head unit, 61 ... a head drive circuit, 62 ... a drive element, 63 ... discharge unit, 64 ... discharge unit group, 65 ... flexible cable, 70 ... control circuit as an example of correction unit, 74 ... error check unit, 741 ... first storage unit as an example of first holding unit, 742 ... Second storage unit as an example of the second holding unit, 743... Comparison detection unit, 75... Discharge control unit, SIn, SIn (K), SIn (C), SIn (M), SIn (Y). Print control data, COM ... drive signal, SP ... selection data, SI ... print data, EI ... pre-correction print data, CP ... verification data, CD ... comparison data, DP1, DP2, DP3, DP4 ... drive Pulse, P: paper as an example of medium, X: scanning direction, Y: transport direction.

Claims (7)

A plurality of driving elements for discharging liquid;
A drive signal generator for generating a drive signal including a plurality of waveforms for driving the drive element;
Data for selecting a waveform from the drive signal is selection data, control data that defines the size of a liquid dot formed by driving the drive element, and the same logical arrangement as at least a part of the selection data A control data generation unit for generating verification data including
The drive signal generation unit and the control data generation unit include the control data and the verification data, and output the integrated control data in which the control data is arranged at a predetermined bit position and the drive signal A control unit,
An error check unit that detects the number of shifts of the logical array in the integrated control data from a comparison between the comparison data including the verification data in the integrated control data input from the control unit, and the selection data;
A correction unit that outputs data at a bit position shifted by the shift number from the predetermined bit position in the input integrated control data as the control data after correction;
An ejection controller that drives the plurality of drive elements based on the control data after the correction and the selection data;
A head unit having the drive element, the error check unit, the correction unit, and the ejection control unit;
A liquid ejection apparatus, comprising: a flexible cable that is a transmission path for the integrated control data and electrically connects the control unit and the head unit. The liquid ejection apparatus according to claim 1, wherein the selection data is transferred from the control unit to the head unit before the integrated control data. The error check unit
A first holding unit that holds the comparison data; and a second holding unit that holds the selection data;
The liquid ejection apparatus according to claim 1, wherein a storage capacity of the first holding unit is larger than a storage capacity of the second holding unit. The verification data area in the comparison data when there is no data shift is a comparison target area,
The error check unit
The selection data is compared with the data in the comparison target area in the comparison data, and when these data do not match, the comparison target area is shifted bit by bit in the comparison data, and the selection data And comparing the data of the comparison target area,
When the selection data and the data in the comparison target area match, the number of shifts of the comparison target area until these data match is detected as the shift number in the input integrated control data The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. The liquid ejection apparatus according to claim 1, wherein the selection data is transferred from the control unit to the head unit before the liquid ejection is started. . The liquid ejection apparatus according to claim 1, wherein the verification data is transferred after the control data when the integrated control data is transferred. A liquid ejection method in which a head drive circuit controls a plurality of drive elements based on drive signals and integrated control data transmitted via a flexible cable by a control unit, and ejects liquid,
The drive signal is a signal including a plurality of waveforms for driving the drive element,
The integrated control data includes the same logical arrangement as control data that defines the size of a liquid dot formed by driving the driving element and at least part of selection data for selecting a waveform from the driving signal. Verification data, and the control data is arranged and transmitted in a predetermined bit position,
The head driving circuit obtaining the selection data;
The head driving circuit detects the number of shifts of the logical array in the integrated control data by comparing the selection data with comparison data that is a part of the integrated control data including the verification data. When,
The head driving circuit treats data at a bit position shifted by the shift number from the predetermined bit position in the integrated control data as the corrected control data, and the corrected control data and the selection data Driving the plurality of drive elements by applying the drive signal to the drive elements based on:
A liquid discharge method comprising:

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