JP2016031993A - Solid state image pickup device and camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art for improving accuracy of focus detection by a solid state image pickup device having a plurality of photoelectric conversion element in one pixel.SOLUTION: A solid state image pickup device having a plurality of pixels comprises: a semiconductor substrate; and a light guide structure located on a light receiving side of the semiconductor substrate. At least one of the plurality of pixels has a plurality of photoelectric conversion elements on the substrate for generating a signal for focus detection. The light guide structure has a first gap for defining an optical path and a second gap for defining an optical path in the pixel having the plurality of photoelectric conversion elements. A distance between an end of the second gap on the side opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate is shorter than a distance between an end of the first gap on the side opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solid-state imaging device and a camera.

  The solid-state imaging device of Patent Document 1 has focus detection pixels in some pixels. The focus detection pixel has a plurality of photoelectric conversion elements, and light obtained by adding different regions of microlenses arranged on the pixels is separately detected by these photoelectric conversion elements. Focus detection by triangulation is performed based on signals obtained by a plurality of photoelectric conversion elements. In the solid-state imaging device of Patent Document 1, an interlayer insulating layer formed on a semiconductor substrate has a gap for separating a plurality of pixels from each other, and a plurality of photoelectric conversion elements in one focus detection pixel in plan view. Have a gap for separating them from each other.

JP 2009-158800 A

  A gap for separating a plurality of pixels and a gap for separating a plurality of photoelectric conversion elements in one pixel have the same height and width. The inventor has found that it is difficult to accurately perform focus detection with such a configuration. An object of the present invention is to provide a technique for improving the accuracy of focus detection by a solid-state imaging device having a plurality of photoelectric conversion elements in one pixel.

  In view of the above problems, the first aspect is a solid-state imaging device having a plurality of pixels, comprising a semiconductor substrate and a light guide structure positioned on a light receiving surface side of the semiconductor substrate, and at least one of the plurality of pixels. One has a plurality of photoelectric conversion elements in the semiconductor substrate to generate a signal for focus detection, and the light guide structure includes a first gap that defines an optical path between pixels, and the plurality of photoelectric conversion elements. A second gap defining an optical path in a pixel having a conversion element, and a distance between an end of the second gap opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate is defined by the first gap. There is provided a solid-state imaging device characterized in that the distance is shorter than the distance between the end opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate. In a second aspect, the solid-state imaging device includes a plurality of pixels, and includes a semiconductor substrate and a light guide structure positioned on a light receiving surface side of the semiconductor substrate, and at least one of the plurality of pixels includes a focus detection A plurality of photoelectric conversion elements in the semiconductor substrate for generating a signal for the first light source, and the light guide structure includes a first gap that defines an optical path between the pixels, and an inner pixel including the plurality of photoelectric conversion elements. There is provided a solid-state imaging device having a second gap defining an optical path of the first gap, wherein the width of the first gap is wider than the width of the second gap. In a third aspect, a solid-state imaging device having a plurality of pixels, the semiconductor substrate, a light guide structure located on a light receiving surface side of the semiconductor substrate, and a side opposite to the light receiving surface of the semiconductor substrate A wiring layer and an interlayer insulating layer, wherein at least one of the plurality of pixels has a plurality of photoelectric conversion elements on the semiconductor substrate to generate a signal for focus detection, and the light guide structure includes: A solid-state imaging device having a first gap that defines an optical path of each pixel is provided.

  The above means provides a technique for improving the accuracy of focus detection by a solid-state imaging device having a plurality of photoelectric conversion elements in one pixel.

The top view of the solid-state imaging device of some embodiments. FIG. 1B is a cross-sectional view of the solid-state imaging device of FIG. 1A. Sectional drawing of the solid-state imaging device of other one part embodiment. Sectional drawing of the solid-state imaging device of other one part embodiment. The figure explaining the modification of the solid-state imaging device of FIG. 1A. The figure explaining the other modification of the solid-state imaging device of FIG. 1A. The top view of the solid-state imaging device of some embodiments. FIG. 6B is a cross-sectional view of the solid-state imaging device in FIG. 6A.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. Throughout the various embodiments, similar elements are given the same reference numerals, and redundant descriptions are omitted. In addition, each embodiment can be appropriately changed and combined. Embodiments described below relate to a solid-state imaging device, and more particularly, to a solid-state imaging device used for a digital camera, a digital video camera, or the like.

<First Embodiment>
A solid-state imaging device 10 according to the present embodiment will be described with reference to FIGS. 1A and 1B. FIG. 1A is a schematic plan view schematically showing a part of the solid-state imaging device 10. This plan view shows a plan view of the surface (light-receiving surface) of the semiconductor substrate 130 included in the solid-state imaging device 10. FIG. 1B is a schematic cross-sectional view along AA ′ in FIG. 1A. The solid-state imaging device 10 has a pixel array composed of a plurality of pixels arranged in a two-dimensional array. In FIG. 1A, attention is paid to four pixels 100, 100a, 100b, and 100c among a plurality of pixels. In FIG. 1B, attention is focused on one pixel 100 of these four pixels and a part of the pixel adjacent to the pixel 100. The pixels 100a, 100b, 100c and other pixels not shown may have the same structure as the pixel 100, or may have other structures.

  As illustrated in FIG. 1A, the pixel 100 includes two light receiving regions 102 and 103 and a wiring region 104. The light receiving regions 102 and 103 are regions that generate charges according to incident light. The wiring region 104 is a region where conductive patterns, plugs, and the like are arranged. The focus detection by the phase difference detection method is performed by the signals obtained in the light receiving regions 102 and 103, respectively. An on-chip lens 101 is disposed in contact with the pixel 100. The on-chip lens 101 may be arranged so as to circumscribe the pixel 100. In this case, a lens having a high light collecting ability without an inter-lens gap can be used as the on-chip lens 101.

  As shown in FIG. 1B, the pixel 100 of the solid-state imaging device 10 includes a semiconductor substrate 130 that is, for example, an n-type silicon substrate and a light guide structure 180 that is positioned on the light receiving surface side of the semiconductor substrate 130 in the cross-sectional view. A p-type well layer 131 is formed on the surface side of the semiconductor substrate 130. An n-type charge storage portion 132 is formed in the well layer 131. Of the charge storage unit 132, portions included in the pixel 100 serve as the charge storage unit 133 and the charge storage unit 134. A high-concentration p-type layer 135 is disposed on the charge storage unit 133 and the charge storage unit 134. The n-type charge storage portion 133 and the p-type semiconductor region around it form a photodiode that is a photoelectric conversion element. This photodiode corresponds to the light receiving region 102 in FIG. The same applies to the charge storage unit 134.

  In the semiconductor substrate 130, a p-type inter-pixel separation unit 136 is disposed between the pixel 100 and a pixel adjacent to the pixel 100. The inter-pixel separation unit 136 separates photodiodes included in different pixels. Further, in the semiconductor substrate 130, an in-pixel separation unit 137 is disposed between the charge storage unit 133 and the charge storage unit 134. The two photodiodes in the pixel 100 are separated by the in-pixel separation unit 137. The potential of the intra-pixel separation unit 137 may be lower than the potential of the inter-pixel separation unit 136. Although not shown, the p-type well layer 131 is formed with a transistor and a floating diffusion layer for transferring and driving the charge of the photodiode.

  As shown in FIG. 1B, on the semiconductor substrate 130, an insulating layer 140 including a gate insulating film, one or more interlayer insulating layers 141, 142, and 143 that are, for example, silicon oxide films, a protective film 144, and the like. Are formed in order from the lower side (semiconductor substrate 130 side). Although not shown, the gate electrode of the transistor described above is formed on the gate insulating film. The interlayer insulating layers 141, 142, and 143 are provided with wiring layers 150 and 152 mainly composed of copper, for example, and wiring layers 154 mainly composed of aluminum, for example. Thereby, the pixel signal is transmitted. The wiring layers 150, 152, and 154 are disposed in the wiring area 104 described above. When copper wiring is used for the wiring layers 150 and 152, copper diffusion prevention layers 151 and 153 may be provided. The diffusion prevention layers 151 and 153 may be selectively removed in the light receiving regions 102 and 103 described above. On the protective film 144, the planarization layer 160, the color filters 161 and 162, the planarization layer 163, and the on-chip lens 101 are provided. The light guide structure 180 is configured by members formed on the semiconductor substrate 130.

  The pixel 100 of the solid-state imaging device 10 has a gap 110 and a gap 120 in the light guide structure 180. As shown in FIG. 1A, the gap 110 is arranged between the light receiving regions 102 and 103 of the pixel 100 and the light receiving regions of other pixels in plan view. More specifically, the gap 110 is disposed between the light receiving regions 102 and 103 and the wiring region 104. The gap 110 surrounds the outer peripheries of the light receiving regions 102 and 103 in a plan view. Thus, the gap 110 defines an optical path between pixels of a plurality of pixels. The gap 120 is disposed between the light receiving region 102 and the light receiving region 103 of the pixel 100. The light receiving region 102 and the light receiving region 103 are divided by the gap 120. Both ends of the gap 120 are in contact with the gap 110. Accordingly, the light receiving regions 102 and 103 are surrounded by the gap 110 and the gap 120, respectively. Thus, the gap 120 defines the optical path within the pixel 100.

  As shown in FIG. 1B, the gap 110 is formed across the three interlayer insulating layers 141-143. That is, the lower end of the gap 110 is at the same height as the lower surface of the interlayer insulating layer 141, and the upper end of the gap 110 is at the same height as the upper surface of the interlayer insulating layer 143. Here, “height” refers to the distance from the surface of the semiconductor substrate 130. The same applies to the following description regarding height. The upper end of the gap 110 is the end of the gap 110 on the side opposite to the semiconductor substrate 130, and the lower end of the gap 110 is the end of the gap 110 on the semiconductor substrate side. It is the end. The same applies to the upper and lower ends of other members located on the semiconductor substrate 130. The gap 120 is formed in one interlayer insulating layer 141. That is, the lower end of the gap 120 is at the same height as the lower surface of the interlayer insulating layer 141, and the upper end of the gap 120 is at the same height as the upper surface of the interlayer insulating layer 141. Further, the upper end of the gap 120 is at the same height as the upper surface of the wiring layer 150. As described above, the height of the upper end of the gap 120 is lower than the height of the upper end of the gap 110.

  The gaps 110 and 120 may be filled with a gas containing air or an inert gas, or may be a vacuum. In the present embodiment, the upper end of the gap 110 is blocked by the protective film 144. Further, the upper end of the gap 120 is closed by the interlayer insulating layer 142. However, the gaps 110 and 120 may be filled with another interlayer insulating layer or another layer. The side surfaces of the gaps 110 and 120 may be smooth surfaces. Here, the “smooth surface” refers to a surface that does not have a step or a corner at the boundary between a plurality of interlayer insulating layers. Specifically, the side surfaces of the gaps 110 and 120 may be flat as shown in FIG. 1B or may be smooth curved surfaces.

  The light flux 170 incident on the pixel 100 from the first direction is guided to the photodiode including the charge storage portion 133, and the light flux 171 incident on the pixel 100 from the second direction is guided to the photodiode including the charge storage portion 134. It is burned. At that time, the component converged by the on-chip lens 101 is confined in the pixel 100 by the gap 110. Further, due to the gap 120, the component of the light beam 170 incident from the first direction and the component of the light beam 171 incident from the second direction are divided into the charge storage unit 133 side and the charge storage unit 134 side. In the present embodiment, since the upper end of the gap 110 is at the same height as the upper surface of the interlayer insulating layer 143, light incident on the pixel 100 is difficult to leak to pixels other than the pixel 100. Further, since the upper end of the gap 120 is lower than the upper end of the gap 110, the component of the light beam 170 incident from the first direction and the component of the light beam 171 incident from the second direction are combined into the charge storage unit. It can be efficiently divided into the 133 side and the charge storage unit 134 side. Thereby, crosstalk between pixels can be suppressed, and highly accurate focus detection can be performed.

  The pixel 100 described in the present embodiment may be applied to all the pixels of the solid-state imaging device 10. Alternatively, the pixel 100 may be applied to only a part of the pixels of the solid-state imaging device 10 and the other pixels may have only one light receiving region. A pixel having only one light receiving region performs normal signal processing and does not perform focus detection. Such a pixel does not have to include the gap 120 and the intra-pixel separation portion 137.

  In the above-described example, the gap 110 is disposed over the three interlayer insulating layers, but may be disposed over the two interlayer insulating layers. In the above-described example, the gap 120 is arranged in one interlayer insulating layer, but may be arranged over two interlayer insulating layers. Either way. The upper end of the gap 120 may be at a position lower than the upper end of the gap 110.

Second Embodiment
A solid-state imaging device according to the second embodiment will be described with reference to FIG. This solid-state imaging device is different from the solid-state imaging device 10 in that the pixel 200 is provided instead of the pixel 100, and other points may be the same. The pixel 200 is different from the pixel 100 in that it has a light guide structure 280 having gaps 210 and 220 and a wiring layer 154 instead of the light guide structure 180 having gaps 110 and 120 and a wiring layer 154. May be the same. The plan view of the solid-state imaging device according to the present embodiment is the same as FIG. 1A, but the widths of the gaps 210 and 220 are different from the gaps 110 and 120 as will be described later. The widths of the gaps 210 and 220 may be measured near the upper ends of the gaps 210 and 220, may be measured near the lower ends, or may be measured at other positions. The height of the gaps 210 and 220 from the semiconductor substrate 130 may be measured at the same position.

  FIG. 2 is a schematic cross-sectional view of the solid-state imaging device of the present embodiment at a position corresponding to FIG. 1B. The height of the upper end of the gap 220 is equal to the height of the upper end of the gap 210. Specifically, both coincide with the height of the interlayer insulating layer 143. Further, the width of the gap 220 is narrower than the width of the gap 210. The width of the gap 210 may be constant at any position of the gap 210. Similarly, the width of the gap 220 may be constant at any position of the gap 220.

  Since the height of the upper end of the gap 220 is equal to the height of the upper end of the gap 210, the component of the light beam 170 incident from the first direction and the component of the light beam 171 incident from the second direction are at the upper end of the gap 220. An on-chip lens 201 having a large curvature is used so as to be separated at a height. In such a case, a component leaking from the gap 210 to another pixel increases. For this reason, the width of the gap 210 is made larger than the width of the gap 220. The width of the second gap 220 is, for example, 100 nm or less. With this size, a reduction in the amount of incident light and generation of stray light due to light reflected at the upper end of the gap 220 can be allowed. Further, with this size, the material of the protective film 144 can be prevented from entering from the upper end of the gap 220.

  The width of the gap 210 is, for example, about 200 nm. With this size, light in the visible light band can be sufficiently separated. The material closing the upper end of the gap 210 may be a metal. If the material is a metal, even if the material enters the gap 210, the light separating function is not impaired. In the present embodiment, the upper end of the gap 210 is closed by the wiring layer 254. Also in this embodiment, crosstalk between pixels can be suppressed, and highly accurate focus detection can be performed.

<Third Embodiment>
A solid-state imaging device according to a third embodiment will be described with reference to FIG. This solid-state imaging device is different from the solid-state imaging device of the second embodiment in that the pixel 300 is provided instead of the pixel 200, and other points may be the same. Further, the pixel 300 is different from the pixel 200 in that it has a light guide structure 380 having a gap 320 instead of the light guide structure 280 having a gap 220, and the other points may be the same. In the present embodiment, the height of the upper end of the gap 320 is lower than the height of the upper end of the gap 210. Further, the width of the gap 320 is narrower than the width of the gap 210. That is, this embodiment can be said to be an embodiment in which the first embodiment and the second embodiment are combined. Therefore, the matters described in these embodiments are also applicable to this embodiment. Also in this embodiment, crosstalk between pixels can be suppressed, and highly accurate focus detection can be performed.

<First Modification>
A first modification of the solid-state imaging device 10 according to the first embodiment will be described with reference to FIG. Matters not mentioned here can follow the first embodiment. The upper end of the gap 120 in the first embodiment was flat. In this modification, a gap 420 is provided instead of the gap 120. The upper end of the gap 420 has a convex shape upward (that is, in a direction away from the semiconductor substrate 130).

  Hereinafter, a method for manufacturing the gap 420 having such a shape will be described. First, a flat interlayer insulating layer 141 is formed, and then a portion other than a predetermined portion of the interlayer insulating layer 141 is protected with a resist, and a groove is formed in the interlayer insulating layer 141 by dry etching. Thereafter, the interlayer insulating layer 142 is formed by chemical vapor deposition under conditions of, for example, the substrate temperature: 390 ° C., the gas pressure: 360 Pa, the applied power: 720 W, and the reaction gas ratio: tetraethoxysilane / oxygen = 1/10. . As a result, a gap 420 whose upper end has a convex shape is formed. Further, for example, the interlayer insulating layer 142 is formed under the conditions of substrate temperature: 410 ° C., gas pressure: 500 Pa, applied power: 800 W, reaction gas ratio: monosilane / ammonia / nitrous oxide / nitrogen = 1/1/1/40. May be. Further, the interlayer insulating layer 142 may be formed under the conditions of substrate temperature: 410 ° C., gas pressure: 600 Pa, applied power: 1200 W, and reaction gas ratio: monosilane / ammonia / nitrogen = 2/1/20. Even under such conditions, the gap 420 having an upwardly convex shape at the upper end is formed.

  Since the upper end of the gap 420 has a convex shape in this way, reflection of light at the upper end of the gap 420 can be reduced, and a decrease in the amount of incident light and generation of stray light can be suppressed. Further, not only the gap 120 but also the upper end of the gap 110 may have a convex shape. The first modification can also be applied to the second embodiment and the third embodiment.

<Second Modification>
A second modification of the solid-state imaging device 10 of the first embodiment will be described with reference to FIG. Matters not mentioned here can follow the first embodiment. In the first embodiment, the pixel 100 of the solid-state imaging device 10 includes two light receiving regions 102 and 103. The solid-state imaging device of the second modified example has a pixel 500 shown in FIG. FIG. 5A is a schematic plan view schematically showing the pixel 500. Since the cross-sectional structure of the pixel 500 is the same as the cross-sectional structure of the pixel 100, overlapping description is omitted.

  As illustrated in FIG. 5A, the pixel 500 includes four light receiving regions 530 to 533 and a wiring region 104. The light receiving regions 530 to 533 are regions that generate charges according to incident light. Focus detection is performed by signals obtained in the light receiving areas 530 to 533. Photodiodes 540 to 543 are arranged one-to-one in the light receiving regions 530 to 533.

  The pixel 500 includes a gap 510 and gaps 520 and 521 in one or more interlayer insulating layers 141, 142, and 143. As shown in FIG. 5A, the gap 510 is arranged between the light receiving regions 530 to 533 of the pixel 500 and the light receiving regions of other pixels in plan view. More specifically, the gap 510 is disposed between the light receiving regions 530 to 533 and the wiring region 104. The gap 510 entirely surrounds the outer periphery of the light receiving regions 530 to 533 in plan view.

  The gap 520 extends in the column direction (vertical direction in the drawing) of the pixel array, is positioned between two light receiving regions adjacent to each other in the column direction among the light receiving regions 530 to 533, and separates both regions. Both ends of the gap 520 are in contact with the gap 510. The gap 521 extends in the row direction of the pixel array (the left-right direction in the drawing), and is positioned between two light receiving regions adjacent to each other in the row direction among the light receiving regions 530 to 533, and separates both regions. Both ends of the gap 521 are in contact with the gap 510.

  Similar to the first embodiment, the height of the upper ends of the gaps 520 and 521 is lower than the height of the upper ends of the gaps 510. The height of the upper end of the gap 520 and the height of the upper end of the gap 521 may be equal to each other or may be different. With a configuration such as the pixel 500, focus detection in two directions is possible.

  A plurality of pixels included in the solid-state imaging device may include a pixel 501 illustrated in FIG. 5B and a pixel 502 illustrated in FIG. The pixel 501 is different from the pixel 500 in that it does not include the gap 521, and the other points may be the same. The pixel 501 has two light receiving regions 534 and 535 divided by a gap 520. Therefore, focus detection in the row direction of the pixel array can be performed. The pixel 502 differs from the pixel 500 in that it does not include the gap 520, and the other points may be the same. The pixel 502 has two light receiving regions 536 and 537 divided by a gap 521. Therefore, focus detection in the column direction of the pixel array can be performed. As described above, since the solid-state imaging device includes both the pixel 501 and the pixel 502, focus detection in two directions can be performed without the pixel 500. By configuring the pixels that do not perform focus detection to have four photodiodes, the difference in configuration between pixels that have different focus detection directions and pixels that do not perform focus detection may be reduced. The second modification can also be applied to the second embodiment and the third embodiment. Further, the second modification may be applied together with the first modification.

<Fourth embodiment>
A solid-state imaging device 60 according to the present embodiment will be described with reference to FIGS. 6A and 6B. FIG. 6A is a schematic plan view schematically showing a part of the solid-state imaging device 60. This plan view shows a plan view of the surface (light-receiving surface) of the semiconductor substrate 630 included in the solid-state imaging device 60. 6B is a schematic cross-sectional view taken along the line BB ′ in FIG. 6A. The solid-state imaging device 60 has a pixel array composed of a plurality of pixels arranged in a two-dimensional array. In FIG. 6A, attention is paid to four pixels 600, 600a, 600b, and 600c among the plurality of pixels. In FIG. 6B, attention is focused on one pixel 600 of these four pixels and a part of the pixel adjacent to the pixel 600. The pixels 600a, 600b, and 600c and other pixels not shown may have a structure similar to that of the pixel 600, or may have other structures. The solid-state imaging device 60 is a so-called back-illuminated solid-state imaging device.

  As shown in FIG. 6A, the pixel 600 has two light receiving regions 602 and 603. The light receiving regions 602 and 603 are regions that generate charges according to incident light. The wiring region 604 is a region where conductive patterns, plugs, and the like are arranged. Focus detection is performed by signals obtained in the light receiving regions 602 and 603, respectively. An on-chip lens 601 is disposed in contact with the pixel 600. The on-chip lens 601 may be arranged so as to circumscribe the pixel 600. In this case, a lens having a high light collecting ability without an inter-lens gap can be used as the on-chip lens 601.

  As shown in FIG. 6B, the pixel 600 of the solid-state imaging device 60 includes a semiconductor substrate 630 that is, for example, an n-type silicon substrate, and a light guide structure 680 that is positioned on the lower surface side of the semiconductor substrate 630. A p-type well layer 631 is formed on the semiconductor substrate 630 on the surface side. An n-type charge storage portion 632 is formed in the well layer 631. Of the charge storage portion 632, portions included in the pixel 600 serve as a charge storage portion 633 and a charge storage portion 634. A high-concentration p-type layer 635 is disposed on the charge storage portion 633 and the charge storage portion 634. The n-type charge storage portion 633 and the p-type semiconductor region around it form a photodiode that is a photoelectric conversion element. This photodiode corresponds to the light receiving region 602 in FIG. 6A. The same applies to the charge storage portion 634.

  In the semiconductor substrate 630, a p-type inter-pixel separation unit 636 is disposed between the pixel 600 and a pixel adjacent to the pixel 600. The photodiodes included in different pixels are separated by the inter-pixel separation unit 636. In the semiconductor substrate 630, an in-pixel separation unit 637 is disposed between the charge storage unit 633 and the charge storage unit 634. The two photodiodes in the pixel 600 are separated by the in-pixel separation unit 637. The potential of the intra-pixel separator 637 may be lower than the potential of the inter-pixel separator 636. Although not shown, the well layer 631 is formed with a transistor and a floating diffusion layer for transferring and driving the charge of the photodiode.

  As shown in FIG. 6B, on the semiconductor substrate 630, an insulating layer 640 including a gate insulating film, one or more interlayer insulating layers 641, 642, 643, which are silicon oxide films, for example, and a protective film 644 are provided. Are formed in order from the lower side (semiconductor substrate 630 side). Although not shown, the gate electrode of the transistor described above is formed on the gate insulating film. The interlayer insulating layers 641, 642 and 643 are provided with wiring layers 650 and 652 mainly made of copper, for example, and wiring layers 654 made mainly of aluminum, for example. Thereby, the pixel signal is transmitted. When copper wiring is used for the wiring layers 650 and 652, copper diffusion prevention layers 651 and 653 may be disposed. A handle substrate 672 is bonded onto the protective film 644.

  The back surface of the semiconductor substrate 630 is polished so that the thickness of the semiconductor substrate 630 becomes 3 μm, for example, and then a high-concentration p-type layer 674 is formed. As shown in FIG. 6B, on the back surface of the semiconductor substrate 630, an insulating layer 684 including an antireflection film and insulating layers 681, 682, 683 made of, for example, a silicon oxide film are sequentially formed from the semiconductor substrate 630 side. The insulating layers 681 to 683 may be formed of an organic film, for example. The insulating layers 681 to 683 may be formed with any number of layers. A planarizing layer 660, color filters 661 and 662, a planarizing layer 663, and an on-chip lens 601 are provided below the insulating layer 683 (light incident side). The light guide structure 680 is configured by members formed under these semiconductor substrates 630. A gap 691 is provided between the color filter 661 and the color filter 662. The total thickness of the insulating layers 681 and 682 may be, for example, 1 μm or more. By having this thickness, even a solid-state imaging device on the backside irradiation side can perform focus detection with high accuracy.

  The pixel 600 of the solid-state imaging device 60 has a gap 610 and a gap 620 in the light guide structure 680. As shown in FIG. 6A, the gap 610 is arranged between the light receiving regions 602 and 603 of the pixel 600 and the light receiving regions of other pixels in plan view. More specifically, the gap 610 has a lattice shape, and each lattice includes a light receiving region of one pixel. The gap 610 entirely surrounds the outer periphery of the light receiving regions 602 and 603 in plan view. As described above, the gap 610 defines an optical path between pixels of a plurality of pixels. The gap 620 is disposed between the light receiving region 602 and the light receiving region 603 of the pixel 600. The light receiving region 602 and the light receiving region 603 are divided by the gap 620. Both ends of the gap 620 are in contact with the gap 610. Accordingly, the light receiving regions 602 and 603 are respectively surrounded by the gap 610 and the gap 620 on the entire circumference. Thus, the gap 620 defines the optical path within the pixel 600.

  As shown in FIG. 6B, the gap 610 is formed across the two insulating layers 681 to 682. That is, the lower end of the gap 610 is at the same height as the lower surface of the insulating layer 682, and the upper end of the gap 610 is at the same height as the upper surface of the insulating layer 681. Here, of the ends of the gap 610, the end on the upper side (semiconductor substrate 630 as viewed from the insulating layers 681 to 682) is referred to as the upper end in the drawing, and the lower side (seen from the insulating layers 681 to 682) in the drawing is the semiconductor substrate 630. The opposite end is called the lower end. The same applies to the upper and lower ends of other members located under the semiconductor substrate 630. “Height” is a distance from the surface of the semiconductor substrate 630. The same applies to the following description regarding height. The gap 620 is formed in one insulating layer 681. That is, the lower end of the gap 620 is at the same height as the lower surface of the insulating layer 681, and the upper end of the gap 620 is at the same height as the upper surface of the insulating layer 681. As described above, the height of the upper end of the gap 620 is lower than the height of the upper end of the gap 610.

  The gaps 610 and 620 may be filled with a gas containing air or an inert gas, or may be a vacuum. In the present embodiment, the upper end of the gap 610 is closed by a light shielding layer 690 that is a metal layer, for example. In addition, the upper end of the gap 620 is blocked by the insulating layer 682. However, the gaps 610 and 620 may be filled with another insulating layer or another layer. The side surfaces of the gaps 610 and 620 may be smooth surfaces.

  The light beam 670 incident on the pixel 600 from the first direction is guided to the photodiode including the charge storage portion 633, and the light beam 671 incident on the pixel 600 from the second direction is guided to the photodiode including the charge storage portion 634. It is burned. At that time, the component converged by the on-chip lens 601 is confined in the pixel 600 by the gap 610. In addition, due to the gap 620, the component of the light beam 670 incident from the first direction and the component of the light beam 671 incident from the second direction are divided into the charge storage unit 633 side and the charge storage unit 633 side. In the present embodiment, the lower end of the gap 610 is at the same height as the lower surface of the insulating layer 682, so that light incident on the pixel 600 is difficult to leak to pixels other than the pixel 600. Further, since the lower end of the gap 620 is at a position lower than the lower end of the gap 610 (position close to the semiconductor substrate 630), the component of the light beam 670 incident from the first direction and the light beam 671 incident from the second direction. Can be efficiently divided into the charge storage portion 633 side and the charge storage portion 633 side. As a result, even in the back-illuminated solid-state imaging device, crosstalk between pixels can be suppressed and high-precision focus detection can be performed.

  The pixel 600 described in the present embodiment may be applied to all the pixels of the solid-state imaging device 60. Alternatively, the pixel 600 may be applied to only some pixels of the solid-state imaging device 60, and the other pixels may have only one light receiving region. A pixel having only one light receiving region performs normal signal processing and does not perform focus detection. Such a pixel may not have the gap 620 and the intra-pixel separation portion 637. In the above structure, the light shielding layer 690 may not be included, and the gap 620 may not be included. The gap 691 between the color filter 161 and the color filter 162 can also be applied to the first to third embodiments.

<Other embodiments>
Hereinafter, as an application example of the solid-state imaging device according to each of the above embodiments, a camera in which the solid-state imaging device is incorporated will be exemplarily described. The concept of a camera includes not only a device mainly intended for photographing but also a device (for example, a personal computer, a portable terminal, a car, etc.) having a photographing function as an auxiliary. The camera may be a module component such as a camera head. The camera includes a solid-state imaging device according to the present invention exemplified as the above-described embodiment, and a signal processing unit that processes a signal output from the solid-state imaging device. The signal processing unit can include, for example, a processor that processes digital data based on a signal obtained from the solid-state imaging device. The A / D converter for generating the digital data may be provided on the semiconductor substrate of the solid-state imaging device, or may be provided on another semiconductor substrate.

DESCRIPTION OF SYMBOLS 10 Solid-state imaging device, 100 pixels, 102,103 light-receiving area | region, 110,120 gap | interval, 130 Semiconductor substrate, 180 Light guide structure

Claims (14)

A solid-state imaging device having a plurality of pixels,
A semiconductor substrate;
A light guide structure located on the light receiving surface side of the semiconductor substrate,
At least one of the plurality of pixels has a plurality of photoelectric conversion elements on the semiconductor substrate to generate a signal for focus detection,
The light guide structure has a first gap that defines an optical path between pixels, and a second gap that defines an optical path in a pixel having the plurality of photoelectric conversion elements;
The distance between the end of the second gap opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate is the distance between the end of the first gap opposite to the semiconductor substrate and the light receiving surface of the semiconductor substrate. A solid-state imaging device characterized by being shorter than the distance. A solid-state imaging device having a plurality of pixels,
A semiconductor substrate;
A light guide structure located on the light receiving surface side of the semiconductor substrate,
At least one of the plurality of pixels has a plurality of photoelectric conversion elements on the semiconductor substrate to generate a signal for focus detection,
The light guide structure has a first gap that defines an optical path between pixels, and a second gap that defines an optical path in a pixel having the plurality of photoelectric conversion elements;
The width of the first gap is wider than the width of the second gap.   3. The solid-state imaging device according to claim 2, wherein an end of the first gap opposite to the semiconductor substrate is closed by a metal layer.   4. The solid-state imaging device according to claim 1, wherein an end of the second gap on the side opposite to the semiconductor substrate has a convex shape in a direction away from the semiconductor substrate. 5.   The second gap extends in a first direction in a plan view with respect to the light receiving surface of the semiconductor substrate, and a second portion extends in a second direction different from the first direction in the plan view. The solid-state imaging device according to claim 1, further comprising: a portion. The at least one pixel includes a first pixel and a second pixel;
The second gap defining the optical path of the first pixel extends in a first direction in a plan view with respect to the light receiving surface of the semiconductor substrate,
The second gap that defines the optical path of the second pixel extends in a second direction different from the first direction in the plan view. Solid-state imaging device.   The said 1st gap | interval is formed over several insulating layers, The side surface of the said 1st gap | interval is smooth in the boundary of several insulating layers, The any one of Claim 1 thru | or 6 characterized by the above-mentioned. The solid-state imaging device described.   The end of the first gap on the semiconductor substrate side and the end of the second gap on the semiconductor substrate side are at the same height from the light receiving surface of the semiconductor substrate. The solid-state imaging device according to any one of the above.   The solid-state imaging device according to any one of claims 1 to 8, wherein the light guide structure further includes an on-chip lens for each of the plurality of pixels. The light guide structure further includes a wiring layer and an interlayer insulating layer,
10. The solid-state imaging device according to claim 1, wherein the first gap and the second gap are included in the interlayer insulating layer. 11.   11. The end of the second gap opposite to the semiconductor substrate and any end of the wiring layer are at the same height from the light receiving surface of the semiconductor substrate. The solid-state imaging device according to any one of the above.   10. The solid-state imaging device according to claim 1, further comprising a wiring layer and an interlayer insulating layer on a second surface side opposite to the light receiving surface of the semiconductor substrate. . A solid-state imaging device having a plurality of pixels,
A semiconductor substrate;
A light guide structure located on the light receiving surface side of the semiconductor substrate;
A wiring layer and an interlayer insulating layer located on the opposite side of the light receiving surface of the semiconductor substrate;
At least one of the plurality of pixels has a plurality of photoelectric conversion elements on the semiconductor substrate to generate a signal for focus detection,
The solid-state imaging device, wherein the light guide structure has a first gap that defines an optical path of each pixel. A solid-state imaging device according to any one of claims 1 to 13,
A signal processing unit for processing a signal obtained by the solid-state imaging device;
A camera comprising:

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