JP2016031968A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the cost of manufacture.SOLUTION: A semiconductor device 1A comprises: a substrate 100A that has a principal surface 101A, an outside surface 103A crossing to the principal surface 101A, and a recessed part 108A recessed from the principal surface 101A, and that is formed of a semiconductor material; a wiring layer 200A at least a part of which is formed on the substrate 100A; one or more elements 311A, 312A, and 313A housed in the recessed part 108A; an encapsulation resin 400A that covers at least a part of the one or more elements 311A, 312A, and 313A; and a metal film 500A formed on the outside surface 103A.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device.

  Various types of semiconductor devices having a specific function with respect to input / output of current from the outside have been proposed (see, for example, Patent Document 1). Generally, in order to fulfill the function of this semiconductor device, a plurality of elements each constituting a part of an electric circuit are incorporated. Metal leads are used for the purpose of supporting these elements and making them conductive. The number, shape, and size of the leads are determined according to the functions, shapes, and sizes of the plurality of elements. The plurality of elements mounted on the leads are covered with a sealing resin. The sealing resin is for protecting a part of these elements and the leads. Such a semiconductor device is used by being mounted on a circuit board of an electronic device, for example.

  The lead is often formed by punching using a mold, for example. The technique using a mold has an advantage that the leads can be formed efficiently and accurately. However, in general, the number, size, and shape of the leads differ depending on the plurality of elements. For this reason, when the function required for the semiconductor device is changed, it is necessary to change the size and shape of the lead. In order to realize this, it is compelled to make a new mold. Since the mold is relatively expensive, when the semiconductor device is produced in a small amount, the cost of the semiconductor device is increased.

  In addition, since the lead is obtained by processing a metal plate, it generally has a flat shape. Although it is possible to obtain a three-dimensional shape by arbitrarily drawing, some restrictions are imposed. The above semiconductor devices are required to have higher functions and more functions year by year. In order to meet this demand, high-density mounting of the plurality of elements or a three-dimensional arrangement other than the flat arrangement is required.

JP 2012-99673 A

  The present invention has been conceived under the circumstances described above, and an object thereof is to provide a semiconductor device capable of reducing the manufacturing cost. It is another object of the present invention to provide a semiconductor device that can alleviate restrictions on the arrangement of a plurality of elements and can be miniaturized. Furthermore, an object of the present invention is to appropriately manufacture such a semiconductor device and allow it to function properly.

  A semiconductor device provided by the first aspect of the present invention includes a main surface, an outer surface intersecting the main surface, a concave portion recessed from the main surface, and a substrate made of a semiconductor material, and at least partly. Comprising: a wiring layer formed on the substrate; one or more elements housed in the recess; and a sealing resin covering at least a part of the one or more elements; And an inclined outer surface interposed between the main surface and the standing outer surface and inclined with respect to both the main surface and the standing outer surface.

  In a preferred embodiment of the present invention, the inclined outer surface is smoother than the standing outer surface.

  In a preferred embodiment of the present invention, the standing outer surface is perpendicular to the main surface.

  In a preferred embodiment of the present invention, the outer surface surrounds the main surface in a normal direction view of the main surface and forms a rectangular ring shape.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the concave portion has an inclined inner side surface inclined with respect to the main surface and a bottom surface.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the concave portion has four inclined inner side surfaces.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In a preferred embodiment of the present invention, an additional element that covers at least a part of the one or more elements is provided, and the recess includes a first recess that accommodates the one or more elements and the additional element. And a second recess located closer to the main surface than the first recess, and the bottom surface constitutes the first bottom surface constituting the first recess, the second recess, and the first recess. A second bottom surface located closer to the main surface than the bottom surface, wherein the inclined inner surface forms a first inclined inner surface that constitutes the first recess, and the second recess, and the second bottom surface And a second inclined inner side surface connected to the main surface.

  In preferable embodiment of this invention, the resin formation part formed in at least one of the said main surface and the said recessed part is further provided.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface.

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the external terminal is formed on the first resin forming portion.

  In a preferred embodiment of the present invention, the additional element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  The method for manufacturing a semiconductor device provided by the second aspect of the present invention includes a step of forming a plurality of recesses recessed from the main surface in a substrate material having a main surface, and partitioning each of the plurality of recesses. A step of forming an inclined groove recessed from the main surface, a step of forming a wiring layer on the substrate material including the plurality of recesses, and mounting a plurality of elements so that at least one is accommodated in each recess. And a step of forming a sealing resin that covers the plurality of elements, and a step of cutting along a cutting line included in the inclined groove as viewed in the normal direction of the main surface. .

  In a preferred embodiment of the present invention, the substrate material is Si, and the step of forming the recess and the step of forming the inclined groove perform anisotropic etching on the main surface of the substrate material. At the same time.

  In a preferred embodiment of the present invention, the concave portion has an inclined inner side surface inclined with respect to the main surface and a bottom surface.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the concave portion has four inclined inner side surfaces.

  In a preferred embodiment of the present invention, in the step of forming the recess, a first recess having a first bottom surface and a first inclined inner surface, a second bottom surface connected to the first inclined inner surface, and the second And a second recess having a second inclined inner surface connected to the bottom surface and the main surface.

  In a preferred embodiment of the present invention, in the step of forming the sealing resin, the inclined groove is exposed from the sealing resin.

  A semiconductor device provided by the third aspect of the present invention includes a main surface, a substrate having a concave portion recessed from the main surface and made of a semiconductor material, and a wiring layer formed at least partially on the substrate. One or more elements accommodated in the recess, a sealing resin covering at least a part of the one or more elements, and a resin forming portion formed on at least one of the main surface and the recess. It is characterized by.

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the wiring layer includes a plurality of external terminals formed on the first resin forming portion. Have

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided.

  In a preferred embodiment of the present invention, the concave portion has an inclined inner side surface inclined with respect to the main surface and a bottom surface.

  In a preferred embodiment of the present invention, the resin forming portion includes a second resin forming portion formed on the bottom surface, and the additional element is mounted on the second resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer includes a plurality of second resin forming portion pads formed on the second resin forming portion for mounting the additional element.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the concave portion has four inclined inner side surfaces.

  In a preferred embodiment of the present invention, the recess includes a first recess that accommodates the one or more elements, and a second recess that is positioned closer to the main surface than the first recess, and the bottom surface. Includes a first bottom surface that constitutes the first recess, and a second bottom surface that constitutes the second recess and is positioned closer to the main surface than the first bottom surface. A first inclined inner surface that constitutes the first recess, and a second inclined inner surface that constitutes the second recess and is connected to the second bottom surface and the main surface, wherein the second resin forming portion includes: Formed on the second bottom surface.

  In a preferred embodiment of the present invention, the substrate has an outer surface intersecting the main surface, and the outer surface is interposed between the standing outer surface and the main surface and the standing outer surface. And an inclined outer surface that is inclined with respect to both the main surface and the standing outer surface.

  In a preferred embodiment of the present invention, the inclined outer surface is smoother than the standing outer surface.

  In a preferred embodiment of the present invention, the outer surface surrounds the main surface in a normal direction view of the main surface and forms a rectangular ring shape.

  In a preferred embodiment of the present invention, an additional element that covers at least a part of the one or more elements is provided, and the recess accommodates the one or more elements, and includes a first bottom surface and a first inclined inner surface. And a second recess having a second bottom surface connected to the first inclined inner surface and a second inclined inner surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the resin forming portion includes a second resin forming portion formed on the second bottom surface, and the additional element is mounted on the second resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer includes a plurality of second resin forming portion pads formed on the second resin forming portion for mounting the additional element.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, the first recess has four first inclined inner surfaces, and the second recess has four four first It has two inclined inner surfaces.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the first inclined inner surface and the second inclined inner surface with respect to the main surface.

  A semiconductor device provided by the fourth aspect of the present invention includes a main surface, an outer surface intersecting with the main surface, a concave portion recessed from the main surface, and a substrate made of a semiconductor material, and at least partly A wiring layer formed on the substrate, one or more elements accommodated in the recess, a sealing resin covering at least a part of the one or more elements, a metal film formed on the outer surface, It is characterized by having.

  In a preferred embodiment of the present invention, the outer surface is interposed between the standing outer surface, the main surface and the standing outer surface, and is inclined with respect to both the main surface and the standing outer surface. The metal film is formed on the inclined outer surface and exposes the standing outer surface.

  In a preferred embodiment of the present invention, the inclined outer surface is smoother than the standing outer surface.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface, and the metal film has a connection path connected to any of the plurality of external terminals.

  In a preferred embodiment of the present invention, the metal film as a whole surrounds the main surface as viewed in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the one or more elements include a wireless communication element.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided, and an additional metal film positioned between the additional element and the one or more elements is provided.

  In a preferred embodiment of the present invention, the outer surface surrounds the main surface in a normal direction view of the main surface and forms a rectangular ring shape.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the concave portion has an inclined inner side surface inclined with respect to the main surface and a bottom surface.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the concave portion has four inclined inner side surfaces.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In preferable embodiment of this invention, the resin formation part formed in at least one of the said main surface and the said recessed part is further provided.

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the wiring layer includes a plurality of external terminals formed on the first resin forming portion. Have

  In a preferred embodiment of the present invention, an additional element that covers at least a part of the one or more elements is provided, and the recess accommodates the one or more elements, and includes a first bottom surface and a first inclined inner surface. And a second recess having a second bottom surface connected to the first inclined inner surface and a second inclined inner surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the additional element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the first inclined inner surface and the second inclined inner surface with respect to the main surface.

  A semiconductor device provided by the fifth aspect of the present invention includes a main surface, a substrate having a recess recessed from the main surface and made of a semiconductor material, and a wiring layer formed at least partially on the substrate. A plurality of elements housed in the recess, and a sealing resin covering at least a part of the plurality of elements, the recess having a bottom surface and at least two inclined inner surfaces sandwiching the bottom surface The plurality of elements are one or more first elements, an opposite main surface that is located on the opposite side of the first element from the bottom surface, and that faces the first element and the opposite main surface A second element having an inclined inclined side surface, wherein the inclined side surface of the second element is supported by the inclined inner side surface of the substrate.

  In a preferred embodiment of the present invention, at least one of the one or more first elements is supported on the bottom surface.

  In a preferred embodiment of the present invention, the wiring layer has an inclined inner surface pad formed on the inclined inner surface for mounting the second element.

  In a preferred embodiment of the present invention, the substrate and the second element are composed of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, each of the main surface and the opposing main surface is either a (100) surface or a (110) surface, and an inclination angle of the inclined side surface with respect to the opposing main surface is The inclination angle of the inclined inner surface with respect to the main surface is the same.

  In a preferred embodiment of the present invention, the substrate has an outer surface intersecting the main surface, and the outer surface is interposed between the standing outer surface and the main surface and the standing outer surface. And an inclined outer surface that is inclined with respect to both the main surface and the standing outer surface.

  In a preferred embodiment of the present invention, the inclined outer surface is smoother than the standing outer surface.

  In a preferred embodiment of the present invention, the outer surface surrounds the main surface in a normal direction view of the main surface and forms a rectangular ring shape.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In a preferred embodiment of the present invention, a conductive wiring pattern is formed in a predetermined region extending from the inclined side surface of the second element to the opposing main surface.

  In a preferred embodiment of the present invention, the second element has two inclined side surfaces sandwiching the opposed main surface, and is supported by the two inclined inner side surfaces via the two inclined side surfaces. Yes.

  In a preferred embodiment of the present invention, the second element is an integrated circuit element.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface.

  In a preferred embodiment of the present invention, a resin forming portion formed on the main surface is further provided, and the wiring layer has a plurality of external terminals formed on the resin forming portion.

  In a preferred embodiment of the present invention, the sealing resin includes a first sealing resin that covers the one or more first elements and a second sealing resin that covers the second elements.

  In a preferred embodiment of the present invention, the second sealing resin exposes the external terminal.

  In preferable embodiment of this invention, the said 2nd sealing resin has a part located in the normal line direction outer side of the said main surface rather than the said main surface.

  In preferable embodiment of this invention, the additional resin formation part formed in the said recessed part is further provided.

  In a preferred embodiment of the present invention, the opposed main surface of the second element is supported by the additional resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of additional resin forming portion pads formed on the additional resin forming portion for mounting the second element.

  In a preferred embodiment of the present invention, a plurality of the second elements are provided at intervals in the normal direction of the main surface.

  A semiconductor device provided by the sixth aspect of the present invention includes a main surface, a substrate having a recess recessed from the main surface and made of a semiconductor material, and a wiring layer formed at least partially on the substrate. One or more first elements housed in the recesses, a sealing resin that covers at least a part of the one or more first elements and is filled in the recesses, and the sealing resin is disposed at a depth of the recesses. And a plurality of columnar conductive portions each penetrating in a direction and connected to a portion of the wiring layer formed in the recess.

  In a preferred embodiment of the present invention, the recess has an inclined inner side surface and a bottom surface that are inclined with respect to the main surface, and the columnar conductive portion is a method of the main surface from the inclined inner surface. It extends along the line direction.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of inclined inner surface pads formed on the inclined inner surface, each of which is connected to one end of the columnar conductive portion.

  In a preferred embodiment of the present invention, each is provided with a plurality of external terminals to which the other ends of the columnar conductive portions are connected.

  In a preferred embodiment of the present invention, the sealing resin covers at least a part of the main surface.

  In a preferred embodiment of the present invention, one end surface of the sealing resin facing the normal direction outward of the main surface and the other end of the columnar conductive portion are flush with each other, and the sealing resin An external terminal pad for mounting the external terminal is formed on the one end surface.

  In a preferred embodiment of the present invention, the concave portion has two inclined inner side surfaces sandwiching the bottom surface.

  In a preferred embodiment of the present invention, a plurality of the columnar conductive portions extend from the two inclined inner side surfaces along the normal direction of the main surface.

  In a preferred embodiment of the present invention, all of the plurality of columnar conductive portions extend from one of the two inclined inner side surfaces along the normal direction of the main surface, and the plurality of external terminals The plurality of first external terminals in a position overlapping any of the columnar conductive portions in the normal direction of the main surface and the plurality of first external terminals are spaced apart from each other with the bottom surface in between. A plurality of second external terminals.

  In preferable embodiment of this invention, the resin formation part formed in the said recessed part is further provided.

  In a preferred embodiment of the present invention, the resin forming portion is formed on the bottom surface.

  In a preferred embodiment of the present invention, a second element covering at least a part of the one or more first elements is provided, and the second element is mounted on the resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of resin forming portion pads formed on the resin forming portion for mounting the second element.

  In a preferred embodiment of the present invention, a second element that covers at least a part of the one or more first elements is provided, and the recess includes a first recess that houses the one or more first elements, and the first element. A second recess that accommodates two elements and is located closer to the main surface than the first recess, and the bottom surface forms a first bottom surface that constitutes the first recess and the second recess. A second bottom surface located closer to the main surface than the first bottom surface, and the inclined inner surface constitutes a first inclined inner surface constituting the first recess, and the second recess, And a second inclined inner side surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the second element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the columnar conductive portion extends from the second inclined inner surface along the normal direction of the main surface.

  In a preferred embodiment of the present invention, the inclined inner surface pad is formed on the second inclined inner surface.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, the first recess has four first inclined inner surfaces, and the second recess has four four first It has two inclined inner surfaces.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a principal part perspective view which shows the semiconductor device based on 1st Embodiment of this invention. FIG. 2 is a main part plan view showing the semiconductor device of FIG. 1. It is sectional drawing which follows the III-III line of FIG. It is sectional drawing which follows the IV-IV line of FIG. FIG. 2 is a perspective view showing a substrate of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view of the main part showing one example of a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a perspective view of relevant parts showing an example of a method of manufacturing the semiconductor device of FIG. 1. FIG. 27 is an essential part cross sectional view showing an example different from FIG. 26 in the method for manufacturing the semiconductor device of FIG. 1. FIG. 29 is a diagram showing steps following FIG. 28. It is a principal part top view which shows the semiconductor device based on 2nd Embodiment of this invention. It is sectional drawing which follows the XXXI-XXXI line | wire of FIG. FIG. 32 is a cross-sectional view similar to FIG. 31 showing a modification of the semiconductor device shown in FIGS. 30 and 31. It is a principal part top view which shows the semiconductor device based on 3rd Embodiment of this invention. It is sectional drawing which follows the XXXIV-XXXIV line | wire of FIG. FIG. 35 is a cross-sectional view similar to FIG. 34 showing a modification of the semiconductor device shown in FIGS. 33 and 34. FIG. 35 is a cross-sectional view similar to FIG. 34 illustrating another modification of the semiconductor device illustrated in FIGS. 33 and 34. It is a principal part top view which shows the semiconductor device based on 4th Embodiment of this invention. It is sectional drawing which follows the XXXVIII-XXXVIII line | wire of FIG. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. FIG. 39 is a cross-sectional view similar to FIG. 38 illustrating a modification of the semiconductor device illustrated in FIGS. 37 and 38. 48 is a schematic plan view of the semiconductor device shown in FIG. 47. FIG. FIG. 39 is a cross-sectional view similar to FIG. 38 illustrating another modification of the semiconductor device illustrated in FIGS. 37 and 38.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  1 to 4 show a semiconductor device according to the first embodiment of the present invention. The semiconductor device 1A of this embodiment includes a substrate 100A, resin forming portions 130A and 140A, a wiring layer 200A, three orientation sensor elements 311A, 312A, and 313A, an integrated circuit element 330A, two capacitors 343A, a sealing resin 400A, and a metal. A film 500A is provided. In FIGS. 1 and 2, the sealing resin 400A is omitted for convenience of understanding, and the three orientation sensor elements 311A, 312A, 313A, the integrated circuit element 330A, and the two capacitors 343A are indicated by imaginary lines. Yes. 3 is a cross-sectional view in the yz plane along the line III-III in FIG. 2, and FIG. 4 is a cross-sectional view in the zx plane along the line IV-IV in FIG.

  1 A of semiconductor devices are comprised as an azimuth | direction detection module which can detect the azimuth | direction of 3 directions with the structure demonstrated below, and can be surface-mounted. As an example of the size of the semiconductor device 1A, the planar view size is about 1.5 mm × 2.0 mm and the thickness is about 0.6 mm.

  The substrate 100A is a base of the semiconductor device 1A, and includes a base 106A and an insulating layer 107A. The substrate 100A has a main surface 101A, a back surface 102A, four outer surfaces 103A, and a recess 108A. The thickness of the substrate 100A is, for example, about 600 μm. In the present embodiment, the main surface 101A and the back surface 102A face opposite sides in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1A. Further, the x direction and the y direction are both perpendicular to the z direction.

The base 106A is made of a single crystal of a semiconductor material, and in this embodiment, is made of a Si single crystal. The insulating layer 107A is made of SiO ₂ in this embodiment. The material of the base 106A is not limited to Si as long as it can form the recess 108A that satisfies the intention described later. The insulating layer 107A covers a portion of the base material 106A that faces from the side opposite to the back surface 102A. The thickness of the insulating layer 107A is, for example, about 0.1 to 1.0 μm.

  FIG. 5 is a perspective view showing the substrate 100A. In the present embodiment, the (100) surface of the base 106A is adopted as the main surface 101A. The recess 108A is recessed from the main surface 101A toward the back surface 102A. In the present embodiment, the recess 108A includes a first recess 110A and a second recess 120A. 110 A of 1st recessed parts are located in the back surface 102A side, and have the 1st bottom face 111A and the four 1st inclination inner side surfaces 112A. The second recess 120A is located closer to the main surface 101A than the first recess 110A, and has two second bottom surfaces 121A and four second inclined inner side surfaces 122A. The shapes of the first recess 110A and the second recess 120A depend on the fact that the (100) plane is adopted as the main surface 101A.

  By forming the recess 108A, the main surface 101A has a rectangular shape in plan view. More specifically, two parts of the main surface 101A that are separated in the y direction across the recess 108A are significantly larger than the two parts that are located apart in the x direction across the recess 108A. ing.

  The first recess 110A has a rectangular shape in plan view. The depth of 110 A of 1st recessed parts is about 440 micrometers, for example. The first bottom surface 111A has a rectangular shape in plan view. The four first inclined inner side surfaces 112A surround the first bottom surface 111A in a plan view, and have a substantially trapezoidal shape with a portion contacting the first bottom surface 111A as an upper base. Each first inclined inner side surface 112A is inclined with respect to the first bottom surface 111A. In the present embodiment, the inclination angle of the first inclined inner side surface 112A with respect to the xy plane is about 55 °. The first inclined inner side surface 112A has a substantially trapezoidal shape and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101A.

  The second recess 120A has a rectangular shape in plan view. The depth of the second recess 120A is, for example, about 120 μm. The two second bottom surfaces 121A have a rectangular shape in plan view and sandwich the first recess 110A. Each second bottom surface 121A is connected to the first inclined inner side surface 112A. The four second inclined inner side surfaces 122A surround the two second bottom surfaces 121A in plan view and have a substantially trapezoidal shape. Each second inclined inner side surface 122A is inclined with respect to the second bottom surface 121A. In the present embodiment, the inclination angle of the second inclined inner side surface 122A with respect to the xy plane is about 55 °. The point that the second inclined inner side surface 122A is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101A.

  The resin forming portions 130A and 140A are for providing a predetermined step on the substrate 100A, and are formed on the substrate 100A (insulating layer 107A). In the present embodiment, the resin forming portion 130 </ b> A is formed on the main surface 101 </ b> A, and is a portion that serves as a base for an external terminal 221 described later. The resin forming portion 130A is formed in two portions of the main surface 101A that are arranged apart from each other in the y direction across the recess 108A. The height of the resin forming portion 130A is, for example, about 50 μm. The resin forming portion 140A is formed on each of the two second bottom surfaces 121A of the second recess 120A, and is a portion on which the integrated circuit element 330A is mounted. In the present embodiment, the height of the resin forming portion 140A is, for example, about 50 μm. These resin forming portions 130A and 140A have a flat top surface and side surfaces 132A and 142A inclined with respect to the top surface. Examples of the material of the resin forming portions 130A and 140A include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The resin forming portions 130A and 140A may be either translucent resin or non-translucent resin, but in the present embodiment, non-translucent resin is preferable.

  The wiring layer 200A is provided with three orientation sensor elements 311A, 312A, 313A, an integrated circuit element 330A, and two capacitors 343A, and constitutes a current path that inputs and outputs to these. The wiring layer 200A is mainly formed on the insulating layer 107A, and in this embodiment, the barrier seed layer 201A and the plating layer 202A are stacked.

  The barrier seed layer 201A is a so-called underlayer for forming a desired plating layer 202A, and is mainly formed on the insulating layer 107A. The barrier seed layer 201A includes, for example, a Ti layer as a barrier layer formed on the insulating layer 107A and a Cu layer as a seed layer stacked on the barrier layer. The barrier seed layer 201A is formed by sputtering, for example. In the present embodiment, the barrier seed layer 201A is formed on predetermined portions on the insulating layer 107A and the resin forming portions 130A and 140A.

  The plating layer 202A is made of, for example, Cu, and is formed by electrolytic plating using the barrier seed layer 201A. The thickness of the plating layer 202A is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200A includes a first bottom surface pad 211A, a first inclined inner side surface pad 212A, a resin forming portion pad 213A, an external terminal 221A, and communication paths 231A, 234A, 235A, and 236A.

  The first bottom surface pad 211A is formed on the first bottom surface 111A of the first recess 110A and has, for example, a rectangular shape. In the present embodiment, four first bottom surface pads 211A are formed. In the present embodiment, the first bottom surface pad 211A is used for mounting the orientation sensor element 311A.

  The first inclined inner surface pad 212A is formed on the first inclined inner surface 112A of the first recess 110A, and has, for example, a rectangular shape. In the present embodiment, four first inclined inner surface pads 212A are formed on two first inclined inner surfaces 112A that are arranged apart from each other in the y direction across the first bottom surface 111A. Each of the four first inclined inner side surface pads 212A is used for mounting the orientation sensor elements 312A and 313A. In the present embodiment, two first inclined inner surface pads 212A are formed on two first inclined inner surfaces 112A that are spaced apart in the x direction across the first bottom surface 111A. These two inclined inner surface pads 212A are used for mounting two capacitors 343A.

  Resin forming portion pad 213A is formed in resin forming portion 140A on second bottom surface 121A, and has a rectangular shape, for example. In the present embodiment, a plurality of resin forming portion pads 213A are formed in the resin forming portion 140A of each second bottom surface 121. More specifically, nine resin forming portion pads 213A arranged in the x direction are arranged apart from each other in the y direction with the first recess 110A interposed therebetween. In the present embodiment, the resin forming portion pad 213A is used for mounting the integrated circuit element 330A.

  The external terminal 221A is formed in the resin forming portion 130A on the main surface 101A, and is used for surface mounting the semiconductor device 1A on, for example, a circuit board of an electronic device (not shown). In the present embodiment, four external terminals 221A are formed for each of the resin forming portions 130A provided at two portions of the main surface 101A that are separated in the y direction across the recess 108A. The external terminal 221A has a structure in which bumps obtained by electroless plating a metal such as Ni, Pd, and Au are formed on the barrier seed layer 201A and the plating layer 202A. Thereby, as shown in FIG. 3, the external terminal 221A has a shape bulging in the z direction.

  The communication paths 231A, 234A, 235A, and 236A are used to configure a path for electrically connecting the first bottom surface pad 211A, the first inclined inner surface pad 212A, the resin forming portion pad 213A, and the external terminal 221A.

  The communication path 231A constitutes a path from the main surface 101A (resin forming portion 130A) to the second bottom surface 121A, and mainly connects the external terminal 221A and the resin forming portion pad 213A. As shown in FIG. 2, in this embodiment, each connecting path 231A reaches the second bottom surface 121A via the second inclined inner side surface 122A of the second recess 120A. A portion of each connecting path 231A formed on the second inclined inner side surface 122A extends along the y direction in a plan view and is not inclined with respect to the y direction.

  The communication path 234A forms a path from the second bottom surface 121A to the first inclined inner side surface 112A, and electrically connects the resin forming portion pad 213A and the first inclined inner side surface pad 212A. In the present embodiment, some of the communication paths 234A extend along the y direction in plan view. The other communication path 234A is bent at the first inclined inner side surface 112A.

  The communication path 235A forms a path from the second bottom surface 121A to the first bottom surface 111A via the first inclined inner surface 112A, and electrically connects the resin forming portion pad 213A and the first bottom surface pad 211A. . In the present embodiment, one communication path 235A extends along the y direction in plan view. Further, the other communication path 235A is bent at the first inclined inner side surface 112A.

  The communication path 236A constitutes a path from the first inclined inner side surface 112A to the first bottom surface 111A, and electrically connects the first inclined inner side surface pad 212A and the first bottom surface pad 211A.

  In the present embodiment, the external terminal 221A located second from the left in the upper part of FIG. 2 is a so-called ground terminal. In addition, the communication path 231A, the resin forming portion pad 213A, the communication path 235A, the first bottom surface pad 211A, the communication path 236A, and the first inclined inner side surface pad 212A that are electrically connected to the external terminal 221A are grounded.

  As shown in FIG. 2, the four outer surfaces 103A of the substrate 100A surround the main surface 101A when viewed in the z direction, and form a rectangular ring shape. More specifically, each outer surface 103A includes an inclined outer surface 104A and a standing outer surface 105A. The inclined outer surface 104A is interposed between the main surface 101A and the standing outer surface 105A, and is inclined with respect to both the main surface 101A and the standing outer surface 105A. In the present embodiment, the inclined outer surface 104A is connected to the main surface 101A, and the standing outer surface 105A is connected to the back surface 102A. In this embodiment, the inclination angle of the inclined outer surface 104A with respect to the xy plane is about 55 °. Note that the point where the inclination angle is 55 ° depends on the use of the (100) plane as the main surface 101A.

  Here, the inclination angle of the inclined outer surface 104A with respect to the xy plane (main surface 101A) is the same as the inclination angle of the first inclined inner surface 112A and the second inclined inner surface 122A with respect to the main surface 101A. Although details will be described later, the inclined outer side surface 104A, the first inclined inner side surface 112A, and the second inclined inner side surface 122A are intended to have the same angle by being formed by batch etching. Differences that inevitably occur due to variations in etching conditions and the like are included in the same range as used in the present invention.

  The standing outer surface 105A is substantially perpendicular to the main surface 101A and substantially parallel to the zx plane or the yz plane. In the present embodiment, the inclined outer surface 104A is smoother than the standing outer surface 105A. Note that the fact that the inclined outer surface 104A is smoother than the standing outer surface 105A in this way depends on the method of manufacturing the semiconductor device 1A described later.

  The metal film 500A is formed on the inclined outer surface 104A. In the present embodiment, as shown in FIG. 2, the metal film 500A covers most of the inclined outer surface 104A, and the metal film 500A as a whole surrounds the main surface 101A when viewed in the z direction. In the present embodiment, the metal film 500 </ b> A has an annular shape as a whole. The metal film 500 </ b> A has a connection path 510 </ b> A for connecting to the external terminal 221. In the present embodiment, the connection path 510A is connected to the external terminal 221 located second from the left in the upper part of FIG. Since the external terminal 221 is a ground terminal as described above, the metal film 500A conducting to the external terminal 221 is also connected to the ground. Similarly to the wiring layer 200A, the metal film 500A has a structure in which a barrier seed layer 201A and a plating layer 202A are stacked. Note that the metal film 500A may have a configuration in which, for example, a plurality of elements, each of which is ground-connected, are arranged in a ring instead of the ring-shaped configuration in which the whole is integrated.

  The three orientation sensor elements 311A, 312A, 313A have detection reference axes along different directions, and are used, for example, to detect the attitude of the semiconductor device 1A with respect to geomagnetism. In the present embodiment, the orientation sensor elements 311A, 312A and 313A have magnetic cores 314A, 315A and 316A as shown in FIG. The magnetic cores 314A, 315A, and 316A are metal rod-like members extending in a predetermined direction, and their longitudinal directions correspond to the detection reference axes of the orientation sensor elements 311A, 312A, and 313A. The direction sensor elements 311A, 312A, and 313A further have coils (not shown) formed so as to surround the magnetic cores 314A, 315A, and 316A. The thickness of the orientation sensor elements 311A, 312A, 313A is, for example, about 80 μm.

  In the present embodiment, the orientation sensor element 311A is supported by the first bottom surface 111A, and is mounted via the solder 351A using the four first bottom surface pads 211A. With such a mounting form, the magnetic core 314A of the orientation sensor element 311A is along the y direction.

  The azimuth sensor element 312A is supported by the upper first inclined inner surface 112A in FIG. 2, and is mounted via the solder 351A using the four first inclined inner surface pads 212A. With such a mounting form, the magnetic core 315A of the orientation sensor element 312A is perpendicular to the x direction and is along the direction included in the yz plane. This direction is parallel to the first inclined inner side surface 112A that supports the orientation sensor element 312A.

  The orientation sensor element 313A is supported by the first inclined inner side surface 112A in the lower part of FIG. 2, and is mounted via the solder 351A using the four first inclined side surface pads 212A. With such a mounting form, the magnetic core 316A of the orientation sensor element 313A is perpendicular to the x direction and is along the direction included in the yz plane. This direction is parallel to the first inclined inner side surface 112A that supports the orientation sensor element 313A.

  In the present embodiment, the orientation sensors 311A, 312A, and 313A have smaller top surfaces located on the side opposite to the bottom surface than the bottom surface on the substrate 100A side. Further, the side surface connecting the bottom surface and the top surface is inclined with respect to the direction in which the bottom surface and the top surface are separated from each other.

  The integrated circuit element 330A is for controlling the direction detection processing using the three direction sensor elements 311A, 312A, and 313A. In the present embodiment, the integrated circuit element 330A is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and the thickness thereof is about 80 to 100 μm.

  The integrated circuit element 330A is supported on the second bottom surface 121A via the resin forming portion 140A, and is mounted via the solder 351A using the resin forming portion pad 213A. As shown in FIG. 2, the integrated circuit element 330 </ b> A is mounted using a plurality of resin forming portion pads 213 </ b> A that are spaced apart in the y direction so that two sides are supported. Further, the integrated circuit element 330A covers most of the first recess 110A except for a part thereof in a plan view. Further, the integrated circuit element 330A overlaps all of the orientation sensor elements 311A, 312A, and 313A in plan view, and also overlaps the two capacitors 343A. As shown in FIGS. 3 and 4, most of the integrated circuit element 330 </ b> A except for its upper end is accommodated in the second recess 120 </ b> A in the z direction. On the other hand, the upper end portion of the integrated circuit element 330A protrudes upward from the second recess 120A.

  The azimuth detection processing by the integrated circuit element 330A using the azimuth sensor elements 311A, 312A, and 313A is performed as follows, for example. As described above, the orientation sensor elements 311A, 312A, and 313A have the magnetic cores 314A, 315A, and 316A each surrounded by the coil. The azimuth sensor elements 311A, 312A, and 313A have the above-described mounting configuration, so that the azimuth sensor elements 311A, 312A, and 313A, that is, the magnetic cores 314A, 315A, and 316A are along different directions. The direction along which these magnetic cores 314A, 315A, and 316A follow is stored as known information in the integrated circuit element 330A.

  The two capacitors 343A are supported by the first inclined inner side surface 112A and are spaced apart in the x direction with the direction sensor element 311A interposed therebetween. Thus, the two capacitors 343A and the orientation sensor element 311A are arranged side by side in the x direction.

  The semiconductor device 1A uses, for example, the orientation sensor elements 311A, 312A, and 313A based on the technique disclosed in Japanese Patent Application Laid-Open No. 2006-47267 to determine the attitude to the geomagnetism in a three-dimensional manner. Can be detected (triaxial detection). The integrated circuit element 330A outputs the orientation detection result of the semiconductor device 1A as a signal from an external terminal 221A in response to an external command or autonomously.

  The sealing resin 400A covers the orientation sensor elements 311A, 312A, 313A and the integrated circuit element 330A, and fills the recess 108A. In the present embodiment, the sealing resin 400A includes a first sealing resin 410A and a second sealing resin 420A.

  The first sealing resin 410A is generally filled in the first recess 110A and covers the entire orientation sensor elements 311A, 312A, and 313A. On the other hand, the first sealing resin 410A does not cover the resin forming portion pad 213A and the integrated circuit element 330A.

  The second sealing resin 420A is generally filled in the second recess 120A and covers all of the integrated circuit element 330A. On the other hand, the second sealing resin 420A exposes the external terminal 221A.

  Examples of the material of the first sealing resin 410A and the second sealing resin 420A include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The first sealing resin 410A and the second sealing resin 420A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, a method for manufacturing the semiconductor device 1A will be described below with reference to FIGS. In addition, in these FIGS. 6-26, the cross section in the yz plane which follows the III-III line | wire of FIG. 2 is shown.

  First, a substrate material 100A ′ is prepared as shown in FIG. The substrate material 100A ′ is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The thickness of the substrate material 100A ′ is, for example, about 600 μm. The substrate material 100A ′ is sized so that a plurality of substrates 100A of the semiconductor device 1A can be obtained. That is, the subsequent manufacturing process is premised on a method of manufacturing a plurality of semiconductor devices 1A in a lump. A method of manufacturing one semiconductor device 1A may be used, but considering industrial efficiency, a method of manufacturing a plurality of semiconductor devices 1A collectively is realistic.

The substrate material 100A ′ has a main surface 101A and a back surface 102A that face opposite sides in the z direction. In the present embodiment, a plane having a crystal orientation of (100) and a (100) plane are adopted as the main surface 101A. Next, a mask layer 191A made of SiO ₂ is formed by oxidizing the main surface 101A, for example. The thickness of the mask layer 191A is, for example, about 0.7 to 1.0 μm.

  Next, as shown in FIG. 7, the mask layer 191A is patterned by etching, for example. Thereby, openings 181A and 182A are formed in the mask layer 191A. The shapes and sizes of the openings 181A and 182A are set according to the shapes and sizes of the first recess 110A and the inclined outer surface 104A to be finally obtained. The opening 181A has, for example, a rectangular shape, and the opening 182A is formed in a rectangular ring shape so as to surround the opening 181A when viewed in the z direction.

  Next, as shown in FIG. 8, a first recess 110A and an inclined groove 183A are formed. The first recess 110A and the inclined groove 183A are formed simultaneously by anisotropic etching using, for example, KOH. KOH is an example of an alkaline etching solution that can realize good anisotropic etching for a Si single crystal. By performing this anisotropic etching, the first concave portion 110A having the first bottom surface 111A and the four first inclined inner side surfaces 112A and the inclined surface having two inclined surfaces (inclined surfaces facing each other in the y direction in FIG. 8). A groove 183A is formed. The angle formed by the first inclined inner surface 112A with respect to the xy plane and the angle formed by the inclined groove 183A with respect to the xy plane are each about 55 °.

  Next, by further patterning the mask layer 191A, a mask layer 192A having an opening 184A is formed. The mask layer 192A has an opening area larger than that of the mask layer 191A. The opening 184A has a rectangular shape, for example. The shape and size of the opening 184A are set according to the shape and size of the second recess 120A to be finally obtained.

  Next, as shown in FIG. 10, a recess 108A is formed. In order to form the recess 108A, for example, the above-described anisotropic etching using KOH is performed. By this anisotropic etching, the first recess 110A becomes deeper and larger, and a second recess 120A is newly formed. The second recess 120A has two second bottom surfaces 121A sandwiching the first recess 110A and four second inclined inner side surfaces 122A surrounding the first recess 110A. Similarly to the first inclined inner side surface 112A, the second inclined inner side surface 122A has an angle of about 55 ° with the xy plane. In this way, by performing anisotropic etching twice, a two-step concave portion 108A having the first concave portion 110A and the second concave portion 120A is formed. In the present embodiment, the depth of the first recess 110A is about 440 μm, and the depth of the second recess 120A is about 120 μm.

  Next, as shown in FIG. 11, the mask layer 192A is removed. This removal is performed by etching using, for example, HF.

Next, as shown in FIG. 12, an insulating layer 107A made of, for example, SiO ₂ is formed. The insulating layer 107A is formed by oxidizing the entire portion of the substrate material 100A ′ opposite to the back surface 102A. Thereby, an insulating layer 107A having a thickness of about 0.7 to 1.0 μm, for example, is obtained.

  Next, as shown in FIG. 13, a resin layer 193A is formed. The resin layer 193A is formed, for example, by spraying a photosensitive epoxy resin. Next, as shown in FIG. 14, the resin layer 193A is patterned. This patterning is performed by removing a desired portion by performing exposure and development using, for example, a photolithography technique on the resin layer 193A. By this patterning, resin forming portions 130A and 140A are formed at predetermined positions on the main surface 101A and the second bottom surface 121A.

  Next, as shown in FIG. 15, a barrier seed layer 201A is formed. The formation of the barrier seed layer 201A is performed by sputtering, for example. Specifically, a layer made of Ti is formed on the insulating layer 107A by sputtering. This layer made of Ti functions as a barrier layer. Next, a layer made of Cu is formed on the barrier layer by sputtering. This layer made of Cu functions as a seed layer. A barrier seed layer 201A is obtained by such sputtering.

  Next, as shown in FIG. 16, a mask layer 291A is formed. The mask layer 291A is formed, for example, by spraying a photosensitive resist resin.

  Next, as shown in FIG. 17, the mask layer 291A is patterned. This patterning is performed by removing a desired portion by performing exposure and development using, for example, a photolithography technique on the mask layer 291A. The shape of the mask layer 291A obtained by this patterning corresponds to the shape of the wiring layer 200A and the metal film 500A described above. Note that the exposure may be performed a plurality of times while changing the focal depth of the exposure in response to the recess 108A having a certain depth.

  Next, as shown in FIG. 18, a plating layer 202A is formed. The plating layer 202A is formed by, for example, electrolytic plating using the seed layer of the barrier seed layer 201A. As a result, a plated layer 202A made of Cu, for example, is obtained. The thickness of the plating layer 202A is, for example, about 5 μm. The plating layer 202A has the shape of the wiring layer 200A and the metal film 500A described above.

  Next, as shown in FIG. 19, the mask layer 291A is deleted. Next, as shown in FIG. 20, a portion of the barrier seed layer 201A exposed from the plating layer 202A is removed. The removal of the barrier seed layer 201A is performed, for example, by wet etching. Thereby, a wiring layer 200A composed of the barrier seed layer 201A and the plating layer 202A both patterned is obtained. In the present embodiment, the metal film 500A including the barrier seed layer 201A and the plating layer 202A is obtained simultaneously with the formation of the wiring layer 200A.

  Next, as shown in FIG. 21, orientation sensor elements 311A, 312A, and 313A are mounted. Solder balls serving as solder 351A are formed on the orientation sensor elements 311A, 312A, and 313A. Further, flux is applied to these solder balls. Using the adhesiveness of the flux, the orientation sensor element 311A is placed on the first bottom surface 111A, and the orientation sensor elements 312A and 313A are placed on the first inclined inner side surface 112A. Then, the mounting of the orientation sensor elements 311A, 312A, and 313A is completed by melting the solder balls in a reflow furnace and then curing them. Further, the two capacitors 343A are mounted on the first inclined inner side surface 112A different from the mounting of the orientation sensor elements 312A and 313A.

  Next, as shown in FIG. 22, a first sealing resin 410A is formed. The first sealing resin 410A is formed by, for example, filling the first recess 110A mainly with a resin material that has excellent permeability and is cured when exposed to light, and then curing the resin material. At this time, the direction sensor elements 311A, 312A, and 313A are covered with the resin material. On the other hand, the resin forming portion pad 213A on the second bottom surface 121A is surely exposed. Examples of the material for forming the first sealing resin 410A include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The first sealing resin 410A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, as shown in FIG. 23, an integrated circuit element 330A is mounted. Solder balls to be the solder 351A are formed on the integrated circuit element 330A. Further, flux is applied to these solder balls. The integrated circuit element 330A is placed on the resin forming portion 140A on the second bottom surface 121A using the adhesiveness of the flux. Then, the mounting of the integrated circuit element 330A is completed by melting the solder ball in a reflow furnace and then curing it.

  Next, as shown in FIG. 24, a second sealing resin 420A is formed. The formation of the second sealing resin 420A is performed by, for example, filling the second recess 120A mainly with a resin material that is excellent in penetrability and cured by photosensitivity, and curing the resin material. At this time, the entire integrated circuit element 330A is covered with this resin material. On the other hand, a part of the plating layer 202A on the main surface 101A is surely exposed. In addition, the second sealing resin 420A is formed so as not to overlap with a cutting region to be described later. Examples of the material for forming the second sealing resin 420A include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The second sealing resin 420A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, as shown in FIG. 25, bumps that bulge in the z direction are formed on the external terminals 221A by electroless plating with a metal such as Ni, Pd, or Au.

  Next, as shown in FIGS. 26 and 27, the substrate material 100A 'is cut by, for example, a dicer Dc. The cutting by the dicer Dc is performed along the cutting line CL included in the inclined groove 183A when viewed in the z direction. At this time, only the substrate material 100A ′ is cut by the dicer Dc, and for example, the second sealing resin 420A is not cut. Through this cutting, the semiconductor device 1A shown in FIGS. 1 to 4 is obtained. The exposed surface generated by this cutting becomes the standing outer surface 105A. The standing outer surface 105A generated by the cutting has a relatively rough surface. On the other hand, the inclined outer surface 104A derived from the inclined groove 183A formed by anisotropic etching has a relatively flat surface and is smoother than the standing outer surface 105A.

  Next, the operation of the semiconductor device 1A and the method for manufacturing the semiconductor device 1A will be described.

  According to the present embodiment, the three orientation sensor elements 311A, 312A, 313A are accommodated in the first recess 110A of the recess 108A of the substrate 100A made of a semiconductor material. For this reason, it is not necessary to provide leads for supporting the three orientation sensor elements 311A, 312A, and 313A. Compared to the case where the leads are molded, the substrate 100A made of a semiconductor material is less expensive to change the shape. Therefore, the cost of the semiconductor device 1A can be reduced. In particular, when the semiconductor device 1A is produced in a small amount, the cost reduction effect is remarkable.

  When manufacturing the semiconductor device 1A, when the substrate material 100A ′ is cut along the cutting line CL included in the inclined groove 183A formed in the main surface 101A, the outer surface 103 of the chip-shaped substrate 100A that is cut and separated is The inclined outer surface 104A, which is a part of the region that was the inclined groove 183A, is included. In the manufacture of the semiconductor device 1A, the cutting operation of the substrate material 100A ′ proceeds while being guided at the site of the inclined groove 183A. According to such a configuration, when the substrate material 100A ′ is cut, it is possible to prevent the substrate material 100A ′ or the substrate 100A from having defects such as wafer cracks and chips. This is suitable for efficiently manufacturing the semiconductor device 1A.

  In the manufacture of the semiconductor device 1A, the inclined groove 183A and the recess 108A (first recess 110A) are formed simultaneously by anisotropic etching. Then, the substrate material 100A 'is cut along the cutting line CL. Since this cutting line CL is included in the inclined groove 183A, the cutting depth of the substrate material 100A 'is smaller than the thickness of the substrate material 100A'. According to such a configuration, the cutting operation of the substrate material 100A ′ can be performed efficiently.

  The standing outer surface 105A constituting the outer surface 103A is a trace of the substrate material 100A ′ cut at the site of the inclined groove 183A. That is, the inclined outer surface 104A formed by anisotropic etching is smoother than the standing outer surface 105A formed by cutting the substrate material 100A ′.

  Since the substrate 100A is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112A and the second inclined inner side surface 122A are formed at a known predetermined angle with respect to the first bottom surface 111A and the second bottom surface 121A. It can be finished as a precisely inclined surface. In particular, when the substrate 100A is made of Si and the (100) plane is adopted as the main surface 101A, the four first inclined inner side surfaces 112A and the four second inclined inner side surfaces 122A with respect to the first bottom surface 111A and the second bottom surface 121A. Can be set to about 55 °. As a result, the semiconductor device 1A can have a well-balanced shape configuration.

  By forming the recess 108A in a two-stage shape with the first recess 110A and the second recess 120A, the first recess 110A can be used as a dedicated space for accommodating the orientation sensor elements 311A, 312A, 313A and the two capacitors 343A. it can.

  Resin forming portions 130A and 140A are provided on the main surface 101A and the recess 108A. According to the configuration including the resin forming portions 130A and 140A, steps can be provided at appropriate positions on the main surface 101A and the recess 108A, and the external terminals 221A and the integrated circuit element 330A can be appropriately mounted. For example, as can be understood with reference to FIGS. 3 and 4, if the integrated circuit element 330A is mounted on the second bottom surface 121A without the resin forming portion 140A, the integrated circuit element 330A may interfere with the capacitor 343A. There is. In contrast, by forming the resin forming portion 140A on the second bottom surface 121A, the main surface of the integrated circuit element 330A avoiding interference with the capacitor 343A without changing the shape or position of the second bottom surface 121A itself. It can be mounted at a position displaced toward the 101A side. As shown in FIG. 3, the integrated circuit element 330A protrudes upward from the main surface 101A. On the other hand, by forming the external terminals 221A on the main surface 101A through the resin forming portion 130A, the external terminals 221A can be projected in the z direction so as to be suitable for surface mounting.

  Since the side surfaces 132A and 142A of the resin forming portions 130A and 140A are inclined, the connection path of the wiring layer 200A formed on the side surfaces 132A and 142A is connected to the external terminal 221A and the resin forming portion pad 213A. Can do.

  A metal film 500A is formed on the inclined outer surface 104A. When the semiconductor device 1A is mounted, the metal film 500A is grounded via the connection path 510A and the external terminal 221A. The metal film 500A having such a configuration functions as an electromagnetic shield in which each element accommodated in the recess 108A prevents the influence of an external electromagnetic wave. In addition, the metal film 500A surrounds the main surface 101A as a whole when viewed in the z direction (viewed in the normal direction of the main surface 101A). According to such an arrangement of the metal film 500A, it can be expected that the effect as an electromagnetic shield is further enhanced.

  Note that the formation range and the like of the metal film 500A may be changed as appropriate. When the metal film 500A is formed in a wider area than the mode shown in FIG. 2, for example, the inclined outer surface 104A is formed wider so that the area of the inclined outer surface 104A is larger than that of the present embodiment, The metal film 500A may be formed in a wider area with respect to the side surface 104A.

  The formation of the metal film 500 </ b> A is performed at the same time as the formation of the wiring layer 200. For this reason, the metal film 500A can be formed efficiently. Further, the inclined outer surface 104A on which the metal film 500A is formed is a smooth surface formed in the same manner as the recess 108A by anisotropic etching using, for example, KOH. Therefore, the metal film 500A can be appropriately formed on the smooth inclined outer surface 104A.

  The integrated circuit element 330A is supported by the second bottom surface 121A and overlaps a part of the first recess 110A in plan view, whereby the direction sensor elements 311A, 312A, 313A and the two capacitors 343A and the integrated circuit in the z direction are overlapped. The element 330A can be three-dimensionally arranged. Thereby, it is possible to achieve both miniaturization and high functionality of the semiconductor device 1A.

  The wiring layer 200A includes the communication paths 231A, 234A, 235A, and 236A, so that desired ones of the external terminal 221A, the resin forming portion pad 213A, the first bottom surface pad 211A, and the first inclined inner side surface pad 212A can be appropriately selected. It can be made conductive. Since the connecting path 231A passes through the second inclined inner side surface 122A, it is possible to appropriately conduct the external terminal 221A and the resin forming portion pad 213A formed on the three-dimensional board 100A. There is little risk of disconnection. Further, since the communication paths 234A, 235A, 236A pass through the first inclined inner side surface 112A, there is little risk of disconnection or the like.

  By covering the three orientation sensor elements 311A, 312A, 313A and the two capacitors 343A with the sealing resin 400A, it is possible to appropriately protect the orientation sensor elements 311A, 312A, 313A and the two capacitors 343A. it can. By configuring the sealing resin 400A to include the first sealing resin 410A and the second sealing resin 420A, the two-stage concave portion 108A including the first concave portion 110A and the second concave portion 120A is appropriately filled. be able to.

  By adopting a configuration in which the first sealing resin 410A is mainly filled in the first recess 110A, the three orientation sensor elements 311A, 312A, 313A and the two capacitors 343A are mounted before the integrated circuit element 330A is mounted. Can be covered properly. Further, by covering the integrated circuit element 330A with the second sealing resin 420A, an unintended gap is not generated between the integrated circuit element 330A and the three orientation sensor elements 311A, 312A, 313A and the two capacitors 343A. The sealing resin 400A can be formed. Since the second sealing resin 420A exposes the external terminal 221A, the semiconductor device 1A can be easily surface-mounted and, for example, the circuit board and the integrated circuit element 330A on which the semiconductor device 1A is mounted and three orientations are mounted. It is possible to appropriately prevent the sensor elements 311A, 312A, 313A and the two capacitors 343A from conducting unfairly.

  In the manufacturing method of the semiconductor device 1A, as a method for cutting the substrate material 100A ′, in addition to the cutting using the dicer Dc shown in FIG. 26, for example, a deep etching method such as plasma dicing or BOSCH method. Various methods can be employed.

  When cutting the substrate material 100A ′ using the deep etching technique, for example, the substrate includes a first step of digging the substrate material 100A ′ to a predetermined depth and a second step of polishing the back side of the substrate material. Material 100A ′ may be cut. In this case, in the first step, as shown in FIG. 28, the vertical groove 185 is formed by digging up to a predetermined depth in the thickness direction by deep digging from the position where the inclined groove 183A is formed. Next, the main surface 101A side of the substrate material 100A 'is supported by a support such as a tape material (not shown). Next, as shown in FIG. 29, the substrate material 100A 'is polished from the back surface 102A side to reach the formation position of the vertical groove 185A. As a result, the substrate material 100A ′ is separated and cut into a plurality of substrates 100A, and the portion where the vertical groove 185 is formed becomes the standing outer surface 105A.

  30 and 31 show a semiconductor device according to the second embodiment of the present invention. The semiconductor device 1B of the present embodiment includes a substrate 100B, a resin forming portion 150B, a wiring layer 200B, an integrated circuit element 330B, a wireless communication element 350B, a sealing resin 400B, and a metal film 500B. In FIG. 30, the sealing resin 400B is omitted for convenience of understanding. Further, in FIG. 30 and FIG. 31, the communication route is omitted.

  The substrate 100B is a base of the semiconductor device 1B and includes a base material 106B and an insulating layer 107B. The substrate 100B has a main surface 101B, a back surface 102B, four outer surfaces 103B, and a recess 108B. The thickness of the substrate 100B is about 600 μm, for example. In the present embodiment, the main surface 101B and the back surface 102B face away from each other in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1B. Further, the x direction and the y direction are both perpendicular to the z direction.

The base material 106B is made of a single crystal of a semiconductor material, and in this embodiment is made of a Si single crystal. The insulating layer 107B is made of SiO ₂ in this embodiment. The material of the base material 106B is not limited to Si, and may be any material as long as the concave portion 108B that satisfies the intention described later can be formed. The insulating layer 107B covers a portion of the substrate 106B that faces from the side opposite to the back surface 102B. The thickness of the insulating layer 107B is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) surface of the base material 106B is employed as the main surface 101B. The recess 108B is recessed from the main surface 101B toward the back surface 102B. In the present embodiment, the recess 108B includes the first recess 110B. The first recess 110B has a first bottom surface 111B and four first inclined inner side surfaces 112B. The shape of the first recess 110B depends on the (100) plane being adopted as the main surface 101B.

  By forming the recess 108B, the main surface 101B has a rectangular shape in plan view. The first recess 110B has a rectangular shape in plan view. The depth of the first recess 110B is, for example, about 440 μm. The first bottom surface 111B has a rectangular shape in plan view. The four first inclined inner side surfaces 112B surround the first bottom surface 111B in a plan view, and have a substantially trapezoidal shape with a portion in contact with the first bottom surface 111B as an upper base. Each first inclined inner side surface 112B is inclined with respect to the first bottom surface 111B. In the present embodiment, the inclination angle of the first inclined inner surface 112B with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112B is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101B.

  The resin forming portion 150B is for providing a predetermined step on the substrate 100B, and is formed on the substrate 100B (insulating layer 107B). In the present embodiment, the resin forming portion 150B is formed on the bottom surface (first bottom surface 111B) of the recess 108B (first recess 110B) and is a portion on which the wireless communication element 350B is mounted. In the present embodiment, the resin forming portion 150B is formed at two portions of the first bottom surface 111B that are separated in the y direction. The height of the resin forming portion 150B is, for example, about 150 μm. The resin forming portion 150B has a flat top surface and a side surface 152B inclined with respect to the top surface. Examples of the material of the resin forming portion 150B include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The resin forming portion 150B may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  The wiring layer 200B is for mounting the integrated circuit element 330B and the wireless communication element 350B, and constituting a current path for inputting / outputting them. The wiring layer 200B is mainly formed on the insulating layer 107B, and in this embodiment, the barrier seed layer 201B and the plating layer 202B are stacked.

  The barrier seed layer 201B is a so-called underlayer for forming a desired plating layer 202B, and is formed on the insulating layer 107B. The barrier seed layer 201B is composed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107B and a Cu layer as a seed layer stacked on the barrier layer. The barrier seed layer 201B is formed by sputtering, for example. In the present embodiment, the barrier seed layer 201B is formed at predetermined sites on the insulating layer 107B and the resin forming portion 150B.

  The plating layer 202B is made of, for example, Cu and is formed by electrolytic plating using the barrier seed layer 201B. The thickness of the plating layer 202B is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200B has a first bottom surface pad 211B, a resin forming portion pad 214B, an external terminal 221B, and a communication path (not shown) for electrically connecting them.

  The first bottom surface pad 211B is formed on the first bottom surface 111B of the first recess 110B. In the present embodiment, a plurality of first bottom surface pads 211B are formed, and these first bottom surface pads 211B are used for mounting the integrated circuit element 330B.

  The resin forming part pad 214B is formed in the resin forming part 150B. In the present embodiment, a plurality of resin forming portion pads 214B are formed in each resin forming portion 150B spaced apart on the first bottom surface 111B. These resin forming portion pads 214B are used for mounting the wireless communication element 350B. Further, since the side surface 152B of the resin forming portion 150B is inclined, the connection path (not shown) of the wiring layer 200B formed on the side surface 152B can be connected to the resin forming portion pad 214B.

  The external terminal 221B is formed on the main surface 101B, and is used for surface mounting the semiconductor device 1B on, for example, a circuit board of an electronic device (not shown). In the present embodiment, a plurality of external terminals 221B are formed in two portions of the main surface 101B that are separated in the y direction across the recess 108B. The external terminal 221B has a structure in which bumps obtained by electroless plating a metal such as Ni, Pd, and Au are formed on the barrier seed layer 201B and the plating layer 202B. Thereby, the external terminal 221B has a shape bulging in the z direction. In the present embodiment, at least one external terminal 221B is a so-called ground terminal.

  As shown in FIG. 30, the four outer surfaces 103B of the substrate 100B surround the main surface when viewed in the z direction and form a rectangular ring shape. More specifically, each outer surface 103B includes an inclined outer surface 104B and a standing outer surface 105B. The inclined outer surface 104B is interposed between the main surface 101B and the standing outer surface 105B, and is inclined with respect to both the main surface 101B and the rising outer surface 105B. In the present embodiment, the inclined outer surface 104B is connected to the main surface 101B, and the standing outer surface 105B is connected to the back surface 102B. In the present embodiment, the inclination angle of the inclined outer surface 104B with respect to the xy plane is about 55 °. Note that the point where the inclination angle is 55 ° depends on the use of the (100) plane as the main surface 101B.

  Here, the inclination angle of the inclined outer surface 104B with respect to the xy plane (main surface 101B) is the same as the inclination angle of the first inclined inner surface 112B with respect to the main surface 101B. The inclined outer surface 104B and the first inclined inner surface 112B are intended to have the same angle by being formed by batch etching. Differences that inevitably occur due to variations in etching conditions and the like are included in the same range as used in the present invention.

  The standing outer surface 105B is substantially perpendicular to the main surface 101B and substantially parallel to the zx plane or the yz plane. In the present embodiment, the inclined outer surface 104B is smoother than the standing outer surface 105B. Note that the fact that the inclined outer surface 104B is smoother than the standing outer surface 105B in this way depends on the manufacturing method of the semiconductor device 1B. Since the standing outer surface 105B is an exposed surface generated by cutting the substrate material, the inclined outer surface 104B formed by etching is smoother than the standing outer surface 105B.

  The wireless communication element 350B is an element for short-range wireless data communication conforming to, for example, the Bluetooth (registered trademark) standard, and is supported on the first bottom surface 111B via the resin forming portion 150B. The wireless communication element 350B is mounted via the solder 351B using a plurality of resin forming portion pads 214B. The wireless communication element 350B is mounted by using a plurality of resin forming portion pads 214B spaced apart in the y direction so that two sides are supported. Further, the wireless communication element 350B overlaps with all of the integrated circuit element 330B in plan view, and is accommodated in the first recess 110B (recess 108B).

  The integrated circuit element 330B is supported by the first bottom surface 111B, and is mounted via the solder 351B using a plurality of first bottom surface pads 211B. The integrated circuit element 330B is for controlling the wireless communication element 350B. In the present embodiment, the integrated circuit element 330B is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and has a thickness of about 80 to 100 μm. When manufacturing the semiconductor device 1B, the integrated circuit element 330B is mounted on the first bottom surface 111B after the formation of the resin forming portion 150B.

  The sealing resin 400B covers the integrated circuit element 330B and the wireless communication element 350B, and fills the recess 108B (first recess 110B). In the present embodiment, the sealing resin 400B includes a first sealing resin 410B and a second sealing resin 420B.

  The first sealing resin 410B covers the entire integrated circuit element 330B. On the other hand, the first sealing resin 410B does not cover the resin forming part pad 214B and the wireless communication element 350B.

  The second sealing resin 420B covers all of the wireless communication element 350B. On the other hand, the second sealing resin 420B exposes the external terminal 221B.

  Examples of the material of the first sealing resin 410B and the second sealing resin 420B include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The first sealing resin 410B and the second sealing resin 420B may be either translucent resin or non-translucent resin, but in this embodiment, non-translucent resin is preferable.

  Next, the operation of the semiconductor device 1B will be described.

  According to the present embodiment, the integrated circuit element 330B and the wireless communication element 350B are arranged and accommodated in the concave portion 108B (first concave portion 110B) of the substrate 100B made of a semiconductor material. Therefore, there is no need to provide leads for supporting the integrated circuit element 330B and the wireless communication element 350B. Compared to the case where the leads are molded, the substrate 100B made of a semiconductor material is less expensive to change the shape. Therefore, the cost of the semiconductor device 1B can be reduced. In particular, when the semiconductor device 1B is produced in a small amount, the cost reduction effect is remarkable.

  Since the substrate 100B is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112B can be finished as a surface that is accurately inclined by a known predetermined angle with respect to the first bottom surface 111B. In particular, when the substrate 100B is made of Si and the (100) plane is adopted as the main surface 101B, the angles of the four first inclined inner side surfaces 112B with respect to the first bottom surface 111B can be set to about 55 °. . As a result, the semiconductor device 1B can have a well-balanced shape configuration.

  A metal film 500B is formed on the inclined outer surface 104B. When the semiconductor device 1B is mounted, the metal film 500B is grounded via the connection path 510B and the external terminal 221B. The metal film 500B having such a configuration functions as an electromagnetic shield in which each element housed in the recess 108B prevents the influence of electromagnetic waves from the outside. Further, the metal film 500B surrounds the main surface 101B as a whole when viewed in the z direction (viewed in the normal direction of the main surface 101B). According to such an arrangement of the metal film 500B, it can be expected that the effect as an electromagnetic shield is further enhanced. In addition, since the semiconductor device 1B of the present embodiment includes the wireless communication element 350B that is easily affected by external electromagnetic waves, the electromagnetic shielding effect by the metal film 500B can be more appropriately enjoyed.

  By forming the resin forming portion 150B at an appropriate position in the recess 108B (first recess 110B), the space for accommodating the integrated circuit element 330B and the wireless communication element 350B can be formed into a two-stage shape. By mounting the integrated circuit element 330B on the first bottom surface 111B and mounting the wireless communication element 350B on the resin forming portion 150B, the integrated circuit element 330B and the wireless communication element 350B are three-dimensionally arranged at different positions in the z direction. be able to. As a result, the semiconductor device 1B can be both downsized and highly functional.

  By forming the resin forming portion pad 214B on the resin forming portion 150B, the wireless communication element 350B can be appropriately mounted on the resin forming portion 150B.

  FIG. 32 shows a modification of the semiconductor device 1B described above. The semiconductor device 1B 'shown in FIG. 32 includes a substrate 100B, a resin forming portion 150B, a wiring layer 200B, an integrated circuit element 330B, an inductor 360B, a sealing resin 400B, a metal film 500B, and a metal film 520B. The semiconductor device 1B 'shown in FIG. 32 includes an inductor 360B instead of the wireless communication element 350B, and additionally includes a metal film 520B, as compared with the semiconductor device 1B described above.

  The inductor 360B is mounted on the resin forming portion 150B and covers at least a part of the integrated circuit element 330B.

  The metal film 520B is located between the inductor 360B and the integrated circuit element 330B, and covers the entire integrated circuit element 330B. The metal film 520B is formed, for example, by forming a metal thin film having a predetermined shape on the first sealing resin 410B. For example, the first sealing resin 410B is formed so that the height position is substantially the same as the resin forming portion 150B, and a metal such as Cu is patterned on the first sealing resin 410B by a technique such as mask vapor deposition. As a result, a metal film 520B is formed. The metal film 520B is conductively connected to a communication path (not shown) formed in the recess 108B (first inclined inner side surface 112B) and the resin forming portion 150B, and is also conductive to the external terminal 221A for the ground terminal. The integrated circuit element 330B may malfunction due to the influence of the magnetic field by the inductor 360B. By disposing the metal film 520B between the inductor 360B and the integrated circuit element 330B, the integrated circuit element 330B is prevented from malfunctioning. can do.

  33 and 34 show a semiconductor device according to the third embodiment of the present invention. The semiconductor device 1C of this embodiment includes a substrate 100C, a wiring layer 200C, a first element 370C, a second element 380C, and a sealing resin 400C. In FIG. 33, the sealing resin 400C is omitted for convenience of understanding. Further, in FIG. 33 and FIG. 34, the communication route is omitted.

  The substrate 100C is a base of the semiconductor device 1C and includes a base material 106C and an insulating layer 107C. The substrate 100C has a main surface 101C, a back surface 102C, four outer surfaces 103C, and a recess 108C. The thickness of the substrate 100C is about 600 μm, for example. In the present embodiment, the main surface 101C and the back surface 102C face away from each other in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1C. Further, the x direction and the y direction are both perpendicular to the z direction.

The base material 106C is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The insulating layer 107C is made of SiO ₂ in this embodiment. The material of the base material 106C is not limited to Si, and may be any material that can form the recess 108C that satisfies the intention described later. The insulating layer 107C covers a portion of the base material 103C that faces from the side opposite to the back surface 102C. The thickness of the insulating layer 107C is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) surface of the base material 106C is employed as the main surface 101C. The recess 108C is recessed from the main surface 101C toward the back surface 102C. In the present embodiment, the recess 108C includes a first recess 110C. The first recess 110C has a first bottom surface 111C and four first inclined inner side surfaces 112C. The shape of the first recess 110C depends on the (100) plane being adopted as the main surface 101C.

  By forming the recess 108C, the main surface 101C has a rectangular ring shape in plan view. The first recess 110C has a rectangular shape in plan view. The depth of the first recess 110C is, for example, about 440 μm. The first bottom surface 111C has a rectangular shape in plan view. The four first inclined inner side surfaces 112C surround the first bottom surface 111C in a plan view, and have a substantially trapezoidal shape with a portion in contact with the first bottom surface 111C as an upper base. Each first inclined inner side surface 112C is inclined with respect to the first bottom surface 111C. In the present embodiment, the inclination angle of the first inclined inner side surface 112C with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112C is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101C.

  The wiring layer 200C is for mounting the first element 370C and the second element 380C and forming a current path for inputting / outputting them. The wiring layer 200C is formed on the insulating layer 107C, and in this embodiment, the barrier seed layer 201C and the plating layer 202C are stacked.

  The barrier seed layer 201C is a so-called underlayer for forming a desired plating layer 202C, and is formed on the insulating layer 107C. The barrier seed layer 201C is made of, for example, a Ti layer as a barrier layer formed on the insulating layer 107C and a Cu layer as a seed layer stacked on the barrier layer. The barrier seed layer 201C is formed by sputtering, for example. In the present embodiment, the barrier seed layer 201C is formed at a predetermined site on the insulating layer 107C.

  The plating layer 202C is made of, for example, Cu and is formed by electrolytic plating using the barrier seed layer 201C. The thickness of the plating layer 202C is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200 </ b> C has a first bottom surface pad 211 </ b> C, a first inclined inner surface pad 212 </ b> C, an external terminal 221 </ b> C, and a communication path (not shown) for electrically connecting them.

  The first bottom surface pad 211C is formed on the first bottom surface 111C of the first recess 110C. In the present embodiment, a plurality of first bottom surface pads 211C are formed, and these first bottom surface pads 211C are used for mounting the first element 370C.

  The first inclined inner surface pad 212C is formed on the first inclined inner surface 112C. In the present embodiment, a plurality of first inclined inner side surface pads 212C are formed on two first inclined inner side surfaces 112C that are arranged apart from each other in the y direction across the first bottom surface 111C. The plurality of first inclined inner side surface pads 212C are used for mounting the second element 380C.

  The external terminal 221C is formed on the main surface 101C, and is used for surface mounting the semiconductor device 1C on, for example, a circuit board of an electronic device (not shown). In the present embodiment, a plurality of external terminals 221C are formed in two portions of the main surface 101C that are separated in the y direction across the recess 108C. The external terminal 221C has a structure in which bumps obtained by electroless plating a metal such as Ni, Pd, and Au are formed on the barrier seed layer 201C and the plating layer 202C. Thereby, the external terminal 221C has a shape bulging in the z direction. In the present embodiment, at least one external terminal 221C is a so-called ground terminal.

  As shown in FIG. 33, the four outer surfaces 103C of the substrate 100C surround the main surface when viewed in the z direction and form a rectangular ring shape. More specifically, each outer surface 103C includes an inclined outer surface 104C and a standing outer surface 105C. The inclined outer surface 104C is interposed between the main surface 101C and the standing outer surface 105C, and is inclined with respect to both the main surface 101C and the rising outer surface 105C. In the present embodiment, the inclined outer surface 104C is connected to the main surface 101C, and the standing outer surface 105C is connected to the back surface 102C. In the present embodiment, the inclination angle of the inclined outer surface 104C with respect to the xy plane is about 55 °. Note that the point where the inclination angle is 55 ° depends on the use of the (100) plane as the main surface 101C.

  Here, the inclination angle of the inclined outer surface 104C with respect to the xy plane (main surface 101C) is the same as the inclination angle of the first inclined inner surface 112C with respect to the main surface 101C. The inclined outer surface 104C and the first inclined inner surface 112C are intended to have the same angle by being formed by batch etching. Differences that inevitably occur due to variations in etching conditions and the like are included in the same range as used in the present invention.

  The standing outer surface 105C is substantially perpendicular to the main surface 101C and substantially parallel to the zx plane or the yz plane. In the present embodiment, the inclined outer surface 104C is smoother than the standing outer surface 105C. Note that the fact that the inclined outer surface 104C is smoother than the standing outer surface 105B in this way depends on the manufacturing method of the semiconductor device 1C. Since the standing outer surface 105C is an exposed surface generated by cutting the substrate material, the inclined outer surface 104C formed by etching is smoother than the standing outer surface 105C.

  The first element 370C is supported by the first bottom surface 111C, and is mounted via the solder 351C using the first bottom surface pad 212C.

  The second element 380C is supported by the first inclined inner surface 112C, and is mounted via the solder 351C using a plurality of first inclined inner surface pads 212C. In the present embodiment, the second element 380C is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and has a thickness of about 80 to 100 μm. In the present embodiment, the second element 380C has an opposing main surface 381C, an opening-side main surface 382C, and two inclined side surfaces 383C. The opposing main surface 381C faces the first element 370C. The opening side main surface 382C is located on the opposite side to the opposing main surface 381C in the z direction. The opening-side main surface 382C has a larger area than the opposed main surface 381C. The two inclined side surfaces 383C are two side surfaces that are separated from each other in the y direction among the four side surfaces that connect the opposing main surface 381C and the opening-side main surface 382C. The inclined side surface 383C is inclined with respect to the opposing main surface 381C, and in this embodiment, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is about 55 °.

  In the present embodiment, the second element 380C is composed of a single crystal of a semiconductor material, for example, the single crystal is Si. Further, the (100) surface of the second element 380C is adopted as the opposing main surface 381C. In addition, the point that the inclination angle of the inclined side surface 383C with respect to the opposed main surface 381C is 55 ° depends on the adoption of the (100) plane as the opposed main surface 381C. Here, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is the same as the inclination angle of the first inclined inner side surface 112C with respect to the main surface 101C described above. The inclined side surface 383C and the first inclined inner side surface 112C are intended to have the same angle by being formed by the same anisotropic etching. Differences that inevitably occur due to variations in etching conditions and the like are included in the same range as used in the present invention.

  In the second element 380C, a wiring pattern 384C made of a conductive metal thin film is formed in a predetermined region extending from the inclined side surface 383C to the opposing main surface 381C. With such a configuration, when the second element 380C is mounted, the first inclined inner side surface 112C and the inclined side surface 383C of the second element 380C face each other so as to be substantially parallel to each other. Therefore, in the second element 380C, the two inclined side surfaces 383C that are spaced apart from each other with the opposing main surface 381C interposed therebetween are supported by the two first inclined inner side surfaces 112C that are separated in the y direction in the first recess 110B. Yes. The second element 380C overlaps all of the first elements 370C in plan view, and is accommodated in the first recess 110C (recess 108C).

  The sealing resin 400C covers the first element 370C and the second element 380C and fills the recess 108C (first recess 110C). In the present embodiment, the sealing resin 400C includes a first sealing resin 410C and a second sealing resin 420C.

  The first sealing resin 410C covers the entire first element 370C. On the other hand, the first sealing resin 410C does not cover the first inclined inner surface pad 212C and the second element 380C.

  The second sealing resin 420C covers the entire second element 380C. On the other hand, the second sealing resin 420C exposes the external terminal 221C.

  Examples of the material of the first sealing resin 410C and the second sealing resin 420C include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The first sealing resin 410C and the second sealing resin 420C may be either translucent resin or non-translucent resin, but in the present embodiment, non-translucent resin is preferable.

  Next, the operation of the semiconductor device 1C will be described.

  According to the present embodiment, the first element 370C and the second element 380C are disposed and accommodated in a stacked manner in the recess 108C (first recess 110C) of the substrate 100C made of a semiconductor material. Therefore, there is no need to provide leads for supporting the first element 370C and the second element 380C. Compared to the case where the leads are molded, the substrate 100C made of a semiconductor material is less expensive to change the shape. Therefore, the cost of the semiconductor device 1C can be reduced. In particular, when the semiconductor device 1C is produced in a small amount, the cost reduction effect is remarkable.

  When the substrate 100C is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112C can be finished as a surface that is accurately inclined by a known predetermined angle with respect to the first bottom surface 111C. In particular, when the substrate 100C is made of Si and the (100) plane is adopted as the main surface 101C, the angles of the four first inclined inner side surfaces 112C with respect to the first bottom surface 111C can be set to about 55 °. . As a result, the semiconductor device 1C can have a well-balanced shape configuration.

  The second element 380C has an inclined side surface 383C. By mounting the second element 380C on the first inclined inner side surface 112C using the inclined side surface 383C, the second element 380C is located between the bottom surface 111C and the single first concave portion 110C (recessed portion 108C). Can be arranged at intervals. Then, the first element 370C can be mounted on the first bottom surface 111C so as to be accommodated at this interval. Therefore, the first element 370C and the second element 380C can be three-dimensionally arranged at different positions in the z direction without forming a space for accommodating the first element 370C and the second element 380C in a two-stage shape. . As described above, the configuration of the present embodiment in which no step is provided in the accommodation space of the first element 370C and the second element 380C can simplify the process for forming the accommodation space. Suitable for manufacturing well.

  The inclined side surface 381C of the second element 380C can be formed at the same time as the formation of the recess 108C by anisotropic etching. Thereby, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is the same as the inclination angle of the first inclined inner side surface 112C with respect to the main surface 101C of the substrate 100C. Accordingly, the posture of the second element 380C can be in a well-balanced state when mounted on the first inclined inner side surface 112C using the inclined side surface 383C.

  When manufacturing the semiconductor device 1C, if the substrate material is cut along a cutting line included in the inclined groove formed on the main surface 101C, the outer surface 103C of the chip-shaped substrate 100C that has been cut and separated is an inclined groove. 104C including an inclined outer surface that is part of the region. In the manufacture of the semiconductor device 1C, the cutting operation of the substrate material proceeds while being guided by the portion of the inclined groove. According to such a configuration, it is possible to suppress the occurrence of defects such as wafer cracking or chipping in the substrate material or the substrate 100C when the substrate material is cut. This is suitable for efficiently manufacturing the semiconductor device 1C.

  In the manufacture of the semiconductor device 1C, the formation of the recess 108C (first recess 110C) and the inclined groove can be performed simultaneously by anisotropic etching. And it cut | disconnects along a cutting line in the case of a cutting | disconnection of board | substrate material. Since this cutting line is included in the inclined groove, the cutting depth of the substrate material is smaller than the thickness of the substrate material. Thereby, the cutting operation of the substrate material can be performed efficiently, and the semiconductor device 1C can be manufactured efficiently.

  FIG. 35 shows a modification of the semiconductor device 1C described above. A semiconductor device 1C ′ illustrated in FIG. 35 includes a substrate 100C, a resin forming portion 150C, a wiring layer 200C, a first element 370C, a second element 380C, and a sealing resin 400C. The semiconductor device 1C ′ shown in FIG. 35 includes a resin forming portion 150C as compared with the semiconductor device 1C described above, and accordingly, the support structure of the second element 380C is different.

  The resin forming portion 150C is for providing a predetermined step in the recess 108C (first recess 110C). In the present embodiment, the resin forming portion 150C is formed on the bottom surface (first bottom surface 111C) of the recess 108C (first recess 110C), and is closer to one end in the y direction of the first bottom surface 111C (closer to the right end in the figure). ). The resin forming portion 150C is for mounting a portion closer to one end of the second element 380C in the y direction. The height of the resin forming portion 150C is, for example, about 150 μm. The resin forming portion 150C has a flat top surface and a side surface 152C inclined with respect to the top surface. Examples of the material of the resin forming portion 150C include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin.

  A resin forming portion pad 214C is formed on the resin forming portion 150C. In the present embodiment, a plurality of resin formation pads 214C are formed side by side in the x direction (the direction perpendicular to the paper surface in FIG. 35). These resin forming portion pads 214C are used for mounting the second element 380C. Further, since the side surface 152C of the resin forming portion 150C is inclined, a connection path (not shown) of the wiring layer 200C formed on the side surface 152C can be connected to the resin forming portion pad 214C.

  In the semiconductor device 1 </ b> C ′ illustrated in FIG. 35, the first inclined inner surface pad 212 </ b> C is formed only on the first inclined inner surface 112 </ b> C on the left side in the drawing among the four first inclined inner surfaces 112 </ b> C in the recess 108 </ b> C.

  In the second element 380C, only the left side surface in the drawing is an inclined side surface 383C. In the second element 380C, the left portion (inclined side surface 383C) in the drawing is supported by the first inclined inner surface 112C, and the right portion (opposing main surface 381C) in the drawing is supported by the resin forming portion 150C. When the second element 380C is mounted, the second element 380C can be easily set at a desired position in the z direction by adjusting the height dimension of the resin forming portion 150C.

  FIG. 36 shows another modification of the semiconductor device 1C described above. The semiconductor device 1C ″ illustrated in FIG. 36 includes a substrate 100C, a resin forming portion 130C, a wiring layer 200C, a first element 370C, two second elements 380C, and a sealing resin 400C. The semiconductor device 1C ″ includes two second elements 380C as compared with the semiconductor device 1C described above, and additionally includes a resin forming portion 130C.

  The resin forming portion 130C is for providing a predetermined step on the substrate 100C, and is formed on the substrate 100C (insulating layer 107C). In the semiconductor device 1C ″ shown in FIG. 36, the resin forming portion 130C is formed on the main surface 101C and is a portion serving as a base of the external terminal 221. The resin forming portion 130C is a concave portion of the main surface 101C. The resin forming portion 130C has a height of, for example, about 50 μm, and is formed with a flat top surface and a top surface of the resin forming portion 130C. Since the side surface 132C of the resin forming portion 130C is inclined, the connection path (not shown) of the wiring layer 200C formed on the side surface 132C is connected to the external terminal 221C. can do.

  In the semiconductor device 1C ″ shown in FIG. 36, a plurality (two) of second elements 380C are provided at intervals in the z-direction. 380C has basically the same configuration as the second element 380C positioned below in the drawing, but the dimension in the y direction is larger than that of the second element 380C positioned below.

  A plurality of first inclined inner surface pads 212C are formed at intervals in the z direction on the first inclined inner surface 112C that supports the two second elements 380C.

  The upper end portion of the second element 380C located in the upper part in the drawing protrudes upward from the recess 108C (first recess 110C). The second sealing resin 420C covers all of the second element 380C located above. Accordingly, the second sealing resin 420C has a portion located on the outer side in the normal direction of the main surface 101C than the main surface 101C.

  According to the semiconductor device 1C ″ shown in FIG. 36, more elements (first elements) are formed at different positions in the z direction without forming a space for accommodating the first element 370C and the second element 380C in a two-stage shape. 370C and the two second elements 380C) can be arranged in three dimensions.

  Also, as shown in FIG. 36, the second element 380C located in the upper part in the drawing protrudes upward from the main surface 101C. On the other hand, by forming the external terminals 221C on the main surface 101C via the resin forming portion 130C, the external terminals 221C can be projected in the z direction so as to be suitable for surface mounting.

  37 and 38 show a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device 1D of the present embodiment includes a substrate 100D, a resin forming portion 150D, a wiring layer 200D, a columnar conductive portion 230D, a first element 370D, a second element 380D, and a sealing resin 400D. In FIG. 37, the sealing resin 400D is omitted for convenience of understanding. 37 and 38, the communication route is omitted.

  The substrate 100D is a base for the semiconductor device 1D, and includes a base material 106D and an insulating layer 107D. The substrate 100D has a main surface 101D, a back surface 102D, and a recess 108D. The thickness of the substrate 100D is about 600 μm, for example. In the present embodiment, the main surface 101D and the back surface 102D face opposite sides in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1D. Further, the x direction and the y direction are both perpendicular to the z direction.

The base 106D is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The insulating layer 107D is made of SiO ₂ in this embodiment. The material of the base material 106D is not limited to Si, and may be any material that can form the recess 108D that satisfies the intention described later. The insulating layer 107D covers a portion of the base material 106D that faces from the side opposite to the back surface 102D. The thickness of the insulating layer 107D is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) surface of the base material 106D is employed as the main surface 101D. The recess 108D is recessed from the main surface 101D toward the back surface 102D. In the present embodiment, the recess 108D includes a first recess 110D. The first recess 110D has a first bottom surface 111D and four first inclined inner side surfaces 112D. The shape of the first recess 110D depends on the (100) plane being adopted as the main surface 101D.

  By forming the recess 108D, the main surface 101D has a rectangular shape in plan view. The first recess 110D has a rectangular shape in plan view. The depth of the first recess 110D is, for example, about 440 μm. The first bottom surface 111D has a rectangular shape in plan view. The four first inclined inner side surfaces 112D surround the first bottom surface 111D in a plan view, and have a substantially trapezoidal shape with a portion in contact with the first bottom surface 111D as an upper base. Each first inclined inner side surface 112D is inclined with respect to the first bottom surface 111D. In the present embodiment, the inclination angle of the first inclined inner side surface 112D with respect to the xy plane is about 55 °. Note that the first inclined inner side surface 112D has a substantially trapezoidal shape and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101D.

  The resin forming portion 150D is for providing a predetermined step on the substrate 100D, and is formed on the substrate 100D (insulating layer 107D). In the present embodiment, the resin forming portion 150D is formed on the bottom surface (first bottom surface 111D) of the recess 108D (first recess 110D), and is a portion on which the second element 380D is mounted. In the present embodiment, the resin forming portion 150D is formed at two portions of the first bottom surface 111D that are separated in the y direction. The height of the resin forming portion 150D is, for example, about 150 μm. The resin forming portion 150D has a flat top surface and a side surface 152D inclined with respect to the top surface. Examples of the material of the resin forming portion 150D include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The resin forming portion 150D may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  The wiring layer 200D is for configuring a current path that is input to and output from the first element 370D and the second element 380D. The wiring layer 200D is mainly formed on the insulating layer 107D. In this embodiment, the wiring layer 200D has a structure in which a barrier seed layer 201D and a plating layer 202D are stacked.

  The barrier seed layer 201D is a so-called underlayer for forming a desired plating layer 202D, and is formed on the insulating layer 107D. The barrier seed layer 201D is formed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107D and a Cu layer as a seed layer stacked on the barrier layer. The barrier seed layer 201D is formed by sputtering, for example. In the present embodiment, the barrier seed layer 201D is formed at predetermined sites on the insulating layer 107D and the resin forming portion 150D.

  The plating layer 202D is made of, for example, Cu and is formed by electrolytic plating using the barrier seed layer 201D. The thickness of the plating layer 202D is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200D includes a first bottom surface pad 211D, a resin forming portion pad 214D, a first inclined inner side surface pad 212D, and a communication path (not shown) for electrically connecting them. .

  The first bottom surface pad 211D is formed on the first bottom surface 111D of the first recess 110D. In the present embodiment, a plurality of first bottom surface pads 211D are formed, and these first bottom surface pads 211D are used for mounting the first element 370D.

  Resin forming part pad 214D is formed in resin forming part 150D. In the present embodiment, a plurality of resin forming portion pads 214D are formed in each resin forming portion 150D spaced apart on the first bottom surface 111D. These resin forming portion pads 214D are used for mounting the second element 380D. Further, since the side surface 152D of the resin forming portion 150D is inclined, the connection path (not shown) of the wiring layer 200D formed on the side surface 152D can be connected to the resin forming portion pad 214D.

  The first inclined inner surface pad 212D is formed on the first inclined inner surface 112D of the first recess 110D. In the present embodiment, a plurality of first inclined inner side surface pads 212D are formed on two first inclined inner side surfaces 112D that are arranged apart from each other in the y direction across the first bottom surface 111D. The first inclined inner side surface pad 212D is a portion to which one end of the columnar conductive portion 230D is connected.

  An external terminal 250D is provided on the sealing resin 400D. The external terminal 250D is used for surface mounting the semiconductor device 1D on a circuit board of an electronic device (not shown), for example. In the present embodiment, the external terminal 250D is provided on the upper surface 421D facing outward in the normal direction of the main surface 101D in the sealing resin 400D (second sealing resin 420D described later). In the present embodiment, a plurality of external terminals 250D are formed at two portions spaced apart in the y direction across the recess 108D. The external terminal 250D has a structure in which bumps obtained by electroless plating of a metal such as Ni, Pd, and Au are formed on an external terminal pad 240D described later. Thereby, the external terminal 250D has a shape bulging in the z direction. In the present embodiment, at least one external terminal 250D is a so-called ground terminal.

  The first element 370D is supported by the first bottom surface 111D, and is mounted via the solder 351D using the first bottom surface pad 211D.

  The second element 380D is supported by the resin forming portion 150D, and is mounted via the solder 351C using a plurality of resin forming portion pads 214D. In the present embodiment, the second element 380D is configured as a so-called ASIC (Application Specific Integrated Circuit) element and has a thickness of about 80 to 100 μm.

  The sealing resin 400D covers the first element 370D and the second element 380D, and fills the recess 108D (first recess 110D). In the present embodiment, the sealing resin 400D includes a first sealing resin 410D and a second sealing resin 420D.

  The first sealing resin 410D covers the entire first element 370D. On the other hand, the first sealing resin 410D does not cover the first inclined inner surface pad 212D and the second element 380D.

  The second sealing resin 420D covers the entire second element 380D. The second sealing resin 420D has an upper surface 421D. Upper surface 421D faces outward in the normal direction of main surface 101D. The second sealing resin 420D covers a part of the main surface 101D. On the other hand, the second sealing resin 420D exposes the external terminal 250D.

  Examples of the material of the first sealing resin 410D and the second sealing resin 420D include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The first sealing resin 410D and the second sealing resin 420D may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  As shown in FIG. 38, the columnar conductive portion 230D penetrates the sealing resin 400D (second sealing resin 420D) in the depth direction of the recess 108D. The columnar conductive portion 230D is connected to a portion of the wiring layer 200D that is formed in the recess 108D, and extends along the z direction (the normal direction of the main surface 101D). In the present embodiment, the lower end of the columnar conductive portion 230D in the drawing is connected to a first inclined inner surface pad 212D formed on the first inclined inner surface 112D. The columnar conductive portion 230D is made of, for example, Cu, and is formed by electrolytic plating using the first inclined inner side surface pad 212D. In the present embodiment, a plurality of columnar conductive portions 230D extend from two first inclined inner side surfaces 112D that are separated in the y direction across the bottom surface 111D. The upper end of the columnar conductive portion 230D in the figure and the upper surface 421D of the second sealing resin 420D are flush with each other.

  External terminal pads 240D are formed on the sealing resin 400D. The external terminal pad 240D is formed on the upper surface 421D of the second sealing resin 420D. In the present embodiment, the external terminal pads 240D are made of Cu, for example, and a plurality of external terminal pads 240D are provided at positions corresponding to the plurality of columnar conductive portions 230D. The external end pad 240D and the external terminal 250D formed thereon overlap the columnar conductive portion 230D when viewed in the z direction. The external terminal pad 240D covers the upper end of the columnar conductive portion 230D and is joined to the upper end of the columnar conductive portion 230D.

  Next, a procedure for forming the columnar conductive portion 230D that penetrates the sealing resin 400D (second sealing resin 420D) will be described with reference to FIGS.

  FIG. 39 shows a state in which the concave portion 108D is formed and the resin forming portion 150D and the wiring layer 200D are formed on the substrate material 100D ′. Thereafter, as shown in FIG. 40, a resist layer 600D is formed. The resist layer 600D is formed, for example, by spraying a photosensitive resist resin.

  Next, as shown in FIG. 41, the resist layer 600D is patterned. This patterning is performed by removing a desired portion by performing exposure and development on the resist layer using, for example, a photolithography technique for 600D. The shape of the resist layer 600D obtained by this patterning corresponds to the shape of the columnar conductive portion 230D described above. Here, an opening 610D corresponding to the shape of the columnar conductive portion 230D is formed in the resist layer, and a part of the first inclined inner side surface pad 212D is exposed. The exposure may be performed a plurality of times while changing the focal depth of the exposure in response to the recess 108D having a certain depth.

  Next, as shown in FIG. 42, a columnar conductive portion 230D is formed. The columnar conductive portion 230D is formed by, for example, electrolytic plating using the first inclined inner surface pad 212D. As a result, a columnar conductive portion 230D made of Cu, for example, is obtained.

  Next, as shown in FIG. 43, the resist layer 600D is removed, and the first element 370D is mounted, the first sealing resin 410D is formed, and the second element 380D is sequentially mounted (see FIG. 44).

  Next, as shown in FIG. 45, a second sealing resin 420 is formed. At this time, the upper end of the columnar conductive portion 230D protrudes from the upper end surface of the second sealing resin 420D. Next, as shown in FIG. 46, the upper part of the second sealing resin 420D is polished so that the upper end of the columnar conductive portion 230D in the figure and the upper surface 421D of the second sealing resin 420D are flush with each other.

  Next, the operation of the semiconductor device 1D will be described.

  According to the present embodiment, the first element 370D and the second element 380D are disposed and accommodated in the recess 108D (first recess 110D) of the substrate 100D made of a semiconductor material in a stacked manner. Therefore, there is no need to provide leads for supporting the first element 370D and the second element 380D. Compared to the case where the leads are molded, the substrate 100D made of a semiconductor material is less expensive to change the shape. Therefore, the cost of the semiconductor device 1D can be reduced. In particular, when a small amount of the semiconductor device 1D is produced, the cost reduction effect is remarkable.

  When the substrate 100D is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112D can be finished as a surface that is accurately inclined by a known predetermined angle with respect to the first bottom surface 111D. In particular, when the substrate 100D is made of Si and the (100) plane is adopted as the main surface 101D, the angles of the four first inclined inner side surfaces 112D with respect to the first bottom surface 111D can be set to about 55 °. . Thereby, it is possible to make semiconductor device 1D into a well-shaped configuration.

  A columnar conductive portion 230D that penetrates the sealing resin 400D is provided. The columnar conductive portion 230D extends in the z direction from the concave portion 108 of the substrate 100D, and is electrically connected to the external terminal 250D. According to such a configuration, the external terminal 250D can be disposed inside the recess 108D when viewed in the z direction (viewed in the normal direction of the main surface 101D). In the present embodiment, the dimension of the substrate 100D in the y direction can be reduced, which is suitable for downsizing the semiconductor device 1D.

  The columnar conductive portion 230D extends in the z direction from the first inclined inner side surface 112D. Thus, the first element 370D, the second element 370D, and the columnar conductive portion 230D are three-dimensionally arranged in a narrow space while avoiding mutual interference.

  The lower end of the columnar conductive portion 230D is connected to the first inclined inner surface pad 212D. The columnar conductive portion 230D rises from the inclined surface in the z-direction on the first inclined inner surface pad 212D using an electrolytic plating method or the like, and is appropriately conductively connected to the first inclined inner surface pad 212D.

  The upper end of the columnar conductive portion 230D is flush with the upper surface 421D of the second sealing resin 420D and is covered with the external terminal pad 240D. According to such a configuration, the columnar conductive portion 230D and the external terminal 250D can be appropriately conductively connected via the external terminal pad 240D.

  By forming the resin forming portion 150D at an appropriate position in the recess 108D (first recess 110D), the space for accommodating the first element 370D and the second element 380D can be formed into a two-stage shape. By mounting the integrated circuit element 370D on the first bottom surface 111D and mounting the second element 380D on the resin forming portion 150D, the first element 370D and the second element 380D are three-dimensionally arranged at different positions in the z direction. be able to. Thereby, it is possible to achieve both miniaturization and high functionality of the semiconductor device 1D.

  47 and 48 show a modification of the semiconductor device 1D described above. 47 and 48 includes a substrate 100D, a resin forming part 150D, a wiring layer 200D, a columnar conductive part 230D, a first element 370D, a second element 380D, and a sealing resin 400D. . 47 and 48 differs from the semiconductor device 1D described above mainly in the arrangement of the columnar conductive portions 230D and the support structure of the second element 380D.

  In the semiconductor device 1D ′ shown in FIG. 47, the resin forming portion 150D is formed on the bottom surface (first bottom surface 111D) of the recess 108D (first recess 110D), and one end of the first bottom surface 111D in the y direction. It is formed in the part (near the right end in the figure). The resin forming portion 150D is for mounting a portion closer to one end in the y direction of the second element 380D.

  In the semiconductor device 1D 'shown in FIGS. 47 and 48, the plurality of columnar conductive portions 230D all extend from the first inclined inner side surface 112D located on the right side in the drawing in the z direction. The plurality of external terminals 250D include a plurality of external terminals 250D (251D) located on the right side in the figure and a plurality of external terminals 250D (252D) located on the left side in the figure. The external terminal 251D overlaps the columnar conductive portion 230D when viewed in the z direction (viewed in the normal direction of the main surface 101D). On the other hand, the external terminal 252D is located away from the external terminal 251D with the bottom surface 111D interposed therebetween. The external terminal 252D and the columnar conductive portion 230 are formed on the second sealing resin 420D and are electrically connected via the wiring pattern 260D. The wiring pattern 260D and the second sealing resin 420D are covered with a resist 700D made of an insulating material. The resist 700 </ b> D exposes the external terminals 251 </ b> D and 252 </ b> D, and covers the other entire z-direction view.

  The left end of the second element 380D in the figure is supported by the first inclined inner surface 112D and is mounted via the solder 351D using the plurality of first inclined inner surface pads 212D. The second element 380D has an opposing main surface 381D, an opening-side main surface 382D, and an inclined side surface 383D. The opposing main surface 381D faces the first element 370D. The opening-side main surface 382D is located on the opposite side to the opposing main surface 381D in the z direction. The opening-side main surface 382D has a larger area than the opposing main surface 381D. The inclined side surface 383D is a side surface facing one side (left side in the figure) in the y direction among the four side surfaces connecting the opposing main surface 381D and the opening-side main surface 382D. The inclined side surface 383D is inclined with respect to the opposing main surface 381D. In the present embodiment, the inclination angle of the inclined side surface 383D with respect to the opposing main surface 381D is about 55 °.

  In the second element 380D, a wiring pattern 384D made of a conductive metal thin film is formed in a predetermined region extending from the inclined side surface 383D to the opposing main surface 381D. With such a configuration, when the second element 380D is mounted, the first inclined inner side surface 112D and the inclined side surface 383D of the second element 380D face each other so as to be substantially parallel to each other.

  In the semiconductor device 1D 'shown in FIGS. 47 and 48, all the columnar conductive portions 230D are collectively formed on the first inclined inner side surface 112D on the right side in the drawing, which is one region. Further, in the second element 380D, the inclined side surface 383D on the left side in the drawing is supported by the first inclined inner side surface 112D. For this reason, it is possible to avoid interference between the plurality of columnar conductive portions 230D and the second element 380D. Therefore, the size of the second element 380D is increased, and the entire semiconductor device 1D ′ is suitable for further downsizing. On the other hand, the external terminal 251D and the external terminal 252D are spaced apart in the y direction. Thereby, the semiconductor device 1D ′ can be mounted in a balanced manner on a substrate of an electronic device.

  FIG. 49 shows another modification of the semiconductor device 1D described above. 49 includes a substrate 100D, a wiring layer 200D, a columnar conductive portion 230D, a first element 370D, a second element 380D, and a sealing resin 400D. The semiconductor device 1D ″ illustrated in FIG. 1D ″ differs from the semiconductor device 1D described above mainly in the shape of the concave portion 108D of the substrate 100D, and does not include the resin forming portion 150D.

  In the semiconductor device 1D ″ shown in FIG. 49, the recess 108D includes a first recess 110D and a second recess 120D. The first recess 110D is located on the back surface 102D side, and includes the first bottom surface 111D and the four first recesses. The second concave portion 120D is located on the main surface 101D side with respect to the first concave portion 110D, and has two second bottom surfaces 121D and four second inclined inner side surfaces 122D. The shapes of 110D and second recess 120D depend on the adoption of (100) surface as main surface 101 D. The configurations of first recess 110D and second recess 120D are the same as those shown in FIG. This is similar to the configuration of the first recess 110A and the second recess 120A.

  The second recess 120D has a rectangular shape in plan view. The two second bottom surfaces 121D have a rectangular shape in plan view and sandwich the first recess 110D. Each second bottom surface 121D is connected to the first inclined inner surface 112D. The four second inclined inner side surfaces 122D surround the two second bottom surfaces 121D in a plan view and have a substantially trapezoidal shape. Each second inclined inner side surface 122D is inclined with respect to the second bottom surface 121D. In the present embodiment, the inclination angle of the second inclined inner side surface 122D with respect to the xy plane is about 55 °. The point that the second inclined inner side surface 122D is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101D.

  In the semiconductor device 1D ″ shown in FIG. 49, the wiring layer 200D includes a first bottom surface pad 211D, a second bottom surface pad 215D, a second inclined inner surface pad 216D, and a communication path (not shown) for electrically connecting them. have.

  The second bottom surface pad 215D is formed on the second bottom surface 121D. In the present embodiment, a plurality of second bottom surface pads 215D are formed on each second bottom surface 121D spaced apart in the y direction across the first bottom surface 111D. These second bottom surface pads 215D are used for mounting the second element 380D.

  The second inclined inner surface pad 216D is formed on the second inclined inner surface 122D of the second recess 120D. In the present embodiment, a plurality of second inclined inner side surface pads 216D are formed on two second inclined inner side surfaces 122D that are arranged apart from each other in the y direction across the first bottom surface 111D. The second inclined inner surface pad 216D is a portion to which one end of the columnar conductive portion 230D is connected.

  In the semiconductor device 1D ″ shown in FIG. 49, the concave portion 108D is formed in a two-stage shape by the first concave portion 110D and the second concave portion 120D, so that the first concave portion 110D is a dedicated space for accommodating the first element 370D. Accordingly, the first element 370D and the second element 380D can be appropriately arranged in a three-dimensional manner.

  The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways.

1A to 1D, 1B ', 1C', 1C ", 1D ', 1D" Semiconductor devices 100A to 100D Substrate 101A to 101D Main surface 102A to 102D Back surface 103A to 103D Outer side surface 104A to 104D Inclined outer surface 105A to 105D Standing outer surface 106A to 106D Base material 107A to 107D Insulating layer 108A to 108D Recess 110A to 110D First recess 111A to 111D First bottom surface 112A to 112D First inclined inner side surface 120A, 120D Second recess 121A, 121D Second bottom surface 122A, 122D 2 inclined inner side surfaces 130A, 130C resin forming portion 140A resin forming portions 150B, 150C, 150D resin forming portion 183A inclined grooves 200A to 200D wiring layers 211A to 211D first bottom surface pads 213A resin forming portion pads 214B to 214D resin forming portion pads 12A, 212C, 212D First inclined side surface pad 215D Second bottom surface pad 216D Second inclined inner side surface pads 221A-221C External terminal 230D Columnar conductive portion 231A, 234A, 235A, 236A Connection path 240D External terminal pad 250D, 251D, 252D External terminal 260D Wiring pattern 311A, 312A, 313A Direction sensor element 330A, 330B Integrated circuit element 343A Capacitor 350B Wireless communication element 351A-351D Solder 360B Inductor 370C, 370D First element 380C, 380D Second element 381C, 381D Opposing main surface 382C , 382D Opening main surface 383C, 383D Inclined side surface 400A-400D Sealing resin 410A-410D First sealing resin 420A-420D Second sealing resin 500A, 500 B Metal film 510A, 510B Connection path

Claims (22)

A substrate having a main surface, an outer surface intersecting the main surface and a recess recessed from the main surface, and made of a semiconductor material;
A wiring layer at least partially formed on the substrate;
One or more elements housed in the recess,
A sealing resin covering at least a part of the one or more elements;
A metal film formed on the outer surface;
A semiconductor device comprising: The outer surface includes a standing outer surface, and an inclined outer surface that is interposed between the main surface and the standing outer surface and is inclined with respect to both the main surface and the standing outer surface,
2. The semiconductor device according to claim 1, wherein the metal film is formed on the inclined outer surface, and the standing outer surface is exposed.   The semiconductor device according to claim 2, wherein the inclined outer surface is smoother than the standing outer surface. The wiring layer has a plurality of external terminals formed on the main surface,
4. The semiconductor device according to claim 2, wherein the metal film has a connection path connected to any one of the plurality of external terminals connected to the ground. 5.   The semiconductor device according to claim 4, wherein the metal film as a whole surrounds the main surface when viewed in the normal direction of the main surface.   The semiconductor device according to claim 4, wherein the one or more elements include a wireless communication element. An additional element covering at least a part of the one or more elements;
The semiconductor device according to claim 2, further comprising an additional metal film positioned between the additional element and the one or more elements.   The semiconductor device according to claim 7, wherein the additional metal film overlaps one of the one or more elements as viewed in the normal direction of the main surface.   The semiconductor device according to claim 8, wherein the additional metal film is conductively connected to any one of the plurality of external terminals that is ground-connected.   The semiconductor device according to claim 2, wherein the outer surface surrounds the main surface in a normal direction view of the main surface and forms a rectangular ring shape.   The semiconductor device according to claim 10, wherein the substrate is made of a single crystal of a semiconductor material.   The semiconductor device according to claim 11, wherein the semiconductor material is Si.   The semiconductor device according to claim 12, wherein the concave portion has an inclined inner side surface inclined with respect to the main surface and a bottom surface. The main surface is a (100) surface,
The semiconductor device according to claim 13, wherein the recess has four inclined inner side surfaces.   The semiconductor device according to claim 14, wherein an inclination angle of the inclined outer surface with respect to the main surface is the same as an inclination angle of the inclined inner surface with respect to the main surface.   The semiconductor device according to claim 2, further comprising a resin formation portion formed on at least one of the main surface and the recess. The resin forming portion includes a first resin forming portion formed on the main surface,
The semiconductor device according to claim 16, wherein the wiring layer has a plurality of external terminals formed in the first resin formation portion. An additional element covering at least a part of the one or more elements;
The recess contains the one or more elements, has a first recess having a first bottom surface and a first inclined inner surface, a second bottom surface connected to the first inclined inner surface, and the second bottom surface and the main surface. The semiconductor device according to claim 17, further comprising: a second concave portion having a second inclined inner side surface connected to the second concave portion.   The semiconductor device according to claim 18, wherein the additional element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.   The semiconductor device according to claim 18, wherein the substrate is made of a single crystal of a semiconductor material.   The semiconductor device according to claim 20, wherein the semiconductor material is Si.   The semiconductor device according to claim 21, wherein an inclination angle of the inclined outer surface with respect to the main surface is the same as an inclination angle of the first inclined inner surface and the second inclined inner surface with respect to the main surface.

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