JP2016028009A - Silicon carbide substrate and silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate and silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide substrate, a silicon carbide semiconductor device and methods of producing a silicon carbide substrate and a silicon carbide semiconductor device, each of which enables the occurrence of a crack in a silicon dioxide layer formed on the silicon carbide substrate to be suppressed.SOLUTION: The method of producing a silicon carbide related to the embodiment has the following steps: preparing a silicon carbide single crystal substrate 80 which has a first principal plane 80a and a second principal plane 80b on the opposite side of the first principal plane 80a, and a first side end part 80c connecting the first principal plane 80a and the second principal plane 80b together, and which has the maximum of the width D of the first principal face 80a larger than 100 mm; forming a silicon carbide epitaxial layer 81 being in contact with the first side end part 80c, the first principal plane 80a, and a boundary 80d between the first principal plane 80a and the first side end part 80c; and removing the silicon carbide epitaxial layer 81 which is formed in contact with the first side end part 80c and the boundary 80d.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide substrate and a silicon carbide semiconductor device, and in particular, a silicon carbide substrate, a silicon carbide semiconductor device, and a carbonized carbon that can suppress cracking of the silicon carbide substrate. The present invention relates to a method for manufacturing a silicon substrate and a silicon carbide semiconductor device.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, use under a high temperature environment, etc., silicon carbide is being adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  The silicon carbide substrate is prepared by chamfering a side surface portion after cutting a silicon carbide single crystal manufactured by, for example, a sublimation method. For example, Japanese Patent Laying-Open No. 2010-64918 (Patent Document 1) describes that a silicon carbide epitaxial layer is formed on a silicon carbide single crystal wafer in which a side surface portion of a silicon carbide substrate is chamfered. Yes.

JP 2010-64918 A

  However, when a silicon carbide semiconductor device is manufactured using a silicon carbide substrate having a silicon carbide epitaxial layer formed on a silicon carbide single crystal that has been chamfered, the silicon dioxide layer formed on the silicon carbide substrate is cracked. There was a case.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a silicon carbide substrate and a carbonized carbon carbide capable of suppressing the occurrence of cracks in the silicon dioxide layer formed on the silicon carbide substrate. A silicon semiconductor device, and a method for manufacturing a silicon carbide substrate and a silicon carbide semiconductor device are provided.

  The method for manufacturing a silicon carbide substrate according to the present invention includes the following steps. A first main surface, a second main surface opposite to the first main surface, a first side end connecting the first main surface and the second main surface, and a first A silicon carbide single crystal substrate having a maximum width of the main surface of greater than 100 mm is prepared. A silicon carbide epitaxial layer in contact with the first side end, the first main surface, and the boundary between the first main surface and the first side end is formed. The silicon carbide epitaxial layer formed in contact with the first side end and the boundary is removed.

  A silicon carbide substrate according to the present invention includes a silicon carbide single crystal substrate and a silicon carbide epitaxial layer. The silicon carbide single crystal substrate includes a first main surface, a second main surface opposite to the first main surface, and a first side end portion connecting the first main surface and the second main surface. And the maximum width of the first main surface is greater than 100 mm. The silicon carbide epitaxial layer in contact with the center of the first main surface includes a third main surface in contact with the center of the first main surface and a fourth main surface opposite to the third main surface. The outer peripheral end of the fourth main surface is located closer to the center side in the direction parallel to the first main surface than the boundary between the first main surface and the first side end.

  According to the present invention, there are provided a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing the silicon carbide substrate and the silicon carbide semiconductor device capable of suppressing the occurrence of cracks in the silicon dioxide layer formed on the silicon carbide substrate. can do.

FIG. 3 is a schematic plan view schematically showing the structure of the silicon carbide substrate in the first embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide substrate in Embodiment 1 of this invention. It is a flowchart which shows schematically the manufacturing method of the silicon carbide substrate in Embodiment 1 of this invention. FIG. 5 is a schematic plan view schematically showing a first step of the method for manufacturing the silicon carbide substrate in the first embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide substrate in Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide substrate in Embodiment 1 of this invention. FIG. 5 is a schematic plan view schematically showing a first example (a) and a second example (b) of the second step of the method for manufacturing the silicon carbide substrate in the first embodiment of the present invention. FIG. 8 is a schematic enlarged plan view of a region C in FIG. 7. It is a cross-sectional schematic diagram of area | region IX-IX in FIG. It is a cross-sectional schematic diagram of area | region XX in FIG. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide substrate in Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide substrate in Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a perspective schematic diagram which shows schematically the structure of the silicon carbide substrate which the silicon carbide semiconductor device in Embodiment 2 of this invention has. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. FIG. 11 is an enlarged schematic cross sectional view schematically showing an end portion of a silicon carbide semiconductor device in a second step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 5th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 6th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 7th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 8th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 9th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 10th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide substrate in Embodiment 3 of this invention. FIG. 14 is an enlarged schematic cross sectional view schematically showing an end portion of a silicon carbide semiconductor device in a second step of the method for manufacturing the silicon carbide semiconductor device in the fourth embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the modification 1 of the 3rd process of the manufacturing method of the silicon carbide substrate in Embodiment 3 of this invention. It is a cross-sectional schematic diagram which shows schematically the modification 2 of the 3rd process of the manufacturing method of the silicon carbide substrate in Embodiment 3 of this invention. FIG. 6 is a schematic plan view schematically showing positions of orientation flat portion OF and index flat portion IF when the fourth surface of the silicon carbide single crystal substrate is a (0001) plane. FIG. 6 is a schematic plan view schematically showing positions of orientation flat portion OF and index flat portion IF when the fourth surface of the silicon carbide single crystal substrate is a (000-1) plane.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

First, the outline of the embodiment of the present invention will be described in the following (1) to (20).
As a result of intensive studies on the cause of cracking of the silicon dioxide layer formed on the silicon carbide substrate, the inventors have obtained the following knowledge and found the present invention. First, when a silicon carbide epitaxial layer is formed on a silicon carbide single crystal substrate, a stepped portion is formed at the outer peripheral end of the silicon carbide epitaxial layer. Thereafter, when the silicon dioxide layer is formed on the epitaxial layer, cracks occur in the silicon dioxide layer so as to cross the surface of the silicon carbide substrate. When the size of the silicon carbide substrate was 100 mm or less, the silicon dioxide layer hardly cracked. However, when the size of the silicon carbide substrate exceeded 100 mm, the silicon dioxide layer cracked remarkably. Cracks in the silicon dioxide layer occur when a heat treatment is performed on the silicon carbide substrate on which the silicon dioxide layer is formed, or the silicon carbide substrate on which the silicon dioxide layer is formed is mounted on the substrate holding chuck. Or when it is removed from the substrate holding chuck. Furthermore, the thermal expansion coefficient of silicon carbide is about seven times the thermal expansion coefficient of silicon dioxide. Considering the above comprehensively, one of the causes of cracking of the silicon dioxide layer is presumed to be stress generated in the silicon dioxide layer due to the difference in thermal expansion coefficient between silicon dioxide and silicon carbide.

  Further, when the stepped portion formed on the outer peripheral end portion of the epitaxial layer is examined in detail, most of the stepped portion is a straight line obtained by projecting a straight line parallel to the <11-20> orientation onto the main surface of the silicon carbide single crystal substrate. It was found that the main surface was formed so as to extend along a straight line rotated within a range of ± 20 °. Since the crack of the silicon dioxide layer extends in the direction in which the step portion extends, it is considered that the crack occurs from the step portion. That is, it is considered that cracking of the silicon dioxide layer can be suppressed by removing the step portion formed at the outer peripheral end portion of the epitaxial layer.

  (1) The manufacturing method of the silicon carbide substrate which concerns on embodiment has the following processes. A first main surface 80a, a second main surface 80b opposite to the first main surface 80a, and a first side end portion 80c connecting the first main surface 80a and the second main surface 80b. A silicon carbide single crystal substrate 80 having a maximum value of width D of first main surface 80a and greater than 100 mm is prepared. Silicon carbide epitaxial layer 81 in contact with first side end portion 80c, first main surface 80a, and boundary 80d between first main surface 80a and first side end portion 80c is formed. Silicon carbide epitaxial layer 81 formed in contact with first side end portion 80c and boundary 80d is removed.

  According to the method for manufacturing a silicon carbide substrate according to the embodiment, the first main surface 80a, the first side end portion 80c, and the boundary 80d of silicon carbide single crystal substrate 80 having a width greater than 100 mm are in contact. After silicon carbide epitaxial layer 81 is formed, silicon carbide epitaxial layer 81 formed in contact with first side end portion 80c and boundary 80d is removed. As a result, the step portion 2 formed on the first side end portion 80c and the boundary 80d is removed, so that when the silicon dioxide layer is formed on the silicon carbide substrate 10, the silicon dioxide layer It can suppress that a crack generate | occur | produces.

  (2) Preferably in the method for manufacturing the silicon carbide substrate according to the embodiment, in the step of forming the silicon carbide epitaxial layer, silicon carbide epitaxial layer 81 having stepped portion 2 on the boundary is formed. In the step of removing the silicon carbide epitaxial layer, the stepped portion 2 is removed. Thereby, when a silicon dioxide layer is formed on silicon carbide substrate 10, it can control effectively that a crack occurs to a silicon dioxide layer.

  (3) Preferably, in the method for manufacturing a silicon carbide substrate according to the embodiment, stepped portion 2 has a first main surface obtained by projecting a straight line parallel to <11-20> direction onto first main surface 80a. It is formed so as to extend along a straight line rotated within a range of ± 20 ° within 80a. The crack of the silicon dioxide layer is particularly a straight line obtained by projecting a straight line parallel to the <11-20> direction onto the first main surface 80a and rotating within a range of ± 20 ° within the first main surface 80a. It is thought that it occurs due to the stepped portion 2 extending along. Therefore, by removing the step portion extending in the above direction, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  (4) In the method for manufacturing a silicon carbide substrate according to the embodiment, preferably, length L3 of stepped portion 2 along the direction from first side end portion 80c toward center 80p is not less than 50 μm and not more than 5000 μm. It is thought that the crack of the silicon dioxide layer occurs due to the step portion 2 having a length of 100 μm or more. Therefore, by removing the step portion 2 having the above length, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  (5) Preferably in the method for manufacturing the silicon carbide substrate according to the embodiment, depth H1 of stepped portion 2 in the direction perpendicular to first main surface 80a is not less than 1 μm and not more than 50 μm. It is considered that the crack of the silicon dioxide layer occurs due to the step portion 2 having a depth of 5 μm or more. Although the depth H1 of the stepped portion 2 tends to increase in proportion to the thickness of the silicon carbide epitaxial layer, the depth H1 may be greater than or equal to the thickness of the silicon carbide epitaxial layer, and may be less than the thickness of the silicon carbide epitaxial layer. Can be. This depends on the growth conditions of the silicon carbide epitaxial layer and the shape of the side end portion 81c (length L2 portion). The relationship between the length L3 and the depth H1 is as follows. Cracks are likely to occur when the length L3 is short and the depth H1 is large, and conversely when the length L3 is long and the depth H1 is small. By removing the step portion having the above depth, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  (6) Preferably in the method for manufacturing a silicon carbide substrate according to the embodiment, thickness H2 of silicon carbide epitaxial layer 81 on center 80p of first main surface 80a is 5 μm or more. It is considered that the stepped portion 2 that causes cracking of the silicon dioxide layer is significantly generated when the thickness of the silicon carbide epitaxial layer 81 is 5 μm or more. Therefore, when the thickness of silicon carbide epitaxial layer 81 is 5 μm or more, it is possible to more effectively suppress the generation of cracks in the silicon dioxide layer.

  (7) The manufacturing method of the silicon carbide semiconductor device which concerns on embodiment has the following processes. A silicon carbide substrate manufactured by the method according to any one of (1) to (6) is prepared. Silicon dioxide layers 61 and 93 arranged to face main surface 10a of silicon carbide epitaxial layer 81 are formed. Thereby, it can suppress that a crack generate | occur | produces with respect to the silicon dioxide layers 61 and 93 arrange | positioned facing the main surface 10a of the silicon carbide epitaxial layer 81. FIG.

  (8) Preferably in the method for manufacturing the silicon carbide semiconductor device according to the embodiment, silicon dioxide layer 61 includes an ion implantation mask 61a. Thereby, it can suppress that a crack generate | occur | produces with respect to the mask 61a for ion implantation.

  (9) In the method for manufacturing a silicon carbide semiconductor device according to the embodiment, preferably, ion implantation mask 61 a is in contact with first side end portion 80 c of silicon carbide single crystal substrate 80. Since the ion implantation mask 61a is formed in contact with the first side end portion 80c from which the step portion 2 has been removed, it is possible to suppress the occurrence of cracks in the ion implantation mask 61a.

  (10) Preferably in the method for manufacturing a silicon carbide semiconductor device according to the embodiment, silicon dioxide layer 93 includes an interlayer insulating film 93. Thereby, it is possible to suppress the occurrence of cracks in the interlayer insulating film 93.

  (11) Preferably in the method for manufacturing the silicon carbide semiconductor device according to the embodiment, thickness H3 of silicon dioxide layers 61 and 93 is not less than 0.8 μm and not more than 20 μm. Thereby, even when the thickness H3 of the silicon dioxide layers 61 and 93 is 0.8 μm or more and 20 μm or less, it is possible to prevent the silicon dioxide layers 61 and 93 from being cracked.

  (12) Preferably, the method for manufacturing the silicon carbide semiconductor device according to the embodiment further includes a step of annealing silicon carbide substrate 10 and silicon dioxide layers 61 and 93 after the step of forming the silicon dioxide layer. Thereby, even when the silicon carbide substrate 10 and the silicon dioxide layers 61 and 93 are annealed, it is possible to prevent the silicon dioxide layers 61 and 93 from being cracked.

  (13) The silicon carbide substrate according to the embodiment includes a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer 81. Silicon carbide single crystal substrate 80 includes a first main surface 80a, a second main surface 80b opposite to the first main surface, and a first main surface 80a connecting the first main surface 80a and the second main surface 80b. And the maximum width D of the first main surface 80a is greater than 100 mm. The silicon carbide epitaxial layer 81 in contact with the center 80p of the first main surface 80a includes a third main surface 10b in contact with the center 80p of the first main surface 80a and a fourth main surface 10b opposite to the third main surface 10b. Main surface 10a. The outer peripheral end portion 81e of the fourth main surface 10a is located closer to the center 80p side in the direction parallel to the first main surface 80a than the boundary 80d between the first main surface 80a and the first side end portion 80c. .

  According to the silicon carbide substrate according to the embodiment, the outer periphery of fourth main surface 10a of silicon carbide epitaxial layer 81 in contact with center 80p of first main surface 80a of silicon carbide single crystal substrate 80 having a width greater than 100 mm. The end portion 81e is located closer to the center 80p side in the direction parallel to the first main surface 80a than the boundary 80d between the first main surface 80a and the first side end portion 80c. Thereby, silicon carbide substrate 10 from which stepped portion 2 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

  (14) In the silicon carbide substrate according to the embodiment, preferably, outer peripheral end portion 81t of third main surface 10b is first than boundary 80d between first main surface 80a and first side end portion 80c. It is located on the center 80p side in the direction parallel to the main surface 80a. Thereby, silicon carbide substrate 10 from which silicon carbide epitaxial layer 81 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

  (15) Preferably in the silicon carbide substrate according to the embodiment, silicon carbide epitaxial layer 81 includes a second side end portion 81c that connects third main surface 10b and fourth main surface 10a. In cross-sectional view, the second side end 81c is formed to have a curvature along the first side end 80c. Thereby, silicon carbide substrate 10 from which stepped portion 2 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

  (16) In the silicon carbide substrate according to the embodiment, preferably, distance L1 in the direction parallel to first main surface 80a from outer peripheral end portion 81e of fourth main surface 10a to boundary 80d is 10 μm or more and 5000 μm. It is as follows. Thereby, silicon carbide substrate 10 in which stepped portion 2 on boundary 80d is effectively removed is obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

  (17) In the silicon carbide substrate according to the embodiment, preferably, thickness H2 of silicon carbide epitaxial layer 81 on center 80p of first main surface 80a is 5 μm or more. It is considered that the stepped portion 2 that causes cracking of the silicon dioxide layer is significantly generated when the thickness of the silicon carbide epitaxial layer 81 is 5 μm or more. Therefore, when the thickness of silicon carbide epitaxial layer 81 is 5 μm or more, it is possible to more effectively suppress the generation of cracks in the silicon dioxide layer.

  (18) A silicon carbide semiconductor device according to an embodiment includes a silicon carbide substrate 10 according to any one of (12) to (14), and a silicon dioxide layer 93 disposed to face silicon carbide epitaxial layer 81. Have Thereby, the crack with respect to the silicon dioxide layer 93 of a silicon carbide semiconductor device can be suppressed.

  (19) Preferably in the silicon carbide semiconductor device according to the embodiment, silicon dioxide layer 93 is interlayer insulating film 93. Thereby, the crack with respect to the interlayer insulation film of a silicon carbide semiconductor device can be suppressed.

  (20) In the silicon carbide semiconductor device according to the embodiment, preferably, thickness H3 of silicon dioxide layer 93 is not less than 0.8 μm and not more than 20 μm. Even when the thickness H3 of the silicon dioxide layer 93 is not less than 0.8 μm and not more than 20 μm, the generation of cracks in the silicon dioxide layer 93 can be suppressed.

Next, embodiments of the present invention will be described in more detail.
(Embodiment 1)
A configuration of silicon carbide substrate 10 according to the first embodiment will be described with reference to FIGS. 1 and 2. Silicon carbide substrate 10 according to the first embodiment mainly includes a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer 81. Silicon carbide single crystal substrate 80 is made of, for example, polytype 4H hexagonal silicon carbide. Silicon carbide single crystal substrate 80 contains an impurity element such as nitrogen, and the conductivity type of silicon carbide single crystal substrate 80 is n-type (first conductivity type). The concentration of impurities such as nitrogen contained in silicon carbide single crystal substrate 80 is, for example, about 1 × 10 ¹⁸ cm ⁻³ or more and about 1 × 10 ¹⁹ cm ⁻³ or less. Silicon carbide single crystal substrate 80 connects first main surface 80a, second main surface 80b opposite to first main surface 80a, and first main surface 80a and second main surface 80b. It has a first side end portion 80c, a boundary 80d between the first side end portion 80c and the first main surface 80a, and an outermost peripheral portion 80e. The first side end portion 80c is a chamfered surface, and is a portion having a curvature that is convex in the outer circumferential direction in a cross-sectional view (a visual field in a direction parallel to the first main surface). The first main surface 80a may be, for example, a {0001} plane, a surface off by about 10 ° or less from the {0001} plane, or about 0.25 ° or less from the {0001} plane. It may be a surface that is turned off. In other words, the first main surface 80a may be, for example, a (0001) plane or a (000-1) plane, or a plane off by about 10 ° or less from the (0001) plane or the (000-1) plane. It may be a surface that is off about 0.25 ° or less from the (0001) plane or the (000-1) plane.

Silicon carbide epitaxial layer 81 is provided in contact with first main surface 80a of silicon carbide single crystal substrate 80. Silicon carbide epitaxial layer 81 has a thickness of, for example, about 5 μm to 40 μm. Silicon carbide epitaxial layer 81 contains an impurity element such as nitrogen, for example, and silicon carbide epitaxial layer 81 has n type conductivity. The impurity concentration of silicon carbide epitaxial layer 81 may be lower than the impurity concentration of silicon carbide single crystal substrate 80. The impurity concentration of silicon carbide epitaxial layer 81 is not less than about 1 × 10 ¹⁵ cm ^{−3 and not} more than about 1 × 10 ¹⁶ cm ⁻³ , for example. Silicon carbide epitaxial layer 81 includes third main surface 10b in contact with first main surface 80a, fourth main surface 10a opposite to third main surface 10b, third main surface 10b, and fourth main surface 10b. A second side end portion 81c connecting the main surface 10a, an outer peripheral end portion 81e of the fourth main surface 10a, and an outer peripheral end portion 81t of the third main surface 10b.

  Referring to FIG. 1, the maximum value of width D of fourth main surface 10a of silicon carbide single crystal substrate 80 of silicon carbide substrate 10 in plan view (field of view of normal direction of fourth main surface 10a) is Greater than 100 mm. Preferably, the maximum value of the width D of the fourth main surface 10a is 150 mm or more. Silicon carbide substrate 10 is substantially circular. Silicon carbide substrate 10 may have an orientation flat portion OF.

  Referring to FIG. 2, silicon carbide epitaxial layer 81 includes a third main surface 10b in contact with center 80p of first main surface 80a, and a fourth main surface 10a opposite to third main surface 10b. including. In a cross-sectional view, the outer peripheral end portion 81e of the fourth main surface 10a has a center 80p in a direction parallel to the first main surface 80a rather than the boundary 80d between the first main surface 80a and the first side end portion 80c. (See FIG. 4). The boundary 80d between the first main surface 80a and the first side end portion 80c may be an inflection point of a line connecting the first main surface 80a and the first side end portion 80c. Silicon carbide epitaxial layer 81 includes a second side end portion 81c that connects third main surface 10b and fourth main surface 10a. The outer peripheral end portion 81e of the fourth main surface 10a may be an inflection point of a line connecting the fourth main surface 10a and the second side end portion 81c. In a cross-sectional view, second side end portion 81 c of silicon carbide epitaxial layer 81 is formed to have a convex curvature in the outer peripheral direction, and extends along first side end portion 80 c of silicon carbide single crystal substrate 80. Is formed. Preferably, the curvature radius of the second side end portion 81c in the sectional view is substantially the same as the curvature radius of the first side end portion 80c.

  The thickness of silicon carbide epitaxial layer 81 on boundary 80d between first main surface 80a and first side end portion 80c is substantially zero, and is on the center 80p (see FIG. 4) of first main surface 80a. Thickness H2 of silicon carbide epitaxial layer 81 located is not less than 5 μm, for example. Further, outer peripheral end portion 81t of third main surface 10b of epitaxial layer 81 is located at boundary 80d between first main surface 80a and first side end portion 80c of silicon carbide single crystal substrate 80. Preferably, in a cross-sectional view, outermost peripheral portion 80e of silicon carbide single crystal substrate 80 is located closer to first main surface 80a than an intermediate position between first main surface 80a and second main surface 80b. Preferably, the distance L4 in the direction parallel to the first main surface 80a from the outer peripheral end portion 81e of the fourth main surface 10a to the boundary 80d is not less than 50 μm and not more than 1000 μm. Further, the shape of the side end portion of silicon carbide substrate 10 may be asymmetrical or symmetric between the fourth main surface 10a side and the second main surface 80b side.

Next, with reference to FIG. 3, a method for manufacturing silicon carbide substrate 10 according to the first embodiment will be described. First, a silicon carbide single crystal substrate preparation step (S10: FIG. 3) is performed. Specifically, referring to FIGS. 4 and 5, for example, by slicing an ingot (not shown) made of single crystal silicon carbide having a polytype of 4H, a silicon carbide single crystal substrate having an n type conductivity type 80 is prepared. Silicon carbide single crystal substrate 80 contains an impurity such as nitrogen. The concentration of impurities such as nitrogen contained in silicon carbide single crystal substrate 80 is, for example, about 1 × 10 ¹⁸ cm ⁻³ or more and about 1 × 10 ¹⁹ cm ⁻³ or less. Silicon carbide single crystal substrate 80 connects first main surface 80a, second main surface 80b opposite to first main surface 80a, and first main surface 80a and second main surface 80b. It has a first side end portion 80c, a boundary 80d between the first side end portion 80c and the first main surface 80a, and an outermost peripheral portion 80e.

  Referring to FIG. 4, silicon carbide single crystal substrate 80 has a center 80p of first main surface 80a in plan view. When the first main surface 80a is a circle, the center 80p is the center of the circle. When the first main surface is not a circle, center 80p passes through the center of gravity of silicon carbide single crystal substrate 80 and is parallel to the normal line of first main surface 80a and the intersection of first main surface 80a. That is. The first main surface 80a may be, for example, a {0001} plane, a surface off by about 10 ° or less from the {0001} plane, or about 0.25 ° or less from the {0001} plane. It may be a surface that is turned off. Maximum value of width D of first main surface 80a of silicon carbide single crystal substrate 80 is larger than 100 mm. Preferably, the maximum value of the width D of the first main surface 80a is 150 mm or more.

  More specifically, referring to FIG. 31, first main surface 80a of silicon carbide single crystal substrate 80 may be, for example, a (0001) plane, or is off by about 10 ° or less from (0001) plane. It may be a plane that is off or about 0.25 degrees or less from the (0001) plane. The (0001) plane is also called a Si plane. When the first main surface 80a is the (0001) plane, the direction a1 perpendicular to the direction in which the orientation flat portion OF extends is the <1-100> direction, and more specifically, the [1-100] direction. It becomes. The direction a2 perpendicular to the direction in which the index flat portion IF extends is the <11-20> direction, more specifically, the [11-20] direction. Referring to FIG. 32, first main surface 80a of silicon carbide single crystal substrate 80 may be, for example, a (000-1) plane, or off by about 10 ° or less from (000-1) plane. It may be a plane that has been turned off, or may be a plane that is off about 0.25 ° or less from the (000-1) plane. The (000-1) plane is also called the C plane. When the first main surface 80a is the (000-1) plane, the direction a1 perpendicular to the direction in which the orientation flat portion OF extends is the <1-100> direction, and more specifically, [1-100]. ] Direction. The direction a4 perpendicular to the direction in which the index flat portion IF extends is the <11-20> direction, more specifically, the [11-20] direction.

  Next, a silicon carbide epitaxial layer forming step (S20: FIG. 3) is performed. Specifically, referring to FIG. 6, silicon carbide epitaxial layer 81 has first main surface 80a and first side end portion 80c of silicon carbide single crystal substrate 80 formed by, for example, a CVD (Chemical Vapor Deposition) method. It is formed in contact with. Silicon carbide epitaxial layer 81 includes third main surface 10b in contact with first main surface 80a, fourth main surface 10a opposite to third main surface 10b, third main surface 10b, and fourth main surface 10b. A second side end portion 81c that connects the main surface 10a, and an outer peripheral end portion 81e of the second side end portion 81c and the fourth main surface 10a.

  More specifically, after silicon carbide single crystal substrate 80 is first disposed in the chamber, silicon carbide single crystal substrate is heated to a temperature of, for example, 1500 ° C. or higher and 1700 ° C. or lower. Thereafter, silicon carbide source gas is introduced into the chamber. The silicon carbide source gas is a gas containing, for example, silane, propane, nitrogen, and ammonia. Thereby, the silicon carbide epitaxial in contact with first main surface 80a of silicon carbide single crystal substrate 80, first side end portion 80c, and boundary 80d between first main surface 80a and first side end portion 80c. Layer 81 is formed.

  With reference to FIG. 7A, a plurality of step portions 2 are formed in the vicinity of the side end portion 81c of the fourth main surface 10a of the epitaxial layer 81 in plan view. Stepped portion 2 is formed to extend from side end portion 81c of silicon carbide single crystal substrate 80 toward the center 80p. Typically, the stepped portion 2 is mainly formed on the orientation flat portion OF side which is the lower side of the fourth main surface 10a in the drawing and the first portion P1 side which is the left side of the fourth main surface 10a in the drawing. It is formed and hardly formed on the second portion P2 side opposite to the first portion P1. When the fourth main surface 10a is the (0001) surface, the first portion P1 is the index flat portion IF, and when the fourth main surface is the (000-1) surface, the second portion. P2 is an index flat portion IF. In any case where the fourth main surface 10a is the (0001) plane or the (000-1) plane, the stepped portion 2 is formed more on the first portion P1 side than on the second portion P2 side.

  Further, referring to FIG. 7B, the stepped portion 2 includes an orientation flat portion OF side which is the lower side of the fourth main surface 10a in the drawing, an opposite side of the orientation flat portion OF, and a fourth main surface. 10a may be formed on the first part P1 side which is the left side in the drawing and on the second part P2 side opposite to the first part P1. In this case, the average length of the stepped portion 2 formed on the second portion P2 side may be longer than the average length of the stepped portion 2 formed on the first portion P1 side. Further, the number of stepped portions 2 formed on the second portion P2 side may be smaller than the number of stepped portions 2 formed on the first portion P1 side. Furthermore, the step part 2 extending along the <1-100> direction may be formed in addition to the step part 2 extending along the <11-20> direction. As in the case of FIG. 7A, when the fourth main surface 10a is the (0001) surface, the first portion P1 is the index flat portion IF, and the fourth main surface is (000-1). In the case of a surface, the second portion P2 is the index flat portion IF.

  The detail of the level | step-difference part 2 is demonstrated with reference to FIGS. As shown in FIG. 8, when the fourth main surface 10a is a {0001} plane, the stepped portion 2 is within ± 4 in the fourth main surface 10a from the <11-20> direction from the second side end portion 81c. It is formed so as to extend along the direction in the range of 20 °. In other words, in the fourth main surface 10a, if the angle formed between the extending direction a3 of the stepped portion 2 and the direction a2 in which the orientation flat portion OF extends is an angle θ, the range of the angle θ is −20 ° or more and 20 ° or less. In addition, regarding the positive / negative of an angle, the case where the level | step-difference part 2 inclines in the <1-100> direction from the <11-20> direction can be made positive. The length of the stepped portion 2 along the direction from the first side end portion 80c of the silicon carbide single crystal substrate 80 toward the center 80p is, for example, not less than 50 μm and not more than 5000 μm. The ratio obtained by dividing the length L3 of the stepped portion 2 by the maximum value of the width of the first main surface 80a is 0.03% or more and 5% or less. A distance L2 from the outer peripheral end of second side end portion 81c of silicon carbide single crystal substrate 80 to boundary 81d is, for example, 150 μm. A distance L1 from the boundary 81d to the end of the stepped portion 2 in a direction a2 parallel to the direction in which the orientation flat portion extends is, for example, 200 μm. The distance L1 is, for example, 200 μm or more and 1000 μm or less, preferably 300 μm or more and 600 μm or less. The length L3 of the step portion 2 along the direction from the first side end portion 80c toward the center 80p is, for example, not less than 50 μm and not more than 5000 μm.

  Referring to FIG. 9, stepped portion 2 is a crack having an opening in fourth main surface 10 a of silicon carbide epitaxial layer 81, and the bottom of stepped portion 2 may be formed in silicon carbide epitaxial layer 81. . The depth H1 from the outermost surface of the fourth main surface 10a to the bottom of the step portion 2 (that is, the depth H1 in the direction perpendicular to the first main surface 80a of the step portion 2) is, for example, 1 μm or more and 50 μm or less. .

  Referring to FIGS. 8 and 10, step portion 2 is formed above silicon carbide single crystal substrate 80 at first side end portion 80 c, above first main surface 80 a and at first side end portion 80 c and first side end portion 80 c. 1 is formed above the boundary 80d with the main surface 80a. Step 3 of step flow growth is formed on fourth main surface 10a of silicon carbide epitaxial layer 81 formed on first main surface 80a. The step portion 2 may be step bunching. Step 3 of step flow growth has a typical value of about 1 nm to 10 nm, but the level difference of the stepped portion 2 is about 1 μm to 50 μm. Stepped portion 2 has a silicon carbide epitaxial layer 81 formed on the first main surface from a portion of silicon carbide epitaxial layer 81 formed on first side end portion 80c where a surface having a plurality of plane orientations is exposed. It may be formed up to this part.

  Referring to FIG. 11, a case is assumed where fourth main surface 10a of silicon carbide epitaxial layer 81 is a surface that is turned off by an angle α in the <11-20> direction from the {0001} plane. Here, it is assumed that the c1 direction is the <0001> direction and the a5 direction is the <11-20> direction. In this case, the direction a2 is a direction a2 along a straight line obtained by projecting a straight line parallel to the <11-20> direction onto the fourth main surface 10a. As shown in FIG. 8, the direction a3 in which the stepped portion 2 extends in the fourth main surface 10a is a fourth straight line obtained by projecting a straight line parallel to the <11-20> direction onto the fourth main surface 10a. This is a direction along a straight line rotated by an angle θ within a range of ± 20 ° in the main surface 10a. Here, the c2 direction is a normal direction of the fourth major surface 10a. When the angle α (off angle) is 0 °, the a2 direction is the <11-20> direction.

  Next, the epitaxial layer end removal step (S30: FIG. 3) is performed. Specifically, referring to FIG. 12, first side end portion 80c of silicon carbide single crystal substrate 80 and second side end portion 81c of silicon carbide epitaxial layer 81 are removed, for example, by polishing or the like. Thus, silicon carbide epitaxial layer 81 formed in contact with first side end portion 80c and boundary 80d is removed. Thereby, stepped portion 2 formed on fourth main surface 10a of silicon carbide epitaxial layer 81 is removed. In FIG. 12, the portion indicated by the broken line is the shape of silicon carbide substrate 10 before polishing, and the portion indicated by the solid line is the shape of silicon carbide substrate 10 after polishing. Preferably, first side end portion 80c of silicon carbide single crystal substrate 80 and second side end portion 81c of silicon carbide epitaxial layer 81 are simultaneously polished in a direction parallel to first main surface 80a. The step portion 2 is removed. Polishing amount L5 of silicon carbide single crystal substrate 80 and silicon carbide epitaxial layer 81 is, for example, about 50 μm or more and 1000 μm or less.

  The removal of the stepped portion 2 may be performed by chamfering or edge polishing, for example. The conditions for chamfering are as follows, for example. Abrasive grain type is diamond or CBN (Cubic Boron Nitride), the grain number is 400 to 2500, and the binder is either metal, electrodeposition, or resin. The end surface of the substrate is pressed against the groove portion having a desired shape, and the end portion of the substrate is chamfered by relatively rotating the substrate and the grindstone. The conditions for edge polishing are, for example, as follows. The type of abrasive grains is diamond or CBN, the count of abrasive grains is from 1000 to 10000, and the edge of the substrate is pushed against a grindstone whose binder is metal, electrodeposition, resin, or hard rubber The substrate end face is polished. The removal of the stepped portion 2 is performed before a silicon dioxide layer forming step (S40: FIG. 15) described later.

Next, functions and effects of silicon carbide substrate 10 according to the first embodiment will be described.
According to the method for manufacturing a silicon carbide substrate according to the embodiment, the first main surface 80a, the first side end portion 80c, and the boundary 80d of silicon carbide single crystal substrate 80 having a width greater than 100 mm are in contact. After silicon carbide epitaxial layer 81 is formed, silicon carbide epitaxial layer 81 formed in contact with first side end portion 80c and boundary 80d is removed. As a result, the step portion 2 formed on the first side end portion 80c and the boundary 80d is removed, so that when the silicon dioxide layer is formed on the silicon carbide substrate 10, the silicon dioxide layer It can suppress that a crack generate | occur | produces.

  According to the method for manufacturing silicon carbide substrate 10 in accordance with the first embodiment, in the step of forming the silicon carbide epitaxial layer, silicon carbide epitaxial layer 81 having stepped portion 2 on the boundary is formed. In the step of removing the silicon carbide epitaxial layer, the stepped portion 2 is removed. Thereby, when a silicon dioxide layer is formed on a silicon carbide substrate, it can control effectively that a crack occurs to a silicon dioxide layer.

  Furthermore, according to the method for manufacturing silicon carbide substrate 10 according to the first embodiment, stepped portion 2 has a first main surface obtained by projecting a straight line parallel to <11-20> direction onto first main surface 80a. It is formed so as to extend along a straight line rotated within a range of ± 20 ° within 80a. The crack of the silicon dioxide layer is particularly a straight line obtained by projecting a straight line parallel to the <11-20> direction onto the first main surface 80a and rotating within a range of ± 20 ° within the first main surface 80a. It is thought that it occurs due to the stepped portion 2 extending along. Therefore, by removing the step portion extending in the above direction, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  Furthermore, according to the method for manufacturing silicon carbide substrate 10 according to the first embodiment, length L3 of stepped portion 2 along the direction from first side end portion 80c toward center 80p is not less than 50 μm and not more than 5000 μm. It is thought that the crack of the silicon dioxide layer occurs due to a step portion having a length of 100 μm or more. Therefore, by removing the step portion 2 having the above length, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  Furthermore, according to the method for manufacturing silicon carbide substrate 10 according to the first embodiment, depth H1 of stepped portion 2 in the direction perpendicular to first main surface 80a is not less than 1 μm and not more than 50 μm. It is considered that the crack of the silicon dioxide layer is generated due to a step portion having a depth of 5 μm or more. Therefore, by removing the step portion having the above depth, it is possible to more effectively suppress the occurrence of cracks in the silicon dioxide layer.

  Furthermore, according to the method for manufacturing silicon carbide substrate 10 according to the first embodiment, thickness H2 of silicon carbide epitaxial layer 81 on center 80p of first main surface 80a is not less than 5 μm. It is considered that the stepped portion 2 that causes cracking of the silicon dioxide layer is significantly generated when the thickness of the silicon carbide epitaxial layer 81 is 5 μm or more. Therefore, when the thickness of silicon carbide epitaxial layer 81 is 5 μm or more, it is possible to more effectively suppress the generation of cracks in the silicon dioxide layer.

  According to silicon carbide substrate 10 in accordance with the first embodiment, fourth main surface 10a of silicon carbide epitaxial layer 81 in contact with center 80p of first main surface 80a of silicon carbide single crystal substrate 80 having a width greater than 100 mm. The outer peripheral end portion 81e is located on the center 80p side in the direction parallel to the first main surface 80a with respect to the boundary 80d between the first main surface 80a and the first side end portion 80c. Thereby, silicon carbide substrate 10 from which stepped portion 2 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

  According to silicon carbide substrate 10 according to the first embodiment, silicon carbide epitaxial layer 81 includes second side end portion 81c that connects third main surface 10b and fourth main surface 10a. In cross-sectional view, the second side end 81c is formed to have a curvature along the first side end 80c. Thereby, silicon carbide substrate 10 from which stepped portion 2 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

Furthermore, according to silicon carbide substrate 10 in accordance with the first embodiment, thickness H2 of silicon carbide epitaxial layer 81 on center 80p of first main surface 80a is not less than 5 μm. It is considered that the stepped portion 2 that causes cracking of the silicon dioxide layer is significantly generated when the thickness of the silicon carbide epitaxial layer 81 is 5 μm or more. Therefore, when the thickness of silicon carbide epitaxial layer 81 is 5 μm or more, it is possible to more effectively suppress the generation of cracks in the silicon dioxide layer.
(Embodiment 2)
With reference to FIGS. 13 and 14, the structure of MOSFET 1 as the silicon carbide semiconductor device according to the second embodiment will be described.

  MOSFET 1 according to the second embodiment mainly includes silicon carbide substrate 10, gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring 95, and drain electrode 98. . Silicon carbide substrate 10 is silicon carbide substrate 10 described in the first embodiment. That is, silicon carbide substrate 10 has a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer 81. Silicon carbide substrate 10 further includes a p-type base region 82, an n-type region 83, and a p-type contact region 84.

The p-type base region 82 has a p-type (second conductivity type). The p-type base region 82 is provided on the n-type drift region 85. The impurity concentration of the p-type base region 82 is, for example, 1 × 10 ¹⁸ cm ⁻³ . N-type region 83 has n-type (first conductivity type). N type region 83 is provided on p type base region 82 so as to be separated from n type drift region 85 by p type base region 82. The p-type contact region 84 has a p-type. The p-type contact region 84 is connected to the source electrode 94 and the p-type base region 82.

  Trench TR is provided in fourth main surface 10a of silicon carbide substrate 10. Trench TR has a wall surface SW and a bottom BT. Wall surface SW passes through n-type region 83 and p-type base region 82 and reaches n-type drift region 85. Wall surface SW includes the channel surface of MOSFET 1 on p-type base region 82.

  Wall surface SW is inclined with respect to fourth main surface 10a of silicon carbide substrate 10, and trench TR extends in a tapered shape toward the opening. The surface orientation of the wall surface SW is preferably inclined by 50 ° or more and 65 ° or less with respect to the (000-1) plane. Bottom BT is located on n-type drift region 85. In the present embodiment, bottom portion BT is a surface substantially parallel to fourth main surface 10a of silicon carbide substrate 10.

  Gate insulating film 91 covers each of wall surface SW and bottom portion BT of trench TR. The gate electrode 92 is provided on the gate insulating film 91. Source electrode 94 is in contact with each of n-type region 83 and p-type contact region 84. The source wiring 95 is in contact with the source electrode 94. Source wiring 95 is, for example, an aluminum layer. The interlayer insulating film 93 insulates between the gate electrode 92 and the source wiring 95. Drain electrode 98 (back electrode) is arranged in contact with silicon carbide single crystal substrate 80.

  Next, a method for manufacturing MOSFET 1 according to the second embodiment will be described with reference to FIGS.

  First, silicon carbide substrate 10 is prepared by a method similar to the method for manufacturing silicon carbide substrate 10 described in the first embodiment. Specifically, a silicon carbide single crystal substrate preparation step (S10: FIGS. 3 and 15), a silicon carbide epitaxial layer formation step (S20: FIGS. 3 and 15), and an epitaxial layer end removal step (S30: 3 and 15) are carried out.

  Next, a step of forming a p-type base region and an n-type drift region is performed. Specifically, referring to FIG. 16, specifically, in order to form p-type base region 82, the entire surface of fourth main surface 10a of n-type drift region 85 is made of, for example, aluminum (Al Impurities for imparting p-type such as) are ion-implanted. Further, in order to form n-type region 83, an impurity for imparting n-type, such as phosphorus (P), is ion-implanted into the entire surface of fourth main surface 10a. In place of ion implantation, epitaxial growth with addition of impurities may be used.

  Next, a silicon dioxide layer forming step (S40: FIG. 15) is performed. Specifically, referring to FIGS. 17 and 18, fourth main surface 10a and second side end portion 81c of silicon carbide epitaxial layer 81 and first side end portion of silicon carbide single crystal substrate 80 are referred to. A silicon dioxide layer 61 is formed in contact with 80c. Silicon dioxide layer 61 is formed by, for example, CVD. Thickness H3 of silicon dioxide layer 61 at a position facing center 80p of silicon carbide single crystal substrate 80 is not less than 0.8 μm and not more than 20 μm, for example. Preferably, the thickness H3 of the silicon dioxide layer 61 is not less than 1.0 μm and not more than 2.2 μm, for example. Next, a heat treatment for densifying the silicon dioxide layer 61 may be performed. The heat treatment for densifying the silicon dioxide layer 61 is performed by holding the silicon dioxide layer 61 in a nitrogen atmosphere at a temperature of 850 ° C. for 30 minutes. Next, a resist layer (not shown) is formed by photolithography so as to have an opening corresponding to the position where the p-type contact region 84 is to be formed on the silicon dioxide layer 61. Next, a part of the silicon dioxide layer 61 is etched to form an ion implantation mask 61 having an opening corresponding to a position where the p-type contact region 84 is to be formed. The ion implantation mask 61 is made of silicon dioxide.

  Next, an ion implantation step (S50: FIG. 15) is performed. Referring to FIG. 19, p-type contact region 84 is formed by ion implantation using ion implantation mask 61. Specifically, using the ion implantation mask 61, an impurity for imparting p-type, such as aluminum (Al), is ion-implanted into the fourth main surface 10a. Next, the ion implantation mask 61 is removed (FIG. 20). In this manner, p-type contact region 84 that connects fourth main surface 10a of silicon carbide substrate 10 and p-type base region 82 is formed by photolithography and ion implantation.

  Next, a heat treatment for activating the impurities is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.

  Referring to FIG. 21, mask layer 40 having an opening is formed on the surface formed of n-type region 83 and p-type contact region 84 by photolithography. As mask layer 40, for example, silicon dioxide can be used. The opening is formed corresponding to the position where trench TR (FIG. 13) is formed.

Next, a recess forming step (S60: FIG. 15) is performed. Specifically, referring to FIG. 22, plasma etching is performed on silicon carbide substrate 10 on which mask layer 40 is formed, so that recess TQ is formed on fourth main surface 10a of silicon carbide substrate 10. Through the opening of mask layer 40, n-type region 83, p-type base region 82, and part of n-type drift region 85 of silicon carbide substrate 10 are removed by etching to form concave portion TQ. . As an etching method, for example, dry etching is used, and more specifically, inductively coupled plasma reactive ion etching (ICP-RIE) can be used. For example, ICP-RIE is performed on fourth main surface 10a of silicon carbide substrate 10 using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas, thereby forming trench TR (FIG. 1). In the region to be formed, a recess TQ having a wall surface A and a bottom portion B substantially along the thickness direction (vertical direction in the drawing) of silicon carbide substrate 10 is formed.

  Next, a thermal etching process is performed (S70: FIG. 15). Specifically, thermal etching is performed on recess TQ formed in silicon carbide substrate 10. In the thermal etching step, the wall surface A of the recess TQ of the silicon carbide substrate 10 is thermally etched in the furnace while supplying a gas containing chlorine into the furnace. Silicon carbide substrate 10 is heated in a furnace at, for example, 1000 ° C. or more and 1800 ° C. or less for about 20 minutes, whereby wall surface A of recess TQ of silicon carbide substrate 10 is etched. Preferably, the temperature of thermal etching of silicon carbide substrate 10 is 800 ° C. or higher, more preferably 1300 ° C. or higher, and further preferably 1500 ° C. or higher. Note that the mask layer 40 made of silicon dioxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the thermal etching of silicon carbide.

  As shown in FIG. 23, by performing the above-described thermal etching step, the wall surface A and the bottom portion B of the recess TQ are etched by, for example, about 2 nm to 0.1 μm, so that the wall surface SW and the bottom portion are formed on the silicon carbide substrate 10. A trench TR formed of BT is formed. Next, the mask layer 40 is removed by an arbitrary method such as etching. Trench TR is formed by a wall surface SW which is a side surface and a bottom portion BT connected to wall surface SW. The bottom BT may be a surface or a line. When the bottom portion BT is a line, the shape of the trench TR is V-shaped when viewed in cross section.

  Next, a gate insulating film forming step (S80: FIG. 15) is performed. Specifically, referring to FIG. 24, after trench TR is formed by thermally etching wall surface A of recess TQ described above, gate insulating film 91 is formed in contact with wall surface SW of trench TR. Further, gate insulating film 91 is formed which covers each of wall surface SW and bottom portion BT of trench TR and is in contact with n-type drift region 85, p-type base region 82, n-type region 83, and p-type contact region 84. Gate insulating film 91 is made of silicon dioxide, and can be formed, for example, by thermal oxidation.

  After the formation of the gate insulating film 91, NO annealing using nitrogen monoxide (NO) gas as an atmospheric gas may be performed. Specifically, for example, silicon carbide substrate 10 on which gate insulating film 91 is formed is held at a temperature of 1100 ° C. or higher and 1300 ° C. or lower for about 1 hour in a nitrogen monoxide atmosphere.

  Next, a gate electrode formation step (S90: FIG. 15) is performed. Specifically, referring to FIG. 25, gate electrode 92 is formed on gate insulating film 91. Specifically, gate electrode 92 is formed on gate insulating film 91 so as to fill the region inside trench TR with gate insulating film 91 interposed therebetween. The gate electrode 92 can be formed by, for example, forming a conductor or doped polysilicon and CMP.

  Next, an interlayer insulating film forming step is performed. Specifically, an interlayer insulating film 93 is formed on gate electrode 92 and gate insulating film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate insulating film 91. Through this opening, each of n-type region 83 and p-type contact region 84 is exposed on fourth main surface 10a. The thickness of the interlayer insulating film 93 is, for example, 1.0 μm. The thickness of the interlayer insulating film 93 is, for example, not less than 0.8 μm and not more than 20 μm, preferably not less than 1.0 μm and not more than 2.2 μm.

  Next, a source electrode forming step (S100: FIG. 15) is performed. Source electrode 94 in contact with each of n type region 83 and p type contact region 84 is formed on fourth main surface 10a. Specifically, for example, a metal film containing Ti, Al, and Si is formed in contact with each of n-type region 83 and p-type contact region 84 by sputtering. Next, the silicon carbide substrate 10 on which the metal film is formed is annealed at about 1000 ° C., so that the metal film is alloyed and a source electrode 94 that is in ohmic contact with the silicon carbide substrate 10 is formed. Similarly, drain electrode 98 may be formed on second main surface 80 b of silicon carbide single crystal substrate 80.

  Referring again to FIG. 13, source wiring 95 is formed so as to be in contact with source electrode 94 and interlayer insulating film 93. For example, a Ti / Al layer is used as the source wiring 95. Thus, MOSFET 1 according to the second embodiment is completed.

Next, the function and effect of MOSFET 1 according to the second embodiment will be described.
According to the method for manufacturing MOSFET 1 according to the second embodiment, silicon carbide substrate 10 manufactured by the method described in the first embodiment is prepared. Silicon dioxide layers 61 and 93 arranged to face main surface 10a of silicon carbide epitaxial layer 81 are formed. Thereby, it can suppress that a crack generate | occur | produces with respect to the silicon dioxide layers 61 and 93 arrange | positioned facing the main surface 10a of the silicon carbide epitaxial layer 81. FIG.

  According to the method for manufacturing MOSFET 1 according to the second embodiment, silicon dioxide layer 61 includes ion implantation mask 61a. Thereby, it can suppress that a crack generate | occur | produces with respect to the mask 61a for ion implantation.

  Further, according to the method for manufacturing MOSFET 1 according to the second embodiment, ion implantation mask 61 a is in contact with first side end portion 80 c of silicon carbide single crystal substrate 80. Since the ion implantation mask 61a is formed in contact with the first side end portion 80c from which the step portion 2 has been removed, it is possible to suppress the occurrence of cracks in the ion implantation mask 61a.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the second embodiment, silicon dioxide layer 93 includes interlayer insulating film 93. Thereby, it is possible to suppress the occurrence of cracks in the interlayer insulating film 93.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the second embodiment, thickness H3 of silicon dioxide layers 61 and 93 is not less than 0.8 μm and not more than 20 μm. Thereby, even when the thickness H3 of the silicon dioxide layers 61 and 93 is 0.8 μm or more and 20 μm or less, it is possible to prevent the silicon dioxide layers 61 and 93 from being cracked.

  Furthermore, the method for manufacturing MOSFET 1 according to the second embodiment further includes the step of annealing silicon carbide substrate 10 and silicon dioxide layers 61 and 93 after the step of forming the silicon dioxide layer. Thereby, even when the silicon carbide substrate 10 and the silicon dioxide layers 61 and 93 are annealed, it is possible to prevent the silicon dioxide layers 61 and 93 from being cracked.

  MOSFET 1 according to the second embodiment includes silicon carbide substrate 10 described in the first embodiment and silicon dioxide layer 93 arranged to face silicon carbide epitaxial layer 81. Thereby, the crack with respect to the silicon dioxide layer 93 of MOSFET1 can be suppressed.

  Further, according to MOSFET 1 according to the second embodiment, silicon dioxide layer 93 is interlayer insulating film 93. Thereby, the crack with respect to the interlayer insulation film 93 of MOSFET can be suppressed.

Furthermore, according to MOSFET 1 according to the second embodiment, silicon dioxide layer 93 has a thickness H3 of not less than 0.8 μm and not more than 20 μm. Even when the thickness H3 of the silicon dioxide layer 93 is not less than 0.8 μm and not more than 20 μm, the generation of cracks in the silicon dioxide layer 93 can be suppressed.
(Embodiment 3)
Next, the configuration of silicon carbide substrate 10 according to the third embodiment will be described. The configuration of silicon carbide substrate 10 according to the third embodiment is the same as the configuration of silicon carbide substrate 10 according to the first embodiment except for the following points. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the same description is not repeated. That is, outer peripheral end portion 81t of third main surface 10b of silicon carbide epitaxial layer 81 of silicon carbide substrate 10 according to Embodiment 1, and first main surface 80a and first side of silicon carbide single crystal substrate 80. Boundary 80d with end 80c is substantially the same position in the direction parallel to first main surface 80a, whereas third boundary of silicon carbide epitaxial layer 81 of silicon carbide substrate 10 according to the third embodiment is the same. The outer peripheral end portion 81t of the main surface 10b is centered in a direction parallel to the first main surface 80a rather than the boundary 80d between the first main surface 80a and the first side end portion 80c of the silicon carbide single crystal substrate 80. Located on the 80p side.

  Referring to FIG. 27, silicon carbide substrate 10 according to the third embodiment mainly includes a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer 81. Silicon carbide epitaxial layer 81 includes a third main surface 10b in contact with center 80p of first main surface 80a and a fourth main surface 10a opposite to third main surface 10b. In a cross-sectional view, the outer peripheral end portion 81e of the fourth main surface 10a has a center 80p in a direction parallel to the first main surface 80a rather than the boundary 80d between the first main surface 80a and the first side end portion 80c. Located on the side. Further, the outer peripheral end portion 81t of the third main surface 10b of the silicon carbide epitaxial layer 81 is first than the boundary 80d between the first main surface 80a and the first side end portion 80c of the silicon carbide single crystal substrate 80. It is located on the center 80p side in the direction parallel to the main surface 80a. The distance L1 in the direction parallel to the first main surface 80a from the outer peripheral end portion 81e of the fourth main surface 10a to the boundary 80d is, for example, 200 μm or more and 1000 μm or less. The distance L1 is preferably 300 μm or more and 600 μm or less. Further, distance L2 in the direction parallel to first main surface 80a from outermost peripheral portion 80e of silicon carbide single crystal substrate 80 to boundary 80d is, for example, 150 μm. Preferably, silicon carbide epitaxial layer 81 is not arranged at boundary 80d and first side end portion 80c of silicon carbide single crystal substrate 80.

  Next, a method for manufacturing silicon carbide substrate 10 according to the third embodiment will be described. The method for manufacturing silicon carbide substrate 10 according to the third embodiment is the same as the method for manufacturing silicon carbide substrate 10 according to the first embodiment, except for the epitaxial layer end portion removing step (S30: FIG. 3).

  Referring to FIG. 3, the silicon carbide single crystal substrate preparation step (S10: FIG. 3) and the silicon carbide epitaxial layer formation step (S20: FIG. 3) are performed by the same method as described in the first embodiment. The

Next, the epitaxial layer end removal step (S30: FIG. 3) is performed. Specifically, referring to FIG. 27, first side end portion 80c of silicon carbide single crystal substrate 80, boundary 80d between first main surface 80a and first side end portion 80c, Silicon carbide epitaxial layer 81 formed on a part of main surface 80a of silicon carbide is removed, and silicon carbide epitaxial layer 81 in contact with center 80p of silicon carbide single crystal substrate 80 remains. Thereby, stepped portion 2 formed at the end of silicon carbide epitaxial layer 81 is removed. The width of silicon carbide epitaxial layer 81 to be removed in the direction parallel to first main surface 80a is distance L2 + distance L1. The distance L2 is, for example, 150 μm, and the distance L1 is, for example, not less than 200 μm and not more than 1000 μm. The distance L1 is preferably 300 μm or more and 600 μm or less. Removal of silicon carbide epitaxial layer 81 may be performed by dry etching or wet etching. The dry etching condition is, for example, a process using plasma that physically uses Ar, or chemically uses SF ₆ , or a combination thereof, and the wet etching condition is, for example, NaOH (sodium hydroxide), or , KOH (potassium hydroxide), or a combination thereof.

  Referring to FIG. 29, silicon carbide epitaxial layer 81 having a thickness approximately equal to the depth of stepped portion 2 is removed by the epitaxial layer end removal step (S30: FIG. 3), and a portion of silicon carbide epitaxial layer 81 is partially removed. It may be left as the remaining epitaxial portion 81f. Remaining epitaxial portion 81f is provided in contact with first side end portion 80c of silicon carbide single crystal substrate 80. Thickness H4 on boundary 80d of remaining epitaxial portion 81f is smaller than thickness H2 of silicon carbide epitaxial layer 81 on center 80p of first main surface 80a. The remaining epitaxial portion 81f is a portion remaining after the stepped portion 2 as described in the first embodiment is removed. Outer peripheral end portion 81e of fourth main surface 10a of silicon carbide epitaxial layer 81 is located closer to center 80p in the direction parallel to first main surface 80a than boundary 80d.

  Referring to FIG. 30, a part of first main surface 80 a and a part of first side end 80 c may be over-etched by the edge removal step (S 30: FIG. 3) of the epitaxial layer. A step surface 80f is formed at the end portion of the first main surface 80a by over-etching a part of the first main surface 80a and a part of the first side end portion 80c. Step surface 80f is formed by etching first main surface 80a along a surface extending from outer peripheral end portion 81e of fourth main surface 10a of silicon carbide epitaxial layer 81 to outer peripheral end portion 81t of third main surface 10b. Formed. The distance from the step surface 80f to the second main surface 80b is shorter than the distance from the first main surface 80a to the second main surface.

Next, the function and effect of MOSFET 1 according to the third embodiment will be described.
According to silicon carbide substrate 10 according to the third embodiment, outer peripheral end portion 81t of third main surface 10b is first than the boundary 80d between first main surface 80a and first side end portion 80c. It is located on the center 80p side in the direction parallel to the main surface 80a. Thereby, silicon carbide substrate 10 from which silicon carbide epitaxial layer 81 on boundary 80d has been removed can be obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked.

Further, according to silicon carbide substrate 10 according to the third embodiment, distance L1 in the direction parallel to first main surface 80a from outer peripheral end portion 81e of fourth main surface 10a to boundary 80d is 10 μm or more and 5000 μm. It is as follows. Thereby, silicon carbide substrate 10 in which stepped portion 2 on boundary 80d is effectively removed is obtained. Therefore, when a silicon dioxide layer is formed on silicon carbide substrate 10, it is possible to prevent the silicon dioxide layer from being cracked. (Embodiment 4)
Next, the structure and manufacturing method of MOSFET 1 according to the fourth embodiment will be described. In the configuration and manufacturing method of MOSFET 1 according to the fourth embodiment, MOSFET 1 according to the fourth embodiment uses silicon carbide substrate 10 according to the third embodiment, whereas MOSFET 1 according to the second embodiment is different from the first embodiment. The other point is the same as MOSFET 1 according to the second embodiment, except that silicon carbide substrate 10 is used.

  With reference to FIG. 28, a method of manufacturing MOSFET 1 according to the fourth embodiment will be described. As described above, the method for manufacturing MOSFET 1 according to the fourth embodiment uses silicon carbide substrate 10 according to the third embodiment.

  A silicon carbide single crystal substrate preparation step (S10: FIG. 3 and FIG. 15) and a silicon carbide epitaxial layer formation step (S20: FIG. 3 and FIG. 15) and the edge removal step of the epitaxial layer (S30: FIGS. 3 and 15) are performed, and silicon carbide substrate 10 shown in FIG. 27 is prepared.

  Next, a silicon dioxide layer forming step (S40: FIG. 15) is performed. Specifically, referring to FIG. 28, silicon dioxide layer 61 as an ion implantation mask includes first side end portion 80c of silicon carbide single crystal substrate 80 and part of first main surface 80a, It is formed in contact with fourth main surface 10a of silicon carbide epitaxial layer 81.

  Thereafter, the same ion implantation process (S50: FIG. 15), recess forming process (S60: FIG. 15), thermal etching process (S70: FIG. 15), gate insulating film, and the same method as described in the third embodiment. The formation step (S80: FIG. 15), the gate electrode formation step (S90: FIG. 15), and the source electrode formation step (S70: FIG. 15) are performed, and the MOSFET 1 shown in FIG. 13 is manufactured.

  In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. It does not matter. In Embodiments 2 and 4, the MOSFET is described as an example of the silicon carbide semiconductor device, but the silicon carbide semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), or the like. May be.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Silicon carbide semiconductor device (MOSFET), 2 level | step difference part, 3 step, 10 Silicon carbide substrate, 10a 4th main surface, 10b 3rd main surface, 40 mask layer, 61 silicon dioxide layer (mask for ion implantation), 80 silicon carbide single crystal substrate, 80a first main surface, 80b second main surface, 80c first side end, 80d, 81d boundary, 80e outermost periphery, 80f stepped surface, 80p center, 81 silicon carbide epitaxial Layer (n-type drift region), 81c second side end portion, 81e, 81t outer peripheral end portion, 81f remaining epitaxial portion, 82 p-type base region, 83 n-type region, 84 p-type contact region, 91 gate insulating film, 92 gate electrode, 93 interlayer insulating film, 94 source electrode, 95 source wiring, 98 drain electrode, A, SW wall surface, B, BT bottom, IF Index flat part, OF orientation flat part, TQ recess, TR trench, a1 <1-100> direction, a2, a4, a5 <11-20> direction, a3 extension direction.

Claims (20)

A first main surface, a second main surface opposite to the first main surface, and a first side end connecting the first main surface and the second main surface; And preparing a silicon carbide single crystal substrate having a maximum width of the first main surface of 150 mm or more;
Forming a silicon carbide epitaxial layer in contact with the first side end, the first main surface, and the boundary between the first main surface and the first side end;
And a step of removing the silicon carbide epitaxial layer formed in contact with the first side end and the boundary. In the step of forming the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a stepped portion on the boundary is formed,
The method for manufacturing a silicon carbide substrate according to claim 1, wherein the stepped portion is removed in the step of removing the silicon carbide epitaxial layer.   The step portion extends along a straight line obtained by projecting a straight line parallel to the <11-20> direction onto the first main surface within a range of ± 20 ° within the first main surface. The method for manufacturing a silicon carbide substrate according to claim 2, formed as described above.   4. The method for manufacturing a silicon carbide substrate according to claim 2, wherein a length of the step portion along a direction from the first side end portion toward the center is not less than 50 μm and not more than 5000 μm.   The depth of the said level | step-difference part of a direction perpendicular | vertical to a said 1st main surface is a manufacturing method of the silicon carbide substrate of any one of Claims 2-4 which are 1 micrometer or more and 50 micrometers or less.   The method for manufacturing a silicon carbide substrate according to claim 1, wherein the thickness of the silicon carbide epitaxial layer on the center of the first main surface is 5 μm or more. Preparing a silicon carbide substrate manufactured by the method according to claim 1;
And a step of forming a silicon dioxide layer disposed to face the main surface of the silicon carbide epitaxial layer.   The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the silicon dioxide layer includes an ion implantation mask.   The method of manufacturing a silicon carbide semiconductor device according to claim 8, wherein the ion implantation mask is in contact with the first side end portion of the silicon carbide single crystal substrate.   The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the silicon dioxide layer includes an interlayer insulating film.   The thickness of the said silicon dioxide layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 7-10 which are 0.8 micrometer or more and 20 micrometers or less.   The method for manufacturing a silicon carbide semiconductor device according to claim 7, further comprising a step of annealing the silicon carbide substrate and the silicon dioxide layer after the step of forming the silicon dioxide layer. A first main surface, a second main surface opposite to the first main surface, and a first side end connecting the first main surface and the second main surface; And the silicon carbide single crystal substrate whose maximum value of the width of the 1st principal surface is 150 mm or more,
A silicon carbide epitaxial layer in contact with the center of the first main surface,
The silicon carbide epitaxial layer includes a third main surface in contact with the center of the first main surface, and a fourth main surface opposite to the third main surface,
An outer peripheral end portion of the fourth main surface is located on the center side in a direction parallel to the first main surface with respect to a boundary between the first main surface and the first side end portion. Silicon substrate.   The outer peripheral end portion of the third main surface is located on the center side in a direction parallel to the first main surface with respect to a boundary between the first main surface and the first side end portion. Item 14. A silicon carbide substrate according to Item 13. The silicon carbide epitaxial layer includes a second side end portion connecting the third main surface and the fourth main surface,
The silicon carbide substrate according to claim 13, wherein the second side end portion is formed to have a curvature along the first side end portion in a cross-sectional view.   The distance of the direction parallel to the said 1st main surface from the outer peripheral edge part of the said 4th main surface to the said boundary is 10 micrometers or more and 5000 micrometers or less, The any one of Claims 13-15 Silicon carbide substrate.   17. The silicon carbide substrate according to claim 13, wherein a thickness of the silicon carbide epitaxial layer on the center of the first main surface is 5 μm or more. A silicon carbide substrate according to any one of claims 13 to 17,
A silicon carbide semiconductor device comprising: a silicon dioxide layer disposed to face the silicon carbide epitaxial layer.   The silicon carbide semiconductor device according to claim 18, wherein the silicon dioxide layer is an interlayer insulating film.   20. The silicon carbide semiconductor device according to claim 18, wherein a thickness of said silicon dioxide layer is not less than 0.8 μm and not more than 20 μm.

Images