JP2016024371A - Printed wiring board and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain thinner wiring lines in a printed wiring board.SOLUTION: A method for manufacturing a printed wiring board is provided, which includes steps of: forming an insulating layer made of an insulating material; forming a seed layer on the insulating layer; forming a first resist pattern composed of a plurality of conductor wiring patterns arranged at a narrow pitch on the seed layer; forming a second resist pattern composed of a plurality of conductor wiring patterns arranged at a narrow pitch on the seed layer; and forming wiring lines by selectively subjecting the seed layer exposed through the first and second resist patterns to electroplating with a wiring material. In the step of forming the second resist pattern, the second resist pattern is formed by applying a resist material while the first resist pattern remains and shifting a position of forming the pattern along the arrangement direction of the first resist pattern from the position where the first resist pattern is formed.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly to a technique for forming a fine wiring structure on a printed board.

  As a multilayer printed wiring board for mounting IC chips (semiconductor elements) etc., interlayer insulation layers and conductor layers are alternately stacked on a resinous core substrate with through-hole conductors, and the conductor layers are connected by via conductors. A printed wiring board is known.

  With recent miniaturization and higher integration of IC chips, for example, the number of conductor pads formed on the uppermost layer of a printed wiring board has increased, and the pitch of conductor pads has been reduced due to the increase in the number of conductor pads. . Along with the narrowing of the pad pitch, the wiring pitch of the printed wiring board is also rapidly thinned (see, for example, Patent Document 1).

  Further, in Patent Document 2, a multilayer wiring board having a sub wiring board on which a wiring pattern is formed at a high density on an insulating resin layer using glass or the like as a support plate and a main wiring board to which the sub wiring board is attached is disclosed. It is disclosed. In this multilayer wiring board, a sub wiring board capable of forming high-density wiring is provided in a portion where two types of IC chips (MPU and DRAM) are connected and a portion where the electrodes of these IC chips are connected. It has been. By adopting such a structure, it is possible to cope with a narrow pitch of mounting pads and wiring patterns.

International Publication No. 2007/129545 JP 2013-214578 A

By the way, considering the relationship between the resolution of the pattern and the depth of focus in a general exposure machine, if the resolution is increased, for example, if the pattern L / S (line and space) is made finer, the depth of focus tends to decrease. . An exposure machine with high resolution is expensive.
Therefore, in an IC chip manufacturing process that requires higher resolution, an exposure machine having a higher resolution is used, and in a printed circuit board manufacturing process that requires a larger depth of focus, an inexpensive and relatively lower resolution exposure machine is used. It is common to use.

However, for example, in the mounting structure 100 as shown in FIGS. 11A and 11B, the two IC chips (CPU 103, memory 105, etc.) arranged adjacent to each other have a high density on the printed circuit board 101. In the case of wiring (reference numeral 107), there are an increasing number of cases that require higher resolution than conventional printed circuit boards. When using an exposure apparatus for IC, there are problems that the depth of focus is small and the cost is high.
An object of the present invention is to provide a technique that enables miniaturization of wiring on a printed wiring board even by using an exposure machine having a relatively low resolution.

  In order to achieve the above object, the invention according to claim 1 includes a step of forming an insulating layer made of an insulating material, a step of forming a seed layer on the insulating layer, and a narrow pitch on the seed layer. Forming a first resist pattern comprising a plurality of conductor wiring patterns arranged in a step, and forming a second resist pattern comprising a plurality of conductor wiring patterns arranged at a narrow pitch on the seed layer. And forming a wiring by selectively electroplating a wiring material on the seed layer exposed from the first and second resist patterns, the method for manufacturing a printed wiring board, In the step of forming the resist pattern 2, a resist material is applied in a state where the first resist pattern is left, and the pattern formation position is changed to the first resist pattern. A second resist pattern is formed by shifting in the arrangement direction of the first resist pattern from the formed position.

  According to the present invention, fine wiring on a printed wiring board can be achieved even with an exposure machine having a relatively low resolution.

The process flow figure showing an example of the manufacturing method of the printed wiring board concerning one embodiment of the present invention Sectional view showing details of fine wiring formation process Sectional view showing details of fine wiring formation process The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view The figure which shows the relationship between sectional drawing in the principal part of the formation process of fine wiring, and a top view It is sectional drawing which shows the mounting example of the printed wiring board using a fine wiring structure, (a) is a built-in type, (b) is a figure which shows a bonding type

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
In this specification, a printed circuit board refers to, for example, a plate-like or film-like component that constitutes an electronic circuit by fixing a large number of electronic components on the surface and connecting the components by wiring. Mainly, a circuit (pattern) wiring is constituted by a conductor such as a copper foil on a substrate impregnated with a resin having an insulating property with respect to a base material. A printed circuit board is also called a printed circuit, a printed wiring, a printed circuit board, a printed wiring board, or the like, but is not interpreted in a narrow sense. Moreover, as a manufacturing method thereof, a coreless method or a method with a core can be used, but it goes without saying that any of these methods can be applied.

  The semi-additive method is, for example, using an insulating substrate coated with an adhesive without copper foil, drilling, depositing electroless copper plating on the entire surface (seed layer formation), forming a circuit pattern with a plating resist, and conducting This is a method of performing electrolytic copper plating as a circuit and etching away unnecessary portions of electroless plating, and is made by the same process as the subtractive pattern plating method. Since electrolytic copper plating is used, there is an advantage that a normal plating resist can be used.

Hereinafter, a printed wiring board and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a process flow diagram showing an example of a method of manufacturing a printed wiring board according to the first embodiment of the present invention. As an example, a wiring structure of a printed board (hereinafter referred to as “printed wiring board”) by a coreless method is shown. It is a figure which shows the example which produces. 2 and 3 are cross-sectional views showing details of the fine wiring formation process. 4 to 10 are diagrams showing the relationship between a cross-sectional view (essential part of FIGS. 2 and 3) and a plan view in the essential part of the fine wiring forming process.
In the following, a case of manufacturing a fine wiring structure as shown in FIG. 11 will be described as an example, but the fine wiring forming technique according to the present embodiment is not limited to such a structure. The resist forming process can be applied to methods other than the semi-additive method. For example, taking the printed wiring board method as an example, it can be applied to a subtractive method, a full additive method, and the like. Below, the example of a process using a semi-additive method is shown.

In the process example shown in FIG. 1, first, in a structure in which, for example, a copper foil 5 (with a thickness of 3 μm to 5 μm) with a carrier 3 made of a Cu foil having a thickness of about 18 μm is formed on both surfaces of a base material 1 such as a prebaked material ( As shown in FIG. 1A, FIG. 1B, and FIG. 4, a conductor pattern 7 is formed on the copper foil 5. 4 to 10, the copper foil 5 and the like on the back side are omitted. The conductor pattern 7 is a pattern having a large size that can be sufficiently resolved by an exposure machine having a resolution for manufacturing a printed circuit board, for example.
Next, as shown in FIG. 1 (c), the surface is covered with an insulating layer 11, and then, as shown in FIGS. 1 (d) and 5, a predetermined region of the insulating layer 11 is opened to form a conductor pattern 7 A via (contact hole) 15 is formed by exposing the surface of. The insulating layer 11 is made of, for example, an insulating resin layer containing an inorganic filler (SiO ₂ ) or an insulating resin layer having photosensitive characteristics. Examples of the main material mainly include epoxy, polyimide, and phenol resin materials, but these are merely examples and are not limited. The filler material is not limited to an inorganic material and may be an organic material. The inclusion may be in a fiber state such as glass cloth. Moreover, the inclusion does not necessarily have to be contained. The insulating layer may be a film or varnish.

Next, fine wiring is formed. Details of the fine wiring forming process will be described later. At this stage, for example, a via 15 penetrating the insulating layer 11 is formed outside the fine wiring structure, and a conductive pad made of a conductive material connected to a board mounting component or the like such as copper is also formed. (FIG. 1 (f)).
Next, as shown in FIG. 1 (g), the lower structure is separated from the carrier 3 by a peeling process to obtain a printed wiring board 21 having a fine wiring structure 17 as shown in FIG. 1 (h). it can.
In the above, the coreless construction method has been described as an example, but a construction method with a core may be used. The cored construction method is, for example, a cored construction method as shown in FIGS. 7A to 7I disclosed in Japanese Patent Application Laid-Open No. 2013-214578. The printed wiring board 21 may be a printed wiring board 21 having a fine wiring structure 17 as shown in FIG.

Details of the fine wiring forming process will be described below.
First, after the steps of FIGS. 2C and 2D corresponding to FIGS. 1C and 1D, the structure shown in FIG. 2D is formed as shown in FIG. 2E-1. For example, the seed layer 31 of electroless copper plating is formed. The seed layer 31 may be a Ti / Cu layer formed by sputtering. The thickness of the seed layer 31 is preferably about 50 to 150 nm, for example. In addition, in order to ensure adhesiveness with the resist layer apply | coated to the following process, you may perform a roughening process process to the said seed layer.
Next, as shown in FIG. 2E-2, for example, an i-line negative dry film (for example, acrylic) having a thickness of about 7 μm is used to form the first resist pattern on the seed layer 31. The first resist layer 33 is formed by coating or laminating. A negative dry film having high chemical resistance has a thickness of about 7 to 10 μm and is not heated after coating or laminating.

Next, the first resist layer 33 is exposed to form a first resist pattern region with a predetermined exposure amount using an i-line projection exposure apparatus. By performing development using a developer after the exposure, a first resist pattern 33a for fine wiring is formed as shown in FIG. 2 (e-3).
In order to cure the first resist pattern 33a and promote cross-linking, for example, heating is performed at 110 ° C. (in the range of about 100 to 120 ° C.) for about 3 minutes to dry. Thereby, the cured first resist pattern 33b can then be formed as shown in FIGS. 2 (e-4) and 6. In this step, heating at a temperature equal to or higher than the heat treatment in the second resist pattern forming step and a long time is preferable. Due to the curing, deformation of the first resist pattern 33b or the like hardly occurs in the subsequent processes.

For example, the first resist pattern 33b has a pattern width of 2 μm and a space between patterns of 6 μm. 2 μm is a dimension that depends on the performance of the exposure machine to be used, and is generally a dimension close to the resolution limit of the exposure machine that is used for miniaturizing the wiring.
Similar wiring patterns are formed at intervals of 6 μm, for example, in a direction intersecting the direction in which the first resist pattern 33b extends. Here, three first resist patterns 33b for wiring are exemplarily shown.

Next, as shown in FIG. 3 (e-5), in order to form a second resist pattern, for example, a second resist layer 35 using a liquid (varnish state) i-line negative resist is formed to a thickness of 5 μm. It is applied with a thickness to cover the entire region including the first resist pattern 33b. Then, for example, heat treatment is performed at 110 ° C. for 3 minutes. The heating temperature is about 100 to 120 ° C., and the thickness of the second resist layer 35 is about 5 to 7 μm. Using the i-line projection exposure apparatus, the region of the second resist pattern is exposed with a predetermined exposure amount smaller than that at the time of forming the first resist pattern. Similar to the first resist pattern region, the second resist pattern region has, for example, a width of about 2 μm and a space of about 6 μm, but the second resist pattern 35a is between the spaces of the first resist pattern. The exposure (i-ray irradiation) position is shifted so that is formed.
As the second resist pattern, the same pattern as the first resist pattern may be shifted and used, or a pattern different from the first resist pattern may be used.
It is preferable to use the same resist material for the first resist pattern 33b and the second resist pattern 35a. One of the reasons is to make the content of the pretreatment process and the resist stripping property in the electrolytic copper plating process described later the same. That is, by using the same resist material, the reactivity of the resist is made the same.

  The advantage of using a negative resist as the resist material for the first resist pattern is that a film material having high chemical resistance can be used in the first resist pattern. One advantage of using a negative resist as the resist material for the second resist pattern is that it is desired to expose a region where the first resist pattern does not exist as a region for forming the second resist pattern. That is, when a positive resist is used instead of a negative resist, the first resist pattern exists in the exposure region when the second resist pattern is formed, and the second resist is affected by the first resist pattern. This is because light during exposure when forming a pattern does not uniformly strike the resist, making it difficult to form a pattern with high accuracy.

After the exposure, the second resist pattern 35a is formed by performing development using a developer. Heat treatment after development is not performed.
At the same time, since the second resist layer 35 on the first resist pattern 33b is also removed, as shown in FIGS. 3E-6 and 7, in the direction in which the wiring patterns arranged at a narrow pitch are arranged. Alternatingly arranged first and second resist patterns 33b and 35a are formed. In the present embodiment, the opening 37 for exposing the conductor pattern 7 through the via 15 is also formed together with the second resist pattern 35b for opening. Here, the pattern is about L / S = 2 μm / 2 μm.

If a negative resist is used as the resist material, the region exposed to light in the exposure process is cross-linked, so that there is an advantage that freezing (cross-linking) dedicated to the first resist pattern is not necessarily required. In the above example, a heating step is included as freezing. However, in practice, the heating step has a strong meaning of improving adhesion because of drying after development, and the actual crosslinking is mainly caused by the exposure step. It is estimated that.
Next, as shown in FIGS. 3 (e-7) and 8, the exposed seed layer using the first resist pattern 33b, the second resist pattern 35a, and the second resist pattern 35b for opening as a mask. For example, electrolytic copper plating layers (wiring layers) 41a and 41b having a thickness of, for example, about 3 μm are selectively formed on 31 by electrolytic plating. At this time, in order to improve the surroundings of the plating solution, it is preferable to perform jet dip, rocking or the like. At this time, the conductor pad 41c may be formed.
Next, as shown in FIGS. 3 (e-8) and 9, the first resist pattern 33b, the second resist pattern 35a, and the second resist pattern 35b for opening are removed with, for example, a mixed solution of an organic amine and a solvent. To do. Then, the wiring layers 41a and 41b can be arranged at a narrow pitch in a direction intersecting with the direction in which the wiring pattern extends.

Next, as shown in FIGS. 3E-9 and 10, the seed layer 31a is isotropically etched away with, for example, a copper etchant based on sulfuric acid / peroxide water. Etching solution when the seed metal is Cu is sulfuric acid / hydrogen peroxide solution or phosphoric acid / hydrogen peroxide solution, and etching solution when the seed metal is Ti is hydrogen peroxide solution, hydrofluoric acid, etc. It is. Since isotropic etching is performed, the widths of the wiring layers 41a and 41b are also narrowed at this time.
Through the above steps, the fine wiring pattern, the first wiring 41a-1 and the second wiring having a line and space (L / S) exceeding the limit of one exposure in the exposure machine, for example, 2 μm / 2 μm. The wiring 41b-1 can be formed. That is, a fine pattern exceeding the resolution limit of the exposure device can be formed.

The structure shown in FIG. 10 includes an insulating layer 11 and a first wiring 41 a-1 and a second wiring 41 b-1 that are provided on the insulating layer 11 and are each composed of a first conductive pattern and a second conductive pattern. It is a printed wiring board.
The size (width W1, W2, height L1, L2, space L11, L12) of the first wiring 41a-1 and the second wiring 41b-1 provided alternately among the plurality of wirings 41a-1, 41b-1. ) Are slightly different from each other over process variations such as dimensions in a process performed in one process of the first wiring 41a-1 and the second wiring 41b-1. The dimensional variation due to the process, for example, results in a dimensional variation of about 10% even in a single formation process. In the two forming steps, it is estimated that a dimensional variation of about 14 to 15% is generated when estimated by the square sum of squares. Therefore, if L / S = 2 μm / 2 μm, there is a variation of about 0.2 μm of 10% even in one process. Therefore, if dimensional variations of 0.2 μm or more are alternately generated, it can be estimated that the method according to the embodiment is used.

The position P3 of the conductor pad 41c-1 formed simultaneously in the same exposure process and the position P1 of the second wiring 41b-1, for example, are lined up almost according to the design dimension in the arrangement direction, and the conductor pad 41c formed in a different exposure process. The position P3 of -1 and the position P2 of the first wiring 41a-1 are not aligned according to the design dimensions.
For the same reason, the positions at which the first wiring 41a-1 and the second wiring 41b-1 provided alternately among the plurality of wiring layers are formed, the interval between the wirings, the width of the wiring layer, the thickness of the wiring layer However, it is possible to recognize that it is manufactured in the manufacturing process according to the present embodiment because it is slightly different from the variation of the process. However, the difference in dimensions is such that there is no problem in practical use.
In the above description, the wirings are alternately arranged. However, for example, two second wirings may be formed between the two first wirings, and the deformation may be performed while maintaining regularity.

By using the above technique, it becomes possible to form a wiring pattern with a narrow pitch exceeding the critical dimension of the resolution of the exposure machine on the printed wiring board by a process similar to the conventional one.
Further, a pattern larger than the limit dimension of the resolution of the exposure apparatus can be formed together. For example, between two IC chips arranged adjacent to each other as shown in FIGS. In the case of wiring on a printed circuit board, it is possible to cope with a case where a wiring layer having a narrower pitch than that of a conventional printed circuit board is formed. In the built-in type in which the wiring 107 in FIG. 11A is built in the printed circuit board 101, the wiring 107 and the IC chips 103 and 105 are connected by solder bumps 109 or the like. In the pasting type in which the wiring 107 in FIG. 11B is pasted on the printed circuit board 101, the wiring 107 is pasted on the printed circuit board 101. Therefore, the solder bump 109a on the printed circuit board 101 and the solder bump 109b on the wiring 107 are The height is adjusted with different heights.
By using the wiring formation technique of the present embodiment, it is only necessary to have the resolution of an exposure machine similar to that of a general printed circuit board exposure machine, so that the cost of the exposure machine can be suppressed.

Each component of the present invention can be arbitrarily selected, and an invention having a selected configuration is also included in the present invention.
(1) Although the resist material is a negative resist in the above embodiment, a positive resist may be used.
(2) In the above embodiment, the wiring pattern has a straight shape, but various patterns can be used depending on the purpose.
(3) In the above embodiment, the second wiring and the conductor pad are formed by a process using the same resist pattern. However, the first wiring and the conductor pad may be formed by a process using the same resist pattern. The pad may be formed by an independent process.
(4) In the above embodiment, the resist pattern is a line and space pattern, but it can be applied to various fine structures.

  The present invention is applicable to a printed wiring board.

1 Base material (substrate)
3 Carrier 5 Copper foil 7 Conductor pattern 11 Insulating layer 15 Via (contact hole)
17 Wiring structure 21 Wiring substrate 31, 31a Seed layer 33 First resist layer 33a First resist pattern 33b Cured first resist pattern 35 Second resist layer 35a Second resist pattern 35b Opening second Resist pattern 41a / 41b Wiring layer 41c Conductor pad 41a-1 First wiring 41b-1 Second wiring 41c-1 Conductor pad

Claims (20)

Forming an insulating layer made of an insulating material;
Forming a seed layer on the insulating layer;
Forming a first resist pattern comprising a plurality of conductor wiring patterns arranged at a narrow pitch on the seed layer;
Forming a second resist pattern comprising a plurality of conductor wiring patterns arranged at a narrow pitch on the seed layer;
Forming a wiring by selectively electroplating a wiring material on the seed layer exposed from the first and second resist patterns, the printed wiring board manufacturing method comprising:
In the step of forming the second resist pattern, a resist material is applied in a state where the first resist pattern is left, and a pattern formation position is changed from the position where the first resist pattern is formed to the first resist pattern. The second resist pattern is formed by shifting in the arrangement direction. In the manufacturing method of the printed wiring board according to claim 1,
The step of forming the first resist pattern includes:
Applying or laminating a first resist material for forming the first resist pattern on the seed layer;
Selectively exposing either the region of the first resist pattern or the other region;
Leaving a first resist material in the region of the first resist pattern using a developer. In the manufacturing method of the printed wiring board according to claim 2,
The step of forming the first resist pattern includes:
A step of curing the first resist pattern during or immediately after the exposure; In the manufacturing method of the printed wiring board according to claim 3,
The step of curing the first resist pattern includes:
It is a step of promoting curing by heating the first resist pattern. In the manufacturing method of the printed wiring board according to claim 2,
The step of forming the first resist pattern includes:
Forming a negative resist;
Cross-linking the negative resist by selectively exposing a region of the first resist pattern during exposure. In the manufacturing method of the printed wiring board according to claim 2,
The step of forming the second resist pattern includes:
Applying a negative resist material for forming the second resist pattern to the entire surface including the first resist pattern;
Selectively exposing a region of the second resist pattern avoiding the first resist pattern by the shift;
And developing the second resist pattern to form the second resist pattern and exposing the first resist pattern. In the manufacturing method of the printed wiring board according to claim 1,
The step of forming the second resist pattern includes:
The second resist pattern is formed between the pitches of the first resist patterns arranged at a narrow pitch by the shift so that the first resist pattern and the second resist pattern are alternately positioned. . In the manufacturing method of the printed wiring board according to claim 7,
The pitch of the first resist pattern and the second resist pattern is set to the minimum pitch depending on the resolution of the resist exposure machine. In the manufacturing method of the printed wiring board according to claim 1,
The same resist material is used as the resist material for the first and second resist patterns. In the manufacturing method of the printed wiring board according to claim 1,
In the step of forming the second resist pattern, an opening pattern for forming a conductor pad is formed,
In the step of electrolytic plating a wiring material on the seed layer, a conductor pad is formed in the opening pattern. In the manufacturing method of the printed wiring board according to claim 10,
The wiring and the conductor pad are formed in the same process. In the manufacturing method of the printed wiring board according to claim 1,
Further, the method includes a step of forming an opening in the insulating layer for forming an outermost conductive circuit layer including a connection pad for a substrate mounting component,
In the step of electrolytic plating a wiring material on the seed layer, the outermost conductive circuit layer is formed. In the manufacturing method of the printed wiring board according to claim 12,
In the step of forming the second resist pattern, an opening pattern for forming the outermost conductive circuit layer is also formed. A printed wiring board comprising an insulating layer made of an insulating material, and a plurality of wirings formed on the insulating layer,
The first wiring and the second wiring are alternately arranged in the arrangement direction of the plurality of wirings arranged in a narrow pitch with the width of the plurality of wirings,
The first wiring and the second wiring have different widths. The printed wiring board according to claim 14,
An interval between the first wiring and the second wiring is alternately different in the arrangement direction of the plurality of wirings. An insulating layer made of an insulating material;
A plurality of conductor pads formed on the insulating layer and connected to the board mounting component;
A conductor wiring pattern having a first conductor pattern and a second conductor pattern formed on the insulating layer between the conductor pads;
A printed wiring board comprising:
The first conductor pattern has a plurality of first wires, the second conductor pattern has a plurality of second wires,
The first wiring and the second wiring are alternately arranged on the insulating layer,
The first wiring and the second wiring have different widths. The printed wiring board according to claim 16, wherein
The positions of the end portions in the arrangement direction of the conductor pads and the second wiring are arranged at equal intervals, and the positions of the end portions in the arrangement direction of the first pads are arranged at equal intervals. Absent. The printed wiring board according to claim 17,
The size of the opening diameter of the conductor pad is at least twice the width of the first wiring and the second wiring. In the printed wiring board according to any one of claims 16 to 18,
The first wiring, the second wiring, and the conductor pad are formed in the same process. A mounting structure for a semiconductor device comprising the printed wiring board according to any one of claims 16 to 19 and first and second semiconductor chips,
On the insulating layer, the first and second semiconductor chips are arranged close to each other,
The first semiconductor chip and the second semiconductor chip are electrically connected via the first wiring and the second wiring.

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