JP2016018947A - Lead frame for semiconductor device and resin-encapsulated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable resin-sealed semiconductor device capable of supporting reduced thickness and increased pins, and a lead frame for a semiconductor device with which the resin-sealed semiconductor device can be achieved.SOLUTION: A lead frame 11 for a semiconductor device includes: a plurality of leads 13 each having external terminals 14 and 15 projecting from a front surface 13a and a rear surface 13b, respectively; and a connection bar 17 supporting the plurality of leads 13. An internal terminal face 16 connected to a semiconductor element is positioned on the front surface or the rear surface of each lead 13, and the positions where the external terminals 14 and 15 exist in a longitudinal direction of the lead 13 are different from each other between adjacent leads.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a resin-encapsulated semiconductor device and a lead frame for a semiconductor device used therefor.

In recent years, semiconductor devices have become increasingly highly integrated, as represented by LSI ASIC (Application Specific Integrated Circuit), due to the progress of high integration and miniaturization technologies, and the trend toward higher performance and lighter and shorter electronic devices. Are becoming more advanced and more functional. In such highly integrated and highly functional semiconductor devices, it is required to increase the total sum of external terminals (pins) and further increase the number of terminals (pins).
For example, a resin-encapsulated semiconductor device has been developed as a package structure that enables high integration and miniaturization in a semiconductor device. Of the resin-encapsulated semiconductor devices, those with four-way terminals have been developed from QFJ (Quad Flat J-leaded) to TQFP (Thin Quad Flat Package), and the leads are made of resin to further reduce the mounting area. Instead of the terminals extending in the lateral direction from the side surface of the sealing body, a surface mount type package such as a QFN (Quad Flat Non-leaded package) in which the terminals are exposed on the lower surface of the resin sealing body has been developed. Furthermore, as QFN has multiple terminals (pins), multiple leads can be placed around the die pad by arranging leads with different lengths alternately (two rows in a staggered pattern), and a wire loop A DR-QFN (Dual Raw Quad Flat Non-leaded package) that connects by changing the height has been developed (Patent Document 1).

JP 2006-19767 A

In the DR-QFN, for example, it is possible to have a package size of 12 mm square and the number of terminals of about 140 pins, and it has been used for resin-encapsulated semiconductor devices for LSI. However, in recent years, LSIs have become more multifunctional, and a resin-encapsulated semiconductor device having more terminals has been demanded.
In addition, in the resin-encapsulated semiconductor device, the increase in the number of terminals on the plane side is based on the premise that a signal is sent to an IC mounted in the plane direction of the substrate, but in recent years external terminals have been provided on the front and back surfaces. By stacking semiconductor devices in the thickness direction, it has become possible to function a plurality of ICs with signals transmitted at a time. If PoP (Package on Package) laminated in the thickness direction is made thinner and multi-pin, it is expected to expand its use as a general-purpose semiconductor package.
The present invention has been made in view of the above-described circumstances, and is a resin-encapsulated semiconductor device that can cope with the reduction in thickness and the number of pins and has high reliability, and such a resin-encapsulated semiconductor. An object of the present invention is to provide a lead frame for a semiconductor device that enables the device.

  In order to achieve such an object, a lead frame for a semiconductor device of the present invention includes a lead having external terminals protruding from the front surface and the back surface, and a connection bar that supports the plurality of leads, and a semiconductor element The internal terminal surface connected to the lead is located on the front surface or the back surface of the lead, and the position where the external terminal exists in the longitudinal direction of the lead is different between adjacent leads.

As another aspect of the present invention, the external terminal projecting from the front surface of the lead and the external terminal projecting from the back surface are present at the same position in the longitudinal direction of the lead, and the internal terminal surface is more of the lead than the external terminal. The configuration is located near the tip.
As another aspect of the present invention, the external terminal protruding from the front surface of the lead and the external terminal protruding from the back surface exist at different positions in the longitudinal direction of the lead, and the lead surface where the internal terminal surface is located, The internal terminal surface was positioned closer to the tip of the lead than the external terminal.
As another aspect of the present invention, the lead thickness defined by the distance between the surface including the terminal surface of the external terminal protruding from the surface of the lead and the surface including the terminal surface of the external terminal protruding from the back surface of the lead. T is in the range of 0.10 to 0.25 mm, and the lead thickness t in the region where no external terminal is present is in the range of 50 to 75% of the thickness T.
As another aspect of the present invention, the material constituting the lead frame for a semiconductor device has a tensile strength of 725 MPa or more.

  The resin-encapsulated semiconductor device of the present invention includes a semiconductor element, a plurality of leads located around the semiconductor element, a connection member that connects an internal terminal surface of the lead and the semiconductor element, the semiconductor element, The lead and a resin member for sealing the connecting member, the lead having external terminals protruding from the front surface and the back surface, the internal terminal surface being located on the front surface or the back surface of the lead, The positions where the external terminals are present in the longitudinal direction differ between adjacent leads, and the terminal surfaces of the external terminals are exposed from the resin member.

As another aspect of the present invention, an external terminal projecting from the front surface of the lead and an external terminal projecting from the back surface are present at the same position in the longitudinal direction of the lead, and the internal terminal surface is closer to the semiconductor than the external terminal. The configuration is such that it is located closer to the element.
As another aspect of the present invention, the external terminal protruding from the front surface of the lead and the external terminal protruding from the back surface exist at different positions in the longitudinal direction of the lead, and the lead surface where the internal terminal surface is located, The internal terminal surface is positioned closer to the semiconductor element than the external terminal.
As another aspect of the present invention, the lead thickness defined by the distance between the surface including the terminal surface of the external terminal protruding from the surface of the lead and the surface including the terminal surface of the external terminal protruding from the back surface of the lead. T is in the range of 0.10 to 0.25 mm, and the lead thickness t in the region where no external terminal is present is in the range of 50 to 75% of the thickness T.

The lead frame for a semiconductor device of the present invention can produce a resin-encapsulated semiconductor device having external terminals on the front and back surfaces, and can make the resin-encapsulated semiconductor device thinner and more pins.
The resin-encapsulated semiconductor device of the present invention can be made thinner and more pins in a PoP (Package on Package).

FIG. 1 is a plan view showing an embodiment of a lead frame for a semiconductor device according to the present invention. FIG. 2 is a partial cross-sectional view taken along line II of the lead frame for a semiconductor device shown in FIG. 3 is a partial cross-sectional view taken along line II-II of the lead frame for a semiconductor device shown in FIG. FIG. 4 is a partial perspective view for explaining leads of the lead frame for a semiconductor device shown in FIG. FIG. 5 is a plan view showing another embodiment of the lead frame for a semiconductor device of the present invention. 6 is a partial cross-sectional view taken along line III-III of the lead frame for a semiconductor device shown in FIG. 7 is a partial cross-sectional view taken along line IV-IV of the lead frame for a semiconductor device shown in FIG. FIG. 8 is a partial perspective view for explaining the leads of the lead frame for a semiconductor device shown in FIG. FIG. 9 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention. FIG. 10 is a plan view showing one surface of one embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 11 is a plan view showing the other surface of one embodiment of the resin-encapsulated semiconductor device of the present invention. 12 is a schematic cross-sectional view taken along line VV of the resin-encapsulated semiconductor device shown in FIGS. FIG. 13 is a schematic cross-sectional view taken along line VI-VI of the resin-encapsulated semiconductor device shown in FIGS. 10 and 11. FIG. 14 is a schematic cross-sectional view showing a state in which two resin-encapsulated semiconductor devices are stacked in the thickness direction, and FIG. 14A shows a V of the resin-encapsulated semiconductor device shown in FIGS. FIG. 14B corresponds to the schematic cross-sectional view taken along the line VI-VI of the resin-encapsulated semiconductor device shown in FIGS. 10 and 11. FIG. 15 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 16 is a plan view showing the other surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 17 is a schematic cross-sectional view taken along the line VII-VII of the resin-encapsulated semiconductor device shown in FIGS. 18 is a schematic cross-sectional view taken along line VIII-VIII of the resin-encapsulated semiconductor device shown in FIGS. 15 and 16. FIG. 19 is a schematic cross-sectional view showing a state in which two resin-encapsulated semiconductor devices are stacked in the thickness direction. FIG. 19A is a diagram VII of the resin-encapsulated semiconductor device shown in FIGS. FIG. 19B corresponds to the schematic cross-sectional view taken along line VIII-VIII of the resin-encapsulated semiconductor device shown in FIGS. 15 and 16. FIG. 20 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 21 is a plan view showing the other surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. 22 is a schematic cross-sectional view taken along the line IX-IX of the resin-encapsulated semiconductor device shown in FIGS. FIG. 23 is a schematic cross-sectional view of the resin-encapsulated semiconductor device shown in FIGS. 20 and 21 taken along line XX. FIG. 24 is a schematic cross-sectional view showing a state in which two resin-encapsulated semiconductor devices are stacked in the thickness direction, and FIG. 24A is an IX of the resin-encapsulated semiconductor device shown in FIGS. FIG. 24B corresponds to the schematic cross-sectional view taken along the line XX of the resin-encapsulated semiconductor device shown in FIGS. FIG. 25 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 26 is a plan view showing the other surface of another embodiment of the resin-encapsulated semiconductor device of the present invention. 27 is a schematic cross-sectional view taken along line XI-XI of the resin-encapsulated semiconductor device shown in FIGS. 25 and 26. FIG. FIG. 28 is a schematic cross-sectional view taken along line XII-XII of the resin-encapsulated semiconductor device shown in FIGS. FIG. 29 is a schematic cross-sectional view showing a state in which two resin-encapsulated semiconductor devices are stacked in the thickness direction, and FIG. 29A is an XI of the resin-encapsulated semiconductor device shown in FIGS. A schematic cross-sectional view taken along the line -XI, FIG. 29B corresponds to a schematic cross-sectional view taken along the line XII-XII of the resin-encapsulated semiconductor device shown in FIGS.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the drawings are schematic or conceptual, and the dimensions of each member, the ratio of sizes between the members, etc. are not necessarily the same as the actual ones, and represent the same members. However, in some cases, the dimensions and ratios may be different depending on the drawing.

[Lead frame for semiconductor devices]
(First embodiment of lead frame)
FIG. 1 is a plan view showing an embodiment of a lead frame for a semiconductor device according to the present invention, FIG. 2 is a partial cross-sectional view taken along line II of the lead frame for a semiconductor device shown in FIG. FIG. 4 is a partial cross-sectional view taken along line II-II of the lead frame for a semiconductor device shown in FIG. 1, and FIG. 4 is a partial perspective view for explaining leads of the lead frame for the semiconductor device shown in FIG.
1 to 4, the lead frame 11 for a semiconductor device according to the present invention includes an outer frame member 12, a plurality of leads 13, and a connection bar 17 that supports the leads.
The lead 13 has an external terminal 14 projecting from the front surface 13a and an external terminal 15 projecting from the back surface 13b on the tip side of the portion supported by the connection bar 17. The lead 13 has an internal terminal surface 16 for connecting to a semiconductor element on the front surface 13a or the back surface 13b. In the illustrated example, the lead 13 has the internal terminal surface 16 on the front surface 13a. In FIG. 1, the external terminals 14 are indicated by hatching.

In the illustrated example, the semiconductor device lead frame 11 is multi-faceted, and one imposition area is indicated as A. Each imposition area A is rectangular, and the connection bar 17 is positioned so as to be four sides of the rectangle. In each imposition area A, the leads 13 protrude from the connection bars 17 on the four sides. The plurality of leads 13 and the connection bars 17 form a substantially flat surface and are surrounded by the tips 13c of the plurality of leads 13. The region 18 is located substantially at the center of each imposition region A.
The positions where the external terminals 14 and 15 are present in the longitudinal direction of the lead 13, that is, in the protruding direction from the connection bar 17, differ between adjacent leads, as shown in FIGS. 1 and 4. In the illustrated example, when attention is paid to the external terminals 14, the external terminals 14 are alternately arranged in a so-called staggered pattern along the longitudinal direction of the connection bar 17. The external terminals 15 are also arranged in a staggered pattern alternately along the longitudinal direction of the connection bar 17. In the present specification, the adjacent leads mean that adjacent leads projecting from the same connection bar in the rectangular connection bars are adjacent to each other. 4 shows the external terminals 14 and 15 in a state where adjacent leads are separated for convenience.

In the illustrated example, in each lead 13, the external terminal 14 projecting from the front surface 13a and the external terminal 15 projecting from the back surface 13b are present at the same position in the longitudinal direction of the lead. For this reason, the positions of the external terminals 14 arranged in a staggered manner and the positions of the external terminals 15 arranged in a staggered manner coincide with each other on the front and back of the leads 13.
Further, the internal terminal surface 16 positioned on the surface 13 a of the lead 13 is positioned closer to the tip 13 c of the lead than the external terminal 14 protruding from the surface 13 a of the same lead 13.

(Second embodiment of lead frame)
FIG. 5 is a plan view showing another embodiment of the lead frame for a semiconductor device of the present invention, and FIG. 6 is a partial sectional view taken along line III-III of the lead frame for a semiconductor device shown in FIG. FIG. 8 is a partial sectional view taken along line IV-IV of the lead frame for a semiconductor device shown in FIG. 5, and FIG. 8 is a partial perspective view for explaining leads of the lead frame for the semiconductor device shown in FIG.
5 to 8, the lead frame 21 for a semiconductor device according to the present invention includes an outer frame member 22, a plurality of leads 23, and a connection bar 27 that supports the leads.
The lead 23 has an external terminal 24 projecting from the front surface 23a and an external terminal 25 projecting from the back surface 23b on the tip side of the portion supported by the connection bar 27. In addition, the lead 23 has an internal terminal surface 26 for connecting to a semiconductor element on the front surface 23a or the back surface 23b. In the illustrated example, the lead 23 has the internal terminal surface 26 on the front surface 23a. In FIG. 5, the external terminal 24 is indicated by a solid oblique line, and the external terminal 25 is indicated by a chained oblique line.

Also in this example, the semiconductor device lead frame 21 is multi-faceted, and one imposition area is indicated as A. Each imposition area A is a rectangle, and the connection bar 27 is positioned so as to be four sides of the rectangle. In each imposition area A, leads 23 project from the connection bars 27 on the four sides, and the plurality of leads 23 and the connection bars 27 form a substantially flat surface and are surrounded by the tips 23 c of the plurality of leads 23. The region 28 is located at the approximate center of each imposition region A.
The positions where the external terminals 24 and 25 exist in the longitudinal direction of the lead 23, that is, in the protruding direction from the connection bar 27, are different between adjacent leads as shown in FIGS. Focusing on the external terminals 24, the external terminals 24 are staggered along the longitudinal direction of the connection bar 27, and the external terminals 25 are also staggered along the longitudinal direction of the connection bar 27. Are arranged in a staggered pattern. In FIG. 8, in order to show the external terminals 24 and 25, the adjacent leads are shown separated from each other for convenience.

In this example, in each lead 23, the external terminal 24 protruding from the front surface 23a and the external terminal 25 protruding from the back surface 23b are present at different positions in the longitudinal direction of the lead. Therefore, the positions of the external terminals 24 arranged in a staggered manner and the positions of the external terminals 25 arranged in a staggered manner do not coincide with each other on the front and back sides of the leads 23.
Further, the internal terminal surface 26 located on the surface 23 a of the lead 23 is located closer to the tip 23 c of the lead than the external terminal 24 protruding from the surface 23 a of the same lead 23. In the illustrated example, in one lead 23 of the adjacent leads 23, the internal terminal surface 26 located on the front surface 23 a and the external terminal 25 located on the back surface 23 b exist at the same position in the longitudinal direction of the lead 23. Yes.
The surfaces including the terminal surfaces 14a and 24a of the external terminals 14 and 24 projecting from the front surfaces 13a and 23a of the leads 13 and 23 constituting the semiconductor device lead frames 11 and 21, and the rear surfaces 13b and 23b of the leads 13 and 23 are projected. The lead thickness T defined by the distance between the external terminals 15 and 25 and the surfaces including the terminal surfaces 15a and 25a is preferably in the range of 0.10 to 0.25 mm. In the illustrated example, the thickness T is the same as the thickness of the outer frame members 12 and 22. Moreover, it is preferable that the thickness t of the lead | read | reeds 13 and 23 of the site | part in which the external terminals 14 and 15 and the external terminals 24 and 25 do not exist exists in the range of 50 to 75% of said thickness T.

  Here, as shown in FIGS. 4 and 8, the connection bars 17 and 27 constituting the semiconductor device lead frames 11 and 21 are portions where the external terminals 14 and 15 and the external terminals 24 and 25 do not exist. The leads 13 and 23 have the same thickness t. This is because, as will be described later, the base material 20 is etched from both sides, so that the half-etched connection bars 17 and 27 and the leads 13 and 23 are connected to each other. In the illustrated example, the front and back surfaces of the connection bars 17 and 27 are the same as the front surfaces 13a and 23a and the back surfaces 13b and 23b of the leads 13 and 23, respectively, and the cross-sectional shape perpendicular to the longitudinal direction of the connection bars 17 and 27 is It has become a rectangle. However, the connection bars 17 and 27 are continuous along the longitudinal direction of the connection bar on the front surface (for example, the surface continuous with the front surface 13a of the lead 13) and the back surface (for example, the surface continuous with the back surface 13b of the lead 13). It may be provided with a protrusion. For example, in the etching process described later, by leaving the surface of the base material 20 in a straight line shape, it is possible to provide continuous protrusions along the longitudinal direction of the connection bars 17, 27. The cross-sectional shape perpendicular to the longitudinal direction is a cross shape, and the strength of the semiconductor device lead frames 11 and 21 can be improved. Further, in the connection bars 17 and 27 having such linear protrusions, the tops of the protrusions are flush with the terminal surfaces 14a and 15a and the terminal surfaces 24a and 25a. Therefore, as will be described later, when the terminal surfaces 14a and 15a of the external terminals 14 and 15 and the terminal surfaces 24a and 25a of the external terminals 24 and 25 are sealed with a resin member so as to be exposed, the connection bars 17 and 27 are connected. The linear top portions of the protrusions located on the front and back sides of the surface are also exposed. Thereby, in dicing cutting for separating into individual semiconductor devices, the linear top portions of the protrusions function as marks, and positioning before work is facilitated. The shape of the protrusion is not particularly limited.

  Examples of the material constituting the lead frames 11 and 21 for semiconductor devices include, for example, a Corson alloy containing copper, nickel and silicon, a copper alloy containing iron, etc., an iron-nickel alloy, and iron-nickel-chromium. Examples thereof include conductive materials such as alloys and iron-nickel-carbon alloys. Among such materials, in particular, a material having a tensile strength of 725 MPa or more, preferably 725 to 900 MPa can be suitably used. When the tensile strength is less than 725 MPa, when the lead thickness T is 0.10 mm and the lead thickness t is 50% of the thickness T, that is, 50 μm, the strength of the leads 13 and 23 becomes insufficient. Deformation is likely to occur, which is not preferable. The upper limit of the tensile strength of the material constituting the semiconductor device lead frames 11 and 21 is preferably 900 MPa as described above. However, the upper limit of the tensile strength is appropriately set in consideration of the conductivity required for the semiconductor device lead frames 11 and 21. can do.

In such a lead frame for a semiconductor device of the present invention, since the leads have external terminals on the front and back surfaces, it is possible to produce a resin-encapsulated semiconductor device having external terminals on the front and back surfaces. Also, since the positions where the external terminals in the longitudinal direction of the leads are different between the adjacent leads, the external terminals can be arranged in a staggered manner, whereby the interval between the leads can be reduced, and the resin It is possible to reduce the thickness and the number of pins of the sealed semiconductor device.
The above-described embodiments of the lead frame for a semiconductor device are examples, and the present invention is not limited to these embodiments.

Next, a manufacturing example of the lead frame for a semiconductor device of the present invention will be described by taking the lead frame 21 for a semiconductor device as an example.
FIG. 9 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention, which is an example of manufacturing the lead frame 21 for a semiconductor device described above. FIG. 9 corresponds to FIG. 7 which is a partial cross-sectional view taken along the line IV-IV of the lead frame for a semiconductor device shown in FIG.
In FIG. 9, a resist pattern 31a is formed on the front surface 20a of the lead frame substrate 20, and a resist pattern 31b is formed on the back surface 20b of the substrate 20 (FIG. 9A). In the illustrated example, one imposition area for multi-imposition is indicated as A.
The base material 20 is made of a conductive base material such as a Corson alloy containing copper, nickel or silicon, a copper alloy containing iron or the like, an iron-nickel alloy, an iron-nickel-chromium alloy, or an iron-nickel-carbon alloy. The thickness can be appropriately set within a range of 0.10 to 0.25 mm. Such a base material 20 is preferably preliminarily subjected to a degreasing process, a cleaning process, and the like.

The resist patterns 31a and 31b can be formed by applying and drying a photosensitive resist, or laminating a photosensitive resist film, exposing through a desired photomask, and developing. The photosensitive resist to be used can be appropriately selected from known photosensitive resists so that the formed resist patterns 31a and 31b function as an etching mask in the etching of the substrate 20.
Next, using the resist patterns 31a and 31b as etching masks, an etching process is performed on both surfaces of the base material 20 to form outer frame members 22, leads 23, and external terminals 24 and 25 (FIG. 9B). )). The etching solution used for the etching treatment can be appropriately selected according to the material of the base material 20. For example, when a copper base material is used as the base material 20, generally an aqueous ferric chloride solution or an aqueous copper chloride solution is used as the etching solution. Can be used as Such an etching process is stopped when the thickness of the lead 23 reaches a desired thickness. The thickness of the lead 23 can be set as appropriate within a range of 50 to 75% of the thickness of the base material 20, for example.

Next, after removing the resist patterns 31a and 31b from the base material 20 subjected to the etching treatment, an etching barrier layer 35 is formed so that an unnecessary region of the lead 23 is exposed (FIG. 9C). The etching barrier layer 35 can be formed using a photosensitive resist similar to the above-described photosensitive resist.
Next, using the etching barrier layer 35 as an etching mask, the exposed lead 23 is removed by etching using an etching solution, and then the etching barrier layer 35 is removed, whereby the lead frame 21 for a semiconductor device is obtained. (FIG. 9D). As the etching solution to be used, the etching solution used in the etching process of the substrate 20 using the resist patterns 31a and 31b as an etching mask can be used. In this etching, etching is preferably performed from both surfaces of the exposed lead 23, but etching from one surface may also be performed.
The above-described manufacturing example of the lead frame for a semiconductor device is an example, and is not limited to such a manufacturing method.

[Resin encapsulated semiconductor device]
(First embodiment of resin-encapsulated semiconductor device)
FIG. 10 is a plan view showing one surface of an embodiment of the resin-encapsulated semiconductor device of the present invention, FIG. 11 is a plan view showing the other surface, and FIG. 12 is shown in FIGS. FIG. 13 is a schematic cross-sectional view taken along line VI-VI of the resin-encapsulated semiconductor device shown in FIGS. 10 and 11.
10 to 13, the resin-encapsulated semiconductor device 51 of the present invention includes a plurality of leads 53 arranged so that the surface 53 a forms a substantially flat surface, and the interior set on the surface 53 a of the lead 53. A semiconductor element 61 mounted so as to be connected to the terminal surface 56 via the connection member 63 is provided at the approximate center of the arrangement of the leads 53. Each lead 53 has an external terminal 54 protruding from the front surface 53a and an external terminal 55 protruding from the back surface 53b. The plurality of leads 53, the semiconductor element 61, and the connection member 63 are sealed with the resin member 65, and the terminal surfaces 54 a and 55 a of the external terminals 54 and 55 included in each lead 53 are exposed from the resin member 65. 10 and 11, the semiconductor element 61 is indicated by a one-dot chain line.

In the illustrated example, the positions where the external terminals 54 and 55 exist in the longitudinal direction of each lead 53 (the direction indicated by the arrow a in FIGS. 12 and 13) are different between adjacent leads. For this reason, the external terminals 54 and 55 are alternately arranged along the side wall surface of the resin-encapsulated semiconductor device 51 in a so-called zigzag pattern, and thus the external terminals 54 and 55 exposed from the resin member 65. The terminal surfaces 54a and 55a are staggered. In each lead 53, the external terminal 54 protruding from the front surface 53 a and the external terminal 55 protruding from the back surface 53 b exist at the same position in the longitudinal direction of the lead 53. For this reason, the positions of the external terminal surfaces 54 a arranged in a staggered manner and the positions of the external terminal surfaces 55 a are the same on the front and back of the resin-encapsulated semiconductor device 51.
Further, in the illustrated example, the internal terminal surface 56 is set to a surface 53 a near the tip of each lead 53 in the apparatus internal direction.

The lead 53 constituting the resin-encapsulated semiconductor device 51 has a thickness T defined by the terminal surface 54a of the external terminal 54 protruding from the front surface 53a and the terminal surface 55a of the external terminal 55 protruding from the back surface 53b of 0. It is preferable that it exists in the range of 10-0.25 mm. Further, it is preferable that the thickness t of the lead 53 at a portion where the external terminals 54 and 55 do not exist is in the range of 50 to 75% of the thickness T. As a material constituting such a lead 53, a Corson alloy containing copper, nickel or silicon, a copper alloy containing iron, etc., an iron-nickel alloy, an iron-nickel-chromium alloy, an iron-nickel-carbon alloy And the like.
The semiconductor element 61 constituting the resin-encapsulated semiconductor device 51 is not particularly limited, but the semiconductor element 61 is mounted in a state of being connected to the internal terminal surfaces 56 of the plurality of leads 53 via the connection members 63. The surface 61 a of 61 is lower than the terminal surface 54 a of the external terminal 54 of the lead 53 and has a thickness that can be sealed with the resin member 65. When the surface 61a of the semiconductor element 61 may be exposed from the resin-encapsulated semiconductor device 51, the thickness of the semiconductor element 61 is such that the surface 61a is flush with the terminal surface 54a of the external terminal 54. Any thickness may be used.
The connection member 63 that connects the internal terminal surface 56 of the lead 53 and the semiconductor element 61 can be made of metal or conductive resin that has been conventionally used for flip chip connection, and is not particularly limited. The resin member 75 can be made of an electrically insulating resin material that has been conventionally used in resin-encapsulated semiconductor devices, and is not particularly limited.

  In such a resin-encapsulated semiconductor device 51, since the external terminals 54 and 55 are arranged in a staggered manner, a large number of leads can be arranged. Then, in a PoP (Package on Package) in which resin-encapsulated semiconductor devices 51 as shown in FIG. 14 are stacked in the thickness direction, it is possible to reduce the thickness and increase the number of pins. In PoP in which the resin-encapsulated semiconductor device 51 is laminated in the thickness direction, the front and back sides are reversed, that is, the terminal surfaces 54a of the external terminals 54 of the resin-encapsulated semiconductor device 51 to be laminated, or the terminals of the external terminals 55 You may laminate | stack so that the surface 55a may be connected. 14A is a schematic cross-sectional view taken along line VV of the resin-encapsulated semiconductor device shown in FIGS. 10 and 11 in a state where two resin-encapsulated semiconductor devices 51 are stacked in the thickness direction. FIG. 14B shows a state in which two resin-encapsulated semiconductor devices 51 are stacked in the thickness direction, and VI of the resin-encapsulated semiconductor device shown in FIGS. It is shown by the schematic sectional drawing in the -VI line.

  Such a resin-encapsulated semiconductor device 51 can be manufactured as follows using, for example, the above-described lead frame 11 for a semiconductor device of the present invention. First, the internal terminal surface 16 (56) set on the surface 13a (53a) of the lead 13 (53) of the lead frame 11 for a semiconductor device and the terminal of the semiconductor element 61 are connected by flip chip connection using the connection member 63. Then, the semiconductor element 61 is mounted so as to cover the region 18 surrounded by the tips 13c of the plurality of leads 13 (53). Thereafter, the semiconductor device lead frame 11 is held by the upper die and the lower die, and the terminal surfaces 14a and 15a (54a and 55a) of the external terminals 14 and 15 (54 and 55) of the semiconductor device lead frame 11 are exposed. Then, the resin member 65 is sealed. At this time, a resin member 65 may be disposed in advance at a desired portion on the surface 13a (53a) side of the lead 13 (53). In such a prior arrangement of the resin member 65, a polyimide tape for resin sealing is applied so that the terminal surface 14 a (54 a) of the external terminal 14 of the lead frame 11 for a semiconductor device is not covered with the resin member 65. Also good. As this resin sealing polyimide tape, a known tape can be used. Then, in order to divide each semiconductor device into individual pieces, the resin-sealed semiconductor device 51 is obtained by dicing and cutting the connection bar 17 of the semiconductor device lead frame 11 with a circular blade.

(Second Embodiment of Resin Sealed Semiconductor Device)
15 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention, FIG. 16 is a plan view showing the other surface, and FIG. 17 is shown in FIGS. FIG. 18 is a schematic cross-sectional view taken along line VII-VII of the resin-encapsulated semiconductor device shown, and FIG. 18 is a schematic cross-sectional view taken along line VIII-VIII of the resin-encapsulated semiconductor device shown in FIGS.
15 to 18, the resin-encapsulated semiconductor device 71 of the present invention includes a plurality of leads 73 arranged so that the surface 73 a forms a substantially flat surface, and the interior set on the surface 73 a of the lead 73. A semiconductor element 81 mounted so as to be connected to the terminal surface 76 via the connection member 83 is provided at the approximate center of the arrangement of the leads 73. Each lead 73 has an external terminal 74 protruding from the front surface 73a and an external terminal 75 protruding from the back surface 73b. The plurality of leads 73, the semiconductor element 81, and the connection member 83 are sealed with the resin member 85, and the terminal surfaces 74 a and 75 a of the external terminals 74 and 75 included in each lead 73 are exposed from the resin member 85. In FIGS. 15 and 16, the semiconductor element 81 is indicated by a one-dot chain line.

In the illustrated example, the positions where the external terminals 74 and 75 exist in the longitudinal direction of each lead 73 (the direction indicated by the arrow a in FIGS. 17 and 18) are different between adjacent leads. For this reason, the external terminals 74 and 75 are alternately arranged along the side wall surface of the resin-encapsulated semiconductor device 71 in a so-called staggered pattern, and thus the external terminals 74 and 75 exposed from the resin member 85. The terminal surfaces 74a and 75a are staggered. In each lead 73, the external terminal 74 protruding from the front surface 73 a and the external terminal 75 protruding from the back surface 73 b exist at different positions in the longitudinal direction of the lead 73. For this reason, the positions of the external terminal surfaces 74 a arranged in a staggered manner and the positions of the external terminal surfaces 75 a are different between the front and back sides of the resin-encapsulated semiconductor device 71.
Further, in the illustrated example, the internal terminal surface 76 is set to a surface 73 a near the tip of each lead 73 in the apparatus internal direction.

  The lead 73 constituting the resin-encapsulated semiconductor device 71 has a thickness T defined by the terminal surface 74a of the external terminal 74 protruding from the front surface 73a and the terminal surface 75a of the external terminal 75 protruding from the back surface 73b of 0. It is preferable that it exists in the range of 10-0.25 mm. Further, it is preferable that the thickness t of the lead 73 at a portion where the external terminals 74 and 75 do not exist be appropriately set within a range of 50 to 75% of the thickness T. The material constituting the lead 73 can be the same as the lead 53 constituting the resin-encapsulated semiconductor device 51 described above.

Further, the semiconductor element 81 constituting the resin-encapsulated semiconductor device 71 is not particularly limited, but is mounted on the internal terminal surfaces 76 of the plurality of leads 73 so as to be connected via the connection members 83. The surface 81 a of the semiconductor element 81 is lower than the terminal surface 74 a of the external terminal 74 included in the lead 73 and has a thickness that can be sealed with the resin member 85. When the surface 81a of the semiconductor element 81 may be exposed from the resin-encapsulated semiconductor device 71, the thickness of the semiconductor element 81 is such that the surface 81a is flush with the terminal surface 74a of the external terminal 74. Any thickness may be used.
The connection member 83 and the resin member 85 that connect the internal terminal surface 76 of the lead 73 and the semiconductor element 81 are the same as the connection member 63 and the resin member 65 that constitute the resin-encapsulated semiconductor device 51 described above. Can do.

In such a resin-encapsulated semiconductor device 71, since the external terminals 74 and 75 are arranged in a staggered manner, a large number of leads can be arranged. Then, the resin-encapsulated semiconductor device 71 as shown in FIG. 19 is connected in the thickness direction with the front and back reversed, that is, the terminal surfaces 75a of the external terminals 75 of the resin-encapsulated semiconductor device 71 to be laminated. In the PoP laminated as described above, it is possible to reduce the thickness and increase the number of pins. In the lamination in which the front and back of the resin-encapsulated semiconductor device 71 are reversed, the terminal surfaces 74a of the external terminals 74 may be connected to each other. 19A is a schematic cross-sectional view taken along line VII-VII of the resin-encapsulated semiconductor device shown in FIGS. 15 and 16 in a state where two resin-encapsulated semiconductor devices 71 are stacked in the thickness direction. FIG. 19B shows a state in which two resin-encapsulated semiconductor devices 71 are stacked in the thickness direction, and VIII of the resin-encapsulated semiconductor device shown in FIGS. 15 and 16. It is shown by the schematic sectional drawing in the -VIII line.
Such a resin-encapsulated semiconductor device 71 can also be manufactured in the same manner as the above-described resin-encapsulated semiconductor device 51 using, for example, the semiconductor device lead frame 21 of the present invention.

(Third embodiment of resin-encapsulated semiconductor device)
20 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention, FIG. 21 is a plan view showing the other surface, and FIG. 22 is shown in FIGS. FIG. 23 is a schematic cross-sectional view taken along the line IX-IX of the resin-encapsulated semiconductor device shown, and FIG. 23 is a schematic cross-sectional view taken along the line XX of the resin-encapsulated semiconductor device shown in FIGS.

20 to 23, the resin-encapsulated semiconductor device 101 of the present invention includes a plurality of leads 103 arranged so that the front surface 103 a forms a substantially flat surface, and the interior set on the back surface 103 b of the lead 103. A semiconductor element 111 connected to the terminal surface 106 via a connecting member 113 that is a wire is provided at the approximate center of the arrangement of the leads 103. Each lead 103 has an external terminal 104 protruding from the front surface 103a and an external terminal 105 protruding from the back surface 103b. The plurality of leads 103, the semiconductor element 111, and the connection member 113 are sealed with a resin member 115, and the terminal surfaces 104 a and 105 a of the external terminals 104 and 105 included in each lead 103 are exposed from the resin member 115. In FIG. 21, the semiconductor element 111 is indicated by a one-dot chain line.
In the illustrated example, the positions where the external terminals 104 and 105 exist in the longitudinal direction of each lead 103 (the direction indicated by the arrow a in FIGS. 22 and 23) are different between adjacent leads. For this reason, the external terminals 104 and 105 are alternately arranged in a staggered manner along the side wall surface of the resin-encapsulated semiconductor device 101, and thus the external terminals 104 and 105 exposed from the resin member 115 are arranged. The terminal surfaces 104a and 105a are staggered. In each lead 103, the external terminal 104 protruding from the front surface 103 a and the external terminal 105 protruding from the back surface 103 b exist at the same position in the longitudinal direction of the lead 103. For this reason, the positions of the external terminal surfaces 104 a arranged in a staggered manner and the positions of the external terminal surfaces 105 a are the same on the front and back of the resin-encapsulated semiconductor device 101.

Further, in the illustrated example, the internal terminal surface 106 is set to the back surface 103b near the tip of each lead 103 in the device internal direction.
The lead 103 constituting the resin-encapsulated semiconductor device 101 has a thickness T defined by the terminal surface 104a of the external terminal 104 projecting from the front surface 103a and the terminal surface 105a of the external terminal 105 projecting from the back surface 103b of 0. It is preferable that it exists in the range of 10-0.25 mm. Further, it is preferable that the thickness t of the lead 103 at a portion where the external terminals 104 and 105 do not exist is in a range of 50 to 75% of the thickness T. The material constituting the lead 103 can be the same as the lead 53 constituting the resin-encapsulated semiconductor device 51 described above.

The connection member 113 that connects the internal terminal surface 106 of the lead 103 and the semiconductor element 111 is a wire. The semiconductor element 111 constituting the resin-encapsulated semiconductor device 101 is not particularly limited, but the surface 111 a of the semiconductor element 111 is connected to the internal terminal surfaces 106 of the plurality of leads 103 by the wires 113 and the leads 103 are The external terminal 104 has a thickness that allows it to be flush with the terminal surface 104 a of the external terminal 104.
The resin member 115 constituting the resin-encapsulated semiconductor device 101 can be the same as the resin member 65 constituting the resin-encapsulated semiconductor device 51 described above.
In such a resin-encapsulated semiconductor device 101, since the external terminals 104 and 105 are arranged in a staggered manner, a large number of leads can be arranged. And in PoP which laminates the resin-encapsulated semiconductor device 101 as shown in FIG. In PoP in which the resin-encapsulated semiconductor device 101 is laminated in the thickness direction, the front and back sides are reversed, that is, the terminal surfaces 104a of the external terminals 104 of the resin-encapsulated semiconductor device 101 to be laminated, or the terminals of the external terminals 105 You may laminate | stack so that the surface 105a may be connected. 24A is a schematic cross-sectional view taken along line IX-IX of the resin-encapsulated semiconductor device shown in FIGS. 20 and 21 in a state where two resin-encapsulated semiconductor devices 101 are stacked in the thickness direction. FIG. 24B shows a state in which two resin-encapsulated semiconductor devices 101 are stacked in the thickness direction, and X of the resin-encapsulated semiconductor device shown in FIGS. It is shown by the schematic sectional drawing in -X-ray.

  The above-described resin-encapsulated semiconductor device 101 can be manufactured as follows, for example, using the above-described lead frame 11 for a semiconductor device of the present invention. First, the lead frame 11 for a semiconductor device is placed on a lower die having a flat plate shape with the back surface 13b (103b) of the lead 13 (103) facing upward, and a plurality of the lead frames 11 for the semiconductor device are configured. The semiconductor element 111 is placed in the region 18 surrounded by the tip 13c of the lead 13 (103). The wire 113 connects the terminal of the semiconductor element 111 and the internal terminal surface 16 (106) set on the back surface 13b (103b) of the lead 13 (103). After that, the semiconductor device lead frame 11 is pressed with an upper mold and sealed with a resin member 115 so that the terminal surface 15a (105a) of the external terminal 15 (105) of the semiconductor device lead frame 11 is exposed. At this time, a resin member 115 may be disposed in advance at a desired portion on the surface 13a (103a) side of the lead 13 (103). In such an arrangement of the resin member 115 in advance, a resin sealing polyimide tape is used so that the terminal surface 14a (104a) of the external terminal 14 (104) of the lead frame 11 for a semiconductor device is not covered with the resin member 115. It may be affixed. As this resin sealing polyimide tape, a known tape can be used. Then, the resin-encapsulated semiconductor device 101 is obtained by dicing and cutting the connection bar 17 of the semiconductor device lead frame 11 with a circular blade in order to divide each semiconductor device.

(Fourth embodiment of resin-encapsulated semiconductor device)
25 is a plan view showing one surface of another embodiment of the resin-encapsulated semiconductor device of the present invention, FIG. 26 is a plan view showing the other surface, and FIG. 27 is shown in FIGS. FIG. 28 is a schematic cross-sectional view taken along line XI-XI of the resin-encapsulated semiconductor device shown in FIG. 28, and FIG. 28 is a schematic cross-sectional view taken along line XII-XII of the resin-encapsulated semiconductor device shown in FIGS.
25 to 28, the resin-encapsulated semiconductor device 121 of the present invention includes a plurality of leads 123 arranged so that the front surface 123a forms a substantially flat surface, and the interior set on the back surface 123b of the lead 123 A semiconductor element 131 connected to the terminal surface 126 via a connection member 133 that is a wire is provided at the approximate center of the arrangement of the leads 123. Each lead 123 has an external terminal 124 protruding from the front surface 123a and an external terminal 125 protruding from the back surface 123b. The plurality of leads 123, the semiconductor element 131, and the connection member 133 are sealed with the resin member 135, and the terminal surfaces 124 a and 125 a of the external terminals 124 and 125 included in each lead 123 are exposed from the resin member 135. In FIG. 26, the semiconductor element 131 is indicated by a one-dot chain line.

In the illustrated example, the positions where the external terminals 124 and 125 exist in the longitudinal direction of each lead 123 (the direction indicated by the arrow a in FIGS. 27 and 28) are different between adjacent leads. For this reason, the external terminals 124 and 125 are alternately arranged in a staggered manner along the side wall surface of the resin-encapsulated semiconductor device 121, and thus the external terminals 124 and 125 exposed from the resin member 135 are arranged. The terminal surfaces 124a and 125a are staggered. In each lead 123, the external terminal 124 protruding from the front surface 123 a and the external terminal 125 protruding from the back surface 123 b exist at different positions in the longitudinal direction of the lead 123. For this reason, the positions of the external terminal surfaces 124 a arranged in a staggered manner and the positions of the external terminal surfaces 125 a are different between the front and back sides of the resin-encapsulated semiconductor device 121.
Further, in the illustrated example, the internal terminal surface 126 is set to the back surface 123b near the tip of each lead 123 in the device internal direction.

The lead 123 constituting the resin-encapsulated semiconductor device 121 has a thickness T defined by the terminal surface 124a of the external terminal 124 protruding from the front surface 123a and the terminal surface 125a of the external terminal 125 protruding from the back surface 123b of 0. It is preferable that it exists in the range of 10-0.25 mm. Further, it is preferable that the thickness t of the lead 123 at a portion where the external terminals 124 and 125 do not exist is in a range of 50 to 75% of the thickness T. The material constituting the lead 123 can be the same as the lead 53 constituting the resin-encapsulated semiconductor device 51 described above.
The connection member 133 that connects the internal terminal surface 126 of the lead 123 and the semiconductor element 131 is a wire. The semiconductor element 131 constituting the resin-encapsulated semiconductor device 121 is not particularly limited, but the surface 131 a of the semiconductor element 131 is connected to the internal terminal surfaces 126 of the plurality of leads 123 by the wires 133. The external terminal 124 has a thickness that allows it to be flush with the terminal surface 124 a of the external terminal 124.
The resin member 135 constituting the resin-encapsulated semiconductor device 121 can be the same as the resin member 65 constituting the resin-encapsulated semiconductor device 51 described above.

In such a resin-encapsulated semiconductor device 121, since the external terminals 124 and 125 are arranged in a staggered manner, a large number of leads can be arranged. Then, the resin-encapsulated semiconductor device 121 as shown in FIG. 29 is connected in the thickness direction with the front and back reversed, that is, the terminal surfaces 125a of the external terminals 125 of the resin-encapsulated semiconductor device 121 to be stacked. In the PoP laminated as described above, it is possible to reduce the thickness and increase the number of pins. In the lamination in which the front and back of the resin-encapsulated semiconductor device 121 are reversed, the terminal surfaces 124a of the external terminals 124 may be connected to each other. 29A is a schematic cross-sectional view taken along line XI-XI of the resin-encapsulated semiconductor device shown in FIGS. 25 and 26, in which two resin-encapsulated semiconductor devices 121 are stacked in the thickness direction. FIG. 29B shows a state in which two resin-encapsulated semiconductor devices 121 are stacked in the thickness direction, and XII of the resin-encapsulated semiconductor device shown in FIGS. It is shown by the schematic sectional drawing in the -XII line.
Such a resin-encapsulated semiconductor device 121 can be manufactured in the same manner as the above-described resin-encapsulated semiconductor device 101 using, for example, the above-described lead frame 21 for a semiconductor device of the present invention.

  The above-described embodiments of the resin-encapsulated semiconductor device are examples, and the present invention is not limited to these embodiments. For example, after mounting a semiconductor element in each imposition area A of the lead frame 11 for a semiconductor device of the present invention with multiple impositions, sealing with a resin member so that the surface of the external terminal of the lead is exposed in each imposition area A Then, the outer frame member 12 may be separated to form a multi-faced resin-encapsulated semiconductor device.

Next, the present invention will be described in more detail with specific examples.
[Example 1]
First, a 0.20 mm thick copper alloy plate (EFTEC98S manufactured by Furukawa Electric Co., Ltd.) was prepared as a lead frame substrate, and a photosensitive resist film (Asahi Kasei E-Materials Co., Ltd.) was prepared on this substrate. AQ series, thickness 0.038 mm) was laminated, exposed through a desired photomask, and developed to form resist patterns on both sides of the substrate (see FIG. 9A).

Next, using the resist pattern as an etching mask, etching was performed from both sides of the base material by spray etching under the following etching conditions, and the ashing processing was stopped when the exposed base material had a thickness of 0.10 mm. As a result, a lead, an outer frame member, and a connection bar with external terminals protruding from the front and back sides were formed (see FIG. 9B).
(Etching conditions)
・ Etching solution: Ferric chloride solution ・ Specific gravity: 35 Baume (Be)
・ Temperature: 55 ℃
・ Spray pressure: 2kg / cm ²

Next, the resist pattern was removed from the etched substrate, and then the above-described photosensitive resist film was laminated, exposed through a desired photomask, and developed. As a result, an etching barrier layer was formed on both surfaces so as to expose an unnecessary region of the lead (see FIG. 9C).
Next, using the etching barrier layer as an etching mask, etching was performed from both sides of the substrate by spray etching under the above etching conditions to remove the exposed leads (see FIG. 9D). Thereafter, the etching barrier layer was removed and washed.

  Thereby, a lead frame for a semiconductor device as shown in FIGS. 1 to 4 was produced. This lead frame for a semiconductor device had 56 faces, and the number of leads in each face area was 148. The positions of the external terminals protruding from the front and back of each lead are the same in the longitudinal direction of the leads, and when the adjacent leads are compared, the positions of the external terminals differ by 500 μm in the longitudinal direction of the leads. It was something to do. The height of the external terminal protruding from such a lead is 50 μm, the thickness of the lead defined by the distance of the surface including the terminal surface of the external terminal protruding from the front and back of the lead is 0.20 mm, and the portion where no external terminal exists The lead thickness was 0.10 mm.

[Example 2]
A lead frame for a semiconductor device as shown in FIGS. 5 to 8 was produced in the same manner as in Example 1 except that the resist pattern formed on both surfaces of the substrate was changed.
This lead frame for a semiconductor device had 56 faces, and the number of leads in each face area was 148. The positions of the external terminals protruding from the front and back of each lead differed in the longitudinal direction of the lead, and the difference in the position was 500 μm in the longitudinal direction of the lead. Further, when the adjacent leads were compared, the position where the external terminal exists was different by 500 μm in the longitudinal direction of the lead. The height of the external terminal protruding from such a lead is 50 μm, the thickness of the lead defined by the distance of the surface including the terminal surface of the external terminal protruding from the front and back of the lead is 0.20 mm, and the portion where no external terminal exists The lead thickness was 0.10 mm.

  The present invention is useful in manufacturing a resin-encapsulated semiconductor device.

11, 21 ... Lead frame for semiconductor device 13, 23 ... Lead 14, 15, 24, 25 ... External terminal 14a, 15a, 24a, 25a ... External terminal surface 16, 26 ... Internal terminal surface 17, 27 ... Connection bar 51, 71, 101, 121 ... Resin-sealed semiconductor devices 53, 73, 103, 123 ... Leads 54, 55, 74, 75, 104, 105, 124, 125 ... External terminals 54a, 55a, 74a, 75a, 104a, 105a , 124a, 125a ... external terminal surfaces 56, 76, 106, 126 ... internal terminal surfaces 61, 81, 111, 131 ... semiconductor elements 63, 83, 113, 133 ... connection members 65, 85, 115, 135 ... resin members

Claims (9)

A lead having external terminals protruding from the front surface and the back surface, respectively, and a connection bar for supporting the plurality of leads,
The internal terminal surface connected to the semiconductor element is located on the front surface or the back surface of the lead,
A lead frame for a semiconductor device, wherein a position where the external terminal exists in a longitudinal direction of the lead is different between adjacent leads.   The external terminal protruding from the front surface of the lead and the external terminal protruding from the back surface are present at the same position in the longitudinal direction of the lead, and the internal terminal surface is positioned closer to the tip of the lead than the external terminal. A lead frame for a semiconductor device according to claim 1.   The external terminal projecting from the front surface of the lead and the external terminal projecting from the back surface are present at different positions in the longitudinal direction of the lead, and the internal terminal surface of the lead surface where the internal terminal surface is located is more than the external terminal. The lead frame for a semiconductor device according to claim 1, wherein the lead frame is located near a tip of the lead.   The lead thickness T defined by the distance between the surface including the terminal surface of the external terminal protruding from the surface of the lead and the surface including the terminal surface of the external terminal protruding from the back surface of the lead is 0.10 to. 4. The semiconductor device according to claim 1, wherein a lead thickness t in a range of 25 mm and no external terminal is in a range of 50 to 75% of the thickness T. 5. Lead frame.   5. The lead frame for a semiconductor device according to claim 1, wherein a tensile strength of a material constituting the lead frame for a semiconductor device is 725 MPa or more. A semiconductor element; a plurality of leads positioned around the semiconductor element; a connecting member that connects the internal terminal surface of the lead to the semiconductor element; and a resin that seals the semiconductor element, the lead, and the connecting member A member, and
The lead has external terminals protruding from the front surface and the back surface, respectively, and the internal terminal surface is located on the front surface or the back surface of the lead,
The position where the external terminal is present in the longitudinal direction of the lead differs between adjacent leads,
A resin-encapsulated semiconductor device, wherein a terminal surface of the external terminal is exposed from the resin member.   The external terminal protruding from the front surface of the lead and the external terminal protruding from the back surface are present at the same position in the longitudinal direction of the lead, and the internal terminal surface is positioned closer to the semiconductor element than the external terminal. The resin-encapsulated semiconductor device according to claim 6.   The external terminal projecting from the front surface of the lead and the external terminal projecting from the back surface are present at different positions in the longitudinal direction of the lead, and the internal terminal surface of the lead surface where the internal terminal surface is located is more than the external terminal. The resin-encapsulated semiconductor device according to claim 6, wherein the resin-encapsulated semiconductor device is located closer to the semiconductor element.   The lead thickness T defined by the distance between the surface including the terminal surface of the external terminal protruding from the surface of the lead and the surface including the terminal surface of the external terminal protruding from the back surface of the lead is 0.10 to. The resin seal according to any one of claims 6 to 8, wherein a thickness t of the lead in a portion having a range of 25 mm and no external terminal is 50 to 75% of the thickness T. Stop-type semiconductor device.

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