JP2016018805A - Bandgap-engineered memory including a plurality of charge trap layers for storing charges - Google Patents

Abstract

A memory that is less likely to cause erase saturation is provided. The memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack includes a multilayer tunnel structure over the channel surface, a first charge storage nitride layer over the multilayer tunnel structure, and a first blocking dielectric layer over the first charge storage nitride layer. A second charge storage nitride layer over the first blocking dielectric layer and a second blocking oxide layer over the second charge storage nitride layer. The multilayer tunnel structure includes a first tunnel oxide layer, a first tunnel nitride layer above the first tunnel oxide layer, and a second tunnel oxide layer above the first tunnel nitride layer. Including. [Selection] Figure 8

Description

  The present technology relates to a flash memory technology, and more particularly, to a charge trap memory technology that is less susceptible to erase saturation despite a large gate voltage and can be adapted to high-speed erase operations and program operations.

  Charge trap memory is a type of non-volatile integrated circuit memory technology that stores data by storing charge using dielectric charge trapping materials. According to an early design called a SONOS device, the source, drain and channel are formed from silicon channel material (S), the tunnel dielectric layer is formed from silicon oxide (O), and the charge storage layer is silicon nitride (N). The blocking dielectric layer is formed from silicon oxide (O) and the gate includes polysilicon (S).

  FIG. 1 is separated from a channel by a stack of dielectric material comprising a source 11 and a drain 12 separated by a channel 10 and a multilayer tunnel dielectric structure 13-15, a charge storage layer 16 and a blocking dielectric layer 17. 1 shows a charge trap memory cell having a field effect transistor (FET) structure with a gate 18.

  A SONOS device is programmed by electron tunneling using one of a number of known bias techniques and is erased by hole tunneling or electron de-trapping. In order to achieve a practical operating speed for the erase operation, the tunnel dielectric layer must be very thin (less than 30 mm). However, at that thickness, the durability and charge retention characteristics of the memory cell are insufficient compared to conventional floating gate technology. Also, in the case of a relatively thick tunnel dielectric layer, the electric field necessary for the erase operation also results in electron injection emanating from the gate and beyond the blocking dielectric layer. Erasing generally requires a large electric field exceeding about 15 MV / cm. This electron injection results in an erase saturation state where the charge level in the charge trap device converges to an equilibrium level. See U.S. Pat. No. 6,057,059 invented by Lue et al. Entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”.

  On the one hand, techniques for improving the performance of tunnel dielectric layers for erasing at lower electric fields have been studied. In FIG. 1, the tunnel dielectric layer includes three-layer bandgap engineered structures 13-15 including layers of silicon oxide, silicon nitride, and silicon oxide.

  FIG. 3 is a graph of flat band voltage versus erase time for the memory cell of FIG. The BE-SONOS memory cell has a p polysilicon gate. A curve 310 is obtained by simulating the erase operation with a gate voltage of −14V. Plot point 311 is obtained by experimental data (Exp) from the erase operation with a gate voltage of −14V. A curve 320 is obtained by simulation (Simulation: Sim) of the erase operation at a gate voltage of −15V. Plot point 321 is obtained from experimental data from an erase operation with a gate voltage of −15V. A curve 330 is obtained by simulating the erase operation with a gate voltage of −16V. Plot point 331 is obtained from experimental data from an erase operation with a gate voltage of −16V. A curve 340 is obtained by simulating the erase operation with a gate voltage of −17V. Plot point 341 is obtained from experimental data from an erase operation with a gate voltage of −17V. A curve 350 is obtained by simulating the erase operation with a gate voltage of −18V. Plot point 351 is obtained from experimental data from an erase operation with a gate voltage of −18V.

  Curves and plot points for small gate voltages indicate overly slow erasures. Curves and plot voltages for larger gate voltages are faster, but erase saturation occurs within 1 second. Since more electrons are injected and stored in the first trap layer (N2), the top oxide (O3) has a large electric field that causes large gate injection.

  On the other hand, techniques for improving the performance of blocking dielectric layers that reduce electron injection from the gate for high electric fields required for erasing have been studied. Prior art techniques have emphasized the advantages of high-k dielectrics such as aluminum oxide. The higher the dielectric constant, the higher the program and erase speeds, improving the memory window at the threshold voltage for the cell, and reducing the effective oxide thickness EOT to reduce the operating voltage during programming and erasing. , Can improve performance. However, it may be difficult to produce high dielectric materials such as aluminum oxide with high quality. Thus, the use of high dielectric constant materials for the blocking dielectric comes at the price of reduced reliability and reduced data retention. For example, high dielectric materials easily generate shallow traps (or dipole relaxation) that result in fast initial charge loss, resulting in a threshold voltage offset in the program verify value.

  In FIG. 2, the blocking dielectric includes a high dielectric constant dielectric layer 17B and a silicon oxide layer 17A. FIG. 4 is a graph of flat band voltage versus erase time for a variation of the memory cell of FIG. 2 excluding the silicon oxide layer 17A. The erase operation is performed at a gate voltage of −18V using the N 2 charge storage nitride layer 16 and the high dielectric constant blocking dielectric layer 17B having a thickness of 70 and 150 respectively at the curve and plot points. Various curves and plot points are shown for various combinations of O1 / N1 / O2, ie, oxide tunnel layer 13, nitride tunnel layer 14, and oxide tunnel layer 15. The result of the erase operation at 15/20/30 O / N1 / O2 is a simulated curve 410 and experimental data plot point 411. The result of the erase operation at 18/20/30 O / N1 / O2 is a simulated curve 420 and experimental data plot point 421. The result of the erase operation at O1 / N1 / O2 of 20/20/30 is a simulated curve 430 and experimental data plot point 431. Again, the curves and plot points for small gate voltages indicate overly slow erasures. Again, the curves and plot points for larger gate voltages are faster, but there is erase saturation within 1 second.

FIG. 5 is a graph of flat band voltage versus erase time for the memory cell of FIG. O1 / N1 / O2 / N2, i.e., oxide tunnel layer 13, nitride tunnel layer 14, oxide tunnel layer 15, charge storage, with respective thicknesses of 13 Å, 20 Å, 25 Å and 50 に お い て at the curves and plot points Using the nitride layer 16, an erase operation is performed with a gate voltage of −15V. Various curves and plot points are shown for different combinations of O3 oxide blocking layer 17A and high dielectric constant blocking dielectric layer 17B. The result of the erase operation with 40/60 O 3 / Al ₂ O ₃ is a simulated curve 510 and an experimental data plot point 511. The result of the erase operation with 50/60 O 3 / Al ₂ O ₃ is a simulated curve 520 and experimental data plot points 521. Again, the curves and plot points for small gate voltages indicate overly slow erasures.

High dielectric constant materials such as Al ₂ O ₃ thin film or HfO ₂ thin film on O3 reduce the electric field at the top dielectric because the high dielectric constant reduces the electric field at O3, thereby reducing erase saturation. Can be useful. However, the introduction of high dielectric materials can lead to significant reliability degradation, such as reduced retention and vulnerability to some fast initial retention drift. For example, high dielectric constant materials have the effect of mitigating the delay in relative permittivity that varies from linear steady state dielectric constant.

  An alternative to high dielectric constant materials to overcome erase saturation is to introduce curvature in the memory cell. For example, a nanowire cell has a central body, concentric rings of increasing diameter, including tunnel oxide rings, silicon nitride rings and blocking oxide rings, and a surrounding gate. However, curvature that is small enough to increase the electric field tends to result in program disturb effects and read disturb effects.

US Pat. No. 7,075,828

  The BE-SONOS technology has been found to overcome many of the problems of the prior art SONOS type memory, such as erase speed, durability, and charge retention, and provide superior performance. However, the problem of erase saturation continues to limit device operating parameters. Furthermore, it is expected that the erase saturation problem will become more serious as the device size is reduced.

  Accordingly, it would be desirable to provide a new memory technology that is easily manufactured in high quality and that overcomes the erasure saturation problem of the prior art technology.

  One aspect of the present technology is a charge trap memory that includes an array of memory cells. Each memory cell in the array includes a gate, a channel material having a channel surface, a dielectric stack between the gate and the channel surface, and a control circuit.

  The dielectric stack includes a multilayer tunnel structure over the channel surface, a first charge storage nitride layer over the multilayer tunnel structure, and a first blocking oxide layer over the first charge storage nitride layer. A second charge storage nitride layer over the first blocking dielectric layer and a second blocking oxide layer over the second charge storage nitride layer.

  The multi-layer tunnel structure includes a first tunnel oxide layer, a first tunnel nitride layer over the first tunnel oxide layer, and a second tunnel oxide layer over the first tunnel nitride layer. Including.

  The control circuit applies a selected one of a plurality of bias arrangements including a program bias arrangement and an erase bias arrangement. A program bias arrangement programs data by moving electrons from the channel surface through a multilayer tunnel structure including a first tunnel nitride layer to the first charge storage nitride layer. The erase bias arrangement moves holes from the channel surface to the first charge storage nitride layer, and using the accumulated electrons in the second charge storage nitride layer, further electrons are transferred to the first charge storage. Data is erased by preventing migration into the storage nitride layer.

  In another aspect of the present technology, the multilayer tunnel structure includes at least a first tunnel dielectric layer having a tunnel valence band edge (a valence band edge of the tunnel layer).

  The control circuit applies a selected one of the plurality of bias arrangements. In the erase bias arrangement, at least a portion of the tunnel valence band edge of the first tunnel dielectric layer has a band energy greater than the channel valence band edge at the channel surface. When no bias is applied to the memory, the tunnel valence band edge of the first tunnel dielectric layer has a lower band energy than the channel valence band edge at the channel surface.

  Yet another aspect of the present technology is a memory that includes an array of memory cells. Each memory cell in the array includes a gate, a channel material having a channel surface, and a dielectric stack between the gate and the channel surface. The dielectric stack includes at least a multi-layer tunnel structure over a channel surface including a first tunnel dielectric layer having a tunnel valence band edge, and a first charge storage dielectric layer over the multi-layer tunnel structure; A first blocking dielectric layer over the first charge storage dielectric layer, a second charge storage dielectric layer over the first blocking dielectric layer, and over the second charge storage dielectric layer A second blocking dielectric layer.

Yet another aspect of the present technology is:
Applying a program bias arrangement that programs data by moving electrons from the channel surface of the channel material of the memory cell through the first tunnel nitride of the memory cell to the first charge storage nitride layer of the memory cell And
Data is erased by moving holes from the channel surface of the channel material of the memory cell through the first tunnel nitride of the memory cell to the first charge storage nitride layer of the memory cell, and the second of the memory cell. Applying an erase bias arrangement that increases the electron density in the charge storage nitride layer to prevent further electrons from migrating into the first charge storage nitride layer;
A method for operating a memory including:

  In one embodiment of the present technology, the erase bias arrangement applied by the control circuit increases the electron density in the second charge storage nitride layer.

  In one embodiment of the present technology, erase saturation does not occur for a control circuit that applies an erase bias arrangement to a memory with programmed data with a gate voltage in the range between 20 volts and 24 volts.

  In various embodiments of the present technology, the first tunnel nitride layer is 20 angstroms or less in thickness, the second charge storage nitride layer is at least 35 angstroms in thickness, and the first charge storage nitride The physical layer is thicker than the second charge storage nitride layer.

  In various embodiments of the present technology, the gate comprises polysilicon, such as n-doped polysilicon or p-doped polysilicon.

  Other aspects and advantages of the present technology will become apparent upon review of the detailed description in the following drawings and claims.

FIG. 4 is a simplified diagram of a BE-SONOS memory cell. 1 is a simplified diagram of a BE-SONOS memory cell including a high dielectric constant blocking dielectric. FIG. 2 is a graph of flat band voltage versus erase time for the memory cell of FIG. 4 is a graph of flat band voltage versus erase time for a variation of the memory cell of FIG. 3 is a graph of flat band voltage versus erase time for the memory cell of FIG. FIG. 3 is a simplified diagram of a BE-SONOS memory cell modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. FIG. 7 is a graph of flat band voltage versus erase time for the memory cell of FIG. 6 and for a memory cell that includes a plurality of nitride layers that accumulate charge but does not include a bandgap engineered tunnel layer. FIG. 7 is a simplified diagram of the modified BE-SONOS memory cell of FIG. 6 with channel tunneling from the channel into the first nitride layer storing charge and into the second nitride layer storing charge. An erase operation for reducing the charge accumulated in the first nitride layer for accumulating charges by electron injection from the gate is shown. FIG. 9 is a band diagram of the modified BE-SONOS memory cell of FIG. 8 and shows how the band diagram varies with the electron density in the second nitride layer that accumulates charge. FIG. 6 shows charge trap efficiency for various nitride thicknesses. FIG. 6 shows charge trap efficiency for various nitride thicknesses. FIG. 6 shows charge trap efficiency for various nitride thicknesses. It is a figure which shows the electric charge trap efficiency of the 1st nitride layer which accumulate | stores an electric charge with thickness reduced. 7 is a graph of flat band voltage versus erase time for the memory cell of FIG. 7 is a graph of trapped charge density versus erase time for different nitride layers for charge storage in the memory cell of FIG. FIG. 7 is a graph of electric field versus erase time for different nitride layers for charge storage in the memory cell of FIG. 7 is a graph of flat band voltage versus erase time with different gate materials for the memory cell of FIG. FIG. 7 is a graph of trapped charge density versus erase time for different gate materials and different nitride layers for charge storage in the memory cell of FIG. FIG. 7 is a graph of electric field versus erase time for different gate materials and different nitride layers for charge storage of the memory cell of FIG. 7 is a graph of flat band voltage versus programming time for the memory cell of FIG. FIG. 7 is a graph of trapped charge density versus programming time for different nitride layers for charge storage in the memory cell of FIG. 7 is a graph of electric field versus programming time for different nitride layers for charge storage in the memory cell of FIG. FIG. 7 is a graph of flat band voltage versus erase voltage and programming voltage for different erase and programming times of the memory cell of FIG. 7 is a graph of flat band voltage versus erase voltage and programming voltage for different sets of memory cell layer thicknesses of FIG. 7 is a graph of flat band voltage versus erase voltage and programming voltage for different sets of memory cell layer thicknesses of FIG. 6, showing non-ideal behavior. It is a band figure about the tunnel dielectric layer which applied the band offset technique in a low electric field. It is a band figure about the tunnel dielectric layer which applied the band offset technique in a high electric field. FIG. 3 is a simplified diagram of a two-dimensional NAND array of BE-SONOS memory cells modified to include a plurality of nitride layers that store charge in addition to the nitride layers in the multilayer tunnel structure. FIG. 3 is a simplified diagram of a three-dimensional vertical gate array of BE-SONOS memory cells modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. FIG. 3 is a simplified diagram of a three-dimensional double-gate vertical channel array of BE-SONOS memory cells modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. FIG. 6 is a simplified diagram of a BE-SONOS memory cell that is modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure and is in a pipe-like double gate arrangement. FIG. 6 is a simplified diagram of a BE-SONOS memory cell that is modified to include a plurality of nitride layers that store charge in addition to the nitride layers in the multilayer tunnel structure and is in a “gate all-around” configuration. 1 is a block diagram of an integrated circuit memory that uses memory cells and a bias circuit according to embodiments of the present technology. FIG. FIG. 30 is a photograph of a BE-SONOS memory cell in a three-dimensional vertical gate array, such as FIG. 29, modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. A BE-SONOS memory in a three-dimensional vertical gate array, such as FIG. 29, modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure and having different layer thicknesses It is a photograph of a cell. FIG. 35 is a graph of threshold voltage versus programming voltage for the memory cell of FIG. FIG. 35 is a graph of threshold voltage versus erase time for the memory cell of FIG. 34. FIG. FIG. 35 is a graph of threshold voltage window versus number of memory cells for the memory cell of FIG. FIG. 35 is a graph of threshold voltage window versus number of memory cells for the memory cell of FIG. 34, showing retention time. 7 is an experimental graph of flat band voltage versus erase voltage and programming voltage for one embodiment of the memory cell of FIG. 7 is an experimental graph of flat band voltage versus erase time for one embodiment of the memory cell of FIG. FIG. 7 is a simulated graph of flat band voltage versus erase time for one embodiment of the memory cell of FIG. FIG. 7 is a simulated graph of trapped charge density versus erase time for different nitride layers for charge storage of one embodiment of the memory cell of FIG. 7 is an experimental graph of flat band voltage shift versus programming time for the first programming in one embodiment of the memory cell of FIG. 7 is an experimental graph of charge density versus programming time for different nitride layers for charge storage in the first programming in one embodiment of the memory cell of FIG. FIG. 7 is an experimental graph of flat band voltage shift versus programming time for a first erase after a first programming in one embodiment of the memory cell of FIG. 7 is an experimental graph of charge density versus programming time for different nitride layers for charge storage for a first erase after a first programming in one embodiment of the memory cell of FIG. FIG. 7 is an experimental graph of flat band voltage shift versus programming time for a second programming after a first erase in one embodiment of the memory cell of FIG. 7 is an experimental graph of charge density versus programming time for different nitride layers for charge storage for a second programming after a first erase in one embodiment of the memory cell of FIG. 7 is a graph of threshold voltage versus programming voltage for a memory cell in the three-dimensional vertical gate array of memory cells of FIG. FIG. 7 is a schematic diagram of a divided page three-dimensional vertical gate array of the memory cell of FIG. 6. FIG. 52 is a graph of a single level cell memory window of memory cells in the array of FIG. 51. FIG. FIG. 52 is a graph of a multi-level cell memory window for memory cells in the array of FIG. 51. FIG. FIG. 52 is a graph of program-verification distribution of memory cells in the array of FIG. 51. FIG. FIG. 5 is a graph of program threshold voltage and erase threshold voltage versus number of program cycles and erase cycles. FIG. 5 is a graph of the IV threshold sub-threshold slope versus the number of program and erase cycles. FIG. 4 is a graph of IV characteristics for programmed and erased memory in different numbers of program and erase cycles. FIG. 7 is a simplified diagram of an electric field in a memory cell that is modified to include a plurality of nitride layers that accumulate charge, similar to FIG. It is a figure which shows the flat band voltage holding result of the memory cell after a thermal stress. It is a figure which shows the charge density maintenance result of the memory cell after a thermal stress. It is a figure which shows the charge density maintenance result of the memory cell after a thermal stress. It is a figure which shows the memory window holding | maintenance result of the memory cell after a thermal stress. The charge loss rate of a memory cell at various temperatures is shown. FIG. 6 shows an erase comparison of different gate doping or work function and O2 thickness. It is a figure which shows a read-out disturb test. FIG. 3 is a schematic diagram of a vertical channel embodiment.

  Detailed descriptions of embodiments of the present technology will be given with reference to the drawings.

  FIG. 6 is a simplified diagram of a BE-SONOS memory cell modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure.

  The memory cell includes a channel 10 in the channel material, and a source 11 and a drain 12 adjacent to the channel 10. The gate 18 in this embodiment includes p polysilicon. n polysilicon can also be used. Other embodiments use a metal, metal compound, or a combination of metal and metal compound, such as platinum, tantalum nitride, metal silicide, aluminum or other metal or metal compound gate material, for the gate 18. Such materials are typically deposited using sputtering and physical vapor deposition techniques and can be patterned using reactive ion etching.

  The dielectric tunnel layer includes a composite of materials, and includes a plurality of layers including a first tunnel layer 13 of silicon oxide, a tunnel layer 14 of silicon nitride, and a second tunnel layer 15 of silicon oxide. Yes.

  The first tunnel layer 13 of silicon dioxide on the surface 10a of the channel 10 may optionally be subjected to post-deposition NO annealing or deposition, for example using in-situ steam generation (ISSG). Formed by performing nitride formation either by adding NO to the atmosphere. The thickness of the first layer 13 of silicon dioxide is less than 20 mm, preferably 7-15 mm. The first tunnel layer 13 can be processed with alternatives such as nitride oxide to improve durability and / or with fluorine treatment to improve interface state quality.

The tunnel layer of silicon nitride 14, also referred to as the tunnel nitride layer, is located on the first layer 13 of silicon oxide and uses, for example, low pressure chemical vapor deposition LPCVD, for example dichlorosilane DCS and NH at 680 ° C. Formed using _three precursors. In an alternative process, the tunnel nitride layer includes silicon oxynitride created using a similar process using an N ₂ O precursor. The thickness of the silicon nitride layer 14 is less than 30 mm, preferably 10-30 mm, and includes, for example, 20 mm. Layer 14 does not accumulate enough charge due to its thinness.

Layer 14 provides a low hole barrier height to facilitate hole injection for -FN erase. However, layer 14 has low trapping efficiency. With various materials and silicon layer 14, their valence band _{offsets, SiO 2 4.4eV, Si 3 N} 4 1.8eV, Ta 2 O 5 3.0eV, BaTiO 3 2.3eV, BaZrO 3 3. 4 eV, ZrO ₂ 3.3 eV, HfO ₂ 3.4 eV, Al ₂ O ₃ 4.9 eV, Y ₂ O ₃ 3.6 eV, ZrSiO ₄ 3.4 eV. Si ₃ N ₄ has the lowest hole barrier height at 1.8 eV, but other materials may be used.

A second tunnel layer 15 of silicon dioxide is located over the tunnel layer 14 of silicon nitride and is formed using, for example, LPCVD high temperature oxide HTO deposition. The thickness of the second tunnel layer 15 of silicon dioxide is less than 45 mm, preferably 15 mm to 45 mm, for example 30 mm. The second tunnel layer 15 provides a sufficient barrier thickness to prevent charge loss to improve charge retention quality. The second tunnel layer 15 prevents direct tunnel leakage. Other low leakage oxides such as Al ₂ O ₃ may be used.

The first charge storage layer 16 in this embodiment comprises silicon nitride, which has a thickness greater than 45 mm, preferably 45 mm to 80 mm, in this embodiment formed using, for example, LPCVD, for example About 55cm is included. Other charge trap materials and structures can be used including, for example, trap layers embedded with silicon oxynitride (Si _x O _y N _z ), silicon rich nitride, silicon rich oxide, nanoparticles, and the like. Various charge trapping materials are described in US Patent Application Publication No. 2006/0261401 issued November 23, 2006 entitled "Novel Low Power Non-Volatile Memory and Gate Stack" by Bhattacharyya. . Alternative to high charge trapping efficiency, oxynitride, silicon rich nitride, nanoparticles and HfO ₂ embedded.

A first blocking layer 17 of silicon dioxide is located on the first charge storage layer 16 and is formed using, for example, LPCVD high temperature oxide HTO deposition. The thickness of the first blocking layer 17 of silicon dioxide is less than 70 mm. This includes, for example, a range of 35 to 70 inches, and further includes, for example, 50 inches. The first blocking layer 17 provides a sufficient barrier thickness to prevent charge mixing and charge transport between the charge storage layers 16 and 19. Other low leakage oxides such as Al ₂ O ₃ are also possible.

The second charge storage layer 19 in this embodiment comprises silicon nitride, and in this embodiment formed using, for example, LPCVD, it has a thickness greater than 30 inches. This includes, for example, a range of 30 to 60 inches, and further includes, for example, about 40 inches. In other embodiments, it is similar to the first charge trapping layer. The second charge storage layer 19 traps electrons during -FN erasure to stop gate electron injection and enables continuous erasure of the first charge storage layer 16 by channel hole injection. Alternative to high charge trapping efficiency, oxynitride, silicon rich nitride, nanoparticles and HfO ₂ embedded.

  A second blocking layer 20 of silicon dioxide is located on the second charge storage layer 19 and is formed using, for example, LPCVD high temperature oxide HTO deposition. The thickness of the second blocking layer 20 of silicon dioxide is less than 60 mm. This includes, for example, a range of 30 to 60 inches, and further includes, for example, 35 inches.

The gate 18 comprises a material selected to provide a sufficient electron barrier height for the blocking dielectric layer. Materials that can be used for the gate 18 include N polysilicon, P polysilicon, Ti, TiN, Ta, TaN, Ru, Pt, Ir, RuO ₂ , IrO ₂ , W, WN, and the like. Because P-polysilicon has a higher work function than N-polysilicon, P-polysilicon has the advantages of easy manufacturing possibilities and process integration.

  In one embodiment, there are only two nitride layers in addition to the tunnel nitride layer. In FIG. 6, in addition to the tunnel nitride layer, only two nitride layers are two charge storage layers.

  FIG. 7 is a graph of flat band voltage versus erase time for the memory cell of FIG. 6 and for a memory cell that includes a plurality of nitride layers that accumulate charge and does not include a bandgap engineered tunnel layer.

  BE modified to include a plurality of charge storage nitride layers having an O1 / N1 / O2 / N2 / O3 / N3 / O4 layer thickness of 11 Å / 20 Å / 25 Å / 55 Å / 50 Å / 40 Å / 35 層The result of the erase operation at a gate voltage of −22V for the −SONOS memory cell is a simulated curve 710. Modified to include multiple charge storage nitride layers with no band gap engineered tunnel layer and layer thickness O1 / N1 / O2 / N2 / O3 of 30/55/50/40/35 The result of an erase operation with a gate voltage of −22V for a SONOS memory cell is a simulated curve 720. Curve 710 reaches a target voltage 730 of -4V in about 2 milliseconds. However, the curve 720 reaches only about 4V even after 1 second. The difference between the curves indicates that the erase operation is slow when there is no multilayer tunnel structure.

  FIG. 8 is a simplified diagram of the modified BE-SONOS memory cell of FIG. 6, with hole tunneling from the channel into the first nitride layer storing charge and second nitriding storing charge. An erase operation for reducing the charge accumulated in the first nitride layer for accumulating charges by electron injection from the gate into the material layer is shown.

  Electron injection occurs from the gate 18, through the upper blocking dielectric 20 and into the upper charge storage layer 19. Hole tunneling occurs from the channel material 10 and enters the lower charge storage layer 16 through the tunnel layers 13-15.

  FIG. 9 is a band diagram of the modified BE-SONOS memory cell of FIG. 8, showing how the band diagram varies with the electron density in the second nitride layer that accumulates charge.

Curves 910 and 913 show the conduction band edge and the valence band edge of the second nitride charge storage layer 19 without N3, ie, no electrons trapped in the second nitride charge storage layer 19, respectively. Curves 920 and 923 show the conduction band edge and valence electrons of the second nitride charge storage layer 19 having a density of N 3, that is, an electron trapped in the second nitride charge storage layer 19 of 6 × 10 ¹² cm ^−2. Each band edge is shown. Curves 930 and 933 respectively indicate the conduction band of the second nitride charge storage layer 19 having a density of 1.2 × 10 ¹³ cm ⁻² of electrons trapped in N 3, the second nitride charge storage layer 19. Edge and valence band edge are shown respectively.

  As the density of trapped electrons in N3 increases, the conduction band edge size of N3 increases. The conduction band edges of adjacent portions of O4 and O3 also increase in size. This conduction band edge shift reduces the conduction band edge gradient at O4, which indicates a reduction in the magnitude of the electric field at O4, which suppresses erase saturation.

  Hole injection through the tunnel layer O1 / N1 / O2 is facilitated by the band edge offset of N1. Hole injection through the tunnel layer will be further discussed in connection with FIGS.

  FIGS. 10-12 show charge trap efficiencies for various nitride thicknesses.

  In FIG. 10, the erase operation is performed on a SONOS memory cell having an O / N / O thickness of 54/70/90.

The result of the erase operation with a gate voltage of 18V is a simulated curve 1010 and experimental data plot point 1011. The result of the erase operation with a gate voltage of 19V is a simulated curve 1020 and experimental data plot point 1021. The result of the erase operation with a gate voltage of 20V is a simulated curve 1030 and experimental data plot point 1031. A sufficiently thick SiN (> 70 Å) has a high capture rate close to ideal full capture. There is no problem as long as the electron trap density exceeds 10 ¹³ cm ⁻² .

  In FIG. 11, the erase operation is performed on a SONOS memory cell having an O / N / O thickness of 54/35/90.

The result of the erase operation with a gate voltage of 16V is a simulated curve 1110 and experimental data plot point 1111. The result of the erase operation with a gate voltage of 17V is a simulated curve 1120 and experimental data plot point 1121. The result of the erase operation with a gate voltage of 18V is a simulated curve 1130 and experimental data plot point 1131. For thinner SiN (<35 Å), the trapping efficiency is greatly reduced. The graph shows the results for the intermediate SiN layer of the SONOS memory cell. This result shows the thickness of SiN in other structures. For example, the second charge storage nitride layer 19 of FIG. 6 is thick enough to store sufficient electron charge to prevent electron injection from the gate. An electron charge density of at least 5 × 10 ¹² cm ⁻² can prevent electron injection from the gate.

  In FIG. 12, the erase operation is performed on a SONOS memory cell having an O / N / O thickness of 54/20/90.

  The result of the erase operation with a gate voltage of 14V is a simulated curve 1210 and experimental data plot point 1211. The result of the erase operation with a gate voltage of 15V is a simulated curve 1220 and experimental data plot point 1221. Very thin SiN (<20Å) nitride results in low or ineffective field traps. For this reason, such thin layers are used in multilayer tunnel structures to provide a band offset effect without charge accumulation.

  FIG. 13 is a diagram showing the charge trapping efficiency of the first nitride layer that accumulates charges with a reduced thickness.

In a BE-SONOS memory cell including a bandgap engineered tunnel layer with an O1 / N1 / O2 thickness of 13/20/25 mm by an erase operation, in response to a 20 μs erase pulse from the gate voltage on the x-axis, y The flat band voltage ΔV _{FB at the} axis changes. The result of the erase operation when the thickness of N2 / O3 is 70/90 mm is a curve 1310. The result of the erase operation when the thickness of N2 / O3 is 50/90 is curve 1320. These results show that when O3 thickness is 90 mm, even if N2 thickness is reduced to only 50 mm, the result is an excellent ISPP slope similar to 70 mm N2 thickness. Is shown. Therefore, N2 can be reduced to 50 mm while still maintaining excellent trap efficiency.

  14 to 16, the plurality of charge storage nitride layers are changed, and the thickness of O1 / N1 / O2 / N2 / O3 / N3 / O4 is 11 Å / 20 Å / 25 Å / 55 Å / 50 Å / 40 Å / 35 ｐ. An erase operation is performed on a SONOS memory cell having a polysilicon gate.

FIG. 14 is a graph of flat band voltage versus erase time for the memory cell of FIG. The result of the erase operation with a gate voltage of −20V is a simulated curve 1410. The result of the erase operation with a gate voltage of −21V is a simulated curve 1420. The result of the erase operation with a gate voltage of −22V is a simulated curve 1430. The result of the erase operation with a gate voltage of −23V is a simulated curve 1440. The result of the erase operation with a gate voltage of −24V is a simulated curve 1450. The -4V target voltage 1460 is achieved more quickly if the gate voltage is increased in the negative direction. With a gate voltage of -23V or -24V, the target voltage is achieved within 1 millisecond. Since erasure saturation is not observed when V _FB <−8 V, a faster erase time can be obtained as the magnitude of the erase bias is higher.

  FIG. 15 is a graph of trapped charge density versus erase time for different nitride layers for charge storage in the memory cell of FIG.

The result of the erase operation with a gate voltage of −24V is a simulated curve 1510 for the density of trapped charges at N2. The result of the erase operation with a gate voltage of −24V is a simulated curve 1520 for the trapped charge density at N3. When V _FB is about −4V, the area density of trapped electrons approaches about 5 × 10 ¹² cm ⁻² in N3.

  The simulation shows that -FN gate injection of electrons into N3 occurs and N3 traps electrons. As the density of trapped electrons in N3 increases, the trapped electrons in N3 gradually delay electron injection from the gate. As N3 traps electrons, N2 continues to trap holes injected from the channel material. The overall effect is that the density of trapped electrons in N3 helps stop gate injection, allows continuous hole injection into N2, and N2 is continuously erased without erase saturation. That's what it means.

  FIG. 16 is a graph of field versus erase time for different nitride layers for charge storage in the memory cell of FIG. The result of the erase operation with a gate voltage of −24V is a simulated curve 1610 for the electric field at N2. The result of the erase operation with a gate voltage of −24V is a simulated curve 1620 for the electric field at N3.

  Simulations show that the electric field at the bottom O1 decreases while the electric field at the top O3 increases significantly during -FN erase. Since the electric field at O3 is high, high oxide quality of O3 is important.

  17 to 19, the plurality of charge storage nitride layers are changed, and the thickness of O1 / N1 / O2 / N2 / O3 / N3 / O4 is 11 mm / 20 mm / 25 mm / 55 mm / 50 mm / 40 mm / 35 mm. An erase operation is performed on the SONOS memory cell.

  FIG. 17 is a graph of flat band voltage versus erase time with different gate materials for the memory cell of FIG.

  The result of an erase operation with a gate voltage of −24V with a p polysilicon gate is a simulated curve 1710. The result of an erase operation with a gate voltage of −24V with an n polysilicon gate is a simulated curve 1720. Whether the gate is n-doped or p-doped, the resulting curve does not show erase saturation.

  FIG. 18 is a graph of trapped charge density versus erase time for different gate materials and different nitride layers for charge storage in the memory cell of FIG.

  The result of an erase operation with a gate voltage of −24V by the p polysilicon gate is a simulated curve 1810 of the charge trapped at N2. The result of an erase operation with a gate voltage of −24V by the p polysilicon gate is a simulated curve 1820 of the charge trapped at N3. The result of an erase operation with a gate voltage of −24V by the n polysilicon gate is a simulated curve 1830 of the charge trapped at N2. The result of an erase operation with a gate voltage of -24V with an n polysilicon gate is a simulated curve 1840 of the charge trapped at N3.

  Simulations show that N3 trapped electrons increase the density with the N gate and compensate for the effects of larger gate injection of electrons. This increase in electron density allows N2 to be continuously erased by hole injection from the channel.

  FIG. 19 is a graph of field versus erase time for different gate materials of the memory cell of FIG. 6 and different nitride layers for charge storage.

  The result of the erase operation with a gate voltage of −24V with the n polysilicon gate is a simulated curve 1910 of the electric field at O1. The result of an erase operation with a gate voltage of -24V with an n polysilicon gate is a simulated curve 1920 of the electric field at O3. The result of the erase operation with a gate voltage of −24V with the p polysilicon gate is a simulated curve 1930 of the electric field at O1. The result of the erase operation with a gate voltage of −24V with the p polysilicon gate is a simulated curve 1940 of the electric field at O 3.

  Multiple charge storage nitride layer BE-SONOS devices are highly resistant to changes in gate implantation. Whenever the electron gate injection becomes large (due to poly gate doping change or electric field enhancement effect), N3 is in contrast to the increased electron gate injection due to the higher charge density of the trapped electrons. Can be compensated. By increasing the charge density of electrons in N3, N2 can continue to be erased by hole injection from the channel.

  20 to 22, the plurality of charge storage nitride layers are changed so that the thickness of O1 / N1 / O2 / N2 / O3 / N3 / O4 is 11 mm / 20 mm / 25 mm / 55 mm / 50 mm / 40 mm / 35 mm. A program operation is performed on a certain SONOS memory cell.

  FIG. 20 is a graph of flat band voltage versus programming time for the memory cell of FIG.

  The result of the program operation with a + 24V gate voltage is a simulated curve 2010. The result of the program operation with a gate voltage of + 23V is a simulated curve 2020. The result of the program operation with a + 22V gate voltage is a simulated curve 2030. The result of the program operation with a gate voltage of + 21V is a simulated curve 2040.

  FIG. 21 is a graph of trapped charge density versus programming time for different nitride layers for charge storage in the memory cell of FIG.

  The result of the program operation with a + 24V gate voltage is a simulated curve 2110 of charge trapped at N2. The result of the program operation with a gate voltage of + 24V is a simulated curve 2120 of the charge trapped at N3.

  FIG. 22 is a graph of electric field versus programming time for different nitride layers for charge storage in the memory cell of FIG.

  The result of the program operation with a gate voltage of + 24V is a simulated curve 2210 of the electric field at O1. The result of the program operation with a gate voltage of + 24V is a simulated curve 2220 of the electric field at O3. The result of the program operation with a gate voltage of + 24V is a simulated curve 2230 of the electric field at O4.

As more electrons are injected into N2, the electric field at O3 increases. As the electric field at O3 increases, the number of detrapped electrons in N2 toward N3 gradually increases. Thus, at higher electron injection levels (V _FB > 6V), more electrons are trapped in N3. Programming saturation is still not observed, and memory cells can be continuously programmed to V _FB > 8V, which is more than sufficient for an MLC (multilevel cell) operating window.

  FIG. 23 is a graph of flat band voltage versus erase voltage and programming voltage for different erase and programming times of the memory cell of FIG.

  SONOS with p polysilicon gates modified with multiple charge storage nitride layers and O1 / N1 / O2 / N2 / O3 / N3 / O4 thicknesses of 11/20/25/55/50/40/35 A program operation and an erase operation are performed on the memory cell.

  The ISP distribution operation and the ISPE operation make the Vt distribution tight. ISPP is incremental step pulse programming that programs the memory in steps to gradually increase the programming voltage. ISPE is incremental step pulse erasing where the device is erased in stages by gradually increasing the erase voltage.

  The result of the program operation with an incremental step pulse program with a pulse time of 20 microseconds is a simulated curve 2310. The result of the program operation with an incremental step pulse program with a pulse time of 200 microseconds is a simulated curve 2320. The result of the program operation with an incremental step pulse program with a pulse time of 2 milliseconds is a simulated curve 2330.

  The result of an erase operation with incremental step pulse erase with a pulse time of 20 microseconds is a simulated curve 2340. The result of the erase operation with incremental step pulse erase with a pulse time of 200 microseconds is a simulated curve 2350. The result of an erase operation with incremental step pulse erase with a pulse time of 2 milliseconds is a simulated curve 2360.

The curve shows a large ISPP / ISPE window without saturation before V _FB = ± 8V. The slopes of the ISPP and ISPE curves are close to the ideal 1 slope.

  In the case of a small memory cell, the charge storage efficiency decreases due to the three-dimensional fringe field effect. Accordingly, the Vt or flat band voltage (VFB) of the three-dimensional memory cell is lower than the Vt or flat band voltage (VFB) of the one-dimensional memory cell. In the case of a three-dimensional memory cell, programming and erasure are overdriven to simulate an actual device / transistor window.

In one embodiment, V _FB = + 5V is reached at approximately + 23V for 20 microseconds, and V _FB = −4V is reached at −23V for 2 milliseconds. The threshold voltage Vt is about + 3V to + 4V for programming, and the threshold voltage Vt is about −2V to −3V for erasing. These program and erase threshold voltages are suitable for multi-level (MLC) memory windows. An MLC memory cell having four logic levels requires a wider memory window than a two-level memory cell.

  FIG. 24 is a graph of flat band voltage versus erase voltage and programming voltage for different sets of memory cell layer thicknesses of FIG.

  Program and erase operations are performed on SONOS memory cells that include a p-polysilicon gate and have a plurality of charge storage nitride layers modified.

  The results of the ISPP program operation with 20 microsecond program pulses with O1 / N1 / O2 / N2 / O3 / N3 / O4 thicknesses of 11 mm / 20 mm / 25 mm / 55 mm / 50 mm / 40 mm / 35 mm were simulated. Curve 2410. The results of the ISPP program operation with 20 microsecond program pulses with O1 / N1 / O2 / N2 / O3 / N3 / O4 thicknesses of 11 mm / 20 mm / 25 mm / 50 mm / 45 mm / 35 mm / 30 mm were simulated. Curve 2420.

  The results of the ISPE erase operation with an erase pulse of 2 ms with O1 / N1 / O2 / N2 / O3 / N3 / O4 thicknesses of 11 mm / 20 mm / 25 mm / 55 mm / 50 mm / 40 mm / 35 mm were simulated. Curve 2430. The results of the ISPE erase operation with a 2 ms erase pulse with O1 / N1 / O2 / N2 / O3 / N3 / O4 thicknesses of 11 mm / 20 mm / 25 mm / 50 mm / 45 mm / 35 mm / 30 mm were simulated. Curve 2440.

  By slightly reducing the layer thickness, the programming voltage is reduced by about 1V to 2V to Vpgm = 21V.

  FIG. 25 is a graph of flat band voltage versus erase voltage and programming voltage for different sets of memory cell layer thicknesses of FIG. 6 and shows non-ideal behavior. The non-ideal behavior is explained as follows. If the charge injected by tunneling is not 100% trapped and trapped in the nitride, the injection efficiency may be less than ideal and the ISPP / ISPE slope may not be equal to 1. This can occur if the thickness of N2 and N3 is insufficient (eg, N2 <4 nm). If there is charge mixing or transport between N2 and N3 during programming / erasing, the ISPP / ISPE slope can also degrade. This can occur when the thickness of O3 is not sufficient (eg, O3 <3 nm).

  FIG. 25 shows curves 2410 and 2430 similar to FIG. However, in FIG. 25, the thickness of the charge storage nitride layer N2 and / or N3 is too thin to show the ideal gradient of ISPP and ISPE. In the physical model, the charge trapping process has a scattering mean free path and the trapping efficiency decreases exponentially when the thickness is less than the mean free path. Alternatively, the blocking oxide layer O3 allows excessive tunneling of electrons into the first nitride charge storage layer. Such non-ideal behavior causes curve 2410 to degrade to curve 2510 and curve 2420 to degrade to curve 2520.

In curve 2510, gradual saturation occurs with V _FB > +8 V, and the non-ideal ISPP slope is not equal to 1 and less than 0.95. Since the blocking oxide layer is too thin, outward tunneling is increased. Charge exchange occurs between N2 / N3 during high electric field + FN tunneling.

In curve 2520, gradual saturation occurs with V _FB > −8 V, and the non-ideal ISPE slope is not equal to 1 and less than 0.95.

  As shown in connection with FIG. 18, there are insufficient electron traps in N3 to stop further electron gate injection. If there is not enough density of electrons trapped in N3 to stop further electron gate injection, the gate injected electrons will reach N2 resulting in slight erase saturation. Charge exchange between N2 / N3 occurs during high electric field-FN tunneling.

  If the thickness of O3 is too small, charge exchange between N2 / N3 may occur. For example, during -FN erase, electrons are trapped in N3 and holes are trapped in N2. When charge exchange occurs, the trapped electrons can travel to N2, thereby degrading the erase window.

  Blocking oxide O3 between N2 and N3 maintains erase performance and avoids excessive non-ideal charge transport between N2 and N3. Excellent charge trapping efficiency is maintained by the sufficient thickness of N2 and N3. As shown in FIGS. 10-13, an N2 thickness of at least 50 も た ら provides sufficient charge storage for the memory window, and an N3 thickness of at least 30 を provides additional electron gate injection. Sufficient charge accumulation is provided to prevent.

  26 is a diagram of the energy levels of the conduction and valence bands of a dielectric tunnel structure including a stack of layers 13-15 of FIG. 1 under a low electric field, the “U-shaped” conduction band and the “inverted U-shaped”. The “type” valence band. From the right side, region 2630 shows the bandgap of the semiconductor body, region 2631 shows the valence and conduction bands for the hole tunnel layer, and region 2632 shows the tunnel nitride layer. The band gap is shown, region 2633 shows the valence band and conduction band for the insulating layer, and region 2634 shows the valence band and conduction band for the charge trapping layer. Electrons represented by a negatively signed circle and trapped in the charge trapping region 2634 cannot tunnel to the conduction band in the channel. This is because the conduction band of the tunnel dielectric layer in all three regions 2631, 2632, 2633 remains high compared to the trap energy level. The likelihood of electron tunneling correlates with the region below the “U-shaped” conduction band in the tunnel dielectric layer and above the horizontal line at the energy level of the trap into the channel. Therefore, electron tunneling is very difficult to occur in a low electric field state. Similarly, holes in the valence band of the channel in region 2630 tunnel to charge trap layer 2634 due to the total thickness of regions 2631, 2632 and 2633, and the height of the high hole tunneling barrier at the channel interface. Be blocked. The likelihood of hole tunneling correlates with the region above the “inverted U-shaped” valence band in the tunnel dielectric layer and below the horizontal line at the energy level of the channel to the charge trapping layer. Therefore, hole tunneling is very difficult to occur in a low electric field state. In an exemplary embodiment where the hole tunnel layer comprises silicon dioxide, a hole tunneling barrier height of about 4.5 eV prevents hole tunneling. The valence band in silicon nitride remains 1.9 eV lower than the valence band in the channel. Thus, the valence band in all three layers 2631, 2632, 2633 of the tunnel dielectric structure remains significantly lower than the valence band in channel 2630, and all the valence bands in layer 2632 remain in valence in channel 2630. It has a lower band energy than the electron band. Thus, the tunnel layers described herein are characterized by band offset properties, and are relatively large hole tunneling barrier heights in the thin region (layer 2631) at the interface with the semiconductor body and from the channel surface. Valence band energy level increase 2637 at a first offset of less than 2 nm. The band offset characteristics also include a valence band energy level reduction 2638 at the second offset from the channel by having a thin layer 2633 of material with a relatively high tunneling barrier height, which is inverted U-shaped. Resulting in a valence band shape of Similarly, the conduction band has a U-shape resulting from the selection of similar materials.

  FIG. 27 shows a band diagram for a dielectric tunnel structure under a field condition of about −12 MV / cm of tunnel layer 2731 for the purpose of inducing hole tunneling (in FIG. 3, the O1 layer is about 15 mm thick) Is). Under an electric field, the valence band tilts upward from the channel surface. Therefore, at the offset distance from the channel surface, the valence band in the tunnel dielectric structure has a greatly increased band energy level, and in the figure rises above the band energy of the valence band in the channel region. The edge of the valence band of the layer 2632 has a higher band energy than the valence band in the channel 2630. Therefore, as the region between the level of the valence band in the channel and the above-described tilted inverted U-shaped valence band in the tunnel stack (shaded in FIG. 27) decreases, the likelihood of hole tunneling is increased. Increases significantly. The band offset effectively eliminates the blocking function of the tunnel nitride layer in region 2732 and the isolation layer in region 2733 from the tunnel dielectric during the application of a high electric field, resulting in a relatively small electric field (eg, E <14 MV / large hole tunneling currents under (cm).

  The isolation layer 2733 isolates the tunnel nitride layer 2732 from the charge trap layer 2734. This increases the effective blocking ability during application of a low electric field to both electrons and holes, improving charge retention.

  The tunnel nitride layer 2732 in this embodiment must be thin enough so that the charge trapping efficiency is negligible. The tunnel nitride layer is a dielectric, not a conductor. Thus, in embodiments using silicon nitride, the tunnel nitride layer should be less than 30 inches thick, and more preferably about 25 inches or less.

  The hole tunnel layer 2731 should be less than 20 inches thick, and more preferably less than 15 inches thick in embodiments using silicon dioxide. For example, in a preferred embodiment, the hole tunneling layer 2731 is about 13 mm thick silicon dioxide and is exposed to a nitridation process as described above, resulting in ultra-thin silicon oxynitride.

  In embodiments of the present technology, a composite of silicon oxide, silicon oxynitride, and silicon nitride provides the required inverted U-shaped valence band and is required for efficient hole tunneling at an offset distance from the channel surface. As long as they have a change in the valence band energy level, the composite of these can be used to implement a tunnel dielectric layer without accurately switching between the layers. Other combinations of materials can also be used to provide band offset technology.

  The description of the dielectric tunnel layer focuses on “hole tunneling” rather than electron tunneling. This is because the present technology has solved a problem related to the necessity of relying on hole tunneling in a SONOS type memory. For example, a tunnel dielectric made of silicon dioxide that is thin enough to support hole tunneling at a practical rate would be too thin to prevent leakage due to electron tunneling. However, the effect of the present technology also improves the performance of electronic tunneling. Thus, both programming by electron tunneling and erasure by hole tunneling are greatly improved using bandgap engineering.

  FIG. 28 is a simplified diagram of a two-dimensional NAND array of BE-SONOS memory cells modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure.

  FIG. 6 illustrates a portion of a NAND string of a BE-SONOS memory cell that has been modified to include a plurality of nitride layers that accumulate charge. Memory cells 2810 and 2820 are examples of the memory cell shown in FIG. Memory cells 2810 and 2820 are on channel material 2830. As a dielectric between adjacent memory cells 2810 and 2820, an insulating dielectric such as an oxide or air gap can be filled to suppress leakage between adjacent word lines. The ONONONO layer may be discontinuous for each of the memory cells 2810 and 2820 or may be continuous between adjacent memory cells 2810 and 2820. The channel material between adjacent memory cells 2810 and 2820 may or may not have junctions with varying levels of doping.

  FIG. 29 is a simplified diagram of a three-dimensional vertical gate array of BE-SONOS memory cells modified to include a plurality of nitride layers that store charge in addition to the nitride layers in the multilayer tunnel structure. FIG. 29 is a perspective view of a NAND flash array, illustrated in such a way that the strips of semiconductor material are joined together into a single decoding structure, and the hard mask and optional implantation steps are shown. . 29 is rotated so that the Y-axis and the Z-axis are in the plane of the paper.

  The insulating layer between the semiconductor material strips in the protruding stack has been removed from the drawing to expose additional structures.

  The multi-layer array is formed on the insulating layer 610 and includes a plurality of conductive lines 625-1,..., 625-n formed in accordance with a plurality of protruding stacks, which are word lines WLn, WLn-1,. Works as. The plurality of protruding stacks includes semiconductor material strips 612, 613, 614 that are coupled by extension portions 612A, 613A, 614A to semiconductor material strips in the same plane within the parallel protruding stack. These extensions 612A, 613A, 614A of the semiconductor material strip are oriented along the X-axis direction and are coupled to a plurality of protruding stacks of semiconductor material strip. Also, as will be described later, these extensions 612A, 613A, 614A extend beyond the end of the array and are arranged to be connected to a decoding circuit for selecting a plane in the array. Yes. These extensions 612A, 613A, 614A are patterned at the same time as the plurality of protruding stacks are defined or when a layer of alternating semiconductor and insulator materials is formed prior to it. be able to.

  In some embodiments, the extensions 612A, 613A, 614A form a stepped structure that terminates the semiconductor material strips 612, 613, 614. These extensions 612A, 613A, 614A can be patterned simultaneously when a plurality of protruding stacks are defined.

  A layer of memory material 615 comprising a multilayer charge trapping structure ONONONO separates conductive lines 625-1 to 625 -n from semiconductor material strips 612 to 614 as detailed above.

  A transistor, for example, a transistor 650 is formed between the extension portions 612A, 613A, and 614A and the conductive line 625-1. A transistor, for example transistor 651, is also formed at the opposite end of the semiconductor material strip to control connection to a common source line (not shown) of the sectors of the array. In transistors 650, 651, a semiconductor material strip (eg, 612) operates as the channel region of the device. The gate structure (eg, 629, 649) is patterned during the same steps as the conductive lines 625-1 to 625-n are defined. The GSL select line 649 can be directed across a plurality of protruding stacks of semiconductor material strips along a row. A silicide layer 626 may be formed along the top surface of the conductive lines and over the gate structures 629,649. The layer of memory material 615 can act as a gate dielectric for the transistor. These transistors 650, 651 operate as select gates coupled to a decoding circuit to select sectors and columns along the protruding stack in the array.

  Optional fabrication steps include forming hard masks 601-1 through 601-n over a plurality of conductive lines, hard mask 648 over GSL select line 649, and hard masks 602 and 603 over gate structure 629. Including that. The hard mask can be formed using a relatively thick layer of silicon nitride or other material that can block the ion implantation process. Selected embodiments to increase the doping concentration in the semiconductor material strips 612-614 and extensions 612A-614A after the hard mask is formed, thereby reducing the resistance of the current path along the semiconductor material strip. Depending on the n-type dopant or p-type dopant implant 600 can be applied. Also, a dopant of a conductivity type opposite to that of the bulk semiconductor material strip (eg, n-type implant, assuming a p-type semiconductor material strip) is applied, and if desired, doped along the semiconductor material strip. Source / drain junctions can be formed. By utilizing controlled implantation energy, the implant can be penetrated through the bottom semiconductor material strip 612 and each of the semiconductor material strips overlying in the stack.

  To program a selected memory cell, in this embodiment, the selected word line is biased at +20 volts, the unselected word line is set to +10 volts, and the selected bit line is Set to 0 volts, set unselected bit lines to 0 volts, set selected SSL lines to 3.3 volts, and unselected SSL and GSL lines to 0 volts It is possible to set. To read selected cells, in this embodiment, the selected word line is biased with a read reference voltage, the unselected word line is set to 6 volts, and the selected bit line is set to 1 Setting the unselected bit line to 0 volts, setting the selected SSL line to 3.3 volts, and setting the unselected SSL line to 0 volts, Is possible.

FIG. 30 is a schematic diagram of a three-dimensional (3D) memory device 100. The memory device 100 includes an array of NAND strings of memory cells and can be a double gate vertical channel memory array (DGVC). The memory device 100 is separated by an insulating material that includes an integrated circuit substrate and at least a bottom plane (GSL) of the conductive strip, a plurality of intermediate planes (WL) of the conductive strip, and a top plane (SSL) of the conductive strip. A plurality of stacked conductive strips. In the example shown in FIG. 30, the stack 110 includes a conductive strip bottom plane (GSL), a plurality of conductive strip intermediate planes (WL) ranging from WL ₀ to WL _N-1, and a conductive strip top plane. (SSL). Here, N can be 8, 16, 32, 64, or the like.

  The plurality of bit line structures are arranged on the plurality of stacks so as to be orthogonal to the plurality of stacks, and have a surface that fits the plurality of stacks. An element 120 is included. A connecting element 130 on the stack connects the inter-stack semiconductor elements 120. The coupling element 130 in this example includes a semiconductor such as polysilicon having a relatively high doping concentration, thereby providing an inter-stack semiconductor body element 120 configured to provide a channel region for cells in the stack. High conductivity.

  The memory device has an ONONONO structure in an interface region at an intersection 180 between the side of the conductive strips of the plurality of intermediate planes (WL) of the stack and the inter-stack semiconductor body element 120 of the plurality of bit line structures. including. In the illustrated example, the memory cell at intersection 180 is formed into a vertical dual gate NAND string where the conductive strips on either side of a single inter-stack semiconductor body element behave as a dual gate, read operation, erase operation and program. It can be operated in cooperation with the operation.

  A reference conductor 160 is disposed between the bottom plane (GSL) of the conductive strip and the integrated circuit board (not shown). At least one reference line comprising an inter-stack vertical conductive element 140 between the stacks in electrical communication with the reference conductor 160 and a coupling element 150 on the stack 110 connecting the inter-stack vertical conductive elements 140. The structure is disposed orthogonal to them across the plurality of stacks. The inter-stack vertical conductive element 140 may have a higher conductivity than the inter-stack semiconductor body element 120.

  The memory device includes a string selection switch 190 in the interface region of the top plane of the conductive strip and a reference selection switch 170 in the interface region of the bottom plane (GSL) of the conductive strip. The dielectric layer of the charge storage structure can operate as a gate dielectric layer for the switches 170, 190 in some examples.

  The memory device includes a first superimposed patterning conductive layer (not shown) connected to a plurality of bit line structures including a plurality of global bit lines coupled to a sensing circuit. The memory device also includes a second overlying conductive layer (not shown), which can be patterned and can be above or below the first patterned conductive layer. The second superimposed conductive layer is connected to at least one reference line structure by contact with the coupling element 150 or the like. The second patterned conductive layer can be connected to at least one reference line structure to a reference voltage source or to a circuit that provides a reference voltage.

  In the example shown in FIG. 30, the coupling element 130 having a bit line structure includes an N-doped semiconductor material. The inter-stack semiconductor body element 120 having a bit line structure includes a lightly doped semiconductor material. In the example shown in FIG. 30, the reference conductor 160 includes an N-doped semiconductor material, and the connecting element 150 having at least one reference line structure includes an N-doped semiconductor material. The at least one baseline inter-stack vertical conductive element 140 also includes an N-doped semiconductor material. In an alternative embodiment, metals or metal compounds can be used instead of doped semiconductors.

  In one embodiment, to reduce the resistance of the reference conductor 160, the memory device can include a bottom gate 101 near the reference conductor 160. During a read operation, the bottom gate 101 is turned on by an appropriate pass voltage applied to one or more doped wells below the substrate, or the other underlying patterned conductor structure, and the conductivity of the reference conductor 160 is increased. Can be increased.

  FIG. 31 shows a BE-SONOS memory cell in a pipe-like double gate configuration that includes a plurality of nitride layers that accumulate charge in addition to the nitride layers in a multilayer tunnel structure and is modified to form an ONONONNO structure FIG. In the horizontal cross section of the embodiment, the outer surface of the silicon oxide layer 3124 in this example contacts the even word line 3125 along the first arcuate edge 3141 and the odd word line 3126 along the second arcuate edge 3142. Contact. Increasing the average radius of curvature of the first arcuate edge 3141 and the second arcuate edge 3142 significantly reduces the electric field enhancement between the word line and adjacent semiconductor material, and provides read disturb and program to the device. Disturbance can be significantly improved.

  Independent double-gate memory structure embodiments can include cross sections that are square, rectangular, circular and / or other shapes in one or more of the word line layers.

  FIG. 32 shows a BE-SONOS memory cell in a “gate all around” configuration modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. FIG.

  The memory cell of FIG. 32 is similar to FIG. However, the word lines are not divided into odd word lines and even word lines by oxide.

  US patent application Ser. No. 14 / 284,306 is hereby incorporated by reference. The multiple charge storage layer cells described herein may be used with the memory devices disclosed in US patent application Ser. No. 14 / 284,306.

  FIG. 33 uses a blocking dielectric engineered BE-SONOS memory cell as described herein having a plurality of charge storage nitride layers and a bandgap engineered tunnel dielectric layer. It is a simple block diagram of an integrated circuit. Integrated circuit 3310 includes a memory array 3312 that is implemented using a blocking dielectric engineered BE-SONOS memory cell as described herein on a semiconductor substrate. A word line (or row) and block select decoder 3314 is coupled to and in electrical communication with a plurality of word lines and block select lines 3316 and is disposed along a row of the memory array 3312. A bit line (column) decoder and driver 3318 is coupled to a plurality of bit lines 3320 arranged along the columns of the memory array 3312 to read data from and write data to the memory cells of the memory array 3312. And electrically communicate with them. The address is provided on the bus 3322 to the word line decoder and driver 3314 and to the bit line decoder 3318. The sense amplifier and data input structures in block 3324, including current sources for read mode, program mode and erase mode, are coupled to bit line decoder 3318 via data bus 3326. Data is supplied to the data input structure of block 3324 via data input line 3328 from an input / output port of integrated circuit 3310 or from another data source internal or external to integrated circuit 3310. In the illustrated embodiment, other circuitry 3330 is included in the integrated circuit 3310, such as a general purpose processor or dedicated purpose circuit, or a combination of modules that provide system-on-chip functionality supported by a memory cell array. Data is supplied from the sense amplifier of block 3324 via data output line 3332 to an input / output port of integrated circuit 3310 or to another data destination internal or external to integrated circuit 3310.

  The array 3312 can be a NAND array, an AND array, or a NOR array, depending on the particular application. The very large memory window available supports multi-bit storage per cell, so the device can include a multi-bit sense amplifier.

  The controller implemented in this example using the bias configuration state machine 3324 is a bias configuration supply voltage source and current source, such as read, program, erase, erase verify, program verify voltage or current for word and bit lines. Control the use of 3336 and use the access control process to control word line / source line operation. The controller uses a selected one of a plurality of bias arrangements. A program bias arrangement programs data by moving electrons from the channel surface through a multilayer tunnel structure including a first tunnel nitride layer to the first charge storage nitride layer. The erase bias arrangement erases data by moving holes from the channel surface to the first charge storage nitride layer, uses the stored electrons in the second charge storage nitride layer, and further Electrons are prevented from moving into the first charge storage nitride layer.

  The controller 3334 can be implemented using dedicated logic circuitry known in the art. In an alternative embodiment, the controller 3334 includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In still other embodiments, the controller 3334 may be implemented using a combination of dedicated logic and general purpose processors.

  FIG. 34 is a photograph of a BE-SONOS memory cell in a three-dimensional vertical gate array, such as FIG. 29, modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure. It is.

  The thickness of O1 / N1 / O2 / N2 / O3 / N3 / O4 is 10Å / 17Å / 18Å / 69Å / 49Å / 49Å / 34Å. The overall thickness is about 24 nm.

  FIG. 35 is modified to include a plurality of nitride layers that accumulate charge in addition to the nitride layers in the multilayer tunnel structure, and in a three-dimensional vertical gate array such as FIG. 29 having different layer thicknesses. It is a photograph of a BE-SONOS memory cell.

  The thickness of O1 / N1 / O2 / N2 / O3 / N3 / O4 is 10Å / 16Å / 18Å / 57Å / 52Å / 30Å / 34Å. The overall thickness is about 22 nm.

  FIG. 36 is a graph of threshold voltage versus programming (pgm) voltage for the memory cell of FIG. Memory cell 3612 is programmed with an ISPP slope of 0.75. The remaining unselected memory cells 3602, 3604, 3606, 3608, 3610, 3614, 3616, 3618, 3620 show little change in threshold voltage, indicating program inhibit. The program inhibit boost channel voltage was 9V.

  FIG. 37 is a graph of threshold voltage versus erase time for the memory cell of FIG. In FIG. 37, the memory cell is erased with gate voltages of −18V (3710), −20V (3720), and −22 (3730). In FIG. 37, the memory cell shows a memory window of about 12V between 6V and -6V. Erase saturation occurred with deep erase of about -6V. 3DVG NAND erase is slowed by erase that limits the channel hole generation rate caused by gate-induced drain leakage (GIDL).

  FIG. 38 is a graph of threshold voltage window versus number of memory cells for the memory cell of FIG.

  The bit distribution for the checkerboard (CKB) programming state 3810 and erase state 3820 is shown. Checkerboard programming cells are in erase voltage distribution 3812 and program voltage distribution 3811. Bit 3820 that has been erased is also shown.

  FIG. 39 is a graph of threshold voltage window versus number of memory cells for the memory cell of FIG. 34, showing retention time.

  After the initial distribution 3910, a bit number distribution indicating retention at various times, ie, program and erase distributions at a program voltage of 2.5V, and 10 minutes, 300 minutes, 600 minutes, 960 minutes, 1600 minutes and 2700. The bit number distribution at the minute point is almost the same.

  40 is a graph of flat band voltage versus erase voltage and programming voltage for one embodiment of the memory cell of FIG.

  Multiple charge storage with p + polysilicon gate and O1 / N1 / O2 / N2 / O3 / N3 / O4 thickness of about 1 nm / 1.5 nm / 2 nm / 5.5 nm / 5.5 nm / 4 nm / 4 nm A program operation and an erase operation are performed on the SONOS memory cell in which the nitride layer is changed.

  The result of the ISPP program operation with a 200 microsecond program pulse is an experimental curve 4020 with a slope of about 0.9. The result of the ISPE erase operation with an erase pulse of 200 microseconds is an experimental curve 4010. Both the ISPP program operation and the ISPE erase operation are performed from a fresh memory cell prior to erase or program.

  FIG. 41 is an experimental graph of flat band voltage versus erase time for one embodiment of the memory cell of FIG.

Multiple charge storage including p + polysilicon gate and O1 / N1 / O2 / N2 / O3 / N3 / O4 thickness of about 1 nm / 1.5 nm / 2 nm / 5.5 nm / 5.5 nm / 4 nm / 4 nm An erase operation is performed on the SONOS memory cell whose nitride layer has been changed. The result of the erase operation with a gate voltage of −18V is an experimental curve 4110. The result of the erase operation with a gate voltage of −20V is an experimental curve 4120. The result of the erase operation with a gate voltage of −22V is an experimental curve 4130. A flat band voltage of less than -4V is achieved within 1 millisecond with a gate voltage of -22V. Erase saturation is observed for V _FB <-5V. Compared to the prior art without multiple charge storage nitride layers, erase saturation is improved (decreased) by more than 3V.

  FIG. 42 is a simulated graph of flat band voltage versus erase time for one embodiment of the memory cell of FIG.

  Multiple charge storage with p + polysilicon gate and O1 / N1 / O2 / N2 / O3 / N3 / O4 thickness of about 1 nm / 1.5 nm / 2 nm / 5.5 nm / 5.5 nm / 4 nm / 4 nm An erase operation is performed on the SONOS memory cell whose nitride layer has been changed. The result of the erase operation with a gate voltage of −18V is an experimental curve 4210 and a simulated curve 4240. The result of the erase operation with a gate voltage of −20V is an experimental curve 4220 and a simulated curve 4250. The result of the erase operation with a gate voltage of −22V is an experimental curve 4230 and a simulated curve 4260. Simulation is performed using a theoretical WKB model.

  43 is a graph of trapped charge density versus erase time for different nitride layers for charge storage in the memory cell of FIG.

The curve simulates the density of trapped charges at N2 (4310) and N3 (4320). After a sufficiently long erase time, N3 begins to trap electrons, N2 undergoes continuous erase (ERS) by substrate hole injection, and the hole density exceeds 1E13 cm ⁻² . After the density of trapped electrons at N3 exceeds 5E12 cm ⁻² , the gate injection stops. N3 traps electrons when holes are injected into N2, but N2 is closer to the channel and has a higher weighting factor for threshold voltage shift, so the threshold voltage decreases continuously.

44 and 45, a gate detection technique and a channel detection technique are applied to experimentally measure the accumulated charge distribution. The channel sensing has a heavily doped p + type gate and a lightly doped p-well. Gate sensing has a lightly doped p-type gate and a heavily doped p-well. The following equations give the charge densities QN2 and QN3 of the respective charge storage nitride layers N2 and N3.

  FIG. 44 is an experimental graph of flat band voltage shift versus programming time for one embodiment of the memory cell of FIG.

  A flat band voltage shift is measured for the first + FN programming at + 20V for a fresh memory cell prior to programming or erasing. Curve 4410 uses a channel sensing technique. Curve 4420 uses gate sensing technology.

  FIG. 45 is an experimental graph of charge density versus programming time for different nitride layers for charge storage for one embodiment of the memory cell of FIG.

  Curve 4510 shows the charge density QN2 at N2 for the first + FN programming at + 20V to a fresh memory cell prior to programming or erasing. Curve 4520 shows charge density QN3 at N3 for the first + FN programming at + 20V to a fresh memory cell prior to programming or erasing.

  Most of + FN injection electrons are stored in N2, and N3 stores far fewer electrons. N2 has excellent capture efficiency, and O3 can prevent most out-tunneling from N2 to N3.

  FIG. 46 is an experimental graph of flat band voltage shift versus erase time for the first erase after the first programming in one embodiment of the memory cell of FIG.

  Curve 4610 shows the measured flat band voltage shift using channel sensing techniques for erasure. Curve 4620 shows the measured flat band voltage shift using a gate sensing technique for erasure.

  The channel sensing technique and the gate sensing technique yield very different results because the N2 and N3 flat band voltage weighting factors are different depending on the distance from the channel or the distance from the gate.

  47 is an experimental graph of charge density versus erase time for different nitride layers for charge storage for the first erase after the first programming in one embodiment of the memory cell of FIG.

  Curve 4710 shows the charge density QN2 at N2 for the first erase. Curve 4720 shows charge density QN3 at N3 for the first erase. Curve 4720 shows that N3 traps an increasing number of electrons with a longer erase time. Curve 4710 shows that N2 undergoes erasure by hole injection and continues to trap holes, allowing deep erasure for the channel sensing device.

  FIG. 48 is an experimental graph of flat band voltage shift versus programming time for a second programming after a first erase in one embodiment of the memory cell of FIG.

  Curve 4810 shows the measured flat band voltage shift using channel sensing techniques for erasure. Curve 4820 shows the measured flat band voltage shift using a gate sensing technique for erasure.

  FIG. 49 is an experimental graph of charge density versus programming time for different nitride layers for charge storage for the second programming after the first erase in one embodiment of the memory cell of FIG.

  Curve 4910 shows charge density QN2 at N2 for the second programming. Curve 4920 shows charge density QN3 at N3 for the second programming. Curve 4920 shows that the previous injected electrons in N3 remain approximately constant during the second + FN programming (from erasure). Curve 4910 undergoes a second programming and shows that trapped holes in N2 recombine with electrons injected from the substrate.

  50 is a graph of threshold voltage versus programming voltage for memory cells in the three-dimensional vertical gate array of memory cells of FIG.

  Curve 5010 shows the threshold voltage of a memory cell undergoing ISPP. The ISPP slope of the 3DVG TFT device is about 0.75, which is less than the ideal value. The reduced ISPP gradient is due to the fringe field effect in small three-dimensional transistors, which modulates the tunnel oxide and blocking oxide electric fields and alters the behavior of the FN tunneling ISPP. Curve 5020 shows the disturb effect of other memory cells in the Z direction that have not been programmed. Curve 5030 shows the disturb effect of other memory cells of other word lines that have not been programmed.

  51 is a schematic diagram of a divided page three-dimensional vertical gate array of the memory cell of FIG. The test chip includes an entire block of 64 word lines of memory cells that undergo checkerboard (CKB) programming. The array includes 64 word lines 5110 labeled G0-G63. Adjacent to the word line 5110 is an even ground select line 5160 above and an odd ground select line 5170 below. Adjacent to the ground selection line, there is a common source line 5140 above and a common source line 5150 below. Adjacent to the common source line is a string select line structure 5180 for pages 1 and 3 above and a string select line structure 5190 for pages 0 and 2 below. There is a bit line 5120 on the top and a bit line 5130 on the bottom. FIG. 52 is a graph of a single level cell memory window of memory cells in the array of FIG.

  Memory cells go through various numbers, ie 1, 2, 10, 50 and 100 program / erase cycles. However, the traces corresponding to different numbers of program / erase cycles are approximately the same. Each of the traces has a plurality of distributions including a block erase distribution 5210, a program disturb distribution 5220, and a program distribution 5230. A block erase distribution 5210 represents a deeply erased threshold voltage distribution of a plurality of nitride layers that accumulate charge. After block erase, the upper upper bound of the block erase distribution may be less than -2V. Even the program disturb distribution 5210 is generally below 0V, allowing a large design window.

  FIG. 53 is a graph of a multi-level cell memory window of memory cells in the array of FIG.

  The memory cells go through various numbers of program / erase cycles: pre-use / fresh, 1, 2, 5, 10, 20, 50, 100, 200, 500 and 1000. However, the traces corresponding to different numbers of program / erase cycles are substantially the same except for one cycle of traces under distribution 5310. Each of the traces has a plurality of distributions including a checkerboard erase verify (CKB EV) distribution 5310, a program verify (PV) 1 distribution 5320, a program verification 2 distribution 5330, and a program verification 3 distribution 5340. doing. A multilevel memory window is more disturbing than a single level cell window, but a multilevel memory window is still preferred.

  FIG. 54 is a graph of the program-verification distribution of memory cells in the array of FIG.

  The distributions included are a random telegraph noise (RTN) distribution 5410, a program verification distribution 5420 for a single word line, and a program verification distribution 5430 for the entire block. Arrow 5440 originates from a defined program verification level of 2V and intersects the distribution peak.

  The single WL PV distribution 5420 is a tight distribution and has a slight offset from the PV level defined in the sensing circuit, which indicates a small fast initial charge loss. The tightness of the distribution is consistent with the RTN distribution 5410. A small PV offset suggests that fast initial charge loss is minimized by low leakage O4 in contact with the gate.

  The block-wide CKB PV distribution 5430 is wider than the single WL PV distribution 5420 due to many interference and back pattern effects. The rightward shift is due to interference and not charge loss.

  FIG. 55 is a graph of program threshold voltage and erase threshold voltage versus number of program cycles and erase cycles.

  The endurance of the device to program and erase cycles is determined under one shot program and erase, or “dumb-mode” conditions. Curve 5520 is the programmed state after 10 microseconds + 22V shot. Curve 5510 is the erased state after a 10 millisecond -20V block erase. At high cycling numbers, degradation is observed in the programmed and erased states. Erase state 5510 has a greater threshold voltage shift than program state 5520 at high cycling numbers.

  FIG. 56 is a graph of the IV characteristic sub-threshold slope versus the number of program and erase cycles.

  Curve 5620 is in the programmed state. Curve 5610 is the erased state. The threshold slope increases due to the occurrence of interface traps.

  FIG. 57 is a graph of IV characteristics for programmed and erased memory at different numbers of program and erase cycles.

  Erase state curves in various numbers of program and erase cycles merge 5720. Each erase state curve represents more program cycles and erase cycles, generally in the direction of the arrow toward the center of the graph. Program state curves in various numbers of program and erase cycles merge at 5710. Similarly, each program state curve represents more program cycles and erase cycles, generally in the direction of the arrow toward the center of the graph. The junction point of the IdVg curve is different between the erased state 5720 and the programmed state 5710. The difference between the junction points will be described with reference to FIG.

  FIG. 58 is a simplified diagram of the electric field in a BE-SONOS memory cell modified to include a plurality of nitride layers that accumulate charge.

The alternating silicon and oxide stack is surrounded by O1 5842, N1 5844, O2 5846 and polysilicon gate 5848. The dashed rectangle is the boundary of the silicon strip 5850 corresponding to the memory cell. The memory cell is programmed as shown by the electrons 5830 stored in N1 5844 on both sides. These accumulated electrons affect the electron density profile, which is in the range of about 10E10 cm ⁻³ to 10E15 cm ⁻³ . At the sides 5810 and 5812 of the silicon strip 5850 proximate to the trapped electrons, the electron density is about 10E10 cm ⁻³ . At the top 5822 and bottom 5824 of the silicon strip 5850 spaced from the trapped electrons, the electron density is about 10E15 cm ⁻³ . The remaining portion of the silicon strip 5850 has an intermediate value of electron density.

  Inverted electrons tend to start near the sidewalls in the PGM state due to fringing field effects. The subthreshold current moves toward the sidewall in the programmed state. This reduces the sensitivity of interface state traps (Dit) at the Si / O1 interface after a greater number of P / E cycling and reduces the threshold voltage shift in the programmed state.

  Therefore, the durability degradation is caused by O1 / Si interface state generation, not by the double trap layer. Durability is improved by enhancing the post stress stress of O1.

  FIG. 59 is a diagram showing a flat band voltage holding result of the memory cell after the thermal stress.

  High temperature 150 ° C. baking is performed. The higher programmed state and the deeply erased state have obvious charge losses after prolonged baking. The holding is excellent for the intermediate level state.

  60 to 61 show the charge density retention results of the memory cells after thermal stress. FIG. 60 shows the area density of trapped electrons in N2. FIG. 61 shows the area density of trapped electrons in N3. Gate and channel detection (GSCS) analysis shows that the charge at N3 is stable. Blocking oxides O3 and O4 can continue to maintain charge retention and prevent charge mixing between N2 and N3.

  FIG. 62 is a diagram showing a memory window holding result of the memory cell after the thermal stress.

  Test chip holding results are shown for CKB program 6210, 25 ° C. 1000 min baking hold 6220 and 85 ° C. 1000 min baking hold 6230. Charge loss is generally a group behavior, whereby the curves overlap without a tail distribution and are all separated into multiple distributions 6240, 6250, 6260 and 6270.

  FIG. 63 shows the charge loss rate of the memory cell at various temperatures, namely 85 ° C. and 25 ° C.

  Curve 6310 is the curve for the 3V lower bound program verification level. Curve 6320 is a curve for the 3V upper bound program verification level. Curve 6330 is a curve for the 2V lower limit program verification level. Curve 6340 is a curve for the 2V upper limit program verification level.

  The charge loss rate below 85 ° C. is less than 30 mV / decade and provides a sufficient detection window after long-term accumulation, but increases significantly at higher baking temperatures. At higher temperatures, the charge loss rate increases significantly and does not follow the simple Arrhenius model.

  FIG. 64 is a diagram showing an erase comparison of different gate doping or work functions and O2 thickness.

  Curve 6410 is for a −20V erase, P + gate, and 20 Å of O 2 thickness. Curve 6420 is for a -20V erase, N + gate, and 20 angstroms of O2 thickness. Curve 6430 is for a -21V erase, P + gate, and 30 Angstrom O2 thickness.

  Changing the poly gate from a P + gate to an N + gate does not affect erase saturation. Gate injection is suppressed by the trapped electrons at N3, rather than a high work function gate. Thus, poly gate doping changes, as well as irregular sharp corners of the gate (which results in large gate implants) are acceptable in the erase window.

  Thicker O2 (> 30 Å) is effective in suppressing charge loss at lower baking temperatures to improve BE-SONOS retention. Thicker O2 further minimizes low field leakage current and prevents detrapping from N2. On the other hand, at higher erase fields, the thicker O2 does not degrade the erase window because the band offset effect eliminates most of the O2 tunneling barrier. Various embodiments solve the trade-off between erasure and retention. Thin O1 and N1 facilitate hole injection during erasure, and thick O2 maintains charge retention at N2.

  FIG. 65 shows a read disturb test.

  Curve 6510 is the curve after the entire block has undergone CKB programming. Curve 6520 is the curve after the entire block has been subjected to 1M read disturb. Both curves behave similarly and have distributions 6530 and 6540. The optimized read waveform prevents hot carrier injection. A small read disturb is evident after the entire 1M block read stress. Due to the flat topology without the electric field enhancement effect from the curve, a high read endurance that is durable over 1M read stress is obtained. The device is very robust against gate stress.

  FIG. 66 is a schematic diagram of a vertical channel embodiment. A flat and planar topology can be implemented with a minimum design rule of 4F2 cell size to maximize the memory density of the 3D NAND flash.

  While the invention has been disclosed by reference to the preferred embodiments and examples described above, it should be understood that these examples are intended to be illustrative rather than limiting. Modifications and combinations will readily occur to those skilled in the art, and such modifications and combinations will be within the scope of the following claims.

Claims (17)

A memory comprising an array of memory cells,
Each memory cell of the array is
The gate,
A channel material having a channel surface;
A dielectric stack between the gate and the channel surface,
A multilayer tunnel structure over the channel surface, the multilayer tunnel structure including at least a first tunnel dielectric layer having a tunnel valence band edge;
A first charge storage dielectric layer on the multilayer tunnel structure;
A first blocking dielectric layer overlying the first charge storage dielectric layer;
A second charge storage dielectric layer overlying the first blocking dielectric layer;
A second blocking dielectric layer overlying the second charge storage dielectric layer;
A dielectric stack comprising:
A control circuit that applies a selected one of a plurality of bias arrangements, the plurality of bias arrangements comprising:
A program bias arrangement for programming data by moving electrons from the channel surface through the multilayer tunnel structure including the first tunnel dielectric layer to the first charge storage dielectric layer;
An erase bias arrangement for erasing data by moving holes from the channel surface to the first charge storage dielectric layer;
A control circuit including:
A memory including an array of memory cells.   2. The memory of claim 1, wherein erase saturation occurs for the control circuit that applies the erase bias arrangement to a gate voltage in the range between 20 and 24 volts in the memory with programmed data. The memory of claim 1, wherein:   The memory of claim 1, wherein the first charge storage dielectric layer has a thickness greater than the second charge storage dielectric layer.   The memory of claim 1, wherein the gate comprises n-type doped polysilicon.   The memory of claim 1, wherein the gate comprises p-type doped polysilicon. The multilayer tunnel structure on the channel surface is
A first tunnel oxide layer;
The first tunnel dielectric comprising a first tunnel nitride layer on the first tunnel oxide layer;
A second tunnel oxide layer on the first tunnel nitride layer;
The first charge storage dielectric layer includes a first charge storage nitride layer over the multilayer tunnel structure;
The first blocking dielectric layer includes a first blocking oxide layer on the first charge storage nitride layer;
The second charge storage dielectric layer includes a second charge storage nitride layer over the first blocking dielectric layer;
The memory of claim 1, wherein the second blocking dielectric layer comprises a second blocking oxide layer over the second charge storage nitride layer.   The memory of claim 6, wherein the erase bias arrangement applied by the control circuit increases the electron density in the second charge storage nitride layer.   The memory of claim 6, wherein the first tunnel nitride layer has a thickness of 20 angstroms or less, and the second charge storage nitride layer has a thickness of at least 35 angstroms.   The first charge storage nitride layer has a thickness in a first range of at least 50 angstroms, and the second charge storage nitride layer is in a second range of 35 angstroms to 50 angstroms. The memory of claim 6, having a thickness.   The memory according to claim 6, further comprising no nitride layer other than the first tunnel nitride layer, the first charge storage nitride layer, and the second charge storage nitride layer. A memory comprising an array of memory cells,
Each memory cell of the array is
The gate,
A channel material having a channel surface and a channel valence band edge;
A dielectric stack between the gate and the channel surface,
A multilayer tunnel structure over the channel surface, the multilayer tunnel structure including at least a first tunnel dielectric layer having a tunnel valence band edge;
A first charge storage dielectric layer on the multilayer tunnel structure;
A first blocking dielectric layer overlying the first charge storage dielectric layer;
A second charge storage dielectric layer overlying the first blocking dielectric layer;
A dielectric stack comprising a second blocking dielectric layer overlying the second charge storage dielectric layer;
A control circuit that applies a selected one of a plurality of bias arrangements,
The plurality of bias arrangements includes an erase bias arrangement in which at least a portion of the tunnel valence band edge of the first tunnel dielectric layer has a band energy greater than the channel valence band edge at the channel surface;
A control circuit, wherein no bias is applied to the memory, the tunnel valence band edge of the first tunnel dielectric layer has a lower band energy than the channel valence band edge at the channel surface;
Including memory.   The memory of claim 11, wherein the control circuit applying the erase bias arrangement provides an increase in electron density in the second charge storage dielectric layer.   12. The memory of claim 11, wherein erase saturation occurs for the control circuit that applies the erase bias arrangement to a gate voltage that is between 20 and 24 volts in the memory with programmed data. The memory of claim 11, wherein:   The memory of claim 11, wherein the first charge storage dielectric layer has a greater thickness than the second charge storage dielectric layer.   The memory of claim 11, wherein the gate comprises n-type doped polysilicon.   The memory of claim 11, wherein the gate comprises p-type doped polysilicon. A memory comprising an array of memory cells,
Each memory cell of the array is
The gate,
A channel material having a channel surface;
A dielectric stack between the gate and the channel surface,
A multilayer tunnel structure over the channel surface, the multilayer tunnel structure including at least a first tunnel dielectric layer having a tunnel valence band edge;
A first charge storage dielectric layer on the multilayer tunnel structure;
A first blocking dielectric layer overlying the first charge storage dielectric layer;
A second charge storage dielectric layer overlying the first blocking dielectric layer;
A second blocking dielectric layer overlying the second charge storage dielectric layer;
A dielectric stack comprising:
Including memory.