JP2016012641A - Solid-state imaging device manufacturing method and electronic information device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent resistance abnormality from being caused as pattern destruction occurs to an electrically unstable place of a conductive layer from a contact hole owing to wafer electrification by plasma processing, and to actualize higher pixels with a predetermined chip size.SOLUTION: A plasma dry etching device (RIE type) which has a low plasma density of 1×1,010/cm3 to 1×1,011/cm3 is used to design and form contact holes as one or a plurality of connection holes of a contact plug 36 so as to have a total base area which is 1/855-1/7,500 of a total area of transfer electrodes 32, 33 which are connected to a drive wiring layer 35 and electrically in a floating state at the point of time of contact hole formation.

Description

  The present invention uses a manufacturing method of a solid-state imaging device composed of a semiconductor element that photoelectrically converts image light from a subject to image and uses the solid-state imaging device manufactured by this manufacturing method as an image input device in an imaging unit. For example, the present invention relates to an electronic information device such as a digital camera such as a digital video camera and a digital still camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television phone device, and a camera-equipped mobile phone device.

  In recent years, solid-state imaging devices are required to have higher pixels, higher sensitivity, higher speed transfer, and the like, and CCD solid-state imaging devices are no exception. In addition, the chip size is required to be manufactured with a chip size equivalent to the conventional one, and a fine processing technique is also required for manufacturing the solid-state imaging device.

  In other words, in a solid-state imaging device, it is necessary to increase the number of pixels without increasing the chip size, so that the number of pixels is increased by reducing the processing pitch for the pixel portion, and the circuit area is reduced by miniaturization for circuits other than the pixel portion. Is required.

  With such a demand for microfabrication technology, for example, in the dry etching process, etching processing using an etching apparatus using a high-density plasma source is increasing. In addition, there has been proposed a method for improving the defect due to the restriction by the layout.

  FIG. 10A to FIG. 10E are schematic manufacturing process cross-sectional views illustrating the conventional method of manufacturing a semiconductor device disclosed in Patent Document 1 for each process.

  As shown in FIG. 10A, a transistor 105 having a gate electrode 103 and source / drain regions 104 on both sides thereof is formed between element isolation films 102 on a semiconductor substrate 101. A first interlayer insulating film 106 is formed thereon.

  First, as shown in FIG. 10B, contact holes are formed in the first interlayer insulating film 106 on the source / drain regions 104, and the tungsten film 107 is sputtered so as to fill the contact holes thereon. Form with.

  Next, as shown in FIG. 10C, the tungsten film 107 is planarized by etching back until the surface of the first interlayer insulating film 106 is exposed. As a result, contact plugs 108 connected to the source / drain regions 104 are formed. On the first interlayer insulating film 106 with the contact plugs 108 buried in, a second wiring film material made of aluminum is formed by sputtering or the like. The first wiring film 109 is formed by patterning this into a predetermined wiring shape by photolithography and etching techniques. A silicon oxide film is formed as the second interlayer insulating film 110 on the predetermined wiring shape of the first wiring film 109.

Subsequently, as shown in FIG. 10D, a patterned resist pattern 111 is formed on the second interlayer insulating film 110. Using this as a mask, a large number of through holes 112 having a diameter of about 0.36 μm are formed in the second interlayer insulating film 110. The through hole 112 is formed by using an inductively coupled plasma etcher. The etching conditions include a source power of 1900 W, a bias power of 1400 W, an etching pressure of 5 mTorr, a gas type and a gas flow rate of C ₂ F ₆ : 10 sccm, C ₄ F ₈ : 6 sccm and Ar: 95 sccm. sccm is cc / min (volume cc flowing in 1 minute).

  Thereafter, as shown in FIG. 10E, the resist pattern 111 on the second interlayer insulating film 110 is removed, and a tungsten film is formed thereon by sputtering or the like. Furthermore, this is etched back. As a result, the contact plug 113 is formed in the through hole 112. Further, an aluminum film is formed by sputtering or the like on the second interlayer insulating film 110 in which the contact plug 113 is embedded, and is patterned into a predetermined wiring shape to form a second wiring film 114.

In this case, as a placement rule between the number of contact holes and the substrate structure, the ratio of the total bottom area of the contact holes 112 (connection holes) and the upper area of the first wiring film 109 connected thereto is 1: 300 to 10,000. The aspect ratio of the contact hole 112 is 4 or less, and the bottom area of the contact hole 112 is 0.1 to 1.0 μm ² .

  Conventionally, when a plurality of contact holes and via holes are formed in the insulating layer at the same time under the same etching conditions, if the metal of the underlying structure is charged, the etching selectivity of the insulating film depends on the type and size of the underlying structure. As a result, the reaction product is deposited inside some of the holes, leading to poor conduction in the holes and high resistance of the holes.

  On the other hand, the contact hole 112 (connection hole) is formed according to the arrangement rule of the substrate structure (the ratio of the total bottom area of the contact hole 112 to the upper area of the first wiring film 109 is about 1: 300 to 10,000). In this case, it is possible to effectively prevent the accumulation and accumulation of reaction products and the like in the connection hole, and when the conductive material is connected through the connection hole, the increase or fluctuation of the contact resistance is prevented. It is supposed to be possible.

JP 2001-308067 A

  Conventionally, when the metal in the underlying structure is charged through a contact hole, the etching selectivity of the insulating film increases, and a reaction product is deposited inside some of the holes to reduce conduction and increase the resistance of the hole. As a result, in the above-described conventional method for manufacturing a semiconductor device disclosed in Patent Document 1, regarding the relationship between the contact (via) processing pattern and the silicon substrate, conduction failure due to plasma processing charging and high hole resistance are achieved. In order to prevent the occurrence of resistance and via processing defects, a predetermined arrangement rule between the number of contact holes and the substrate structure is determined by layout restrictions (ratio of the total bottom area of the contact holes 112 and the top area of the first wiring film 109). Is about 1: 300 to 10,000).

  However, for a solid-state imaging device, particularly a CCD solid-state imaging device, the outline dimensions are determined by the specifications, and the wiring layer for applying a voltage to the gate electrode through the contact hole is almost the same as the outline dimensions due to the operating principle of the CCD. Since the gate electrode area which is the same and has the same potential as that of the single contact hole is substantially determined by the number of pixels and the pixel size and becomes large, it is difficult to restrict the layout.

  Moreover, in the manufacture of a CCD type solid-state imaging device, the gate insulating film is thick, causing symptoms different from those caused by the microfabrication process, and the chip size and the number of pixel arrays are almost unambiguous with respect to the required characteristics. Therefore, it is very difficult to restrict the layout.

  That is, the present inventor has found a new problem that a symptom of pattern destruction that is different from a symptom in which a reaction product accumulates in a hole generated by the above-described microfabrication process and poor conduction occurs.

  Here, a description will be given of a pattern destruction symptom peculiar to a CCD type solid-state imaging device, which is generated due to an overwhelmingly large area of the gate electrode and a large amount of charge charged in the gate electrode.

  First, at the time of contact etching of the contact hole, the gate electrode through the wiring layer from the contact hole is in an electrically floating state, and the etching of the insulating film is completed in the middle of the contact etching process and connected to the gate electrode. The wiring layer is exposed to plasma through the contact hole. Thereafter, the charge supplied from the plasma in a state where overetching is applied is accumulated in the wiring layer which is in an electrically floating state and the gate electrode connected thereto. Charge exceeding the charging capacity of the wiring layer and the gate electrode in a floating state is charged, and the concentration of charges occurs there due to the small bottom area of the contact hole. As a result, pattern destruction occurs at electrically unstable locations such as the wiring layer having the highest resistance at the same potential as the contact hole and the location where it is connected to the gate electrode, and further causes resistance abnormality.

  The present invention solves the above-mentioned conventional problems, and can prevent the occurrence of pattern breakdown due to wafer charging by plasma processing in an electrically unstable portion of the conductive layer from the contact hole and further causing resistance abnormality. A solid-state imaging device manufacturing method capable of realizing a high pixel size with a predetermined chip size, and an electronic device such as a camera-equipped mobile phone device using a solid-state imaging device manufactured by this manufacturing method as an image input device in an imaging unit The purpose is to provide information equipment.

  The method for manufacturing a solid-state imaging device according to the present invention includes a total of the charge transfer electrodes on an interlayer insulating film on a wiring layer connected to a charge transfer electrode for transferring charges from a photoelectric conversion unit that photoelectrically converts incident light. Compare the ratio of the total area of one or more connection holes to the upper area with a threshold value, and select either high plasma density or low plasma density plasma etching treatment to prevent pattern destruction of the connection holes And a connection hole forming step of forming the one or more connection holes reaching the wiring layer, thereby achieving the above object.

Preferably, the low plasma density in the method for producing a solid-state imaging device of the present invention is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less, and the high plasma density is 1 × 10 ¹¹ / cm ^3. Density exceeding.

Further preferably, in the method of manufacturing a solid-state imaging device of the present invention, the low plasma density plasma etching treatment is preferably performed using at least one of Ar gas and O ₂ or CO gas, and C ₄ F ₆ and C ₅ F _8. , One or more gases of C ₄ F ₈ and C ₂ F ₆ are used.

  Further preferably, in the method for manufacturing a solid-state imaging device according to the present invention, a ratio B / A of the total area B of the one or more connection holes to the total area A of the charge transfer electrode is the predetermined threshold area ratio 1 /. When it is larger than C, the high plasma density plasma etching process is performed, and the ratio B / A of the total area B of the one or more connection holes to the total area A of the charge transfer electrode is the predetermined threshold area ratio 1 When in the range of / C to 1/7500, the low plasma density plasma etching process is performed.

  Further preferably, in the method for manufacturing a solid-state imaging device of the present invention, a charge transfer electrode forming step for forming the charge transfer electrode on a substrate via a gate insulating film is provided before the connection hole forming step.

Further preferably, the method for manufacturing a solid-state imaging device of the present invention uses a low plasma density plasma dry etching apparatus (RIE type) having a plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. When the contact hole is formed, the total bottom of 1 / C (1/855 in the first embodiment) to 1/7500 with respect to the total area of the charge transfer electrodes connected to the drive wiring layer 35 and in an electrically floating state It has a connection hole forming step of forming a contact hole as one or a plurality of connection holes of the contact plug so as to have an area, whereby the above object is achieved.

  The solid-state imaging device of the present invention has a transfer electrode on the substrate for transferring the charge accumulated in the photoelectric conversion unit in the substrate, and prevents pattern destruction due to charge concentration during the plasma dry etching process. One or a plurality of connection holes are formed so as to have a total area within a predetermined threshold range with respect to the upper area of the transfer electrode, whereby the above object is achieved.

  The electronic information device of the present invention uses a solid-state image sensor manufactured by the method for manufacturing a solid-state image sensor of the present invention as an image input device in an image pickup unit, and thereby achieves the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, the interlayer insulating film on the wiring layer connected to the charge transfer electrode for transferring the charge from the photoelectric conversion unit that photoelectrically converts the incident light is provided with one or more of the total area A of the charge transfer electrode. Depending on the ratio B / A of the total area B of the connection holes, either high plasma density or low plasma density plasma etching treatment is selected so as to prevent the pattern destruction of the connection holes, and the wiring layer is reached. A connection hole forming step of forming the one or more connection holes;

  Accordingly, the ratio B / A of the total area B of one or more connection holes to the total upper area A of the charge transfer electrodes is compared with a threshold value, so that the high plasma density and the low plasma are prevented so as to prevent the pattern destruction of the connection holes. Since one of the plasma etching processes of the density is selected, it is possible to prevent the wafer from being charged by the plasma process from causing the pattern breakdown at the electrically unstable portion of the conductive layer from the contact hole and further causing the resistance abnormality. Therefore, it is possible to realize a high pixel with a predetermined chip size.

  As described above, according to the present invention, the ratio B / A of the total area B of one or a plurality of connection holes to the total upper area A of the charge transfer electrodes is compared with the threshold value to prevent pattern destruction of the connection holes. In order to select either high plasma density or low plasma density plasma etching process, the wafer charging by the plasma process causes the pattern breakdown at the electrically unstable part of the conductive layer from the contact hole, and further the resistance abnormality This can be prevented and high pixels can be realized with a predetermined chip size.

It is a top view which shows typically the example of a principal part structure in the partial pixel array of the CCD type solid-state image sensor in Embodiment 1 of this invention. FIG. 2 is a vertical cross-sectional view taken along line A-A ′ schematically showing a partial pixel array of the CCD solid-state imaging device of FIG. It is a figure which shows the experimental result at the time of contact formation in the total bottom area of a contact hole with respect to the total area of a transfer electrode when each plasma etching apparatus of a high plasma density and a low plasma density is used. FIG. 6 is a vertical cross-sectional view taken along line A-A ′ of FIG. 1 schematically showing a region including one pixel portion of a CCD type solid-state imaging device in Embodiment 2 of the present invention. It is a top view which shows typically the pixel array area | region of the CCD type solid-state image sensor in Embodiment 3 of this invention, and the other connection structural example of the exterior. It is a top view which shows typically the pixel array area | region of the CCD type solid-state image sensor in Embodiment 4 of this invention, and the example of a connection structure of the exterior. It is a top view which shows typically the pixel array area | region of the CCD type solid-state image sensor in Embodiment 4 of this invention, and the other connection structural example of the exterior. It is a longitudinal cross-sectional view which shows typically the example of a principal part structure of the CMOS solid-state image sensor which concerns on Embodiment 5 of this invention. FIG. 9 shows, as Embodiment 7 of the present invention, an electronic information device using any one of the CCD type solid-state imaging devices 1 and 1A to 1D and the CMOS type solid-state imaging device 1E according to Embodiments 1 to 6 of the present invention as an imaging unit. It is a block diagram which shows the example of schematic structure. (A)-(e) is a schematic manufacturing process sectional drawing which shows the manufacturing method of the conventional semiconductor device currently disclosed by patent document 1 for every process.

  Embodiments 1 to 6 of the solid-state imaging device and the manufacturing method thereof according to the present invention, and a mobile phone with a camera using, for example, a high-quality solid-state imaging device manufactured by these manufacturing methods as an image input device for an imaging unit Embodiment 7 of an electronic information device such as an apparatus will be described in detail with reference to the drawings. In addition, each thickness, length, etc. of the structural member in each figure are not limited to the structure to illustrate from a viewpoint on drawing preparation. Furthermore, Embodiments 1 to 6 of the solid-state imaging device and the manufacturing method thereof according to the present invention can be variously modified within the scope shown in the claims. That is, embodiments obtained by further combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention. Furthermore, it is possible to combine at least two of the first to sixth embodiments.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a configuration example of a main part in a partial pixel array of a CCD solid-state imaging device according to Embodiment 1 of the present invention.

  In FIG. 1, a CCD solid-state imaging device 1 according to the first embodiment includes a plurality of photoelectric conversion units 2 (a plurality of photodiode units; here) as a plurality of light receiving units that photoelectrically convert image light from a subject and image it. Only one is shown) is arranged in a two-dimensional matrix in the matrix direction (vertical and horizontal directions) to form an imaging region. A vertical transfer register 3 having a CCD structure formed on the signal charge reading side (here, the left side of the photoelectric conversion unit 2) corresponding to each of the plurality of photoelectric conversion units 2 in the column direction (vertical direction) is arranged in the vertical direction (vertical direction). Direction). Each of the signal charges transferred in the vertical direction (vertical direction) from the plurality of vertical transfer registers 3 is transferred in the horizontal direction (horizontal direction) on the signal output unit side that is output as an imaging signal for each pixel. One horizontal transfer register (not shown) having a CCD structure is disposed on the terminal end side of the plurality of vertical transfer registers 3.

  The vertical transfer register 3 is arranged on the surface portion side of a semiconductor substrate (not shown) with a predetermined width in plan view, and a vertical charge transfer unit 31 (transfer channel) for transferring each signal charge in the vertical direction. Two charge transfer electrodes 32 and 33 for driving (hereinafter simply referred to as transfer electrodes) are sequentially and repeatedly arranged in the vertical direction via a gate oxide film (not shown) on the vertical charge transfer portion 31 having a predetermined width in plan view. It has been. The contact plugs 34 connected to the interlayer insulating film (not shown) provided so as to cover the two transfer electrodes 32 and 33 and the contact plugs 34 are connected to the transfer electrodes 32 and 33 in the vertical and horizontal directions. A drive wiring layer 35 for applying a charge transfer voltage is formed.

  The drive wiring layer 35 is arranged on the left and right sides in the plan view of the photoelectric conversion unit 2 and around the top and bottom so as to open above the photoelectric conversion unit 2. Another interlayer insulating film (not shown) is provided on the interlayer insulating film provided with the contact plugs 34 and the drive wiring layer 35 thereon, and the other interlayer insulating film (not shown) is provided. Also, one or a plurality of contact plugs 36 (three in this case) are provided. Charge transfer is performed for each of the two transfer electrodes 32 and 33 adjacent to each other via the drive wiring layer 35 on another interlayer insulating film (not shown) so as to be connected to one or a plurality of contact plugs 36. A drive wiring layer (not shown) for applying a voltage is provided.

  The region of one pixel portion of the CCD solid-state image pickup device 1 of Embodiment 1 is configured by a planar view region including the photoelectric conversion unit 2 and the two transfer electrodes 32 and 33 on the left side thereof.

  FIG. 2 is a vertical cross-sectional view taken along the line A-A ′ schematically showing a region including one pixel portion of the CCD type solid-state imaging device of FIG. 1.

  In FIG. 2, the CCD solid-state imaging device 1 according to the first embodiment has a plurality of photoelectric conversion units 2 made of photodiodes that photoelectrically convert incident light to generate signal charges as light receiving elements in a matrix with predetermined intervals. Are provided on the surface side of the substrate 4 such as a silicon substrate. An imaged signal charge is read from the photoelectric conversion unit 2 adjacent to each photoelectric conversion unit 2 to the charge transfer unit 31 through the signal reading unit 5. A channel stop 6 is provided on the side opposite to the signal reading unit 5 (reading gate) with respect to the charge transfer unit 31 so that signal charges are not mixed with the adjacent photoelectric conversion unit 2.

  A gate oxide film 7 as a gate insulating film is formed on the entire surface side of the substrate 4 on which the photoelectric conversion unit 2, the signal reading unit 5, the charge transfer unit 31, and the channel stop 6 are formed. The gate oxide film 7 may be a silicon oxide film (thermal oxide film or low-temperature oxide film), a silicon nitride film instead of the silicon oxide film, or a laminated film thereof. Further, a BPSG film may be used instead of the single layer film of silicon oxide film or silicon nitride film. The film thickness is 20 nm here.

  An antireflection film 8 such as a SiN film or a SiON film for absorbing incident light is provided on the gate oxide film 7 above the center of the photoelectric conversion unit 2. Further, on the gate oxide film 7 on the charge transfer unit 31 and the signal readout unit 5, charge transfer electrodes 32 and 33 for controlling the charge transfer of the signal charges from the photoelectric conversion unit 2 in the vertical direction are sequentially and repeatedly arranged. Are arranged.

  Contact plugs 34 are provided on the interlayer insulating film 9 provided on the transfer electrodes 32 and 33 so as to be connected to the transfer electrodes 32 and 33, respectively. On the interlayer insulating film 9, a drive wiring layer 35 for applying a drive voltage to the transfer electrodes 32 and 33 is formed in a predetermined wiring pattern so as to be connected to the contact plug 34. An interlayer insulating film 10 is formed on the drive wiring layer 35.

  In order to prevent incident light from being reflected by the transfer electrodes 32 and 33 and the drive wiring layer 35 to generate noise, the light shielding film 11 is formed on the interlayer insulating films 9 and 10 and the transfer electrodes 32 and 33 and contact plugs. 34 and the drive wiring layer 35 are formed so as to cover the top and sides of the drive wiring layer 35 and to open the photoelectric conversion units 2.

The transfer electrodes 32 and 33 are composed of a P (phosphorus) -doped polysilicon film or a laminated film including the same, and the film thickness thereof is constant between 100 nm and 200 nm. The interlayer insulating films 9 and 10 are formed of any one of a silicon oxide film, a PSG (Phospho Silicate Glasses) film, a BSG film, and a BPSG film, and the film thickness thereof is about 300 nm to 600 nm. Furthermore, the contact plug 34, the drive wiring layer 35, and the contact plug 36 are made of tungsten, aluminum, or the like. The contact holes forming the contact plugs 34 and 36 are formed such that the contact hole has an aspect ratio of 4 or less and the contact hole has a bottom area of about 0.1 to 0.5 μm ² . A TiN film may be formed at the bottom of the contact hole constituting the contact plug 34 in order to improve the contact property between the transfer electrodes 32 and 33 directly below the P-doped polysilicon film. The shape of these contact holes in a plan view is a circular shape or a square shape. When the shape of the contact hole in the plan view is square, the bottom area can be earned at the corner portion compared to the circular shape of the inscribed circle.

  Further, an antireflection film 8 is formed on each photoelectric conversion unit 2 via a gate oxide film 7. Above the antireflection film 8, an interlayer insulating film 12 and an optical waveguide member are formed from the opening of the light shielding film 11. A color filter 14 having a predetermined color array via 13 and a microlens 15 for condensing light on the photoelectric conversion unit 2 are disposed. Both the color filter 14 and the microlens 15 (condensing lens) are positioned so as to correspond to the positions of the respective photoelectric conversion units 2.

  With the above configuration, light incident on an imaging region in which a plurality of pixel portions are arranged in a two-dimensional matrix is first collected by the microlens 15, then from the color filter 14 to the optical waveguide member 13, and further to the light. The light is efficiently condensed on the photoelectric conversion unit 2 through the antireflection film 8.

  Next, the light incident on each photoelectric conversion unit 2 is photoelectrically converted by each photoelectric conversion unit 2 to become each signal charge constituting a captured image. These signal charges are read out from the photoelectric conversion units 2 to the charge transfer units 31 through the signal reading units 5 by the transfer electrodes 33.

  Subsequently, each signal charge read to each charge transfer unit 31 through the signal reading unit 5 is transferred in the vertical direction on the terminal end side of the plurality of vertical transfer registers 3 and then transferred to one horizontal transfer. Charges are sequentially transferred in a horizontal direction (lateral direction) on the signal output unit side by a register (not shown). The signal output unit sequentially outputs each image signal for each pixel. As a result, the imaging signal of the subject is output to a signal processing unit (not shown) and subjected to predetermined signal processing to become an image signal. This image signal is displayed on the display unit or stored in the memory unit. To do.

  Here, the characteristic configuration of the present invention will be described in detail.

In the CCD type solid-state imaging device 1 according to the first embodiment, C ₄ F ₆ , C ₅ F ₈ , C ₄ are formed when the contact hole as the connection hole on the drive wiring layer 35 is formed by plasma dry etching. The plasma density is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less using one or more gases of F ₈ and C ₂ F ₆ , Ar gas, and O ₂ or CO gas. The low plasma density plasma etching apparatus (parallel plate RIE type) is used. As a result, the wafer is charged by the plasma processing, causing pattern destruction at an electrically unstable portion of the path from the contact hole to the transfer electrodes 32 and 33 via the drive wiring layer 35 and further causing resistance abnormality. Therefore, stable contact resistance can be obtained, and high pixels can be realized with a predetermined chip size.

That is, when the ratio of the total bottom area to the total top area (the top area of the gate electrode) of the transfer electrodes 32 and 33 (here, fractional display) is 1/855 to 1/7500, Contact that makes contact with the interlayer insulating films 10 and 12 on the drive wiring layer 35 by using a plasma etching apparatus (parallel plate RIE type) having a low plasma density of × 10 ¹⁰ / cm ^{3 to} 1 × 10 ¹¹ / cm ³ Contact holes as one or a plurality of connection holes to be plugs 36 are formed.

On the other hand, a plasma etching apparatus (ICP type; inductively coupled plasma type) having a high plasma density exceeding 1 × 10 ¹¹ / cm ³ is suitable for finer microfabrication and 1 × 10 ¹⁰ / cm ³ or more 1 × 10 ¹¹ Compared with the case of using a plasma etching apparatus with a low plasma density of / cm ³ or less, the processing time (man-hour) can be shortened in the contact hole. Thus, the use of a plasma etching apparatus having a high plasma density exceeding 1 × 10 ¹¹ / cm ³ is more advantageous for man-hours and miniaturization.

However, when a plasma etching apparatus having a high plasma density exceeding 1 × 10 ¹¹ / cm ³ is used, the total bottom area is larger than the total top area of the transfer electrodes 32 and 33 (total top area of the gate electrode). Since pattern destruction occurs in the vicinity of 1/855, the above pattern destruction is not caused by using a plasma etching apparatus having a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. One corresponding to the contact plug 36 and the interlayer insulating films 10 and 12 within a total bottom area of 1/855 to 1/7500 with respect to the total top area of the transfer electrodes 32 and 33 (top area of the gate electrode). Alternatively, it is designed to form contact holes as a plurality of connection holes.

  Based on this, a manufacturing method of the CCD solid-state imaging device 1 of the first embodiment will be described.

  In the manufacturing method of the CCD type solid-state imaging device 1 of the first embodiment, the signal charge accumulated in the photoelectric conversion unit 2 is passed through the gate oxide film 7 on the substrate 4 and the signal readout unit 5 is passed through the charge transfer unit 31. After reading, a charge transfer electrode forming step of repeatedly forming a plurality of transfer electrodes 32 and 33 for controlling charge transfer in the charge transfer unit 31 in the charge transfer direction (vertical direction) as a unit, and on the gate oxide film 7 One or more contact plugs 34 are formed in the interlayer insulating layer 9 formed on the transfer electrodes 32 and 33, and the drive wiring layer 35 is formed on the interlayer insulating layer 9 so as to be connected to the one or more contact plugs 34. And a pattern formed by charge concentration in plasma dry etching processing on the interlayer insulating layers 10 and 12 formed on the interlayer insulating layer 9 and the driving wiring layer 35. In order to prevent breakage, a connection hole forming step of forming a contact hole as one or a plurality of connection holes reaching the drive wiring layer 35, and a conductive material (here, tungsten) is embedded in the one or more contact holes, A contact plug forming step for forming a contact plug 36 for connection to the transfer electrodes 32 and 33 via the drive wiring layer 35 and the contact plug 34.

  The manufacturing method of the CCD type solid-state imaging device 1 of Embodiment 1 will be described in more detail.

  As shown in FIGS. 1 and 2, a contact hole (later contact plug 36) for applying a charge transfer voltage to the transfer electrodes 32 and 33 in order to read out and transfer the charge accumulated in the photoelectric conversion unit 2 is provided. The interlayer insulating films 10 and 12 are formed through the drive wiring layer 35 outside the pixel array region (imaging region). At this time, the total area of the transfer electrodes 32 and 33 having the same potential as that of the drive wiring layer 35 is determined almost uniquely by the required number of pixels and the chip size. Is designed by adjusting the size (diameter or one side) and the number of contact holes so that the total area of the bottom of the contact hole becomes 1/855 (predetermined threshold area ratio) to 1/7500 of the total area of the transfer electrodes 32 and 33. .

  In short, the contact hole is formed by plasma dry etching, but the total area of the bottom of the contact hole exceeds 1/855 with respect to the total area of the transfer electrodes 32 and 33 (1 / 855-1 / 7500). Outside of the range, it is possible to process a good contact hole without depending on the plasma density at the time of dry etching, but it is necessary to increase the number of pixels required for the CCD type solid-state imaging device 1 and to limit the chip area. Cannot be satisfied.

  On the other hand, when the total area of the bottom part of the contact hole is a predetermined threshold area ratio of 1/855 or less with respect to the total area of the transfer electrodes 32 and 33 (within a range of 1/855 to 1/7500), During the plasma dry etching process of the contact plug 36), the etching reaches the drive wiring layer 35, and when the over-etching is performed, the transfer wiring 32, Although charges are accumulated on 33, charge concentration occurs due to the small total area of the contact holes. As a result, pattern destruction occurs at an electrically unstable place such as a place connected to the drive wiring layer 35 having the same potential as the contact hole and the highest resistance, and further resistance abnormality is caused.

  That is, at the time of plasma dry etching of the contact hole to be the contact plug 36 later, the transfer electrodes 32 and 33 are electrically floating from the drive wiring layer 35 in the CCD type solid-state imaging device 1, and the plasma dry etching process of the contact hole is performed. In the middle of the etching, the etching of the interlayer insulating films 10 and 12 is completed, and the drive wiring layer 35 is exposed to plasma through the contact hole. Thereafter, the charge supplied from the plasma in a state where over-etching is applied is accumulated in the transfer electrodes 32 and 33 from the drive wiring layer 35 which is in an electrically floating state. It is considered that pattern destruction occurs at an electrically unstable portion (the bottom of the contact plug 36) by charging a charge exceeding the charging capacity of the transfer electrodes 32 and 33 from the drive wiring layer 35 in a floating state.

Therefore, when plasma dry etching of contact holes is performed, the plasma density is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less with a plasma processing apparatus (parallel plate RIE type) having a low plasma density. It is desirable that, for example, by performing plasma dry etching with parallel plate RIE type equipment, it is possible to significantly suppress charge accumulation in the drive wiring layer 35, and an electrically normal CCD without pattern destruction. Type solid-state imaging device 1 can be manufactured.

At this time, for example, the SiO ₂ film (silicon oxide film) formed by the known plasma CVD method is used as the interlayer insulating films 10 and 12, and the interlayer on the drive wiring layer 35 is, for example, 100 nm to 500 nm in contact etching. It is necessary to etch the insulating films 10 and 12. At this time, the contact etching conditions are, for example, an RF power of 900 W to 1800 W and a pressure of 50 mTorr when a parallel plate type RIE apparatus (plasma density: 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less) is used. The treatment is performed at 80 mTorr and a gas flow rate of C ₄ F ₈ / Ar / O ₂ at a flow rate ratio of 5/15/200 sccm, respectively. The etching gas used for dry etching is C4F8. However, it is known that CFx (x = 1 to 3) is easily generated in plasma. C ₄ F ₈ , C ₄ F ₆ , C it is possible to perform the same etching also Ar, by adjusting the etching parameters flow rate, etc. of the CO and O ₂ gas at ₂ F _6.

Further, when the total area of the bottom surface of the contact hole is smaller than 1/7500 of the total area of the transfer electrodes 32 and 33 (outside the range of 1/855 to 1/7500), the contact hole that is actually etched is processed. If the size (diameter) of the film is small and the plasma density is 1 × 10 ¹¹ / cm ³ or less, the etching process becomes difficult, and further measures are required.

  After the contact hole is formed, a conductive material (tungsten in this case) is embedded in the contact hole, and the contact plug 36 is electrically connected to the drive wiring layer 35 (not included in the pixel array). A conductive layer (not shown) for application is formed. Thereafter, the color filter 14 and the microlens 15 are formed on the color filter 14 so as to correspond to the plurality of photoelectric conversion units 2 arranged in a matrix, thereby manufacturing the CCD solid-state imaging device 1 of the first embodiment. it can.

  FIG. 3 is a diagram showing an experimental result when a contact is formed in the total bottom area of the contact hole with respect to the total area of the transfer electrodes 32 and 33 when each plasma etching apparatus having a high plasma density and a low plasma density is used.

As shown in FIG. 3, a low plasma density plasma etching apparatus (RIE type) having a plasma density of 1 × 10 ¹⁰ / cm ³ of 1 × 10 ¹⁰ / cm ^{3 to} 1 × 10 ¹¹ / cm ^3. ), When the total bottom area of the contact hole with respect to the total area of the gate electrodes (transfer electrodes 32, 33) is 1/854, the defect rate including contact hole formation and pattern destruction is 1%. It was a contact hole formation failure and no pattern destruction failure. Also, using a low plasma density plasma etching apparatus (RIE type) with a plasma density of 1 × 10 ¹⁰ / cm ³ , the total bottom of the contact hole (contact hole) with respect to the total area of the gate electrode (transfer electrodes 32, 33) When the area was 1/860, the failure rate was 0% including contact hole formation failure and pattern destruction failure.

In contrast, by using a plasma etching apparatus of a high plasma density of the plasma density is 1.6 × 10 ¹¹ / cm ³ of the range of plasma density exceeds 1 × 10 ¹¹ / cm ³ to (ICP type), the gate When the total bottom area of the contact hole (contact hole) with respect to the total area of the electrodes (transfer electrodes 32 and 33) was 1/854, the defect rate including contact hole formation failure and pattern destruction failure was 65%. Even if the contact hole formation failure includes 1%, the defect rate of the pattern destruction failure is 64% by subtracting it. Further, using a high plasma density plasma etching apparatus (ICP type) having a plasma density of 1.6 × 10 ¹¹ / cm ³ , contact holes (contact holes) with respect to the total area of the gate electrodes (transfer electrodes 32 and 33) are formed. When the total bottom area was 1/386, the defect rate including contact hole formation and pattern destruction was 0%.

Therefore, even in the above experimental results, when a contact hole is formed using a low plasma density plasma dry etching apparatus (RIE type) having a plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less, One or more connection holes of the contact plug 36 so as to have a total bottom area of 1/855 to 1/7500 with respect to the total area of the transfer electrodes 32 and 33 that are connected to the drive wiring layer 35 and are electrically floating. If the contact hole is designed and formed, it is possible to prevent the pattern breakdown at the electrically unstable portion from the contact hole to the drive wiring layer 35 due to the wafer charging by the plasma processing and further causing the resistance abnormality. I was able to confirm that I could do it.

  As described above, according to the first embodiment, the structure of the pixel array and the transfer electrodes 32 and 33 in the pixel array are required in the manufacture of the CCD type solid-state imaging device 1 in the demand for higher pixels. Design by optimizing the ratio between the total area and the total bottom area of the contact hole with the same potential, and controlling the plasma density in plasma dry etching of the corresponding contact hole between the high plasma density and the low plasma density This suppresses the charge accumulated in the chip and prevents pattern breakdown at the electrically unstable portion from the contact hole to the drive wiring layer 35 due to wafer charging by plasma processing and further causing resistance abnormality. Thus, it is possible to increase the number of pixels with a predetermined chip size.

  In short, to limit the gate capacity per unit contact hole area, or to form a contact hole with low-density plasma equipment when the gate capacity exceeds the threshold, stabilize the contact hole processing without pattern destruction, The CCD type solid-state imaging device 1 having higher pixels can be manufactured with high quality.

(Embodiment 2)
In the first embodiment, the interlayer insulating layers 10 and 12 on the drive wiring layer 35 are connected in the plasma dry etching process with a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. One or a plurality of connection holes having a total bottom area of 1/855 to 1/7500 with respect to the total area of the transfer electrodes 32 and 33 that are connected to the drive wiring layer 35 and are in an electrically floating state at the time of forming the holes. The connection hole forming step for forming the contact holes is described in the case of the gate capacitance of the transfer electrodes 32 and 33 when the thickness of the gate oxide film 7 on the substrate 4 is 20 nm. On the other hand, in the second embodiment, when the gate capacitance of the gate oxide film 7 on the substrate 4 is 30 nm thicker than 20 nm, the gate capacitance that can be stored in the transfer electrodes 32 and 33 is small. Thus, the value of the predetermined threshold area ratio 1/855 becomes smaller in the range of the total bottom area of the contact hole with respect to the total area of the transfer electrodes 32 and 33, in which the plasma dry etching process with a low plasma density is performed. Shift in the direction of narrowing the range of 1/855 to 1/7500. Further, in the case of a gate capacitance in which the thickness of the gate oxide film 7 on the substrate 4 is 10 nm thinner than 20 nm, the gate capacitance that can be stored in the transfer electrodes 32 and 33 is greatly increased, and the low plasma density is reduced. A range in which the plasma dry etching process is performed, and of the threshold range of the total bottom area of the contact hole with respect to the total area of the transfer electrodes 32 and 33, the value of the predetermined threshold area ratio 1/855 increases and becomes 1 / 855-1 The range of / 7500 is shifted in the direction of wider outside of 1/855. Here, a case where the gate oxide film 7 is as thin as 10 nm and the gate capacitance increases will be described.

  4 is a vertical cross-sectional view taken along line A-A ′ of FIG. 1 schematically showing a region including one pixel portion of the CCD solid-state imaging device according to Embodiment 2 of the present invention. Members having the same operational effects as the constituent members described in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 4, the CCD solid-state imaging device 1A of the second embodiment is different from the CCD solid-state imaging device 1 of the first embodiment in that the thickness of the gate oxide film 7A is 10 nm. The film thickness is half that of 20 nm of the thickness of the gate oxide film 7. As a result, the gate capacity that can be stored in the floating transfer electrodes 32 and 33 formed on the substrate 4 through the half thin gate oxide film 7A is as much as the transfer electrodes 32 and 33 approach the substrate 4. For example, it is increased by about 4 times as being inversely proportional to the square of the distance. For this reason, when the contact hole of the contact plug 36 is formed, the driving wiring is formed from the contact plug 36 using a plasma etching apparatus (RIE type) having a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. A predetermined threshold area ratio “1” having a bottom area of “1/855 to 1/7500” with respect to a total upper area of the transfer electrodes 32 and 33 connected via the layer 35 and the contact plug 34 (total area of the gate electrode) If the contact hole as one or a plurality of connection holes to be the contact plug 36 is formed so as to have a total area exceeding / 855 ”, for example, by a simple calculation and shifted to a range of“ 1/213 to 1/7500 ”. Good. In this case, even if a plasma etching apparatus (ICP type) having a high plasma density of 1 × 10 ¹¹ / cm ³ or more is used, the range in which pattern destruction does not occur becomes narrow, and 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 6 ^The range for preventing pattern destruction using a plasma etching apparatus (RIE type) having a low plasma density of ¹¹ / cm ³ or less is widened.

Therefore, the plasma etching apparatus (ICP type) with a high plasma density of 1 × 10 ¹¹ / cm ³ or more is used for miniaturization and reduction of man-hours, or 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / Although a low plasma density plasma etching apparatus (RIE type) of cm ³ or less is used, the predetermined threshold range (ratio) varies depending on the thickness of the gate oxide film 7A. The threshold regarding the ratio of the hole bottom area to the total upper area of the transfer electrodes 32 and 33 is a predetermined threshold area ratio 1/855 when the thickness of the gate oxide film 7 is 20 nm, and is predetermined when the thickness of the gate oxide film 7A is 10 nm. The value exceeds the threshold area ratio 1/855 (for example, 1/213).

As described above, according to the second embodiment, a plasma etching apparatus (RIE type) having a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less is used when forming the contact hole of the contact plug 36. Thus, the bottom area has a predetermined threshold range (threshold at one end) with respect to the total upper area (total area of the gate electrode) of the transfer electrodes 32 and 33 connected from the contact plug 36 via the drive wiring layer 35 and the contact plug 34. Contact holes as one or a plurality of connection holes to be the contact plugs 36 are formed in the interlayer insulating films 10 and 12 so that the total area becomes a value exceeding 1/855.

  As a result, it is possible to prevent the pattern breakdown at the electrically unstable portion from the contact hole to the drive wiring layer 35 due to the wafer charging by the plasma processing, and further to cause the resistance abnormality, and at a predetermined chip size. High pixel count can be realized.

  In the first and second embodiments, one or more of the transfer electrodes 32 and 33 that are connected to the drive wiring layer 35 and are in an electrically floating state have a total bottom area within a predetermined threshold range with respect to the total area. A contact hole is formed as a connection hole. In this case, the total area of the upper surface of the drive wiring layer 35 is not added to the total area (upper area) of the transfer electrodes 32 and 33 connected to the drive wiring layer 35. The transfer electrodes 32 and 33 are arranged close to each other on the substrate 4 via the gate oxide film 7, and the gate capacitance between the substrate 4 and the transfer electrodes 32 and 33 via the gate oxide film 7 is reduced by gate oxidation. Since the gate capacitance between the substrate 4 and the drive wiring layer 35 through the film 7 and the interlayer insulating film 9 is overwhelmingly large, the substrate 4 and the drive wiring through the gate oxide film 7 and the interlayer insulating film 9 Ignoring the gate capacitance between layers 35 It is good to.

In the second embodiment, the case where the thickness of the gate oxide film 7 is 10 nm has been described. However, the present invention is not limited to this, and when the thickness of the gate oxide film 7 is 30 nm, the thickness of 1.5 is formed on the substrate 4. The gate capacitance that can be stored in the transfer electrodes 32 and 33 in the floating state formed through the double-thick gate oxide film is the square of the distance by the distance that the transfer electrodes 32 and 33 are moved 1.5 times on the substrate 4. For example, it decreases to about 0.44 times. For this reason, when the contact hole of the contact plug 36 is formed, the driving wiring is formed from the contact plug 36 using a plasma etching apparatus (RIE type) having a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. The total area where the bottom area is shifted to a range of “1/1943 to 1/7500” with respect to the total upper area (total area of the gate electrode) of the transfer electrodes 32 and 33 connected via the layer 35 and the contact plug 34 Thus, a contact hole as one or a plurality of connection holes to be the contact plug 36 may be formed. In this case, even if a high plasma density plasma etching apparatus (ICP type) of 1 × 10 ¹¹ / cm ³ or more is used, the range in which pattern destruction does not occur becomes wide, and a high plasma of 1 × 10 ¹¹ / cm ³ or more is obtained. By using a density plasma etching apparatus (ICP type), it is possible to realize further miniaturization processing and shortening of man-hours.

(Embodiment 3)
In the third embodiment, a case will be described in which the drive wiring layer 35 is drawn out from both sides of a plurality of pixel portions for each row and the contact plug 36B is formed on each of them in order to adjust the total area of the bottom of the contact hole. To do.

  FIG. 5 is a plan view schematically showing an example of a connection configuration example of a pixel array region of the CCD solid-state imaging device and the outside thereof in Embodiment 3 of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated to the member which show | plays the same effect as the structural member described in FIG.1, FIG2 and FIG.4.

  In FIG. 5, the CCD solid-state imaging device 1 </ b> B according to the third embodiment includes a plurality of photoelectric conversion units 2 as a plurality of light receiving units that photoelectrically convert image light from a subject to image 2 in a matrix direction (vertical and horizontal directions). The pixel array region 20 (imaging region) is configured by being arranged in a matrix with dimensions. A planar view region having the photoelectric conversion unit 2 and the two transfer electrodes 32 and 33 on the left side is configured as a pixel unit 21.

  In order to make it possible to adjust so that the total area of the bottom of the contact hole to be the contact plug 36B is maximized, the drive wiring layer 35 is led out from both sides of the plurality of pixel portions 21 for each row and is placed on them. Contact plugs 36B are respectively formed. Here, the contact plugs 36B are described only for the third row from the top, but the contact plugs 36B are provided on the respective drive wiring layers 35 drawn from both sides with respect to all rows. In the pixel array region 20, only the 10th row and the 12th column are shown, but in the normal imaging unit (pixel array region 20), there are many more matrices.

A contact hole of the contact plug 36B for applying a voltage to the transfer electrodes 32 and 33 to transfer the signal charge accumulated in the photoelectric conversion unit 2 is formed on the drive wiring layer 35 on the drive wiring layer 35 outside the pixel array region 20. It is formed through the films 10 and 12. At this time, since the total area of the transfer electrodes 32 and 33 having the same potential as that of the drive wiring layer 35 is almost uniquely determined by the required number of pixels and the chip size, the area of the bottom of the contact hole is transferred. In the case of designing by adjusting the size (diameter or one side) and the number of contact holes so that the threshold value of the area of the electrodes 32 and 33 exceeds, for example, 1/855, high plasma of 1 × 10 ¹¹ / cm ³ or more. Even if a high-density plasma etching apparatus (ICP type) is used, fine processing can be performed and the number of processes can be shortened without causing pattern destruction. Also, the contact hole size (diameter or one side) and the number of contact holes are adjusted so that the area of the bottom of the contact hole is, for example, 1/855 to 1/7500 as the threshold range of the area of the transfer electrodes 32 and 33. In this case, pattern destruction occurs in the plasma etching apparatus (ICP type) using a low plasma density plasma etching apparatus (RIE type) of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. Pattern destruction can be prevented.

As described above, according to the third embodiment, the pixel array region 20 (imaging region) is obtained by pulling out the drive wiring layers 35 from both sides of the plurality of pixel units for each row and providing the contact plugs 36B on them. The total area of the bottom of the contact hole that becomes the contact plug 36B can be increased to the maximum. Here, with respect to the total area of the transfer electrodes 32 and 33 in the plurality of pixel portions 21 for one row, a plurality of contact holes on the drive wiring layer 35 drawn from both sides of the plurality of pixel portions 21 for one row are provided. The ratio of the total area of the bottom can be greatly increased, and even if a plasma etching apparatus (ICP type) with a high plasma density of 1 × 10 ¹¹ / cm ³ or more is used, patterning does not occur and miniaturization is performed. And the threshold range which can implement | achieve shortening of a man-hour can be expanded. When a plasma etching apparatus (ICP type) with a high plasma density of 1 × 10 ¹¹ / cm ³ or more is used, such as in the case of a CCD type solid-state imaging device, 1 × Pattern destruction can be prevented by forming contact holes using a plasma etching apparatus (RIE type) having a low plasma density of 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less.

(Embodiment 4)
In the third embodiment, in order to adjust the total area of the bottoms of one or a plurality of contact holes, the drive wiring layers 35 are drawn from both sides of the plurality of pixel portions 21 for each row, and the contact plugs 36B are respectively formed thereon. The case where the ratio of the total area of the bottom of one or more contact holes to the total area of the transfer electrodes 32 and 33 in the pixel array region 20 (imaging region) is maximized has been described. 4, in order to adjust the total area of the bottoms of the contact holes, the drive wiring layers 35 are drawn out from both sides of the plurality of pixel parts 21 in the row, and a pair of adjacent drive wirings connected to each other. The contact plugs 36C are formed on the layer 35, so that contact is made in the pixel array region 20 (imaging region). It will be described to reduce to a minimum the total area of the bottom of the hole.

  FIG. 6 is a plan view schematically showing an example of a pixel array region of a CCD solid-state imaging device and an external connection configuration in Embodiment 4 of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated to the member which show | plays the same effect as the structural member described in FIG.1, FIG2 and FIG.4.

  In FIG. 6, in the CCD solid-state imaging device 1 </ b> C according to the third embodiment, a plurality of photoelectric conversion units 2 serving as a plurality of light receiving units that photoelectrically convert image light from a subject to capture two in the matrix direction (vertical and horizontal directions). The pixel array region 20 (imaging region) is configured by being arranged in a matrix with dimensions. A planar view region having the photoelectric conversion unit 2 and the two transfer electrodes 32 and 33 on the left side is configured as a pixel unit 21.

  In order to make the adjustment possible so as to reduce the total area of the bottom of the contact hole that becomes the contact plug 36C, the drive wiring layer 35 is drawn out from both sides of the plurality of pixel portions 21 for each row, Contact plugs 36C are respectively formed on a pair of adjacent drive wiring layers 35 connected to each other by the drive wiring layer 35C. In the pixel array region 20, only the 10th row and the 12th column are shown, but in the normal imaging region (pixel array region 20), there are many more matrices.

A contact hole of a contact plug 36C for applying a voltage to the transfer electrodes 32 and 33 for reading out and transferring the signal charge accumulated in the photoelectric conversion unit 2 is formed on the drive wiring layer 35 outside the pixel array region 20. It is formed through the interlayer insulating films 10 and 12. At this time, since the total area of the transfer electrodes 32 and 33 having the same potential as that of the drive wiring layer 35 is almost uniquely determined by the required number of pixels and the chip size, the area of the bottom of the contact hole is transferred. In the case of designing by adjusting the size (diameter or one side) and the number of contact holes so that the threshold value of the area of the electrodes 32 and 33 exceeds, for example, 1/855, high plasma of 1 × 10 ¹¹ / cm ³ or more. Even if a high-density plasma etching apparatus (ICP type) is used, fine processing can be performed and the number of processes can be shortened without causing pattern destruction. Also, the contact hole size (diameter or one side) and the number of contact holes are adjusted so that the area of the bottom of the contact hole is, for example, 1/855 to 1/7500 as the threshold range of the area of the transfer electrodes 32 and 33. In this case, pattern destruction occurs in the plasma etching apparatus (ICP type) using a low plasma density plasma etching apparatus (RIE type) of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. Pattern destruction can be prevented.

As described above, according to the fourth embodiment, the drive wiring layer 35 is drawn out from both sides of the plurality of pixel units for each row, and contacts are made on the adjacent pair of drive wiring layers 35 respectively connected to every other one. By providing the plugs 36C, the total area of the bottoms of the contact holes that become the contact plugs 36C in the pixel array region 20 (imaging region) can be reduced to the minimum. Here, the plurality of pixel portions 21 for one row with respect to the total area of the transfer electrodes 32 and 33 in the plurality of pixel portions 21 in every other row (about half of all the transfer electrodes 32 and 33 in the pixel array region 20). along with pulling out from both sides, it is possible to reduce the ratio of the total area of the bottom of the plurality of contact holes on the drive wiring layers 35 of the adjacent pair connected respectively to every other them greatly, 1 × 10 ¹¹ / Even if a plasma etching apparatus (ICP type) with a high plasma density of cm ³ or more is used, the threshold range in which miniaturization and reduction of man-hours can be realized without causing pattern destruction. When a plasma etching apparatus (ICP type) having a high plasma density of 1 × 10 ¹¹ / cm ³ or more is used, if it is within a threshold range exceeding the threshold value causing pattern destruction, 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ^A contact hole can be formed using a plasma etching apparatus (RIE type) with a low plasma density of ¹¹ / cm ³ or less to prevent pattern destruction.

  In the third embodiment, a case where the total area of the bottoms of the contact holes is maximized in the pixel array region 20 (imaging region) will be described. In the fourth embodiment, the contact in the pixel array region 20 (imaging region) is described. Although the case where the total area of the bottom of the hole is reduced to the minimum has been described, the present invention is not limited to this, and the total area of the bottom of the contact hole of the third embodiment and the total area of the bottom of the contact hole of the fourth embodiment are not limited thereto. The total area of the bottom of the contact hole between the minimum and the minimum can be designed by adjusting the size (diameter or one side) and the number of contact holes. The case will be described with reference to FIG.

  FIG. 7 is a plan view schematically showing another connection configuration example of the pixel array region of the CCD type solid-state imaging device and the outside thereof in the fourth embodiment of the present invention.

  In FIG. 7, in order to adjust the total area of the bottom of the contact hole that becomes the contact plug 36D, the drive wiring layer 35 is drawn out from both sides of the plurality of pixel portions 21 for each row, and the drive wiring layer 35 and its Every other driving wiring layer 35 is connected by a driving wiring layer 35D, and each driving wiring layer 35 adjacent to the driving wiring layer 35 and every other driving wiring layer 35 are connected by a driving wiring layer 35D. Contact plugs 36D are respectively formed on a pair of drive wiring layers 35 adjacent to the above. The four rows are repeatedly formed, and contact plugs 36D are formed on the pair of adjacent drive wiring layers 35 for conveyance for every four rows. Here, only the 10th row and the 12th column are shown in the pixel array region 20, but there are many more matrices in the normal imaging region (pixel array region 20).

(Embodiment 5)
In the first to fourth embodiments, in order to prevent pattern destruction, contact holes are formed using a plasma etching apparatus (RIE type) having a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. Although the case where the characteristic configuration to be formed is applied to any of the CCD type solid-state imaging devices 1 and 1A to 1D has been described, in the fifth embodiment, in order to prevent pattern destruction, 1 × 10 ¹⁰ / cm ³ or more 1 A case will be described in which a characteristic configuration in which contact holes are formed using a plasma etching apparatus (RIE type) with a low plasma density of × 10 ¹¹ / cm ³ or less is applied to the CMOS solid-state imaging device 1E.

  The CMOS type solid-state imaging device (CMOS image sensor) is a photoelectric conversion unit that photoelectrically converts incident light by a vertical transfer register 3 having a CCD structure, like the CCD type solid-state imaging device 1 and 1A to 1D (CCD image sensor). The signal charge from 2 is transferred in the vertical direction, and each signal charge from the vertical transfer register 3 is transferred in the horizontal direction by a horizontal transfer register (not shown) of the CCD structure without using a CCD structure. A control line composed of aluminum (Al) wiring or the like like a device reads out a signal charge from a photoelectric conversion unit for each pixel, converts it into voltage, and amplifies the signal according to the conversion voltage for each pixel unit. Each imaging signal is sequentially read from the selected pixel.

The transfer electrodes 32 and 33 in the CCD structure for charge transfer of the CCD type solid-state imaging device 1, 1 </ b> A to 1 </ b> D are in a floating state, and not only the total area occupied in the imaging region is very wide, but also the gate oxide film 7 or 7 </ b> A is provided. Therefore, the charging capacity of the transfer electrodes 32 and 33 is very large. For this reason, in the manufacture of the CCD type solid-state imaging device 1, 1A to 1D, there is a symptom (pattern destruction) that is different from the conventional symptom that occurs in the microfabrication process (conduction failure due to accumulation of reaction product on the bottom of the contact hole). Occur. In order to solve such a new problem, in the first embodiment, the size (diameter of the contact hole) is set so that the total area of the bottom of the contact hole exceeds 1/855 as a threshold of the total area of the transfer electrodes 32 and 33. If one side) and the number can be adjusted, the pattern can be finely processed without causing pattern destruction using a plasma etching apparatus (ICP type) with a high plasma density of 1 × 10 ¹¹ / cm ³ or more. The man-hour can be shortened. Further, the size (diameter or one side) and the number of contact holes are adjusted so that the total area of the bottom of the contact hole is 1/855 to 1/7500 as the threshold range of the total area of the transfer electrodes 32 and 33. If possible, pattern destruction occurs in the plasma etching apparatus (ICP type) using a plasma etching apparatus (RIE type) with a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less. However, pattern destruction can be prevented. This can also be applied to the CMOS solid-state imaging device 1E shown in FIG.

  Hereinafter, a configuration example of a main part of the CMOS solid-state imaging device 1E according to the fifth embodiment will be described in detail with reference to FIG.

  FIG. 8 is a longitudinal sectional view schematically showing an example of the configuration of the main part of a CMOS solid-state imaging device according to Embodiment 5 of the present invention.

  In FIG. 8, in the CMOS solid-state imaging device 1E according to the fifth embodiment, a plurality of pixel portions 42 are arranged on a substrate 41 in a matrix. In each pixel portion 42, a photoelectric conversion portion 43 (photodiode as a light receiving portion) is formed for each pixel portion 42 as a surface layer of the semiconductor substrate 41. Adjacent to the photoelectric conversion unit 43, a charge transfer unit 44 of a charge transfer transistor for transferring signal charges to a floating diffusion unit (charge voltage conversion unit) FD is provided. On the charge transfer portion 44, a transfer electrode 46 as an extraction electrode is provided via a gate oxide film 45. Further, the signal charge transferred to the floating diffusion unit FD is converted into a voltage for each photoelectric conversion unit 43, and is amplified by an amplification transistor (not shown) in accordance with the converted voltage to be used as an imaging signal for each pixel unit. A reading circuit for reading is provided.

  As the readout circuit, a reset transistor for resetting the floating diffusion portion FD to a predetermined voltage (for example, a power supply voltage), and a signal is amplified according to the potential of the floating diffusion portion FD after the reset and a signal is output to the signal line. An amplifying transistor is provided in the logic transistor region 47. The logic transistor region 47 is provided for each pixel portion 42 with an element isolation layer STI interposed therebetween.

  Above the transfer electrode 46, the floating diffusion portion FD, and the logic transistor region 47, a circuit wiring portion of the readout circuit and a circuit wiring portion connected to the transfer electrode 46 and the floating diffusion portion FD are provided. Yes. An interlayer insulating film 48 is formed on the gate oxide film 45 and the transfer electrode 46, a wiring layer 49 is formed thereon, another interlayer insulating film 50 is formed thereon, and another wiring layer 51 is formed thereon. The circuit wiring portion is configured by forming.

  Also, between the wiring layer 49 and the transfer electrode 46, between the wiring layer 49 and the floating diffusion portion FD, and between the wiring layer 49 and the source (S) / drain (D) and gate (G) of the logic transistor region 47, respectively. In addition, contact plugs 52 made of a conductive material (for example, tungsten) are formed, and contact plugs 53 are formed between each wiring layer 49 and each wiring layer 51 thereon, and are made of aluminum, copper, or the like. The wiring layers 49 and 51 are electrically connected to the transfer electrode 46, the floating diffusion portion FD, and the source (S) / drain (D) and gate (G) of the logic transistor region 47, respectively.

  On the interlayer insulating film 50, color filters 54 of R, G, B color arrangement (for example, Bayer arrangement) arranged for each photoelectric conversion unit 43 so as to correspond to the photoelectric conversion units 43 are formed. A microlens 55 for condensing light to the photoelectric conversion unit 43 is formed on the photoelectric conversion unit 43 via a planarizing film (not shown). In this case, the microlens 55 may be formed of a color filter material. In this case, the color filter 54 and its planarization film are not required separately.

  The floating state with a high charging capacity includes the transfer electrode 46 and the gate (G) of the logic transistor region 47. Here, the transfer electrode 46 will be described. When a contact hole is formed using a high plasma density plasma etching apparatus (ICP type), a transfer electrode 46 is formed using a low plasma density plasma etching apparatus (RIE type) within a threshold range (area ratio range) that causes pattern destruction. By forming a contact hole that becomes the contact plug 53 connected to the contact hole 53, the present invention that can prevent the pattern destruction of the contact hole can be applied to the transfer electrode 46 of the CMOS type solid-state imaging device 1E.

For example, if the thickness of the gate oxide film 45 is 20 nm, the total area of the transfer electrode 46 that is connected to the wiring layer 49 and is in an electrically floating state at the time of contact hole formation is the same as in the first embodiment. Plasma dry etching with a low plasma density of 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less if it can be designed within the threshold range of the total bottom area of contact holes of 1/855 to 1/7500. By forming a contact hole as one or a plurality of connection holes on the wiring layer 49 using an apparatus (RIE type), the electrically conductive layer is electrically unstable from the contact hole due to wafer charging by plasma processing. It is possible to prevent pattern destruction and further causing resistance abnormality.

Further, the size (diameter or one side) and the number of contact holes are adjusted so that the total area of the bottom of the contact hole that becomes the contact plug 53 exceeds 1/855 as a threshold of the total area of one or a plurality of transfer electrodes 46. Can be designed (outside the range of 1/855 to 1/7500) using a plasma etching apparatus (ICP type) with a high plasma density of 1 × 10 ¹¹ / cm ³ or more without causing pattern destruction, Microfabrication can be performed and man-hours can be shortened.

  As described above, according to the fifth embodiment, the structure of the pixel array and the total area of the transfer electrode 46 in the pixel array are demanded in the demand for higher pixels when manufacturing the CMOS solid-state imaging device 1E. The total bottom area of the contact plug 53 (contact hole) on the wiring layer 49 having the same potential as that of the contact hole 53 is optimized and the plasma density in plasma dry etching of the corresponding contact hole is increased according to the design value. By controlling between the plasma density and the low plasma density, the charge accumulated in the chip is suppressed, and pattern destruction occurs in electrically unstable portions of the conductive layer from the contact hole due to wafer charging by plasma processing. Furthermore, it is possible to prevent abnormal resistance and to realize a high pixel with a predetermined chip size.

  In short, to limit the gate capacity per unit contact hole area, or to form a contact hole with low-density plasma equipment when the gate capacity exceeds the threshold, stabilize the contact hole processing without pattern destruction, A CMOS-type solid-state imaging device 1E having higher pixels can be manufactured.

(Embodiment 6)
In light of the above Embodiments 1 to 5, in Embodiment 6, as a method for manufacturing a solid-state imaging device, charges from the photoelectric conversion unit 2 that photoelectrically converts incident light are transferred onto a substrate via a gate insulating film. A charge transfer electrode forming step for forming a transfer electrode for the electrode, and an interlayer insulating film on the wiring layer connected to the transfer electrode, with one or a plurality of contact holes (connection holes) for the total area A of the charge transfer electrode Depending on the ratio B / A of the total area B, either high plasma density or low plasma density plasma etching treatment is selected to prevent contact hole (connection hole) pattern destruction, and the wiring layer is reached. Alternatively, a connection hole forming step of forming a plurality of contact holes (connection holes) is included.

  The ratio B / A of the total area B of one or more connection holes to the total upper area A of the charge transfer electrode is compared with a threshold value (reference value), and a high plasma density and a low plasma density are prevented so as to prevent pattern destruction of the connection holes. Select one of the plasma etching processes of plasma density.

As described above, the low plasma density (RIE type) is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less, and the high plasma density (ICP type) is a density exceeding 1 × 10 ¹¹ / cm ^3. It is. As described above, the low plasma density plasma etching process includes Ar gas and at least one gas of O ₂ or CO gas, C ₄ F ₆ , C ₅ F ₈ , C ₄ F ₈ and C ₂ F _6. One or more of these gases are used.

  Further, the ratio B / A of the total area B of one or a plurality of contact holes (connection holes) to the total upper area A of the charge transfer electrode is a predetermined threshold area ratio 1 / C (in the first embodiment, the ICP type from the experimental results) However, if the value is larger than the threshold value 1/855 at which pattern destruction does not occur, plasma etching treatment with high plasma density is performed, and one or more contact holes (connection holes) for the total area A of the charge transfer electrode The ratio B / A of the total area B is a predetermined threshold area ratio 1 / C (threshold 1/855 for the RIE type alone in the first embodiment, but from the experimental results, the threshold 1/855 at which pattern destruction does not occur even with the ICP type. If the value is within the range of 1/7500, the low plasma density plasma etching process is performed.

  As described above, according to the sixth embodiment, the ratio B / A between the total area A of the transfer electrodes and the total bottom area B of the contact hole having the same potential is designed to be optimized, and the contact hole corresponding thereto is designed. By controlling the plasma density in plasma dry etching between a high plasma density and a low plasma density, the charge accumulated in the chip is suppressed, and the electrical charge from the contact hole to the wiring layer due to wafer charging by plasma processing is suppressed. It is possible to prevent pattern destruction at a stable location and further to cause resistance abnormality, and it is possible to increase the number of pixels with a predetermined chip size.

  In short, if the gate capacity per unit contact hole area is constrained or the gate capacity exceeds a threshold value, contact holes are formed by low density plasma equipment (RIE type), so that contact hole processing can be performed without pattern destruction. It is possible to stabilize and manufacture a solid-state imaging device having higher pixels with high quality.

(Embodiment 7)
FIG. 9 shows, as Embodiment 7 of the present invention, an electronic information device using any one of the CCD type solid-state imaging devices 1 and 1A to 1D and the CMOS type solid-state imaging device 1E according to Embodiments 1 to 6 of the present invention as an imaging unit. It is a block diagram which shows the example of schematic structure.

  In FIG. 9, an electronic information device 90 according to the seventh embodiment includes an imaging unit 91 that is one of the CCD solid-state imaging devices 1 and 1A to 1D and the CMOS solid-state imaging device 1E according to the first to sixth embodiments of the present invention, A memory unit 92 such as a recording medium that enables data recording after the color image signal from the image pickup unit is processed for a predetermined signal for recording, and the color image signal from the image pickup unit 91 is subjected to a predetermined signal process for display A display unit 93 such as a liquid crystal display device that can be displayed on a display screen such as a liquid crystal display screen later, and transmission / reception that enables communication processing after performing predetermined signal processing for color image signals from the imaging unit 91 for communication A communication unit 94 such as an apparatus, and an image output unit 95 such as a printer that can perform print processing after performing a predetermined print signal processing for color image signals from the imaging unit 91 for printing. That. The electronic information device 90 is not limited to this, but in addition to the imaging unit 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output unit 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the seventh embodiment, the contact hole processing can be stabilized without pattern destruction, and the CCD solid-state imaging devices 1 and 1A to 1D and the CMOS solid-state of the first to sixth embodiments having higher pixels. It is possible to obtain a high-quality electronic information device using any one of the imaging elements 1E for the imaging unit.

  As a result, based on the color image signal from the imaging unit 91, it can be displayed on the display screen, or it can be printed out (printed) by the image output unit 95 on the paper. The communication data can be satisfactorily communicated by wire or wirelessly, can be stored favorably by performing predetermined data compression processing in the memory unit 92, and various data processing can be satisfactorily performed.

  In addition, as mentioned above, although this invention was illustrated using preferable Embodiment 1-7 of this invention, this invention should not be limited and limited to this Embodiment 1-7. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 7 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device configured by a semiconductor element that photoelectrically converts image light from a subject to capture an image, a manufacturing method thereof, and a solid-state imaging device manufactured by the manufacturing method as an image input device for an imaging unit. Plasma processing in the field of electronic information devices such as digital cameras such as digital video cameras and digital still cameras, image input cameras such as surveillance cameras, scanner devices, facsimile devices, television telephone devices, and mobile phone devices with cameras. Due to the wafer charging, it is possible to prevent the pattern breakdown from occurring in the electrically unstable portion of the conductive layer from the contact hole and further to cause the resistance abnormality, and it is possible to realize a high pixel with a predetermined chip size.

DESCRIPTION OF SYMBOLS 1, 1A-1D CCD type solid-state image sensor 2 Photoelectric conversion part 3 Vertical transfer register of CCD structure 31 Vertical charge transfer part (transfer channel)
32, 33 Transfer electrode 34, 36, 36B to 36D Contact plug 35, 35C, 35D Drive wiring layer 4 Substrate 5 Signal readout unit 6 Channel stop 7, 7A Gate oxide film 8 Antireflection film 9, 10, 12 Interlayer insulating film 11 Light shielding film 13 Optical waveguide member 14 Color filter 15 Micro lens 20 Pixel array region 21 Pixel unit 1E CMOS solid-state imaging device 41 Substrate 42 Pixel unit 43 Photoelectric conversion unit 44 Charge transfer unit 45 Gate oxide film 46 Transfer gate (transfer electrode)
47 Logic transistor region 48, 50 Interlayer insulating film 49, 51 Wiring layer 52, 53 Contact plug 54 Color filter 55 Micro lens STI Element isolation layer FD Floating diffusion part 90 Electronic information device 91 Solid-state imaging device 92 Memory part 93 Display part 94 Communication unit 95 Image output unit

Claims (6)

  One or a plurality of connection holes for the total area A of the charge transfer electrode is formed on the interlayer insulating film on the wiring layer connected to the charge transfer electrode for transferring the charge from the photoelectric conversion unit that photoelectrically converts incident light. The ratio B / A of the total area B is compared with a threshold value, and either high plasma density or low plasma density plasma etching treatment is selected so as to prevent pattern destruction of the connection hole, and the wiring layer is reached. A method for manufacturing a solid-state imaging device, comprising a connection hole forming step for forming the one or more connection holes. 2. The solid-state imaging device according to claim 1, wherein the low plasma density is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹¹ / cm ³ or less, and the high plasma density is a density exceeding 1 × 10 ¹¹ / cm ^3. Manufacturing method. The low plasma density plasma etching process includes Ar gas and at least one of O ₂ or CO gas and one of C ₄ F ₆ , C ₅ F ₈ , C ₄ F ₈ and C ₂ F _6. Or the manufacturing method of the solid-state image sensor of Claim 2 using several gas.   When the ratio B / A of the total area B of the one or more connection holes to the total upper area A of the charge transfer electrode is larger than the predetermined threshold area ratio 1 / C, the plasma etching process with the high plasma density is performed. When the ratio B / A of the total area B of the one or more connection holes to the total area A of the charge transfer electrode is in the range of the predetermined threshold area ratio 1 / C to 1/7500, the low plasma density The manufacturing method of the solid-state image sensor of Claim 1 or 2 which performs plasma etching process of this.   The method of manufacturing a solid-state imaging device according to claim 1, further comprising a charge transfer electrode forming step of forming the charge transfer electrode on a substrate via a gate insulating film before the connection hole forming step.   An electronic information device using a solid-state imaging device manufactured by the method for manufacturing a solid-state imaging device according to claim 1 as an image input device for an imaging unit.