JP2016009512A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately detect a defect of a capacitive element.SOLUTION: A potential change unit HFCIR changes a voltage between a lower electrode LE and an upper electrode UE either from a reference potential to 0 V or from 0 V to the reference potential for 100 ns or more. This potential change may be performed a plurality of times. After that, the potential of the lower electrode LE is measured to determine whether or not the capacitive element CP is defective. A control unit CCIR1 controls the operations of the potential change unit HFCIR and potential switching unit VCCIR.

Description

  The present invention relates to a semiconductor device, and is a technique applicable to a semiconductor device having a capacitor, for example.

  In many cases, a capacitive element is mounted on a semiconductor device. This capacitive element has a configuration in which a dielectric film is sandwiched between two electrodes, and is used, for example, in a memory or an analog circuit. One of the characteristics required for the capacitor element is a hold characteristic of accumulated charges. One of the factors affecting this characteristic is the quality of the dielectric film. For example, Patent Document 1 describes performing a stress test of a capacitive element by applying a predetermined DC voltage or pulse voltage between two electrodes in a capacitive element constituting a DRAM. According to this stress test, it is described that defective cells of DRAM can be screened.

JP H04-293247 A

  As a result of investigation by the present inventors, it has been found that there is a defect that cannot be detected by a test method in which a predetermined DC voltage or pulse voltage is applied between two electrodes. The inventor has studied a method for enabling detection of such defects. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes a capacitive element, a voltage changing unit, and a control unit. The capacitive element has a configuration in which a first electrode, a dielectric film, and a second electrode are stacked in this order. The voltage changing unit changes the voltage between the first electrode and the second electrode from the reference potential to 0 V or from 0 V to the reference potential over a time of 100 ns or more. The control unit controls the voltage changing unit.

  According to the one embodiment, it is possible to accurately detect a defect of the capacitive element.

It is a circuit diagram which shows the structure of the semiconductor device SD which concerns on embodiment. It is an example of sectional drawing of semiconductor device SD. It is a timing chart which shows an example of operation of control part CCIR1, 1st potential generating part VCIR1, and potential change part HFCIR. It is a timing chart which shows the modification of FIG. It is a timing chart which shows the modification of FIG. It is a timing chart which shows the modification of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a circuit diagram showing a configuration of a semiconductor device SD according to the embodiment. The semiconductor device SD has a memory region MR and a circuit region CIR. A DRAM (memory element) and its peripheral circuit CCIR2 are formed in the memory region MR. In the circuit region CIR, a logic circuit and an analog circuit are formed.

  Specifically, in the memory region MR, a capacitive element CP, transistors TR1, TR2, and TR11, a word line WL, a bit line BL, a word voltage control unit WCIR, a bit voltage control unit BCIR, and a peripheral circuit CCIR2 are formed. . One electrode (first electrode: specifically, a lower electrode LE described later) of the capacitive element CP is connected to the bit line BL via the transistor TR1. The gate electrode of the transistor TR1 is connected to the word line WL. The potential of the word line WL is controlled by the word voltage control unit WCIR. The potential of the bit line BL is controlled by the bit voltage controller BCIR through the transistor TR11. The bit voltage controller BCIR is connected to the gate electrode of the transistor TR11. When the transistor TR11 is turned on, the potential of the bit line BL rises.

  In the circuit region CIR, a potential switching unit VCCIR, a first potential generating unit VCIR1, a second potential generating unit VCIR2, a potential changing unit HFCIR, and a control unit CCIR1 are formed. The first potential generation unit VCIR1 and the second potential generation unit VCIR2 are connected to the other electrode (second electrode: specifically, an upper electrode UE described later) of the capacitive element CP through the potential switching unit VCCIR. . The first potential generator VCIR1 applies the first potential (Vcc) to the upper electrode UE. The second potential generator VCIR2 applies a potential (second potential) lower than Vcc to the upper electrode UE. The second potential is, for example, Vcc / 2. The potential switching unit VCCIR selects one of the first potential generation unit VCIR1 and the second potential generation unit VCIR2, and is the electrode (specifically, an upper portion to be described later) of the capacitive element CP that is not connected to the bit line BL. To the electrode UE). The voltage generated by the first potential generator VCIR1 and the second potential generator VCIR2 is a DC voltage.

  A potential changing unit HFCIR is also connected between the potential switching unit VCCIR and the first potential generating unit VCIR1. The potential changing unit HFCIR changes the voltage applied to the upper electrode UE, that is, the voltage between the lower electrode LE and the upper electrode UE from the reference potential to 0 V, or from 0 V to the reference potential, over a time of 100 ns or more. . The reference potential is, for example, the potential generated by the first potential generator VCIR1, that is, the maximum value of the voltage applied between the lower electrode LE and the upper electrode UE during the operation of the DRAM. The potential change unit HFCIR is, for example, a high frequency generation circuit. The high frequency generated by the potential changing unit HFCIR is, for example, 10 kHz or more and 10 MHz or less. Details of the operation of the potential changing unit HFCIR will be described later.

  The control unit CCIR1 controls operations of the first potential generation unit VCIR1, the second potential generation unit VCIR2, the potential change unit HFCIR, and the potential switching unit VCCIR. When operating the memory in the memory region MR, the controller CCIR1 connects the second potential generator VCIR2 to the upper electrode UE of the capacitive element CP. Thereby, a fixed potential lower than Vcc, for example, Vcc / 2 is applied to the upper electrode UE. On the other hand, the control unit CCIR1 connects the first potential generation unit VCIR1 and the potential change unit HFCIR to the upper electrode UE when inspecting the capacitive element CP. Thereby, when inspecting the capacitive element CP, the potential of the upper electrode UE changes. Note that while the potential of the upper electrode UE is changing, the potential of the lower electrode LE of the capacitive element CP is fixed to 0V. For this reason, the voltage between the lower electrodes LE of the upper electrode UE changes.

  FIG. 2 is an example of a cross-sectional view of the semiconductor device SD. The semiconductor device SD is formed using the substrate SUB. The substrate SUB is a semiconductor substrate such as a silicon substrate. On the substrate SUB, the transistor TR1 shown in FIG. 1 is formed. The region where the transistor TR1 is formed is isolated from other regions by the element isolation film STI. Further, transistors TR2 and TR3 are formed on the substrate SUB. The transistor TR2 is a part of the peripheral circuit CCIR2. The transistor TR3 is formed in the circuit area CIR and constitutes a circuit in the circuit area CIR. Note that the transistor TR11 illustrated in FIG. 1 also has the same configuration as the transistors TR2 and TR3.

  On the substrate SUB, an etching stopper film EST1, an insulating film DL1, an etching stopper film EST2, an insulating film DL2, and a multilayer wiring layer MINSL are formed in this order. A bit line BL is formed on the insulating film DL1. The bit line BL is connected to the transistor TR1 through a bit contact BCT embedded in the insulating film DL1. The insulating film DL2 covers the bit line BL.

  The multilayer wiring layer MINSL has a configuration in which an etching stopper film EST and an interlayer insulating film INSL are repeatedly stacked. A wiring INC2 and a via VA2 are embedded in each of the interlayer insulating films INSL. The wiring INC2 and the via VA2 are Cu, for example, and are formed using a damascene method. One of the wirings INC2 is connected to the transistor TR3 through a contact CT2 embedded in the insulating film DL2 and a contact CT1 embedded in the insulating film DL1.

  A capacitive element CP is formed in the multilayer wiring layer MINSL. The capacitive element CP is embedded in the recess TRN2. The recess TRN2 is formed in the plurality of interlayer insulating films INSL and at least one etching stopper film EST. The lower electrode LE, the dielectric film CDL, and the upper electrode UE of the capacitive element CP are stacked in this order on the bottom surface and the side surface of the recess TRN2. The lower electrode LE is a conductive film containing, for example, titanium, the dielectric film CDL is an insulating film containing, for example, zirconia, and the upper electrode UE is, for example, a conductive film containing titanium. The lower electrode LE is connected to the transistor TR1 through the capacitor contact CCT2 embedded in the insulating film DL2 and the etching stopper film EST2, and the capacitor contact CCT1 embedded in the insulating film DL1 and the etching stopper film EST1.

  A recess TRN1 is further formed in the interlayer insulating film INSL that overlaps the upper end of the recess TRN2 in the multilayer wiring layer MINSL. The recess TRN1 is formed only in one interlayer insulating film INSL, and includes a plurality of recesses TRN2 inside in a plan view. In other words, the plurality of recesses TRN2 are formed at the bottom of the recess TRN1. A capacitive element CP is embedded in each of the plurality of recesses TRN2. The dielectric film CDL and the upper electrode UE are also formed in the region where the recess TRN2 is not formed in the recess TRN1. In other words, the upper electrode UE is an electrode common to the plurality of capacitive elements CP.

  In addition, a plate electrode PL is embedded in a portion of the recess TRN1 and the recess TRN2 that is not filled with the lower electrode LE, the dielectric film CDL, and the upper electrode UE. The plate electrode PL is formed in the same process as the wiring INC2 embedded in the interlayer insulating film INSL in which the recess TRN1 is formed. In this case, the plate electrode PL is formed of Cu, for example. However, the plate electrode PL may be formed of other metals.

  A wiring INC2 is connected to the plate electrode PL through a via VA1. The wiring INC2 is connected to the potential switching unit VCCIR shown in FIG.

  FIG. 3 is a timing chart illustrating an example of operations of the control unit CCIR1, the first potential generation unit VCIR1, and the potential change unit HFCIR. This figure shows changes in the potentials of the word line WL, the upper electrode UE, and the lower electrode LE when one cell is inspected. FIG. 3B shows a case where the dielectric film CDL of the capacitive element CP is normal, and FIG. 3A shows a case where a defect exists in the dielectric film CDL.

  The cell inspection is performed, for example, when a signal is input from the outside (for example, a tester) to the control unit CCIR1. Before the inspection is performed, since the second potential generator VCIR2 is connected to the upper electrode UE of the capacitive element CP, the potential of the upper electrode UE is, for example, Vcc / 2. On the other hand, the potential of the lower electrode LE of the capacitive element CP is also the same as that of the upper electrode UE.

  When inspecting the capacitive element CP of a certain cell, the control unit CCIR1 controls the word voltage control unit WCIR and inputs a high signal to the word line WL connected to the transistor TR1 of the cell. As a result, the transistor TR1 is turned on, and the potential of the lower electrode LE of the capacitive element CP becomes 0V. Thereafter, the transistor TR1 is turned off.

  In this state, the control unit CCIR1 controls the potential switching unit VCCIR, connects the potential changing unit HFCIR and the first potential generating unit VCIR1 to the upper electrode UE of the capacitive element CP, and operates the potential changing unit HFCIR. Thereby, the potential of the upper electrode UE gradually changes between 0 V and Vcc. In other words, the voltage between the lower electrode LE and the upper electrode UE gradually changes between 0 V and Vcc. At this time, the time to reach Vcc from 0 V is, for example, 100 ns or more, preferably 1 ms or more, or 10 ms or more, and is sufficiently longer than the time (for example, 10 ns) when rising from 0 V to Vcc with a rectangular wave.

  A minute defect may occur in the dielectric film CDL of the capacitive element CP. If this defect exists, there is a possibility that electrons are trapped in this defect when electric charge is accumulated in the capacitive element CP. When electrons are trapped in the dielectric film CDL, a leak path is formed in the dielectric film CDL. In order to detect such a defect in the dielectric film CDL, it is necessary to trap electrons in the defect and to detect a current leak caused thereby.

  On the other hand, the voltage suitable for trapping electrons in the defect of the dielectric film CDL differs depending on the type of the defect and the position of the defect in the film thickness direction of the dielectric film CDL. Even when a voltage higher than this suitable voltage is applied, electrons are not trapped by defects in the dielectric film CDL and pass through. For this reason, it is difficult to detect the above-described defects by applying a rectangular wave between the upper electrode UE and the lower electrode LE as in a general inspection of the capacitive element CP.

  On the other hand, in the present embodiment, the voltage between the lower electrode LE and the upper electrode UE gradually changes between 0 V and Vcc. Therefore, even if there are defects at various positions of the dielectric film CDL, a voltage optimum for these defects is always applied to the dielectric film CDL for a certain period of time. Therefore, when a defect exists in the dielectric film CDL, electrons are trapped in these and a leak path is formed in the dielectric film CDL. Then, as shown in FIG. 3A, current gradually flows from the upper electrode UE to the lower electrode LE, and electric charges accumulate in the lower electrode LE. Along with this, the potential of the lower electrode LE gradually increases from 0V. In the example shown in FIG. 3A, the dielectric film CDL has a plurality of defects, and electrons are gradually trapped in these defects. For this reason, the potential of the lower electrode LE rises stepwise.

  Then, after inputting a constant inspection voltage to the upper electrode UE, the control unit CCIR1 controls the potential switching unit VCCIR to connect the second potential generation unit VCIR2 to the upper electrode UE of the capacitive element CP. Thereby, the potential of the upper electrode UE is fixed. In this state, the control unit CCIR1 controls the word voltage control unit WCIR, inputs a high signal to the word line WL connected to the transistor TR1 of the cell, and measures the potential of the lower electrode LE. When the potential of the lower electrode LE at this time is equal to or higher than the reference value, it is determined that the capacitive element CP is defective.

  In the example illustrated in FIG. 3, the potential changing unit HFCIR changes the potential of the upper electrode UE only in one cycle in a sine wave shape. However, the change in the potential of the upper electrode UE is not limited to the example shown in FIG. For example, as shown in FIG. 4, the potential changing unit HFCIR may gradually increase the potential of the upper electrode UE only once from 0 V to Vcc. 5 and 6, the potential changing unit HFCIR may apply a sine wave having a center voltage and an amplitude of Vcc / 2 to the upper electrode UE a plurality of times. According to the example shown in FIGS. 5 and 6, the voltage between the lower electrode LE and the upper electrode UE repeatedly changes between 0 V and Vcc. For this reason, the number of times that the voltage between the lower electrode LE and the upper electrode UE becomes a voltage at which charges are trapped by defects increases. Therefore, the possibility that a defective capacitive element CP can be detected increases.

  As described above, according to the present embodiment, when the capacitance element CP is inspected, the voltage between the lower electrode LE and the upper electrode UE gradually changes between 0 V and Vcc. Therefore, even if there are defects at various positions of the dielectric film CDL, a voltage optimum for these defects is always applied to the dielectric film CDL for a certain period of time. Therefore, the defective capacitive element CP can be detected based on the potential of the lower electrode LE.

  In the above example, the capacitive element CP constitutes a DRAM. However, the same inspection as in the above embodiment may be performed on the capacitive element constituting the analog circuit.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BCIR Bit voltage controller BCT Bit contact BL Bit line CCIR1 Controller CCIR2 Peripheral circuit CCT1 Capacitor contact CCT2 Capacitor contact CDL Dielectric film CIR Circuit region CP Capacitor element CT1 Contact DL1 Insulating film DL2 Insulating film EST Etching stopper film EST1 Etching stopper film EST2 Etching Stopper film HFCIR Potential change part INC2 Wiring INSL Interlayer insulating film LE Lower electrode MINSL Multilayer wiring layer MR Memory area PL Plate electrode SD Semiconductor device STI Element isolation film SUB Substrate TR1 Transistor TR11 Transistor TR2 Transistor TR3 Transistor TRN1 Recess TRN2 Recess UE Upper electrode VA1 Via VA2 Via VCCIR Potential switching unit VCIR1 First potential generating unit V CIR2 Second potential generator WCIR Word voltage controller WL Word line

Claims (6)

A capacitive element in which the first electrode, the dielectric film, and the second electrode are laminated in this order;
A voltage changing unit that changes the voltage between the first electrode and the second electrode from a reference potential to 0 V or from 0 V to the reference potential over a time of 100 ns or more;
A control unit for controlling the voltage changing unit;
A semiconductor device comprising: The semiconductor device according to claim 1,
The capacitive element is part of a storage element;
The semiconductor device, wherein the reference potential is a maximum value of a voltage applied between the first electrode and the second electrode during operation of the memory element. The semiconductor device according to claim 1,
The voltage changing unit is a semiconductor device that repeatedly changes a voltage between the first electrode and the second electrode between a reference potential and 0V. The semiconductor device according to claim 1,
A fixed potential generator for applying a fixed voltage between the first electrode and the second electrode;
A switching unit for selecting and connecting either the voltage changing unit or the fixed potential generating unit between the first electrode and the second electrode;
With
The control unit is a semiconductor device that controls the switching unit. The semiconductor device according to claim 1,
The control unit is a semiconductor device that operates the voltage changing unit when testing the capacitive element. The semiconductor device according to claim 5,
A transistor connected to the first electrode;
The control unit sets the voltage between the first electrode and the second electrode to 0, and then operates the voltage changing unit after turning off the transistor.

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