JP2016009156A - Gate driver circuit and el display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate driver circuit and EL display device that can decrease an amount of heat generation without reducing a picture quality.SOLUTION: An EL display device 1 comprises: a gate signal line 17; a source signal line 18; a display pixel 16; a gate driver IC21; a source driver IC22; and a TCON27. The TCON27 is configured to: determine a pixel row to be selected so that voltage signal amplitude to be output by the source driver IC22 is small; control a PdatB terminal; apply an ON-voltage to a gate signal line 17b according to a selected sequence to turn on a switch transistor 11b; write a picture signal of the source driver IC22 in a capacitor 19b; further turn on a transistor 11c during a blanking period; and, after writing a Vref voltage in a voltage capacitor 19a, turn on a transistor 11e to copy the picture image held in the capacitor 19b in the capacitor 19a .

Description

  The present disclosure relates to a gate driver circuit and an EL display device.

  As a display device using a current-driven light emitting element, an EL display using an organic electroluminescence element (hereinafter referred to as an EL element) is known. This EL display has the advantages of good viewing angle characteristics and low power consumption.

  The EL display includes a plurality of scanning lines (a plurality of gate signal lines), a plurality of signal lines (a plurality of source signal lines), a plurality of display pixels, a driving circuit, and the like. Each of the plurality of display pixels is disposed at an intersection of the gate signal line and the source signal line, and includes a switching element, a capacitor element (capacitor), a drive transistor, an EL element, and the like. Further, a method for suppressing the peak current or the like has been studied (for example, see Patent Document 1).

  In the EL display, a source driver IC (circuit) that outputs a video signal or the like is arranged in order to control the light emission luminance of a selected pixel. A source driver IC (circuit) applies a video signal to a source signal line. In the EL display, an on voltage or an off voltage is applied to the gate signal line connected to the selected pixel in order to control the light emission timing of the selected pixel. In recent years, EL displays tend to have higher definition and larger screens.

Japanese Patent Laid-Open No. 2005-70426

  However, an EL display using a large-screen size and high-definition display panel tends to increase the load capacity of the source signal line and increase the writing speed. If the load capacity of the source signal line is large and the writing speed (operation frequency) is high, the amount of heat generated by the source driver IC (circuit) (Integrated Circuit) that drives the source signal line increases. When the heat generation amount is expected to exceed the heat resistance of the source driver IC, there is a problem that a heat dissipation mechanism is required to prevent the source driver IC from being damaged. Further, the heat generated by the source driver IC is transferred to the display area of the EL display panel, which causes a problem that the EL element of the pixel is deteriorated. If the heat dissipation mechanism is large, the thickness of the panel module increases, and the EL display panel (EL display display) thin characteristic cannot be exhibited.

  Accordingly, the present disclosure provides a gate driver circuit and an EL display device that can reduce the amount of heat generated without deteriorating the video quality.

  A gate driver circuit according to one embodiment of the present disclosure is a gate driver circuit used in an EL display device having a display screen in which pixels having EL elements are arranged in a matrix, and includes a shift register circuit and a decoder circuit. The output of the shift register circuit and the output of the decoder circuit are made to correspond to the output of the gate signal line formed on the display screen.

  According to the EL display device of the present disclosure, it is possible to provide a gate driver circuit and an EL display device that can reduce the amount of heat generation without reducing the image quality.

It is explanatory drawing which shows an example of the load capacity | capacitance of the source signal line | wire of an EL display panel. It is a figure which shows the relationship between the luminance value of each line of an image, and the output voltage of a source driver circuit. It is a figure which shows an example of a structure of the EL display apparatus which concerns on embodiment. It is a circuit diagram which shows an example of the pixel structure of the EL panel which concerns on embodiment. It is explanatory drawing of the structure which has arrange | positioned the display pixel in the matrix form on the display screen. It is a block diagram which shows an example of a structure of gate driver IC. It is a figure which shows the structure to which the some gate driver IC was connected. It is a block diagram which shows an example of a functional structure of TCON. It is a figure which shows the display pixel for 11 pixel rows. It is the figure which illustrated the index value of 11 pixel rows. It is a figure explaining the order of writing concerning an embodiment. It is a figure explaining the drive system which concerns on the modification of embodiment. It is a graph which shows the index value of each pixel row before rearrangement of a writing order. It is a graph which shows the index value of each pixel row after rearrangement of the writing order concerning an embodiment. It is a figure which shows an example of the image displayed on a display screen. It is a figure which shows an example of the image displayed on a display screen. It is a figure explaining the state in which the display image is rewritten in the conventional drive system. It is a figure explaining the rewriting state and display state of a display image by the drive method of the EL display device concerning an embodiment. It is a figure explaining the circuit operation of a display pixel. It is a figure explaining the circuit operation of a display pixel. It is a figure explaining the circuit operation of a display pixel. It is a figure explaining the circuit operation of a display pixel. It is a circuit diagram which shows an example of the pixel structure of the EL panel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is a block diagram which shows an example of the gate driver IC which concerns on the modification of embodiment. It is a block diagram which shows an example of the gate driver IC which concerns on the modification of embodiment. It is a figure which shows an example of the flame | frame comprised by several subfields. It is a figure which shows an example of the output electric power of the source driver IC which concerns on a modification in embodiment. It is a figure which shows an example of the output electric power of the source driver IC which concerns on a modification in embodiment. It is a circuit diagram which shows an example of a structure of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a figure explaining operation | movement of the display pixel which concerns on the modification of embodiment. It is a circuit diagram which shows an example of the pixel structure of the EL panel which concerns on the modification of embodiment. It is a circuit diagram which shows an example of the pixel structure of the EL panel which concerns on the modification of embodiment. FIG. 10 is a configuration diagram in which a gate driver circuit and a source driver circuit are connected to an EL panel according to a modification of the embodiment. It is a figure explaining operation | movement of the gate driver IC which concerns on embodiment. It is an external view which shows an example of the external appearance of EL display apparatus.

(Knowledge that became the basis of the present invention)
The inventor has found that the following problems occur with respect to the EL display described in the “Background Art” column.

  As described above, in the EL display, the load capacity of the source signal line increases as the display panel has a large screen size such as a display screen size of 40 inches or more. Therefore, the amount of heat generated by the source driver IC that charges and discharges the source signal line tends to increase. In addition, in an EL display, a high-definition display panel such as a 4K2K panel (a panel having 4K × 2K or more pixels) or an 8K4K panel has a shorter selection period of one pixel row. Therefore, the change speed (frequency) of the video signal output from the source driver IC increases, and the amount of heat generated by the source driver IC increases.

  FIG. 1 is an explanatory diagram illustrating an example of a load capacity of a source signal line of an EL display panel. The output power Ps of the source driver IC 22 shown in the figure is expressed as Ps = K · C × V × V × F. Here, K is a proportional constant, C is a parasitic capacitance of the source signal line, V is a change voltage (potential difference) of the video amplitude voltage, and F is a frequency converted from a selection time of one pixel row. Therefore, the output power Ps of the source driver IC is proportional to the frequency obtained by converting the parasitic capacitance of the source signal line, the square of the change voltage of the video amplitude voltage, and the selection time of one pixel row. If the display panel has a frame frequency of 120 Hz and 4K2K, the number of pixel rows is 2160. Therefore, F = 120 × 2160 and about 260 kHz.

  An EL display using a high-definition display panel tends to increase the load capacity C of the source signal line and increase the writing speed (corresponding to F). Further, since the charge / discharge capacity is proportional to the square of the potential difference V, the influence of the potential difference is large.

  The 8K4K panel has twice as many pixel rows as the 4K2K panel, so if the frame rate is the same, the driving capability required for the source driver IC 22 is twice that of the normal source driver IC 22. Become.

  FIG. 2 is a diagram illustrating the relationship between the luminance value of each row of the image and the output voltage of the source driver circuit 14. A display image of the panel is schematically shown on the left side of FIG. The display image in FIG. 2 is a one-pixel row monochrome horizontal stripe image. Also, the output voltage of the source signal line is shown on the right side of FIG. Smin is the minimum gradation voltage (black display), and Smax is the maximum gradation voltage (white display).

  In the graph shown on the right side of FIG. 2, the horizontal axis represents the output voltage of the source driver circuit 14, and the vertical axis represents time (the downward direction is +). Therefore, the vertical axis is an axis indicating the order of writing. Since the display image is a one-pixel row monochrome horizontal stripe image, the voltage output from the source driver circuit 14 changes to Smax and Smin for each pixel row.

  As shown in FIG. 2, when the pixel row composed of white pixels having the maximum luminance value and the pixel row composed of black pixels having the minimum luminance value are alternately arranged, the source The output voltage of the driver circuit 14 becomes maximum. That is, since the maximum voltage Smax and the minimum voltage Smin are repeated in one pixel row, the potential difference V (= Smax−Smin) is maximized. Therefore, the power per terminal of the source driver circuit 14 is maximized.

  When the amplitude voltage of the video signal output to the source signal line by the source driver IC included in the source driver circuit 14 increases, the amount of heat generated by the source driver IC increases. If the heat generation amount is large, the source driver IC is thermally destroyed and normal operation cannot be performed. Therefore, a heat dissipation mechanism for cooling the source driver IC is required. For this reason, when a heat dissipation mechanism is provided as in a conventional display device, the number of parts required for heat dissipation of the EL display increases, which causes a problem that it is difficult to reduce the thickness of the panel.

  On the other hand, in the EL display device according to the present embodiment, the order of pixel rows to be selected is determined so that the voltage signal amplitude output from the source driver IC by TCON becomes small. Specifically, the TCON controls the PdatB terminal, applies an on voltage to the gate signal lines in the selected order, turns on the transistors in the corresponding pixel row, and writes the video signal of the source driver IC to the capacitor. In the blanking period, the transistor of the pixel on the display screen is turned on, and the Vref voltage is written to the capacitor. Then, the transistor is turned on and the video signal held in the capacitor is copied to the capacitor.

As described above, the charge / discharge capability of the source signal line is determined by CV ² F, but the load capacitance C and frequency F of the source signal line 18 are determined to some extent by the specifications of the EL panel. In the display device having the above configuration, the voltage difference (V) is suppressed by rearranging the rows to be displayed, so that the charge / discharge capability required for the source driver IC can be reduced.

  Hereinafter, a gate driver circuit according to an embodiment and an EL display device using the gate driver circuit will be specifically described with reference to the drawings.

  It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure.

  In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

  In addition, each drawing may be omitted, enlarged, or reduced for easy understanding and drawing. In addition, portions with the same numbers or symbols have the same or similar forms or materials, functions or operations, or related matters or actions.

(Embodiment)
In the EL display device of this embodiment, the selection order of the gate signal lines is rearranged so that the output power of the source driver IC is reduced (the pixel rows to be selected are rearranged. The order of the pixel rows to be selected is changed). . Further, in order to prevent the video quality from deteriorating due to the selection order of the gate signal lines, a pixel or panel configuration capable of separately executing the writing process and the display process is employed for the display pixel. Even in a pixel in which a video signal writing process is performed, the EL element employs a configuration in which a current can be supplied from a driving transistor based on a video signal before writing.

[1. Configuration of EL display device]
The structure of the EL display device according to this embodiment will be described with reference to FIGS.

  FIG. 3 is a diagram illustrating an example of a configuration of the EL display device according to the embodiment. As shown in the figure, the EL display device 1 according to the present embodiment includes an EL panel 29, a source driver IC 22, a source PCB (Printed Circuit Board) 26, a gate driver IC 21, and a gate PCB 25. , TCON (control circuit, timing controller) 27.

  The gate driver IC 21 is mounted on a gate COF (Chip on Film, Chip on Flexible) 23. The source driver IC 22 is mounted on the source COF 24.

  In addition, the EL panel 29 on which the source signal line 18 and the gate signal line 17 are formed, and the gate COF 23 and the source COF 24 are connected. Further, the gate COF 23 and the gate PCB 25 are connected, and the source COF 24 and the source PCB 26 are connected.

  The gate driver circuit 12 is usually composed of a plurality of gate driver ICs 21. The source driver circuit 14 includes a plurality of source driver ICs 22.

  Note that the gate driver circuit 12 is not limited to the gate driver IC 21. For example, a built-in gate driver circuit formed by the same process as the transistors constituting the display pixel 16 may be used. Further, the source driver circuit 14 is not limited to being configured by the source driver IC 22. For example, it may be a built-in source driver circuit formed by the same process as the transistors constituting the display pixel 16.

  The EL panel 29 includes a plurality of gate signal lines 17 arranged for each row, a plurality of source signal lines 18 arranged for each column, a display screen 28 (corresponding to a display unit), and a glass substrate. The display screen 28 includes a plurality of display pixels 16 arranged in a matrix at each intersection of the gate signal line 17 and the source signal line 18. On the glass substrate, wiring (gate signal line 17 and source signal line 18) that connects the display screen 28 to the gate COF 23 and the source COF 24 is formed.

  The display screen 28 is an area for displaying an image, and the plurality of display pixels 16 are arranged in a matrix at positions that can be visually recognized by the user.

  Note that although the gate driver IC 21 and the source driver IC 22 are described as being mounted on the COF, the present embodiment is not limited to this. For example, bumps are formed on the terminals of the gate driver IC 21 and the source driver IC 22 and mounted on the terminals (gate signal line terminal, source signal line terminal) of the EL panel 29 via an ACF film by a COG (chip on glass) method. It may be mounted on the EL panel 29.

[2. Display Pixel Configuration]
The display pixel 16 corresponds to one of the three primary colors R (red), G (green), and B (blue). A set of three display pixels 16 of RGB constitutes one pixel. A plurality of display pixels 16 constituting the same pixel are arranged adjacent to each other.

  In addition, the display pixel 16 of this embodiment has a configuration in which voltage signal writing and EL element light emission can be performed independently. With this configuration, even when the selection order of the gate signal lines is varied in one frame, display switching can be performed simultaneously in all the display pixels 16. For this reason, in the EL display device according to the present embodiment, two frames are not mixedly displayed, and it is possible to prevent deterioration in video quality.

  FIG. 4 is a circuit diagram illustrating an example of a pixel configuration of the front EL panel according to the embodiment. As shown in the figure, the display pixel 16 includes switching transistors 11b to 11e, capacitors 19b and 19a, a driving transistor 11a, and an EL element (light emitting element) 15.

  The switching transistors 11b to 11e are P-channel MOS transistors. The switching transistor 11b to 11e causes a writing operation to write a voltage signal to the capacitor 19b, a reset operation to reset the gate terminal voltage of the capacitor 19a or the driving transistor 11a, and a voltage signal written to the capacitor 19b is copied to the capacitor 19a. Copying operation and light emitting operation for emitting light from the EL element 15 can be performed. Details will be described later.

  The switch transistor 11b is an example of a switch circuit that switches between selection and non-selection of the display pixel 16, and is configured by a P-channel MOS transistor. The switching transistor 11b switches between conduction and non-conduction between the source signal line 18 and the node N1 according to a selection signal applied to the gate signal line 17b.

  The switch transistor 11e is an example of a switch circuit that switches connection and disconnection between the capacitor 19b and the capacitor 19a, and the conduction between the node N1 and the node N2 according to the signal applied to the gate signal line 17a. Switch non-conduction.

  The switching transistor 11c switches whether or not the voltage Vref is input to the node N2 in accordance with a signal applied to the gate signal line 17c. The voltage Vref is an initialization voltage for initializing the capacitor 19a or the drive transistor 11a, or a predetermined voltage applied to the terminal of the capacitor 19a or the gate terminal of the drive transistor 11a.

  The switch transistor 11d is an example of a switch circuit that switches between connection and disconnection of the drive transistor 11a and the EL element 15, and the drive transistor 11a supplies the EL element 15 with a signal applied to the gate signal line 17d. Switching between supply and non-supply of drive current.

  The drive transistor 11a is a P-channel MOS transistor, and supplies a drive current corresponding to the magnitude of the voltage signal written in the capacitor 19a to the EL element 15. The drive transistor 11a has a gate terminal connected to the node N2, a drain terminal connected to the anode electrode of the EL element 15, and an anode voltage Vdd input to the source terminal.

  The EL element 15 is an element that emits light according to the drive current supplied from the drive transistor 11a. In the EL element 15, the cathode voltage Vss is input to the cathode electrode, and the anode electrode is connected to the switching transistor 11d.

  The capacitor 19b is an example of a write capacitor into which a voltage signal is written by the source driver IC 22, and one end is connected to the node N1, and the reference voltage Vref is input to the other end.

  The capacitor 19a is an example of a display capacitor to which the voltage signal of the capacitor 19b is copied (accepts the electric charge of the capacitor 19b). One end of the capacitor 19a is connected to the node N2, and the other end receives the voltage Vdd.

  The driving transistor 11a and the switching transistors 11b to 11e are described as thin film transistors (TFTs), but are not limited thereto. An FET, a MOS-FET, a MOS transistor, or a bipolar transistor may be used. These are also basically thin film transistors. In addition, it goes without saying that varistors, thyristors, ring diodes, photodiodes, phototransistors, PLZT elements may be used. Alternatively, an element that functions in combination may be used.

  The transistor is not limited to a thin film element, and may be a transistor formed on a silicon wafer. For example, a transistor formed of a silicon wafer, peeled off and transferred to a glass substrate is exemplified. Further, a display panel in which a transistor chip is formed using a silicon wafer and a glass substrate is mounted by bonding is exemplified.

  Note that the transistor preferably employs an LDD (Lightly Doped Drain) structure for both n-type and p-type transistors.

  In addition, the transistor includes high-temperature polysilicon (HTPS), low-temperature polysilicon (LTPS), continuous grain silicon (CGS), and continuous oxide semiconductor (CGS). : Transparent Amorphous Oxide Semiconductors (IZO), Amorphous Silicon (AS), Infrared RTA (RTA: Rapid thermal annealing) may be used.

  In FIG. 4, all the transistors constituting the display pixel 16 are p-type. However, the invention is not limited to the p-type transistors of the display pixel 16. You may comprise only n-type. Moreover, you may comprise using both n-type and p-type.

  The switching transistors 11b to 11c are not limited to n-type or p-type transistors, and may be analog switches configured using both p-type transistors and n-type transistors, for example.

  The transistor preferably has a top gate structure. By employing the top gate structure, the parasitic capacitance is reduced, and the gate electrode pattern of the top gate becomes a light shielding layer, and light emitted from the EL element is blocked by the light shielding layer, so that malfunction of the transistor and off-leakage current can be reduced.

  It is preferable to implement a process that can employ copper wiring or copper alloy wiring as the wiring material of the gate signal line 17 or the source signal line 18 or both of the gate signal line 17 and the source signal line 18. Thereby, the wiring resistance of the signal line can be reduced, and a larger EL display panel can be realized.

  The gate signal line 17 driven (controlled) by the gate driver IC (circuit) is preferably reduced in impedance.

  In particular, it is preferable to employ low temperature polysilicon (LTPS). In the low-temperature polysilicon, the transistor has a top gate structure and a small parasitic capacitance, so that n-type and p-type transistors can be manufactured, and a copper wiring or copper alloy wiring process can be used for the process. The copper wiring preferably employs a three-layer structure of Ti—Cu—Ti.

  When the transistor is a transparent amorphous oxide semiconductor (TAOS), the wiring such as the gate signal line 17 or the source signal line 18 preferably employs a three-layer structure of Mo—Cu—Mo.

  The capacitors 19a and 19b are formed or arranged so as to overlap (overlap) at least one of the source signal line 18 and the gate signal line 17. In this case, the degree of freedom in layout is improved, a wider space between elements can be secured, and the yield is improved.

  The source signal line 18 and the gate signal line 17 are insulated by forming an insulating film or an insulating film (planarizing film) made of an acrylic material, and a pixel electrode is formed on the insulating film.

  FIG. 5 is an explanatory diagram of a configuration in which the display pixels 16 are arranged in a matrix on the display screen 28 of FIG. A cathode wiring (cathode electrode) 82 is connected to the cathode terminal of the EL element 15 of each display pixel 16, and a cathode voltage Vss is applied. An anode wiring (anode electrode) 81 is connected to the source terminal of the drive transistor 11a of each display pixel 16, and an anode voltage Vdd is applied. A gate driver circuit 12 is connected to the gate signal lines 17a to 17d, and a source driver circuit 14 is connected to the source signal line 18.

  With the above-described configuration, the display pixel 16 can perform voltage signal writing and light emission of the EL element 15 independently. Detailed operation will be described later.

[3. Configuration of source driver IC]
As shown in FIG. 3, the source driver IC 22 is mounted on a source COF 24 that is a flexible film. The source driver IC 22 applies a voltage signal having a voltage value corresponding to the pixel value of the display pixel 16 connected to the source signal line 18 to each source signal line 18 based on the data signal from the TCON 27. The source PCB 26 is a printed circuit board that connects the source COF 24 and the TCON 27.

  The source driver IC 22 includes a gamma circuit (not shown), a decoding circuit (not shown) for an inputted differential signal, a two-stage latch circuit (not shown), and an output buffer circuit (not shown). And a delay circuit (not shown).

[4. Configuration of gate driver IC]
As shown in FIG. 3, the gate driver IC 21 is mounted on a gate COF 23 that is a flexible film. The gate driver IC 21 applies, to the gate signal line 17 selected by the TCON 27, a voltage value selection signal that turns on the switching transistors 11 b to 11 e of the display pixel 16 connected to the gate signal line 17. Further, the gate driver IC 21 sets a voltage value for turning off the switching transistor of the display pixel 16 connected to the gate signal line 17 for each of the gate signal lines 17 not selected (unselected) by the TCON 27. The non-selection signal is applied.

  Note that the non-selection signal may be expressed as an off signal or an off voltage. In addition, the selection signal may be expressed as an on signal or an on voltage. It may also be called an operating voltage.

  The gate driver IC 21 according to the present embodiment is configured so that the gate signal lines 17a to 17d to which the selection signal is applied can be designated in an arbitrary order.

  FIG. 6 is a block diagram illustrating an example of the configuration of the gate driver IC 21. As shown in FIG. 6, the gate driver IC 21 includes four decoder / output circuits 311a to 311d.

  In the present embodiment, the description will be made assuming that four decoder / output circuits 311a to 311d are provided, but the present invention is not limited to this. The gate driver IC 21 shown in FIG. 6 is illustrated on the assumption that it corresponds to the pixel circuit of one pixel and four gate signal lines in FIG. If it is a pixel circuit of one pixel and two gate signal lines, a gate driver circuit incorporating two decoders / output circuits may be configured.

  In addition, when the display panel is a pixel circuit with one pixel and four gate signal lines, and even-numbered pixel rows and odd-numbered pixel rows are drawn in a staggered manner, gate driver circuits with two decoders and output circuits are arranged on the left and right sides of the screen. That's fine.

  The decoder / output circuit 311a is in charge of the output terminal VoutA, and the decoder / output circuit 311b is in charge of the output terminal VoutB. The decoder / output circuit 311c is in charge of the output terminal VoutC, and the decoder / output circuit 311d is in charge of the output terminal VoutD.

  A gate signal line 17a is connected to the output terminal VoutA, and a gate signal line 17b is connected to the output terminal VoutB. A gate signal line 17c is connected to the output terminal VoutC, and a gate signal line 17d is connected to the output terminal VoutD.

  By setting the high impedance terminal HiZ terminal to the H level, the Vout terminal becomes high impedance, and the gate signal line 17 connected to the Vout terminal and the gate driver IC 21 can be disconnected. By setting the high impedance terminal HiZ terminal to the L level, an on voltage or an off voltage can be output from the Vout terminal. The high impedance terminal HiZ terminal is pulled down in the gate driver IC 21.

  The Von terminals (VonA, VonB, VonC, VonD) connected to the decoder / output circuits 311a to 311d or the gate driver IC 21 are configured to be able to independently apply the on voltage Von. The on voltage (Von) is a voltage that turns on the switching transistors 11b to 11e, and the off voltage (Voff) is a voltage that turns off the switching transistors 11b to 11e. Therefore, the ON voltage applied to the VonA terminal is output to the output terminal VoutA, the ON voltage applied to the VonB terminal is output to the output terminal VoutB, and the VonC terminal is applied to the output terminal VoutC. The on-voltage is output, and the on-voltage applied to the VonD terminal is output to the output terminal VoutD.

  The pixel circuit of the EL display device shown in FIG. 4 and FIG. 34 to be described later includes a large number of transistors. In many cases, the on-voltage required for each transistor is different. The gate driver IC 21 in this embodiment is configured so that different on-voltages or off-voltages can be output from each output circuit. For example, the switching transistor 11d needs a higher on-voltage than the other transistors.

  Each of the decoder / output circuits 311a to 311d or the gate driver IC 21 is connected to a Voff terminal so that an off voltage Voff can be applied. The off voltage Voff is common to the four decoder / output circuits. Note that the off-voltage is not limited to common, and different output circuits may be used.

  The on voltage (Von) is a voltage that turns on the switching transistors 11b to 11e, and the off voltage (Voff) is a voltage that turns off the switching transistors 11b to 11e.

  The gate driver IC 21 has a chip select CS terminal. The chip select CS terminal is a setting terminal that operates by a logic voltage. When the logic voltage applied to the chip select CS terminal is at the H level, the corresponding gate driver IC 21 is enabled, and the switch transistor 11b is switched from the gate output terminal Vout selected by the output pin selection data Pdat terminal to the gate signal line 17. The on-voltage that turns on ~ 11e is output. When the logic voltage applied to the chip select CS terminal is at the L level, the corresponding gate driver IC 21 is not selected, and an off voltage for turning off the switching transistors 11b to 11e is applied from all the gate output terminals Vout to the gate signal line 17. Is output.

  Therefore, by controlling the CS terminal, an arbitrary gate driver IC 21 can be selected from the plurality of gate driver ICs 21, and the operation or non-operation can be controlled.

  The pin selection terminal Pdat (PdatA, PdatB, PdatC, PdatD) is composed of 8 terminals. In other words, it is 8 bits, and one of 180 outputs Vout (VoutA, VoutB, VoutC, VoutD) is selected by a logic signal applied to 8 terminals, and an on-voltage is output to the selected Vout terminal. The off voltage is output to the Vout terminal.

  A parallel signal n (bit) (n is an integer of 2 or more) is applied to the pin selection terminal Pdat, and at least a selection voltage that is one or more outputs Vout is output from n + 1 outputs Vout.

  The number of output terminals VoutA, VoutB, VoutC, and VoutD in this embodiment is 180 for each example, and the present invention is not limited to this. Further, the use of 8 terminals for PdatA, PdatB, PdatC, and PdatD is an example, and the present invention is not limited to this. If the Pdat terminal is 8 terminals (8 bits), 256 terminals can be selected by the power of 2. Up to 256 Vout (VoutA, VoutB, VoutC, VoutD) can be selected.

  The all-on terminals (AON) are logic terminals that control each decoder / output circuit 311a to 311d to output an on-voltage to all the output terminals Vout.

  The all-on terminal AONA is in charge of the decoder / output circuit 311a, and the all-on terminal AONB is in charge of the decoder / output circuit 311b. The all-on terminal AONC is in charge of the decoder / output circuit 311c, and the all-on terminal AOND is in charge of the decoder / output circuit 311d.

  For example, when all ON terminals AONA of the decoder / output circuit 311a are set to H level, ON voltages are output to VoutA1 to VoutA180. When all the ON terminals AOND of the decoder / output circuit 311d are set to the H level, an ON voltage is output to VoutD1 to VoutD180. Therefore, the transistor 11d connected to the gate signal line 17d assigned to VoutD is in an operating state (ON state).

  When the display screen 28 is connected to VoutA to VoutD, the display screen 28 can be collectively controlled by setting all the ON terminals AONA to AOND of the decoder / output circuits 311a to 311d to the H level.

  When all ON terminals AON of the decoder / output circuit 311a are set to L level, the ON voltage and OFF voltage output from Vout1 to Vout180 are set based on the logic signal of the Pdat terminal. At this time, the enable terminal EN needs to be set to H level. When the enable terminal EN is set to L level, off voltages are output from all the Vout terminals (Vout1 to Vout180).

  When the enable terminal EN of the decoder / output circuit 311d is set to the H level, the logic signal at the Pdat terminal becomes valid, and an ON voltage is output from the corresponding Vout terminal (any one of Vout1 to Vout180). When the enable terminal EN of the decoder / output circuit 311d is set to the L level, the logic signal of the Pdat terminal becomes invalid, and the off voltage is output from all the Vout terminals (Vout1 to Vout180).

  The output change is synchronized with the rising timing of the clock signal at the CLK terminal (CLKA, CLKB, CLKC, CLKD) by applying logic to the AON, Pdat, and EN terminals. However, normally, the CLKA, CLKB, CLKC, and CLKD terminals are electrically short-circuited, and the decoder / output circuits 311a, 311b, 311c, and 311d are used in common.

  Of the 180 gate signal lines 17, the decoder / output circuits 311 a to 311 d apply the voltage Von to the gate signal line 17 designated by Pdat and apply the voltage Voff to the other gate signal lines 17.

  FIG. 7 is a diagram showing a configuration in which a plurality of gate driver ICs 21 are connected. By setting the chip select CSA terminal to H, the gate driver IC 21a is selected. By setting the chip select CSB terminal to H, the gate driver IC 21b is selected.

  By setting the chip select CSA terminal to H and specifying the gate signal line 17a to which the ON voltage is applied at the PdatA terminal, the ON voltage is applied to the corresponding gate signal line 17a and the other gate signal line 17a is turned OFF. A voltage is applied.

  By specifying the gate signal line 17b to which the ON voltage is applied at the PdatB terminal, the ON voltage is applied to the corresponding gate signal line 17b and the OFF voltage is applied to the other gate signal line 17b.

  By specifying the gate signal line 17c to which the ON voltage is applied at the PdatC terminal, the ON voltage is applied to the corresponding gate signal line 17c, and the OFF voltage is applied to the other gate signal line 17c.

  By specifying the gate signal line 17d to which the ON voltage is applied at the PdatD terminal, the ON voltage is applied to the corresponding gate signal line 17d and the OFF voltage is applied to the other gate signal line 17d.

  When PdatA = 0, all gate signal lines 17a are set to off voltage. When PdatA = 1, the first gate signal line 17a is turned on, and the other gate signal lines 17a are turned off. Similarly, when PdatB = 0, all gate signal lines 17b are set to an off voltage. When PdatC = 0, all the gate signal lines 17c are set to the off voltage. When PdatD = 0, all the gate signal lines 17d are set to the off voltage.

  The Von terminal to which the ON voltage is applied is set in common by the plurality of gate driver ICs 21. The Voff terminal to which the off voltage is applied is set in common for the plurality of gate driver ICs 21.

  All ON terminals AON terminals (AONA, AONB, AONC, AOND) are set in common by a plurality of gate driver ICs 21. For example, when the AONA terminal is set to H, the ON voltage is output from the VoutA terminal. If the gate signal line 17a is connected to the VoutA terminal, the ON voltage is output to all the gate signal lines 17a on the display screen 28. For example, in the pixel circuits of FIGS. 4 and 34, the switching transistor 11e of the display screen 28 is turned on.

  Similarly, when the AONB terminal is set to H, the ON voltage is output from the VoutB terminal. If the gate signal line 17b is connected to the VoutB terminal, the ON voltage is output to all the gate signal lines 17b on the display screen 28. In the pixel configuration of FIG. 4, the switching transistor 11 b connected to the gate signal line 17 b is a transistor that applies a video signal to the display pixel 16. Therefore, in the driving method in the present embodiment, the gate signal line 17 b selects one pixel row in synchronization with the source driver circuit 14 and applies a video signal to the display pixel 16. Therefore, the AONB terminal is set to the L level and used.

  By setting the AONC terminal to H, an ON voltage is output from the VoutC terminal. If the gate signal line 17c is connected to the VoutC terminal, the ON voltage is output to all the gate signal lines 17c on the display screen 28. For example, in the pixel circuits of FIGS. 4 and 34, the switching transistor 11c of the display screen 28 is turned on.

  By setting the AOND terminal to H, an ON voltage is output from the VoutD terminal. If the gate signal line 17d is connected to the VoutD terminal, the ON voltage is output to all the gate signal lines 17d on the display screen 28.

  If the EN terminal is H, the selection of the gate signal line is enabled by the Pdat terminal. If the EN terminal is L, selection of the gate signal line is invalidated by the Pdat terminal, and an off voltage is output to all the gate signal lines.

  The data applied to the Pdat terminal is latched and input to the gate driver IC 21 by the clock applied to the CLK terminal.

[5. Configuration of TCON (control circuit, timing controller)
In order to facilitate understanding, it is expressed as a luminance or a voltage difference, and the luminance or the voltage difference corresponds to a voltage or a potential difference. The current can also be expressed as a voltage. Thus, brightness and current can be replaced by voltage. In addition, luminance, current, or voltage can be converted into electric power.

  A signal output from the source driver circuit 14 is a voltage, and the voltage is written into the pixel, converted into a current by the driving transistor 11a, and this current flows to the EL element 15, and the EL element 15 has a luminance corresponding to the voltage. Emits light. As described above, the signal output from the source driver is not limited to the voltage. For example, it may be a current.

  The voltage output from the source driver circuit 14 is converted by means such as a constant conversion coefficient, conversion equation, or conversion table, and is applied to the EL element 15 of the display pixel 16 to become luminance (or luminous flux amount). Further, the potential difference (voltage difference) is converted into a voltage difference by means of a constant conversion coefficient or conversion equation or conversion table.

  Needless to say, the conversion coefficient and the like may be set in consideration of the efficiency of the EL elements of the R, G, and B pixels.

  The TCON 27 controls each operation of the display pixel 16 described above and determines the order of writing in one frame.

  FIG. 8 is a block diagram illustrating an example of a functional configuration of the TCON 27. In FIG. 8, only the configuration necessary for describing the present embodiment is shown, and the other configuration is omitted. As shown in FIG. 8, the TCON 27 includes a potential difference calculation unit 231, a rearrangement unit 232, a gate driver control unit 233, and a source driver control unit 234. Detailed operation of each part will be described later.

  In the present embodiment, the TCON 27 is described as an example where it is configured by a dedicated LSI (Large Scale Integration), but the present invention is not limited to this. The TCON 27 may be configured by, for example, a computer system or an electronic circuit including a microprocessor (MPU), a ROM, a RAM, and the like. In this case, each operation described above can be realized by the microprocessor operating in accordance with a computer program for executing each operation described above.

[6. Write operation]
The TCON 27 reduces the output power of the source driver IC 22, so that the write order is such that the voltage signal difference between two consecutive rows (hereinafter referred to as “voltage difference” as appropriate) is small. Sort by. As described above, the output power Ps of the source driver IC 22 is defined by CV ² F. That is, the output power Ps of the source driver IC 22 or its magnitude or magnitude ratio is determined according to the square of the difference between the voltage signals corresponding to V. The output power Ps of the source driver IC 22 can be reduced by rearranging the order of writing so that the voltage signal difference is reduced.

Specifically, first, in the present embodiment, the potential difference calculation unit 231 calculates an index value for setting the order of writing in units of rows. The index value indicates the voltage of each row. Here, as the index value, the sum of squares of the voltage signal (= Σ _{k =} 1 to m (Luma (k)) ² , k is an integer, m is the number of pixels included in one row, and Luma (k) Calculates the voltage value indicated by the voltage signal corresponding to the display pixels 16 in the k columns. This is obtained for all pixel rows.

  FIG. 9A is a diagram illustrating display pixels 16 for 11 pixel rows, and FIG. 9B is a diagram illustrating index values for 11 pixel rows. Here, a case where rearrangement is performed for the 11 pixel rows will be described as an example. FIG. 9A shows pixel row 1 to pixel row 11. The left column of FIG. 9B shows that the index values of pixel row 1 to pixel row 11 are 23, 17, 1, 5, 19, 2, 15, 29, 7, 18, 2, respectively. ing. In the middle column of FIG. 9B, a writing order 1 (before replacement) that is the order of writing before rearrangement is shown, and the order is assigned in order from the first row.

  The rearrangement unit 232 of the TCON 27 rearranges the index values in ascending order and sets the writing order in the rearranged order. In the right column of FIG. 24B, writing order 2 (after replacement), which is the order of writing after rearrangement, is shown. In this writing order 2, the writing order is the third line, the sixth line, the eleventh line, the fourth line, the ninth line, the seventh line, the second line, the tenth line, the fifth line, the first line, It is the order of the 8th line.

  By changing the order of the pixel rows to which the video signal is applied as in the writing order 2 made by the rearrangement unit 232, the amplitude difference of the video signal output from the source driver IC 22 (source driver circuit 14) is reduced.

  Thus, in the “write order 1 (before replacement)”, the total value of the voltage square value is 23 → 17 → 1 → 5 → 19 → 2 → 15 → 29 → 7 → 18 → 2 On the other hand, in “write order 2 (after replacement)”, the total value of the voltage square value becomes 1 → 2 → 2 → 5 → 7 → 15 → 17 → 18 → 19 → 23 → 29, and the value changes The amount becomes smaller. Thereby, the power output from the source driver IC 22 (source driver circuit 14) is reduced, and the heat generation and overheating of the source driver IC 22 (source driver circuit 14) are suppressed.

  As shown in FIG. 2, in a horizontal stripe image in which adjacent pixel rows are displayed in black and white, in the conventional driving method, as shown in the rightmost graph of FIG. 2, every one horizontal scanning period (one pixel row selection period). In addition, the amplitude voltage of the source signal line 18 varies between Smax and Smin. Therefore, the power supplied from the source driver circuit 14 (source driver IC 22) to the source signal line 18 is very large, and the source driver circuit 14 is overheated.

  Overheating of the source driver circuit 14 (source driver IC 22) causes the EL panel 29 to overheat, leading to a reduction in the life of the EL element 15 and occurrence of color unevenness in the display image.

  FIG. 10 is a diagram for explaining the write order according to the embodiment. Specifically, FIG. 3 is a diagram showing a video signal (output voltage) of the source driver IC 22 when the frame writing order shown in FIG. 2 is rearranged by the method of the present embodiment. In the writing order shown in FIG. 10, first, each pixel row to which the maximum voltage Smax is applied is sequentially selected, and a voltage is applied to each pixel row. Next, each pixel row to which the minimum voltage Smin is applied is sequentially selected, and a voltage is applied to each pixel row. Therefore, the order in which the voltage is applied to each pixel row is as shown in FIG. Here, the display on the display screen 28 of the display panel is the same as the display in FIG.

  In the writing order in FIG. 10, the voltage difference of the output voltage is generated only when the voltage is written in the pixel row 16 b as compared with the writing order in FIG. 2, and the driving ability required for the source driver IC 22 jumps. In addition, the amount of heat generated can be reduced.

  As shown in FIG. 10, first, a pixel row for white pixel display is selected, and then a pixel row for black display is selected. Therefore, the selected pixel row is 16a → 16c → 16e → 16g → 16i → 16k →... → 16b → 16d → 16f → 16h → 16j →. Therefore, the video amplitude voltage output from the source driver circuit 14 hardly changes.

  Therefore, the power supplied from the source driver circuit 14 to the source signal line 18 becomes very small. Therefore, the source driver circuit 14 is not overheated, the EL panel 29 is not overheated, the life of the EL element 15 is reduced, and the occurrence of color unevenness in the display image can be suppressed.

  In the writing order according to Embodiment 1 shown in FIGS. 9A and 9B, the sum of the voltage square values of the pixel row is obtained from the voltage applied to each pixel of each pixel row, and each pixel of the obtained pixel row is obtained. The order of the pixel rows to be selected is set based on the difference between the voltage applied to the sum of the voltage square values of the pixel rows. However, the driving method of the present disclosure is not limited to this. The power of the source driver IC 22 is the sum of values obtained from the amplitude voltage difference of each source signal line 18. One source signal line 18 is connected to pixels in one pixel column. For example, depending on the display image, in the source signal line 18 in the k-th column, the pixel row 12th → pixel row 1st → pixel row 3rd → pixel row 8th → pixel row 11th →... However, in the source signal line 18 in the (k + 1) th column, the pixel row first → the pixel row eighth → the pixel row seventh → the pixel row twelfth → the pixel row second →・ Selecting may cause the smallest power.

  FIG. 11 is a diagram for explaining a driving method according to a modification of the embodiment. In FIG. 11, display pixel 16 (k, 1) = 17, display pixel 16 (k, 2) = 2, display pixel 16 (k, 3) = 10, display pixel 16 (k, 4), which are arbitrary pixel rows. ) = 108, display pixel 16 (k, 5) = 54, and display pixel 16 (k, 6) = 67 are set as index values. Further, display pixel 16 (m, 1) = 1, display pixel 16 (m, 2) = 5, display pixel 16 (m, 3) = 17, display pixel 16 (m, 4) = any pixel row Assume that the index values of 119, display pixel 16 (m, 5) = 110, and display pixel 16 (m, 6) = 32 are set.

  For ease of explanation, the index value of each pixel is an index value converted into electric power output from each source signal line 18 of the source driver IC 22 such as the square of the voltage amplitude difference. That is, the description will be made assuming that the difference between the two index values corresponds to (or is based on) the electric power or the heat generation amount.

  One source signal line 18 is connected to display pixels 16 belonging to one pixel column. By selecting the order of writing to the display pixels 16 so that the difference between the index value of the voltage applied to any display pixel 16 and the index value of the voltage applied to the other display pixels 16 is minimized, The source driver IC 22 generates the least amount of heat. However, the gate driver IC 21 selects one pixel row. Therefore, the video voltage output from the source driver circuit 14 needs to be aligned with the pixel row selected by the gate driver circuit 12.

  At this time, when the pixel row selected by the gate driver circuit 12 is the k-th pixel row, it is necessary to select the pixel row selected by the gate driver circuit 12 so that the output power of the source driver circuit 14 is reduced. . The pixel row to be selected is a pixel row that is not yet selected in the frame in which the video is currently being rewritten. This non-selected pixel row is defined as the m-th pixel row.

  One source signal line 18 is connected to display pixels 16 in one pixel column. Therefore, the calculation of the display pixel 16 (k, 1) and the display pixel 16 (m, 1), the calculation of the display pixel 16 (k, 2) and the display pixel 16 (m, 2), the display pixel 16 (k, 1) 3) calculation of display pixel 16 (m, 3), calculation of display pixel 16 (k, 4) and display pixel 16 (m, 4), display pixel 16 (k, 5) and display pixel 16 (m) , 5), the display pixel 16 (k, 6) and the display pixel 16 (m, 6), and so on.

  Note that the m-th pixel row is a plurality of pixel rows that are not yet selected in the frame in which the video is currently being rewritten. A difference in index value is obtained between each pixel in the k pixel row and the m pixel row, and a difference in index values between the display pixels in the pixel row is summed.

  As an example, in FIG. 11, the difference between the index values is the first pixel column (17-1) + the second pixel column (5-2) + the third pixel column (17-10) + the fourth pixel column (119-108) +5. Pixel column (110-54) +6 pixel column (67-22) = 16 + 3 + 7 + 11 + 56 + 45 = 138.

  As described above, the index value of the currently selected k pixel row and an arbitrary m pixel row are compared and calculated to obtain the sum of the index value differences, and the index value difference sum is minimized. Find the pixel row. As a result, the gate driver circuit 12 selects the m pixel row and outputs the video signal of the m pixel row from the source driver circuit 14.

  In the next horizontal scanning period, the m-th pixel row is set as the k-th pixel row, and an operation is performed to obtain the next m-pixel row that has not yet been selected in the frame in which the current video is being rewritten.

  In order to change the order of the pixel rows to be selected, the gate driver control unit 233 controls the gate signal line 17 selected by the gate driver IC 21 (gate driver circuit 12) (applying an on-voltage). The TCON 27 controls the Pdat of the gate driver circuit 12.

  As shown in FIG. 11, it is necessary to obtain a voltage difference (video signal voltage difference) for each pixel connected to each source signal line 18. The voltage difference between the pixels is summed in the pixel rows, the magnitude relation of the obtained sum is obtained, and the order of the pixel rows to be selected is obtained. The voltage difference between the pixels in the first pixel row and the second pixel row has a combination of (n−1) if there are n pixel rows. The combination calculation can be obtained by performing calculation processing using data stored in the memory.

  FIG. 12 is a graph showing the index value of each pixel row before the rearrangement of the writing order. However, in FIG. 12, the index value (value corresponding to the voltage amplitude difference) of each pixel row is expressed as a vertical axis value as one index value for easy understanding.

  The horizontal axis is an axis indicating the order of writing. When one screen is composed of 2160 pixel rows, the range is 1 to 2160. In FIG. 12, for ease of illustration and easy understanding, the number of pixel rows is 12 pixel rows, and the first to twelfth rows are represented.

  In the conventional driving method, video signal voltages are sequentially applied from the first pixel row to the twelfth pixel row. Therefore, the change in the video signal voltage output from the source driver IC 22 is large, and the source driver IC 22 is overheated.

  FIG. 13 is a graph showing the index value of each pixel row after the rearrangement of the writing order according to the embodiment. In FIG. 13, the vertical axis is an axis indicating an index value, and the horizontal axis is an axis indicating the order of writing. However, the numerical value attached to the horizontal axis is a value indicating which pixel row the bar graph corresponds to.

In the graph of FIG. 13, the index value difference is smaller between two pixel rows in which the writing order is continuous as compared to the graph of FIG. 12. A small difference in index value means that the output power of the source driver IC 22 is small. As described above, the output power of the source driver IC 22 is defined by CV ² F and is proportional to the square of the output voltage difference V. By rearranging the order of writing, as shown in FIG. 13, the output voltage difference V can be reduced, and the output voltage of the source driver IC 22 can be reduced. According to the writing order in FIG. 13, the pixel row to be selected is controlled so that the amount of change in the video amplitude voltage is small. Therefore, the change in the video signal voltage output from the source driver IC 22 is small, and the source driver IC 22 does not overheat. Further, as shown in FIG. 13, in the written image 1, a low pixel row is selected from a pixel row having a high video amplitude voltage, and in a written image 2, a high pixel row is selected from a pixel row having a low video amplitude voltage.

  By driving as described above, driving power can be reduced. That is, the writing pixel row is selected so that the difference in the video signal voltage is reduced between the frames (writing images).

  In FIG. 13, the writing order is illustrated as the case where the index values are rearranged in descending order (in descending order), but the index values may be rearranged in ascending order (in order from the smaller order).

  The video signal voltage is stored in a frame memory built in the TCON 27 or the like. Using the data stored in the frame memory, the voltage value of the pixel row is obtained.

  In brief, the voltage value of the video signal applied to each pixel is summed up in each pixel row, and the selection order of the pixel row to be selected is obtained by the summed value. A pixel row is selected by the gate driver IC 21. For example, in the left column of FIG. 9B, when 23, 17, 1, 5, 19,..., 2 and 2 are the sum of the voltages of the pixel rows, as shown in the right column of FIG. 11, 4, 7,..., 1 and 8 pixel rows are sequentially selected, and a video signal voltage is applied from the source driver to the pixels in each pixel row.

  The power of the source driver circuit 14 can be reduced by changing the order of pixel rows to be written. Obtaining the voltage difference (video signal voltage difference) for each pixel connected to each source signal line is the most accurate means of realization. However, in this case, the operation quantity becomes large. In order to select a pixel row to be written, for example, representative values of each pixel row (for example, index values of an odd pixel column, an even column pixel column, a pixel column that is a multiple of 16) are compared, and each index value of the pixel row is compared. (Calculation value) The calculation quantity can be reduced by obtaining the order of the pixel rows so that the difference is minimized.

  14 and 15 are diagrams illustrating examples of images displayed on the display screen 28, respectively.

  As shown in FIG. 14, in the display image (vertical lamp image) in which the video signal voltage applied to the pixel row smoothly changes in the vertical direction of the screen, from the first pixel row to the last pixel row or from the last pixel row. Since the pixel row is sequentially rewritten in the first pixel row, there is no sense of incongruity when the image is rewritten even if the driving method in this embodiment is performed.

  On the other hand, in the frame image as shown in FIG. 15, for example, the writing order is rearranged in order from the smallest luminance value. In this case, the video signal voltage of the relatively dark area B is first written, then the video signal voltage of the intermediate brightness area C is written, and finally the relatively bright area A video signal voltage is written. According to the writing order according to the present embodiment, the area B, C, and A are rewritten in this order.

  “Rewriting in the order of regions B, C, and A” is a conceptual expression for facilitating understanding. In the driving method of the EL display device of the present disclosure, the pixel row is selected so that the voltage difference between the pixel row or the pixels of each pixel becomes small. Therefore, pixel rows are not sequentially selected in the vertical direction or the downward upper direction of the screen in the areas A, B, and C. However, for ease of realization, it is also within the scope of the present invention to sequentially select the areas A, B, and C in the up and down direction or the lower and upper direction of the screen. For example, it is needless to say that some pixel rows in the region A are written, then some pixel rows in the region C are written, and some remaining pixel rows in the region A are written.

  Here, when a display pixel that cannot be independently written is used instead of a circuit that can independently perform voltage signal writing and video display like the pixel circuit according to the present embodiment, two pixels are displayed on one screen. There is a period in which frames are displayed together.

  In the display image of FIG. 15, the A area has many relatively bright pixels or pixel rows, the B area has many relatively dark pixels or pixel rows, and the C area has many relatively intermediate gradation pixels or pixel rows. Therefore, when the driving method according to the present embodiment is performed, the image of the A area is rewritten, the image of the C area is then rewritten, and then the image of the B area is rewritten. For this reason, since the region where the image is rewritten may change suddenly, a sense of incongruity occurs when the image is rewritten.

  FIG. 16 is a diagram for explaining a state in which a display image is rewritten in the conventional driving method. The order of display images is frame (display image) A → frame (display image) B → frame (display image) C.

  As shown in FIG. 16, first, an image of frame A is displayed on the display screen 28. Next, images of frame B are sequentially displayed from the top of the display screen 28 (A1). When the image of frame A is rewritten to the image of frame B, the image of frame C is then sequentially displayed from the top of the display screen 28 (A2). A1 and A2 indicate the state of the video actually displayed on the screen. In the display image by the conventional driving method shown in FIG. 16, voltage signal writing and video display cannot be performed independently, and each pixel row is directed downward from the top (in order from pixel row 1) downward. The case where it selects is illustrated.

  In this case, two frames are mixedly displayed on one screen. When switching from frame A to frame B as in A1, the next frame B video is displayed in the upper part of the screen and the current frame A video is displayed in the lower part of the screen. When switching from frame B to frame C as in A2, the next frame C video is displayed in the upper part of the screen and the current frame B video is displayed in the lower part of the screen.

  Thus, in the conventional driving method, the rewritten image display and the displayed image display are the same. That is, the pixel row in which the image is rewritten is driven so that it can be visually seen at the same time as the image is rewritten.

  FIG. 17 is a diagram for explaining a display image rewrite state and a display state by the driving method of the EL display device according to the embodiment. As shown in FIG. 17, in the driving method according to the present embodiment, A1 and A2 being rewritten are not visually recognized (displayed). After one frame image is rewritten, it is displayed as a display image (B1 and B2).

  Note that A1 and A2 in FIG. 17 illustrate the video signal voltages held in the display pixels 16 arranged in a matrix as “images being rewritten” for easy understanding. That is, A1 and A2 in FIG. 17 indicate voltages held in the display pixel 16, and are not strictly images. On the other hand, B1 and B2 in FIG. 17 illustrate actual images displayed on the display screen 28.

  As shown at A1 in FIG. 17, the image of frame A is held in each display pixel 16 of the panel, and then the image of frame B is sequentially rewritten from the upper pixel row of the panel. In this state, an image of frame A is displayed as shown in B1 of FIG.

  When each display pixel 16 is rewritten with the image of frame B, the image of frame C is successively held in the display pixel 16 from the upper part of the panel (A2 in FIG. 17). Further, at the timing when the image of frame B is rewritten on all display pixels 16, the image of frame B is displayed as shown in B2 of FIG. Further, the image of frame C is displayed at the timing when the image of frame C is rewritten on all display pixels 16.

  Here, the time for changing from the frame A to the image display of the frame B is a short time. Further, the time for changing from the frame B to the image display of the frame C is short. The short time is, for example, a blanking period. The image display is changed by switching the switching transistor 11d of FIGS. 4 and 34 from on to off. However, as will be described later, a black display period of the blanking period is necessary for image display switching control. As an example, the black display period is a period of 1/100 to 10/100 of one frame period.

  As described above, in the driving method according to the present embodiment, an image in the middle of rewriting is not displayed (viewed), and is driven so that an image is displayed at the timing when one frame image is rewritten. The One frame period is 120 Hz or more.

  As described above, A1 and A2 in FIG. 17 are not “display images” but actually signal voltages written in the display pixels 16. The signal voltage is a voltage held in the capacitor 19 b of the display pixel 16 and is a voltage based on the video signal output from the source driver circuit 14.

  On the other hand, the visually recognized display images are B1 and B2 in FIG. The display image at A1 is B1, and the display image at A2 is B2. In the display image, the drive transistor 11a supplies a light emission current to the EL element 15 based on the voltage held in the capacitor 19a of the display pixel 16, and the EL element 15 emits light.

  The current supplied to the EL element 15 is on / off controlled by the switching transistor 11d. In the driving method in the present embodiment, the switching transistor 11d is controlled to be off during the blanking period. During the blanking period, reset processing and copy processing are performed. In addition, the switching transistor 11d is controlled to be turned on / off also during duty driving in which a black band is displayed on the screen and the position of the black band is scanned.

  In this embodiment, as described above, in FIG. 15, voltage signals are written in the order of regions B, C, and A. Then, when the voltage signal writing and the video display cannot be performed independently as in the conventional writing method, two frames A and B or B and C are displayed in a mixed manner. And the video quality may be degraded.

  Even in the case of one frame image, the display image is uncomfortable in the following cases. For example, the image of the A area is rewritten, the image of the C area is then rewritten, and then the image of the B area is rewritten. Compared with the case where images are rewritten sequentially in the vertical direction of the screen, the display image in the specific area of the display screen is rewritten, so that the area where the display image is rewritten appears to be a noise display. In particular, when the display image is a moving image display, the noise display becomes significant.

  On the other hand, in the present embodiment, as described above, the display pixel 16 that can independently perform voltage signal writing and video display is used. For this reason, video switching is performed simultaneously in the light emission processing for all the pixel rows.

  That is, the image on which the voltage signal is written is not displayed as a display image, and the display image is displayed on the display screen based on the voltage of the capacitor 19a for which the voltage writing has been completed. Accordingly, as shown in FIG. 15, even when the voltage signals are written in the order of the regions B, C, and A, the image at the time of writing is not displayed, so that the conventional display image does not feel strange.

  In the present embodiment, as shown in B1 and B2 of FIG. 17, video switching is performed at the same timing in all pixel rows. Video switching is preferably performed during a blanking period of one frame period. When one frame is composed of a plurality of subfields, it is preferable that the video signal is switched in the blanking period of all the subfields or in an arbitrary subfield period. In this embodiment, two frames are not mixedly displayed on one screen.

  As described above, in this embodiment, the order of writing is rearranged. Therefore, when voltage signal writing and video display cannot be performed independently, two frames are further fragmented on one screen. May be mixed and displayed. On the other hand, if the display pixel 16 of this embodiment is used, voltage signal writing and video display can be performed independently, so that two frames are not mixedly displayed on one screen. Therefore, it is possible to prevent a decrease in video quality due to rearrangement of the writing order.

  As described above, in the EL display device 1 of the present embodiment, the order of writing is rearranged, and the writing of voltage signals and the display of video can be performed independently. As a result, the EL display device 1 reduces the driving capability required for the source driver IC without degrading the video quality, suppresses the heat generation amount of the source driver IC, and eliminates the need for providing a special heat dissipation mechanism. It becomes possible.

[7. Operation of display pixel]
The operation of the display pixel 16 shown in FIG. 4 will be described with reference to FIGS.

  With the configuration shown in FIG. 4, the display pixel 16 can perform the writing process of the video signal Vsig (voltage signal) and the light emission process of the EL element 15 independently. That is, in the display pixel 16, a writing process, a reset process, a copy process (copy process), and a light emission process are executed.

  18 to 21 are diagrams for explaining the circuit operation of the display pixel 16. Each process is executed by the TCON 27 controlling each circuit constituting the EL display device 1.

  The circuit operations shown in FIGS. 19 and 20 are simultaneously performed on all the pixels of the display screen in a blanking period of one frame. In the circuit operation shown in FIG. 18, the video signal voltage is sequentially applied to the capacitor 19b one pixel row at a time other than the blanking period of one frame from the top to the bottom of the screen. The circuit operation shown in FIG. 20 is performed at a time other than the blanking period of one frame. During the blanking period, the switching transistor 11d of the display pixel 16 is off, and no light emission current is supplied to the EL element 15.

  The circuit operations shown in FIGS. 19 and 20 are performed simultaneously on all the pixels of the display screen 28 in the blanking period of one frame, but the present invention is not limited to this. For example, the operations shown in FIGS. 19 and 20 may be sequentially performed by combining a plurality of pixel rows in the blanking period. Alternatively, one pixel row may be sequentially selected at high speed.

  In the writing process, a voltage signal (video signal voltage) is written to the capacitor 19b while causing the EL element 15 to emit light according to the current voltage signal of the capacitor 19a. The pixel row to be selected is performed by logic data applied to the PdatB terminal in the gate driver IC 21 of FIG.

  In the driving method in the present embodiment, the source driver IC 22 is described as outputting a voltage signal, but the present invention is not limited to this. For example, a video signal output from the source driver IC 22 (source driver circuit 14) may be a current signal. The current signal is configured to be converted into a voltage by the display pixel 16 and held in the capacitor 19b. Alternatively, the display pixel 16 is configured to hold a current as a video signal.

  FIG. 18 is a diagram illustrating states of the switching transistors 11b to 11e in the writing process. As shown in FIG. 18, in the writing process, the switching transistors 11b and 11d are turned on, and the switching transistors 11e and 11c are turned off. By setting the state of each transistor in this way, the next voltage signal can be written to the capacitor 19b while causing the EL element 15 to emit light according to the current voltage signal. This state corresponds to A1 and A2 in FIG.

  In the writing process of FIG. 18, FIG. 9A, FIG. 9B, FIG. 11, FIG. 10, FIG. Since the above driving method has already been described, the description thereof is omitted.

  FIG. 19 is a diagram illustrating the states of the switching transistors 11b to 11e in the reset process. In the reset process, the capacitor 19a is reset in a state where the light emission of the EL element 15 is stopped. The reset process includes concepts such as an initialization process and a predetermined state process. For example, the terminal voltage of the capacitor 19a, the initialization of the driving transistor 11a, or a process for making the operation constant.

  The reset process is performed by turning on the switching transistor 11c. The reset process is performed simultaneously on all the pixels on the display screen 28. The on-control of the switching transistor 11c is performed by setting the AONC terminal in FIG.

  In the reset process, the Vref voltage is applied to the gate terminal of the driving transistor 11a and one terminal of the capacitor 19a. The Vref voltage is set to a voltage equal to or lower than the cut-off voltage of the drive transistor 11a.

  Further, the capacity of the capacitor 19a: The capacity of the capacitor 19b is preferably 1: 1 or more and 1: 5 or less.

  As shown in FIG. 19, in the reset process, the switching transistor 11c is turned on, and the switching transistors 11b, 11e, and 11d are turned off. Since the switching transistors 11b and 11e are turned off, the capacitor 19b retains charges corresponding to the next voltage signal. Further, since the switching transistor 11c is on, the voltage Vref is input to the gate terminal of the driving transistor 11a and one end of the capacitor 19a. Thereby, the transistor 11a is initialized.

  During the reset process, the EL transistor 15 does not emit light because the switching transistor 11d is in an off state.

  Note that, by setting the voltage Vref to a voltage (Vt voltage or less) that turns off the drive transistor 11a, the drive transistor 11a can be maintained in a cut-off state even when the voltage Vref is applied to the gate terminal of the drive transistor 11a. . Therefore, even if the switching transistor 11d is in an on state, no current is supplied from the driving transistor 11a to the EL element 15. In this case, the switching transistor 11d need not be turned off.

  FIG. 20 is a diagram illustrating the states of the switching transistors 11b to 11e in the copy process. In the copy process, the next voltage signal written to the capacitor 19b is copied to the capacitor 19a while the light emission of the EL element 15 is stopped.

  The copy process is performed by turning on the switching transistor 11e. The copy process is performed simultaneously for all the pixels on the display screen 28. The on-control of the switching transistor 11e is performed by setting the AONA terminal in FIG. As shown in FIG. 20, in the copy process, the switching transistor 11e is turned on, and the switching transistors 11b, 11c, and 11d are turned off. When the switching transistor 11c is turned off and the switching transistor 11e is turned on, one end of the capacitor 19b and one end of the capacitor 19a are connected, and the next voltage signal written in the capacitor 19b is copied to the capacitor 19a. You can (write).

  The capacitor 19a is connected to the gate terminal of the drive transistor 11a. Therefore, the drive transistor 11a supplies current to the EL element 15 based on the voltage held in the capacitor 19a. During the period in which the copy process is executed, the EL transistor 15 does not emit light because the switch transistor 11d is in an off state.

  FIG. 20 is a diagram illustrating states of the switching transistors 11b to 11e in the light emission process. In the light emission process, the EL element 15 emits light.

  The light emission process is performed by turning on the switching transistor 11d. The light emission process is simultaneously performed on all the pixels on the display screen 28. The on-control of the switching transistor 11d is performed by setting the AOND terminal of the gate driver IC 21 in FIG.

  As shown in FIG. 20, in the light emission process, the switching transistor 11d is turned on and the switching transistors 11b to 11c are turned off. Thus, by setting the state of each transistor, the EL element 15 can emit light according to the next voltage signal.

  As shown in FIG. 18, in the circuit configuration of the display pixel 16 of the present disclosure, a video signal voltage can be written to the pixel even when a current is supplied to the EL element 15. A voltage corresponding to the video signal written to the pixel in the previous frame period is held by the capacitor 19a, and the driving transistor 11a supplies a current to the EL element 15 based on the voltage held by the capacitor 19a.

  The operation of writing the signal voltage to the capacitor 19b in FIG. 18 corresponds to the driving state described in A1 and A2 in FIG. The image display operation in FIG. 20 corresponds to the drive operation described in B1 and B2 in FIG. The driving transistor 11a supplies a light emission current to the EL element 15 based on the terminal voltage of the capacitor 19a.

  In the current frame period, pixel rows are sequentially selected by the gate driver IC 21, and the source driver IC 22 applies a video signal to the selected pixels. In the display pixel 16, a voltage corresponding to the video signal is held in the capacitor 19b. In each blanking period of one frame, the voltage held in the capacitor 19b is copied to the capacitor 19a. During this period, the display screen 28 is maintained in a non-display state. As an example, the non-display state period is a blanking period.

  In the next frame, the drive transistor 11a supplies current to the EL element 15 based on the voltage held in the capacitor 19a.

  As described above, the display pixel 16 according to the present embodiment includes the capacitors 19a and 19b that hold a voltage based on the video signal. The video signal from the source driver IC 22 is held in the capacitor 19b and copied to the capacitor 19a during a blanking period or the like. A switching transistor as a switch is disposed between the capacitors 19a and 19b, and a voltage signal based on the video signal is copied to the capacitor 19a by the switching transistor. The capacitor 19a is connected to the gate terminal of the drive transistor 11a, and the drive transistor 11a supplies a light emission current to the EL element 15 based on the voltage signal copied to the capacitor 19a.

  In the above embodiment, the capacitors 19a and 19b for holding the voltage based on the video signal are provided. However, the present invention is not limited to this. For example, two memory circuits may be constituted by transistors or the like, and the memory circuit may hold a voltage based on the video signal. Further, the voltage based on the video signal may be held in the gate capacitance of the MOS transistor.

  Further, the present invention is not limited to changing the image display of the entire screen at the same timing (changing the display state of the entire display screen at once). For example, the screen is divided into two parts at the top and bottom of the screen, the image display at the top of the screen is changed in the first half of one frame, and the image display at the bottom of the screen is changed in the half of the second half of one frame. May be. At this time, the blanking period is set twice in one frame.

  The EL display device 1 according to the present embodiment holds the video signal in the capacitor 19b formed in each display pixel 16 in the image display state (first period). In a period such as a blanking period (second period), the signal held in the capacitor 19b is copied to the capacitor 19a while the image is not displayed (the current is not supplied to the EL element 15). In the image display state (first period), the drive transistor 11a supplies a light emission current to the EL element 15 based on the magnitude of the signal held in the capacitor 19a. Although the capacitors 19a and 19b hold signals such as voltage, the present invention is not limited to capacitors. For example, a circuit (for example, a current mirror circuit or a current copier circuit) that allows a current value based on a signal to flow for a certain period using an operational amplifier, a transistor, or the like may be formed to hold the signal.

  By repeatedly executing the writing process, the reset process, the copy process, and the light emission process, video (for example, a moving image) can be displayed. In the light emission processing, the switching of the frame display can be simultaneously executed in all the display pixels 16 by simultaneously switching the switching transistors 11d from the OFF state to the ON state for all the display pixels 16. That is, two frames can be prevented from being displayed together.

  In the driving method in the above embodiment, the switching transistor 11 c is formed in the pixel circuit of the display pixel 16. However, when the initialization process of the driving transistor 11a is unnecessary, the switching transistor 11c does not have to be formed as illustrated in FIG. In this case, the process and operation of FIG. 19 are not necessary. FIG. 22 is a circuit diagram illustrating an example of a pixel configuration of an EL panel according to a modification of the embodiment.

  23 to 28 are diagrams illustrating the operation of the gate driver IC 21 (gate driver circuit 12) according to the embodiment. Here, FIG. 23 corresponds to FIG. FIG. 26 corresponds to FIG. FIG. 27 corresponds to FIG. FIG. 28 corresponds to FIG.

  The gate driver IC 21 (gate driver circuit 12) in the present embodiment can control (set) all on or all off the corresponding gate signal lines 17a, 17b, 17c, and 17d. Further, any one or more gate signal lines can be selected from the gate signal lines 17a, 17b, 17c, and 17d, and an ON voltage can be applied.

  The gate driver IC 21 is exemplified by the configuration shown in FIG. Also, the configuration shown in FIGS. 29 and 30 is exemplified.

  FIG. 29 and FIG. 30 are block diagrams each showing an example of a gate driver IC according to a modification of the embodiment.

  For example, the gate driver IC 21 (gate driver circuit 12) can apply an off voltage to the gate signal line 17a in charge, or can apply an on voltage. Further, any one of the gate signal lines 17a in charge can be selected and an on voltage can be applied, and an off voltage of another gate signal line 17a can be applied.

  Further, for example, the gate driver IC 21 (gate driver circuit 12) can apply an off voltage to the gate signal line 17b in charge or can apply an on voltage. Further, any one of the gate signal lines 17b in charge can be selected and applied with an on voltage, and an off voltage of another gate signal line 17b can be applied.

  Further, for example, the gate driver IC 21 (gate driver circuit 12) applies an off voltage to the gate signal lines 17a, 17c, and 17d in charge, and any one or more gate signal lines among the gate signal lines 17b in charge. By selecting 17b, a video signal voltage can be applied to the pixel row connected to the selected arbitrary gate signal line 17b.

  23 to 25 show the operation of the gate driver circuit 12 when a video signal is applied to each pixel row. An off voltage is applied to the gate signal lines 17a and 17c of all the pixel rows of the display screen 28. Therefore, the switching transistors 11e and 11c are in the off state. A turn-on voltage is applied to the gate signal line 17d, the switching transistor 11d is turned on, and the light emission current of the drive transistor 11a is supplied to the EL element 15.

  In FIG. 23, the ON voltage is supplied to the gate signal line 17b of the display pixel 16b, and the video signal voltage Vsig2 is applied from the source driver circuit 14 to the capacitor 19b of the display pixel 16b. The off voltage is supplied to the gate signal lines 17b of the other display pixels 16a and 16c.

  In FIG. 24, the on-voltage is supplied to the gate signal line 17b of the display pixel 16c, and the video signal voltage Vsig3 is applied from the source driver circuit 14 to the capacitor 19b of the display pixel 16c. The off voltage is supplied to the gate signal lines 17b of the other display pixels 16a and 16c.

  In FIG. 25, the ON voltage is supplied to the gate signal line 17b of the display pixel 16a, and the video signal voltage Vsig1 is applied from the source driver circuit 14 to the capacitor 19b of the display pixel 16a. The off voltage is supplied to the gate signal lines 17b of the other display pixels 16a and 16c.

  As shown in FIGS. 23 to 25, the order (pixel row number) of the display pixels to which the video signal is written is designated by TCON27 in FIG. 8, and the gate driver circuit 12 is turned on to the gate signal line 17b of the designated pixel row. Apply voltage. A pixel row is specified by the Pdat terminal of the gate driver IC 21. By controlling the Pdat terminal, it is possible to select a pixel row at random.

  In FIG. 23 to FIG. 25, an ON voltage is applied to the gate signal line 17 d and the light emission current from the drive transistor 11 a is supplied to the EL element 15. A light emission current from the drive transistor 11a corresponding to the voltage of the capacitor 19a is supplied to the EL element 15, and the EL element 15 emits light.

  FIG. 26 is a diagram for explaining the operation of the gate driver circuit 12 during the reset processing operation. An off voltage is applied to the gate signal lines 17a, 17b, and 17d of all the pixel rows on the display screen 28. Therefore, the switching transistors 11e, 11b, and 11d are in an off state. A turn-on voltage is applied to the gate signal line 17c, and the switching transistor 11c is turned on.

  When the switching transistor 11c is turned on, the reset voltage Vref is applied to the gate terminal of the driving transistor 11a. Note that the operation of FIG. 26 is performed during the blanking period.

  FIG. 27 is a diagram for explaining the operation of the gate driver circuit 12 during the copy processing operation. An off voltage is applied to the gate signal lines 17b, 17c, and 17d of all the pixel rows on the display screen 28. Therefore, the switching transistors 11e, 11c, and 11d are in an off state. A turn-on voltage is applied to the gate signal line 17a, and the switching transistor 11e is turned on.

  When the switching transistor 11e is turned on, a voltage signal based on the video signal voltage written in the capacitor 19b is applied to the gate terminal of the driving transistor 11a. FIG. 27 is performed during the blanking period.

  FIG. 28 is a diagram for explaining the operation of the gate driver circuit 12 during the image display operation. An off voltage is applied to the gate signal lines 17a, 17b, and 11c of all the pixel rows on the display screen 28. Therefore, the switching transistors 11e, 11b, and 11c are off. A turn-on voltage is applied to the gate signal line 17d, and the switching transistor 11d is turned on.

  When the switching transistor 11d is turned on, the current from the driving transistor 11a is supplied to the EL element 15, and the EL element 15 emits light based on the supplied current. In addition, FIG. 28 is implemented other than the blanking period (image display period).

[8. When the frame consists of multiple subfields]
A modification of the present embodiment will be described with reference to FIGS. In this modification, a case will be described in which a frame is obtained by superimposing a plurality of subfields.

  FIG. 31 is a diagram illustrating an example of a frame including a plurality of subfields. In each subfield, the luminance value increases as the subscript (number) value decreases, and the luminance value decreases as the subscript value increases. For each display pixel 16, a desired luminance can be obtained by selecting a subfield to be lit according to the luminance value.

  A video signal of one frame is decomposed into a plurality of subfields. Ex. In the embodiment of A, each subfield is divided by luminance (brightness). Ex. Needless to say, as shown in B, the video data may be divided into subfields by upper bits to lower bits. For example, when the video signal is 8 bits, one frame is composed of 8 subfields. The source driver IC outputs the voltage value weighted to the bit to the source signal line in each subfield. In this case, the index value of each pixel row can be obtained by obtaining the number of bits “1”. In addition, the index value with other pixel rows can be obtained by comparing the position of the bit “1”.

  32 and 33 are diagrams each illustrating an example of output power of the source driver IC 22 according to a modification of the embodiment.

  32 and 33, first, the order of writing is rearranged within the subfield. 32 and 33 show a case where one frame is composed of four subfields for the sake of explanation.

  In FIG. 32, the display order of the fields is not rearranged, and the order of writing is rearranged within the subfields. In FIG. 32, in all of the subfields 1 to 4, the index values (= the total value of the squares of the voltage signal) are rearranged in descending order, and the writing order is set in the rearranged order.

  As described above, the index values are large in the order of subfields 1 to 4 (index value of subfield 1> index value of subfield 2> index value of subfield 3> index value of subfield 4). For this reason, when the index values are rearranged in descending order for each field, the index values are rearranged in descending order for the entire frame. Thereby, the difference in the output voltage of the source driver IC 22 can be reduced over the entire frame.

  In FIG. 33, the display order of subfields is set in the order of subfields 4 to 1. Further, in FIG. 33, the index values are rearranged in ascending order for each subfield. That is, in FIG. 33, the index values are rearranged in ascending order in the entire frame. Thereby, the difference in the output voltage of the source driver IC 22 can be reduced.

  The video signal voltage is stored in a frame memory built in the TCON 27 or the like. The frame memory is further divided into a plurality of subfields. First, frame memory data is calculated and image data is divided into a plurality of subfields. Using the stored data, the voltage value of the pixel row in each subfield is obtained.

  Briefly, the voltage value of the video signal applied to each display pixel is summed in each pixel row of each subfield, and the selection order of the pixel row to be selected is obtained by the summed value.

  It is necessary to obtain a voltage difference (video signal voltage difference) between display pixels connected to each source signal line. The voltage difference between the display pixels is summed in the pixel rows, the magnitude relation of the obtained sum is obtained, and the order of the pixel rows to be selected is obtained. Note that the voltage difference between the pixels in the first pixel row and the second pixel row has a combination of (n−1) if there are n pixel rows. The combination calculation can be obtained by performing calculation processing using data stored in the memory.

  The power of the source driver circuit 14 can be reduced by changing the order of pixel rows to be written. Obtaining the voltage difference (video signal voltage difference) for each pixel connected to each source signal line is the most accurate means of realization. However, the calculation quantity is large in the case of calculating the voltage difference between pixels. In order to select a pixel row to be written, a representative value of each pixel row (for example, an odd pixel column, a prime pixel column, a pixel column that is a multiple of 64) is compared, and each index value (calculated value) difference of the pixel row is The calculation quantity can be reduced by obtaining the pixel row order to the minimum. Moreover, it is preferable to change the representative value of each pixel row (for example, an odd pixel column, a prime pixel column, a pixel column that is a multiple of 64, etc.) for each subfield.

[9. Other examples of display pixel configuration]
Another example of the configuration of the display pixel will be described with reference to FIG.

  FIG. 34 is a circuit diagram illustrating an example of the configuration of the display pixel 16 according to a modification of the embodiment. As shown in the figure, the display pixel 16 includes switching transistors 11b to 11g, capacitors 19b and 19a, a driving transistor 11a, and an EL element (light emitting element) 15.

  The switch transistor 11b is an example of a switch circuit that switches between selection (on voltage) and non-selection (off voltage) of the display pixel 16, and is configured by an N-channel MOS transistor. The switching transistor 11b switches between conduction (on) and non-conduction (off) between the source signal line 18 and the node N1 in accordance with a selection signal applied to the gate signal line 17b. The switching transistor 11b has a function of applying the video signal voltage applied to the source signal line 18 to the capacitor 19b. The switching transistor 11b has a gate terminal connected to the gate signal line 17b, a drain terminal connected to the source signal line 18, and a source terminal connected to one terminal of the capacitor 19b. The other terminal of the capacitor 19b is connected to the electrode to which the correction voltage Ve is applied.

  The switching transistors 11c to 11g are N channel type MOS transistors. Write operation for writing a voltage signal to the capacitor 19b by the switching transistors 11c to 11g, a reset operation for resetting the capacitor 19a, a copy operation for copying the voltage signal written to the capacitor 19b to the capacitor 19a, and an EL element A light emitting operation for performing 15 light emission can be performed.

  The switching transistor 11e is an example of a switching transistor that switches between connection and disconnection between the capacitor 19b and the capacitor 19a. The switch transistor 11e is electrically connected between the node N1 and the node N2 in accordance with a signal applied to the gate signal line 17a. And non-conducting.

  The gate terminal of the switching transistor 11e is connected to the gate signal line 17a. The drain terminal is connected to one terminal of the capacitor 19b, and the other terminal is connected to the gate terminal of the driving transistor 11a.

  The switching transistor 11c switches whether or not to input the voltage Ve to the node N2, in accordance with a signal applied to the gate signal line 17c. The voltage Ve is a voltage for initializing or stabilizing the capacitor 19a and the driving transistor 11a. The source terminal of the switch transistor 11c is electrically connected to the source terminal of the drive transistor 11a. The voltage Ve is applied or supplied to the drain terminal of the switching transistor 11c. The gate terminal of the switching transistor 11c is connected to the gate signal line 17c.

  The switch transistor 11d has a gate connected to the gate signal line 17d, one of the source and drain terminals connected to the drain terminal of the drive transistor 11a, and a switch circuit that switches connection and disconnection between the drive transistor 11a and the EL element 15. It is an example. The switching transistor 11d is composed of, for example, an n-type thin film transistor (n-type TFT), and supply or non-supply of drive current to the EL element 15 by the drive transistor 11a according to a signal applied to the gate signal line 17d. And switch.

  In the switching transistor 11f, the gate terminal is connected to the gate signal line 17f, one of the source and the drain is connected to Vref2, and the voltage Vref2 is input to the node N2 in accordance with the signal applied to the gate signal line 17f. Switch between no. The voltage Vref2 is a voltage for canceling the offset of the driving transistor 11a.

  The switching transistor 11g switches whether to apply the voltage Vini to the source terminal of the driving transistor 11a according to a signal applied to the gate signal line 17g. The initial voltage Vini is applied or supplied to the drain terminal of the switching transistor 11g.

  The voltages Vref and Vini are voltages for performing offset cancellation of the drive transistor 11a. The switching transistor 11f and the switching transistor 11g are configured by, for example, n-type thin film transistors (n-type TFTs).

  The drive transistor 11 a is a drive element whose drain is connected to the anode voltage Vdd that is the first power supply line and whose source terminal is connected to the anode of the EL element 15. The drive transistor 11a converts a voltage corresponding to the signal voltage applied between the gate and the source into a drain current corresponding to the signal voltage. Then, this drain current is supplied to the EL element 15 as a signal current. The drive transistor 11a is composed of, for example, an n-type thin film transistor (n-type TFT).

  The EL element 15 is an element that emits light according to the drive current supplied from the drive transistor 11a. In the EL element 15, the cathode voltage Vss is input to the cathode electrode, and the anode electrode is connected to the switching transistor 11d.

  The capacitor 19b is a capacitor to which a voltage signal is written by the source driver IC 22, and one end is connected to the node N1 and the correction voltage Ve is applied to the other end. The capacitor 19b stores the potential of the source signal line 18 in a state where the switching transistor 11b is conductive. At this time, the image of the previous frame is held in the capacitor 19a, and the drive transistor 11a supplies a light emission current to the EL element 15 based on the voltage held in the capacitor 19a.

  The capacitor 19a is a capacitor to which the voltage signal of the capacitor 19b is copied (accepts the electric charge of the capacitor 19b), one end is connected to the node N2, and the other end is connected to the anode terminal of the EL element 15. The capacitor 19a is a capacitor having a first electrode connected to the gate terminal of the drive transistor 11a and a second electrode connected to the source terminal of the drive transistor 11a. The capacitor 19a holds a voltage corresponding to the signal voltage supplied from the source signal line 18. For example, after the switching transistors 11b, 11e, and 11c are turned off, the potential between the gate and source electrodes of the driving transistor 11a. Is stably maintained, and the current supplied from the driving transistor 11a to the EL element 15 is stabilized.

  The capacitors 19a and 19b are formed or arranged so as to overlap (overlap) the source signal line 18 or the gate signal line 17. In this case, the degree of freedom in layout is improved, a wider space between elements can be secured, and the yield is improved. The above items are applied to the display panel in this embodiment.

  With the above-described configuration, the display pixel 16 can independently perform voltage signal writing and EL element light emission.

  Although not shown in FIG. 34, the anode voltage Vdd, the cathode voltage Vss, and the correction voltages (Vref2, Vini, Ve) are each commonly connected to all the display pixels 16, and a voltage generation circuit (not shown). Connected). When the voltage obtained by adding the light emission start voltage of the EL element 15 to the threshold voltage of the drive transistor 11a is greater than 0V, Vini may be substantially the same voltage as the cathode voltage Vss. As a result, the types of output voltages of the voltage generation circuit (not shown) are reduced, and the drive circuit is simplified.

  Note that since the channel of the transistor is bidirectional, the names of the source terminal and the drain terminal are for ease of explanation, and the source terminal and the drain terminal may be interchanged. The names of the source terminal and the drain terminal are for convenience or ease of explanation, and the other source terminal and drain terminal may be a first terminal, a second terminal, or the like. Although the transistor is described as an N-channel transistor, it can be replaced with a P-channel transistor.

  The term “electrically connected” refers to a state in which a voltage path and a current path are formed, or a state in which a path can be formed. For example, even if the third transistor is disposed between the first transistor and the second transistor, the first transistor and the second transistor are electrically connected. In this specification, connection may be used as an electrical connection meaning.

  35 to 41 are diagrams for explaining the operation of the display pixel according to the modification of the embodiment. In FIGS. 35 to 41, unlike FIG. 34, each transistor is a p-type TFT, but the circuit function is the same.

  Regarding the light emission period and the non-light emission period, when the switching transistor 11d is in the ON state, the EL element 15 is supplied from the anode voltage Vdd, and the EL element 15 is in the light emission state (light emission period). Since the drive current (drain-source current) Id is supplied from the anode voltage Vdd to the EL element 15 through the drive transistor 11a, the EL element 15 emits light with luminance corresponding to the drive current Id. Further, when the switching transistor 11d is turned off, the current flowing through the EL element 15 is cut off, and the light emission of the EL element 15 is stopped (non-light emitting period).

  FIG. 35 is a diagram illustrating states of the switch elements (switch transistors) 11b to 11g in the writing process. In the figure, the video signal voltage is sequentially applied to the capacitor 19b one pixel row at a time other than the blanking period of one frame from the top to the bottom of the screen. The operation shown in FIG. 35 is performed at a time other than the blanking period of one frame. During the blanking period, the switching transistor 11d of the display pixel 16 is off, and no light emission current is supplied to the EL element 15. Further, the process of applying the video signal to the capacitor 19b during the blanking period is allowed. In the writing process of FIG. 35, the switching transistors 11b and 11d are in the on state, and the switching transistors 11e, 11c, 11f, and 11g are in the off state. By setting the state of each transistor in this way, the next voltage signal can be written to the capacitor 19b while causing the EL element 15 to emit light according to the current voltage signal. 35, FIG. 11, FIG. 15, FIG. 15, FIG. 9A, FIG. 9B, FIG. 12, FIG. 13, FIG. Since the above driving method has already been described, the description thereof is omitted.

  FIG. 36 shows a pixel operation state during a preparation period for offset cancellation correction. In the preparation period for the offset cancellation correction, the switching transistor 11f is turned on, the reference voltage Vref2 is applied to the gate terminal of the driving transistor 11a, the switching transistor 11g is turned on, and the initial voltage Vini is applied to the anode terminal of the EL element 15. Is done. The gate potential Vg of the drive transistor 11a becomes the reference voltage Vref2. The source potential Vs of the drive transistor 11a is at the initial voltage Vini that is sufficiently lower than the reference voltage Vref2.

  Here, the initial voltage Vini is set so that the gate-source voltage Vgs of the drive transistor 11a is larger than the offset cancel voltage Vth of the drive transistor 11a. In this way, the preparation for the offset cancel correction operation is completed by initializing the gate potential Vg of the drive transistor 11a to the reference voltage Vref2 and the source potential Vs to the low potential Vini, respectively.

  Next, as shown in FIG. 37, when the switching transistor 11g is turned off, a selection voltage (on voltage) is applied to the gate signal line 17d, and the switching transistor 11d is turned on, an anode voltage is applied to the drain terminal of the driving transistor 11a. Vdd is applied. Then, the source potential Vs of the drive transistor 11a starts to rise. Eventually, the gate-source voltage Vgs of the drive transistor 11a becomes the offset cancel voltage Vth of the drive transistor 11a, and a voltage corresponding to the offset cancel voltage Vth is written into the capacitor 19a.

  Here, for convenience, a period during which a voltage corresponding to the offset cancel voltage Vth is written to the capacitor 19a is referred to as an offset cancel correction period. In this offset cancellation correction period, the cathode voltage Vss of the cathode electrode is set so that the EL element 15 is cut off in order to prevent the current from flowing exclusively to the capacitor 19a and not to the EL element 15. Set it. Alternatively, it is set to a voltage obtained by subtracting the Vth voltage or more from the cathode voltage Vss. Therefore, Vss> Vini is set. For example, when the cathode voltage Vss = + 2 (V), Vini = −2 (V) is exemplified.

  As shown in FIG. 38, the switching transistors 11d, 11e, and 11c are turned off. At this time, the gate of the drive transistor 11a is in a floating state, but since the gate-source voltage Vgs is equal to the offset cancel voltage Vth of the drive transistor 11a, the drive transistor 11a is in a cutoff state. Therefore, the drain-source current Id does not flow.

  In FIG. 39, the switching transistor 11c is turned on, and the Ve voltage (correction voltage) is applied to the capacitor 19a. The Ve voltage is a voltage that corrects the signal voltage held in the capacitor 19b and the Vt voltage held in the capacitor 19a. The correction voltage process is performed in a state where the light emission of the EL element 15 is stopped.

  Further, the capacity of the capacitor 19a: The capacity of the capacitor 19b is preferably 1: 1 or more and 1: 5 or less.

  FIG. 39 is a diagram illustrating states of the switching transistors 11b to 11g in the reset process. As shown in FIG. 39, in the correction voltage process, the switching transistor 11c is turned on, and the switching transistors 11b, 11e, 11d, 11f, and 11g are turned off. In the copy process, the next voltage signal written to the capacitor 19b is copied to the capacitor 19a while the light emission of the EL element 15 is stopped.

  FIG. 40 is a diagram illustrating states of the switching transistors 11b to 11g in the copy process. As shown in FIG. 40, in the copy process, the switching transistor 11e is turned on, and the switching transistors 11c, 11d, 11f, and 11g are turned off. When the switching transistor 11c is turned off and the switching transistor 11e is turned on, one end of the capacitor 19b and one end of the capacitor 19a are connected, and the next voltage signal written in the capacitor 19b is copied to the capacitor 19a. You can (write).

  The capacitor 19a is connected to the gate terminal of the drive transistor 11a. Therefore, the drive transistor 11a supplies current to the EL element 15 based on the voltage held in the capacitor 19a. During the period in which the copy process is executed, the EL transistor 15 does not emit light because the switch transistor 11d is in an off state.

  In the light emission process, the EL element 15 emits light. FIG. 41 is a diagram illustrating states of the switching transistors 11b to 11e in the light emission process. As shown in FIG. 41, in the light emission process, the switching transistor 11d is turned on, and the switching transistors 11b to 11c, 11f, and 11g are turned off. Thus, by setting the state of each transistor, the EL element 15 can emit light according to the next voltage signal.

  As shown in FIGS. 35 to 41, in the pixel configuration according to the embodiment of the present disclosure, the video signal voltage can be written to the pixel even when a current is supplied to the EL element 15. A voltage corresponding to the video signal written to the pixel in the previous frame period is held by the capacitor 19a, and the driving transistor 11a supplies a current to the EL element 15 based on the voltage held by the capacitor 19a.

  Here, the writing operation of the signal voltage to the capacitor 19b in FIG. 35 corresponds to the driving state described in A1 and A2 in FIG. The image display operation in FIG. 41 corresponds to the drive operation described in B1 and B2 in FIG. The driving transistor 11a supplies a light emission current to the EL element 15 based on the terminal voltage of the capacitor 19a.

  In the current frame period, pixel rows are sequentially selected by the gate driver IC 21 (gate driver circuit 12), and the source driver IC applies a video signal to the selected pixels. In the pixel, a voltage corresponding to the video signal is held in the capacitor 19b. In each blanking period of one frame, the voltage held in the capacitor 19b is copied to the capacitor 19a. During this period, the display screen is maintained in a non-display state.

  In the next frame, the driving transistor 11a supplies current to the EL element 15 based on the voltage held in the capacitor 19a.

  As described above, the display pixel 16 according to the modification of the present embodiment includes the capacitors 19a and 19b that hold the voltage based on the video signal. Further, it is characterized by comprising means for copying a signal based on the video signal held in the capacitor 19b to the capacitor 19a.

  In the modification, the capacitors 19a and 19b for holding the voltage based on the video signal are provided. However, the present invention is not limited to this. For example, two memory circuits may be constituted by transistors or the like, and the memory circuit may hold a voltage based on the video signal. Further, the voltage based on the video signal may be held in the gate capacitance of the MOS transistor.

  In the driving method in the present embodiment described above, the switching transistor 11 c is arranged as the pixel circuit of the display pixel 16. However, when the correction process of the driving transistor 11a is unnecessary, the switching transistor 11c does not have to be formed as illustrated in FIG. FIG. 42 is a circuit diagram illustrating an example of a pixel configuration of an EL panel according to a modification of the embodiment. In this case, the operation of FIG. 39 is unnecessary.

  FIG. 43 is a circuit diagram illustrating an example of a pixel configuration of an EL panel according to a modification of the embodiment. As illustrated in FIG. 43, an embodiment in which the switching transistor 11f that applies the reset voltage Vref2 is also used as the switching transistor 11c is illustrated. When the switching transistor 11f in FIGS. 37 and 38 is turned on, the switching transistor 11c is turned on to apply the Vref2 voltage to the gate terminal of the driving transistor 11a. Other operations are the same as those in the embodiment described with reference to FIGS.

  FIG. 44 is a configuration diagram in which the gate driver circuit 12 and the source driver circuit 14 are connected to an EL panel according to a modification of the embodiment. Also in the pixel configuration of FIG. 34, the offset cancel operation of FIGS. 36 to 38 is performed using the gate driver IC 21 described with reference to FIG.

  However, in the driving method according to this modification, it is not necessary to perform the offset cancel operation on the display pixels on the entire screen at once. For example, the offset cancel operation may be performed sequentially from the pixel row at the top of the screen.

  29, 30, and 45 are a block diagram and an explanatory diagram of the gate driver IC 21 (gate driver circuit 12) in the present embodiment. 45 is an explanatory diagram corresponding to FIG.

  As shown in FIGS. 29 and 30, the gate driver IC 21 includes four shift register / output circuits 432 a to 432 d.

  29 and 30, it is assumed that four shift registers / output circuits 432a to 432d are provided. However, the present invention is not limited to this. If it is a pixel circuit of one pixel and two gate signal lines, a gate driver circuit 12 incorporating two shift registers and output circuits may be configured.

  In addition, when the display panel is a pixel circuit of one pixel and four gate signal lines, and even-numbered pixel rows and odd-numbered pixel rows are drawn in a staggered manner, gate driver circuits 12 having two shift registers and output circuits are provided on the left and right sides of the screen. What is necessary is just to arrange.

  FIG. 45 shows an example in which six shift registers / output circuits are provided in the gate driver IC 21 so as to correspond to the pixel circuit of the one-pixel six-gate signal line in FIG.

  The shift register / output circuit 432a is in charge of the output terminal VoutA, and the shift register / output circuit 432b is in charge of the output terminal VoutB. The shift register / output circuit 432c is in charge of the output terminal VoutC, and the shift register / output circuit 432d is in charge of the output terminal VoutD. A gate signal line 17a is connected to the output terminal VoutA, and a gate signal line 17b is connected to the output terminal VoutB. A gate signal line 17c is connected to the output terminal VoutC, and a gate signal line 17d is connected to the output terminal VoutD.

  Each shift register / output circuit 432a to 432d or the gate driver IC 21 is configured to be able to independently apply an ON voltage Von to the Von terminals (VonA, VonB, VonC, VonD).

  Therefore, the ON voltage applied to the VonA terminal is output to the output terminal VoutA, the ON voltage applied to the VonB terminal is output to the output terminal VoutB, and the VonC terminal is applied to the output terminal VoutC. The on-voltage is output, and the on-voltage applied to the VonD terminal is output to the output terminal VoutD.

  Each shift register / output circuit 432a to 432d or the gate driver IC 21 is configured such that an on-voltage Vof can be independently applied to a Voff terminal (VoffA, VoffB, VoffC, VoffD).

  Accordingly, the off voltage applied to the VoffA terminal is output to the output terminal VoutA, the off voltage applied to the Voff terminal is output to the output terminal VoutB, and the VoffC terminal is applied to the output terminal VoutC. The off voltage is output, and the off voltage applied to the VoffD terminal is output to the output terminal VoutD.

  The gate driver IC 21 has a chip select CS terminal. The chip select CS terminal is a setting terminal that operates by a logic voltage. When the logic voltage applied to the chip select CS terminal is at the H level, the corresponding gate driver IC is enabled and the gate output terminal Vout selected by the output pin selection data Pdat terminal or the gate signal selected by the shift register / output circuit An on voltage or an off voltage for turning on the switching transistor is output to the line 17. When the logic voltage applied to the chip select CS terminal is at the L level, the corresponding gate driver IC is not selected, and an off voltage for turning off the switching transistor is output from all the gate output terminals Vout to the gate signal line 17. .

  Therefore, by controlling the CS terminal, an arbitrary gate driver IC 21 can be selected from the plurality of gate driver ICs 21 and controlled to operate or not operate.

  By setting the high impedance terminal HiZ terminal to the H level, the Vout terminal becomes high impedance, and the gate signal line 17 connected to the Vout terminal and the gate driver IC 21 can be disconnected. By setting the high impedance terminal HiZ terminal to the L level, an on voltage or an off voltage can be output from the Vout terminal. The high impedance terminal HiZ terminal is pulled down in the gate driver IC 21. The high impedance terminal HiZ terminal is used when inspecting whether any of the gate driver ICs 21 mounted on the panel is defective. Also used for panel process inspection and evaluation.

  Note that a high impedance terminal HiZ terminal is also added to the source driver IC 22 in this embodiment. By setting to H level, the output terminal connected to the source signal line becomes high impedance, and the source driver IC 22 and the source signal line can be separated. By setting the high impedance terminal HiZ terminal to the L level, a video signal can be output to the source signal line. The high impedance terminal HiZ terminal is pulled down in the source driver IC 22. The high impedance terminal HiZ terminal is used when inspecting whether any of the plurality of source driver ICs 22 mounted on the panel is malfunctioning. Also used for panel process inspection and evaluation.

  The pin selection terminal Pdat is composed of 8 terminals. That is, the output of the decoder circuit 431 is selected by a logic signal that is 8 bits and applied to the 8 terminals.

  The number of output terminals VoutA, VoutB, VoutC, and VoutD in this embodiment is 180 for each example, and the present invention is not limited to this. If the Pdat terminal is 8 terminals (8 bits), 256 terminals can be selected by the power of 2.

  The all-on terminals (AON) are logic terminals that control the on-voltage to be output to all the output terminals Vout terminals in each of the shift register / output circuits 432a to 432d.

  The all-on terminal AONA is in charge of the shift register / output circuit 432a, and the all-on terminal AONB is in charge of the shift register / output circuit 432b. The all-on terminal AONC is in charge of the shift register / output circuit 432c, and the all-on terminal AOND is in charge of the shift register / output circuit 432d.

  29, 30, and 45 and FIG. 6 are different from the gate driver IC 21 (gate driver circuit 12) of FIG. 6 in that a decoder / output circuit is arranged, whereas the gate of FIG. The driver IC 21 (gate driver circuit 12) includes a shift register / output circuit and a common decoder circuit 431 for a plurality of shift registers / output circuits.

  In FIG. 29, the shift register / output circuits 432a to 432d are four circuits. However, this is an example, and the present invention is not limited to four circuits. For example, in the pixel circuit of FIG. 34, since there are six types of gate signal lines 17 for one pixel, six shift registers / output circuits are provided in the gate driver circuit 12. The above matters also apply to the embodiment of FIG.

  Each of the shift register / output circuits 432a to 432d mainly includes a shift register circuit 443, a selector circuit 444, and an output buffer circuit 445.

  A clock terminal CLK and a start signal input / output terminal STV are connected to the shift register circuit 443. Since the clock terminal of the shift register / output circuit 432a is CLKA, the start signal input / output terminal is STVA, and these terminals are bidirectional, they are CLKAa, CLKAb, STVAa, and STVAb.

  The data signal input to the start signal input / output terminal STV is taken into the shift register circuit 443 at the rising timing of the clock signal input to the clock terminal CLK, and the data is shifted in the shift register in synchronization with the clock signal. . The gate signal line 17 from which the ON voltage is output is determined by the shifted data.

  A direction selection terminal DIR that determines a shift direction is connected to the shift register circuit 443. When the DIR terminal is H, the shift direction is set from left to right. When the DIR terminal is L, the shift direction is set from right to left.

  Each of the shift register / output circuits 432a to 432d has a shift register circuit 443, and data is input to the input terminal (STV terminal) of the data signal, and the clock input to the clock terminal (CLK terminal) Data shifts in the shift register circuit 443. The on-voltage is output to the Vout terminal corresponding to the position where data exists. By using the shift register circuit 443, an on-voltage can be applied to continuous gate signal lines.

  The output buffer circuit 445 is connected to an all-on terminal AON terminal, an on-voltage application terminal Von terminal, an off-voltage application terminal Voff terminal, and an enable terminal EN. These terminals have been described with reference to FIG.

  The decoder circuit 441 is connected to a pin selection terminal Pdat and a clock terminal CLK. The decoder circuit 441 has 180 outputs (POUT), and one of the outputs POUT is selected (an ON voltage is selected as an output position) by an 8-bit logic signal applied to the Pdat terminal. The above items are the same as those in FIG.

  The output POUT of the decoder circuit 441 and the output of the shift register circuit 443 are input to the selector circuit 444. Whether the output POUT of the decoder circuit 441 is input to the output buffer circuit by the selection terminal SP connected to the selector circuit 444. Whether the output of the shift register circuit 443 is input to the output buffer circuit is controlled.

  When the logic voltage at the SP terminal is H, the output POUT of the decoder circuit 441 is input to the output buffer circuit. When the logic voltage at the SP terminal is L, the output of the shift register circuit 443 is input to the output buffer circuit.

  Arbitrary gate signal line positions can be selected at random by the decoder circuit 441. In addition, the gate signal line positions can be sequentially selected by the shift register circuit 443. Therefore, an arbitrary gate signal line position can be selected at random by controlling the SP terminal, or the gate signal line positions can be selected in order. Further, as in FIG. 6, all-on control can be performed by the EN terminal and the AON terminal. Each gate signal line 17 is connected to the Vout terminal.

  The decoder circuit 441 is used to select the switching transistor 11b that applies a video signal to the capacitor 19b. By the decoder circuit 441, the selected pixel rows described in FIGS. 8 to 10, 13, 15, 15, 23 to 25, and 31 to 33 can be arbitrarily selected (not sequentially). Therefore, the power of the source driver circuit 14 (source driver IC 22) can be greatly reduced, and problems such as overheating are eliminated.

  The selection of the pixel row in which the video signal is written (designation of the position of the gate signal line) may be one circuit in the gate driver IC 21. Therefore, as shown in FIGS. 29 and 30, the decoder circuit is one circuit. The output POUT of the decoder circuit 441 is connected to a selector circuit 444 of a plurality of shift register / output circuits 432a to 432d. The output POUT is controlled by the selector circuit 444 to control whether or not it is output to the Vout terminal. Therefore, under the control of the selector circuit 444, the output POUT of the decoder circuit 441 can be output to any of VoutA, VoutB, VoutC, and VoutD.

  When the SP terminal of the selector circuit 444 is at the H logic level, the switch of the selector circuit 444 is connected to the b contact, and the output POUT of the decoder circuit 441 is output from the output terminal Vout via the output buffer circuit 445. When the SP terminal of the selector circuit 444 is at the L logic level, the switch of the selector circuit 444 is connected to the contact a, and the output POUT of the shift register circuit 443 is output from the output terminal Vout via the output buffer circuit 445.

  By using the output of the shift register circuit 443, it is possible to easily control the gate signal lines 17 to be sequentially selected such as an offset cancel operation. By using the output of the decoder circuit 441, it is possible to easily control the gate signal line 17b that needs to be randomly selected (rearranged) described with reference to FIG.

  The shift registers / output circuits 432 a to 432 d are provided corresponding to the types of the gate signal lines 17. The shift registers / output circuits 432a to 432d are used when the offset cancel operation is performed in the order of the pixel rows as described with reference to FIGS. As shown in FIGS. 18 and 19, when all the display screens 28 are collectively implemented, it is realized by controlling the AON terminal and the EL terminal.

  The CS terminal and the like are the same as in FIG. Further, since the other configurations are the same, description thereof will be omitted. VDD and VSS are logic power supply voltages of the gate driver IC.

  FIG. 45 is a configuration diagram in which a plurality of gate driver ICs 21 are mounted on the EL display device 1. In the pixel circuit of FIG. 34, it is assumed that the VoutA terminal applies an on-voltage or an off-voltage to the gate signal line 17a, the VOUTB terminal applies an on-voltage or an off-voltage to the gate signal line 17b, and the VoutC terminal applies the gate signal line 17c. When an on voltage or an off voltage is applied to the gate signal line 17d, an on voltage or an off voltage is applied to the gate signal line 17d, an on voltage or an off voltage is applied to the gate signal line 17e, and the VoutF terminal is The description will be made assuming that an on voltage or an off voltage is applied to the gate signal line 17f.

  By setting the chip select CSA terminal to the H level, the gate driver IC 21a is selected, and the input to the logic terminal of the gate driver IC 21a becomes valid. When the chip select CSA terminal is set to L level, off voltages are output from all Vout terminals (VoutAA to VoutAF).

  Similarly, the gate driver IC 21 (x is b to n) is selected by setting the chip select CSx (x is B to N) terminal to the H level, and the logic of the gate driver IC 21 x (x is b to n). Input to the terminal is valid. When the chip select CSx (x is B to N) terminal is set to L level, off voltages are output from all Vout terminals (VoutxA to VoutxF).

  All ON terminals AON terminals have 6 wires, and each wire is connected to the shift register / output circuits 432a to 432f. For example, if the six AON terminals are AONA, AONB, AONC, AOND, AONE, and AONF, and the shift register / output circuits 432a to 432f are used, the AONA terminal turns on the output VoutA of the shift register / output circuit 432a. (Vout A1 to 180 output all ON voltages).

  Similarly, the AONB terminal controls the output VoutB of the shift register / output circuit 432b to be fully ON (VoutB1 to 180 output ON voltage). The AONC terminal controls the output VoutC of the shift register / output circuit 432c to be fully on (Vout C1 to 180 all output an on voltage). The AOND terminal controls the output VoutD of the shift register / output circuit 432d to be fully ON (VoutD1 to 180 all output ON voltages). The AONE terminal controls the output VoutE of the shift register / output circuit 432e to be fully on (VoutE1 to 180 all output an on voltage). The AONF terminal controls the output VoutF of the shift register / output circuit 432f to be fully ON (VoutF1 to 180 output ON voltage).

  By setting the high impedance terminal HiZ terminal to the H level, the Vout terminal becomes high impedance, and the gate signal line 17 connected to the Vout terminal and the gate driver IC 21 can be disconnected. By setting the high impedance terminal HiZ terminal to the L level, an on voltage or an off voltage can be output from the Vout terminal. The high impedance terminal HiZ terminal is pulled down in the gate driver IC 21. The high impedance terminal HiZ terminal is used when inspecting whether any of the gate driver ICs 21 mounted on the panel is defective. Also used for panel process inspection and evaluation.

  If the EN terminal is H, the data input to the Pdat terminal and the shift register circuit 443 (data input from the STV terminal) becomes valid, and the ON voltage is output from the Vout terminal in charge to the gate signal line. If the EN terminal is L, the data input to the Pdat terminal and the shift register circuit 443 (data input from the STV terminal) becomes invalid, and an off voltage is output to all the gate signal lines in charge.

  Here, the EN terminal is set to ENA, ENB, ENC, END, ENE, ENF, the shift register circuit 443 is set to 443A, 443B, 443C, 443D, 443E, 443F, and the output buffer circuit 445 is set to 445A, 445B, 445C, 445D, 445E, 445F, the selector circuit 444 is 444A, 444B, 444C, 444D, 444E, 444F, and the selection terminal SP connected to the selector circuit is the SPA, SPB, SPC, SPD, SPE, SPF terminal. .

  For example, by setting the SPA terminal and the L level and the ENA terminal to the H level, the switch (see FIG. 30) in the selector circuit 444A selects the terminal b, and the output of the shift register circuit 443A becomes the output buffer circuit 445A. To the gate signal line 17a.

  By setting the SPA terminal and the ENA terminal to the H level, the logic signal set to the Pdat terminal becomes valid, and the switch (see FIG. 30) in the selector circuit 444A selects the terminal a and sets the decoder circuit 441. The turned-on voltage output terminal position is output from the output buffer circuit 445A.

  By setting the ENA terminal to the L level, the output buffer circuit 445A outputs an off voltage to all the VoutA terminals.

  By setting the SPB terminal, the L level, and the ENB terminal to the H level, the switch (see FIG. 30) in the selector circuit 444B selects the terminal b, and the output of the shift register circuit 443B passes through the output buffer circuit 445B. To the gate signal line 17b.

  By setting the SPB terminal and ENB terminal to the H level, the logic signal set to the Pdat terminal becomes valid, and the switch (see FIG. 30) in the selector circuit 444B selects the terminal a and sets the decoder circuit 441. The turned-on voltage output terminal position is output from the output buffer circuit 445B.

  By setting the ENB terminal to the L level, the output buffer circuit 445B outputs an off voltage to all the VoutB terminals. Hereinafter, since the same applies to the other outputs VoutC to VoutF, description thereof will be omitted.

  CLKxa (hereinafter, x is A to F) and CLKxb are bidirectional input / output terminals. STVxa and STVxb are also bidirectional input / output terminals. Data input to the shift register circuit 443x is set in the STVxa or STVxb terminal. Data input to the STVxa or STVxb terminal is taken into the shift register circuit 443x at the rising edge of the clock signal input to CLKxa and CLKxb. Data taken into the shift register circuit 443x is sequentially shifted in the shift register circuit 443x in response to the rising edge of the clock signal input to CLKxa and CLKxb. The data position in the shift register 443x is a position for outputting the ON voltage.

  The SP terminal controls whether the ON voltage position set by the decoder circuit 441 is output to the output buffer circuit 445x or the output of the shift register circuit 443x is output to the output buffer circuit 445x.

  As described above, the gate driver circuit 12 (gate driver IC 21) according to this embodiment includes one decoder circuit 441 and a plurality of shift register circuits 443.

  The decoder circuit 441 controls the gate signal line 17b to which the switching transistor 11b for writing the video signal to the pixel is connected in the pixel circuits of FIG. 4 and FIG. The decoder circuit 441 has 8 bits, and one gate signal line 17b can be selected from among the gate signal lines 17b in charge by 8 bits.

  Therefore, the driving described in FIGS. 8 to 10, 12, 13, 15, 31 to 33 and the like to rearrange the selected “pixel rows” and reduce the video amplitude output from the source driver IC 22. The system can be easily realized.

  Further, by controlling the AON terminals (AONA to AONF), the switching transistor 11e and the switching transistor 11c on the display screen 28 can be turned on during the blanking period in the pixel circuits of FIGS.

  Therefore, the compensation process for the drive transistor 11a and the process for copying the video data held in the capacitor 19b to the capacitor 19a can be performed simultaneously on all display screens.

  Further, by sequentially shifting the data position to the shift register circuit 443, the gate signal lines 17 to be selected can be sequentially selected. Therefore, the pixel row position for selecting the offset cancel operation described with reference to FIGS. 36 to 38 can be sequentially shifted.

  Further, the gate driver circuit 12 according to the present embodiment includes a shift register circuit and a decoder circuit, and one of the outputs of the shift register circuit and the decoder circuit is formed on the display screen. It corresponds to the output of the gate signal line.

  Further, the gate driver circuit according to the present embodiment shifts input data in the shift register, and changes the plurality of first outputs in accordance with the position of the data in the shift register. A decoder circuit that selects one output from the second output of m (m is an integer of n + 1 or more) from parallel data of n (n is an integer of 2 or more) bits, a first output, And a selection circuit that outputs to the third output, and the third output of the selection circuit is electrically connected to the gate signal line formed on the display screen. It is characterized by that.

  With the above configuration, in the pixel configuration of FIG. 4 and FIG. 34, an arbitrary gate signal line 17b is selected and the switching transistor 11b is turned on so that the change in the video amplitude becomes small. A video signal or a voltage based on the video signal can be written.

  Further, the selection voltage can be applied to the gate signal lines 17a formed on the display screen by controlling or operating the AON terminal, and the signal (voltage) held in the capacitor 19b is moved or copied to the capacitor 19a. can do. In this operation, the switching transistor 11d can be turned off and the EL element 15 can be controlled so that no light emission current is supplied.

  The EL display device according to this embodiment uses the gate driver circuit according to the above embodiment. Further, the control circuit calculates an index value of the video signal applied to the pixel row of the display screen, rearranges the order of the pixel row using the index value, and based on the result of the rearrangement of the order of the pixel row. Thus, the gate signal line 17b is selected.

  The control circuit obtains the square of the potential difference between the first voltage value of the video signal applied to an arbitrary pixel row and the second voltage of the pixel row applied to a pixel row other than the pixel row, and squares the potential difference. The order of the pixel rows to be selected is rearranged so that the value of is reduced.

(Other embodiments)
As described above, the gate driver circuit and the EL display device using the gate driver circuit have been described based on the embodiment, but the present disclosure is not limited to the embodiment. Unless it deviates from the gist of the present disclosure, various modifications conceived by those skilled in the art have been made in this embodiment, and forms constructed by combining components in different embodiments are also within the scope of one or more aspects. It may be included.

  For example, in the above-described embodiment and modification, the total value of the squares of the luminance values is obtained as the index value indicating the brightness of each row of the plurality of display pixels, and the total value of the square differences of the voltage signals is obtained. I asked, but it is not limited to this. The index value may be, for example, an average value of pixels in one row, an average value of squares, or the like.

  In the above embodiment and the modification, the index values are rearranged in descending order or ascending order. In Modification 2, it is determined for each field or frame whether the index values are rearranged in descending order or ascending order. is not. For example, for each field or frame, a pattern that defines whether the index values are sorted in ascending order or descending order may be set in advance. Specifically, for example, since it is generally considered that the difference between the index values between the minimum values and between the maximum values becomes small, the index values are rearranged in descending order or in ascending order for each field or frame. Alternatively, it may be set alternately.

  In the above embodiment, the source driver circuit 14 is described as having a source driver IC. However, the configuration of the source driver circuit 14 is not limited to the source driver IC composed of a semiconductor chip. Absent. For example, a transistor formed of a silicon wafer, peeled off and transferred to a glass substrate is exemplified. Further, a display panel in which a transistor chip is formed using a silicon wafer and a glass substrate is mounted by bonding is exemplified. Alternatively, the source driver circuit 14 may be formed directly on a glass substrate on which pixels, transistors, and the like are formed using low-temperature polysilicon, high-temperature polysilicon, TAOS technology, or the like. That is, the source driver circuit 14 may be formed using a pixel and transistor formation process. The above matters also apply to the gate driver IC. That is, the gate driver circuit may be formed over the glass substrate at the same time as the pixel or the like using the same process as the pixel and the transistor.

In the present invention, the signal output from the source driver is a voltage signal (voltage programming method), but is not limited thereto. For example, it may be a current signal (current programming method). Even the current is expressed as the amplitude of the video signal, the current can be regarded as a voltage, and the heat generation can be calculated as CV ² F relative to the current I → the voltage V. Alternatively, heat generation can be calculated as being proportional to CV ² F.

  The comprehensive or specific aspect according to the above embodiment may be realized by a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM. You may implement | achieve with arbitrary combinations of a circuit, a computer program, or a recording medium.

  Further, the gate driver circuit 12 and the EL display device 1 according to the present embodiment are mounted on a thin flat TV 31 as shown in FIG. With the gate driver circuit 12 and the EL display device 1 according to the present embodiment, a thin flat TV including a high-quality EL panel 29 with reduced heat generation is realized.

  The present disclosure can be used for a display device such as an EL display using an organic electroluminescence (EL) element.

DESCRIPTION OF SYMBOLS 1 EL display apparatus 11a Drive transistor 11b, 11c, 11d, 11e, 11f, 11g Switch transistor 12 Gate driver circuit 14 Source driver circuit 15 EL element (light emitting element)
16, 16a, 16b, 16c Display pixels 17 Gate signal lines 17a, 17b, 17c, 17d, 17e, 17f, 17g Gate signal lines 18 Source signal lines 19a, 19b Capacitors 21, 21a, 21b, 21n Gate driver ICs
22 Source Driver IC
23 Gate COF
24 source COF
25 Gate PCB
26 Source PCB
27 TCON (control circuit, timing controller)
28 Display screen 29 EL panel 31 Thin flat TV
81 Anode wiring (anode electrode)
82 Cathode wiring (cathode electrode)
231 Potential difference calculation unit 232 Rearrangement unit 233 Gate driver control unit 234 Source driver control unit 311a, 311b, 311c, 311d Decoder / output circuit 431, 441 Decoder circuit 432a, 432b, 432c, 432d, 432e, 432f Shift register / output circuit 443 Shift register circuit 444 Selector circuit 445 Output buffer circuit

Claims (10)

A gate driver circuit used in an EL display device having a display screen in which pixels having EL elements are arranged in a matrix,
A shift register circuit;
A decoder circuit;
One of outputs of the shift register circuit and the output of the decoder circuit corresponds to an output of a gate signal line formed on the display screen. A gate driver circuit used in an EL display device having a display screen in which pixels having EL elements are arranged in a matrix,
A shift register circuit that shifts input data in a shift register and changes a plurality of first outputs in correspondence with the position of the data in the shift register;
a decoder circuit that selects one output from m (m is an integer of n + 1 or more) second outputs from n (n is an integer of 2 or more) bits of parallel data;
A selection circuit that selects one of the first output and the second output as a third output;
The gate driver circuit, wherein the third output of the selection circuit is electrically connected to a gate signal line formed on the display screen. The pixel is
The EL element;
A drive transistor for supplying a light emission current to the EL element;
A first switching transistor for supplying a signal corresponding to the video signal;
A capacitor for holding a signal corresponding to the video signal;
A second switching transistor for supplying a signal held in the capacitor to the driving transistor;
A first gate signal line and a second gate signal line are formed on the display screen,
A selection voltage or a non-selection voltage is applied to the first and second gate signal lines,
The first switching transistor is connected to the first gate signal line;
The second switching transistor is connected to the second gate signal line;
The gate driver circuit according to claim 1, wherein the position of the selection voltage applied to the first gate signal line is based on an output of the decoder circuit. The pixel is
The EL element;
A drive transistor for supplying a light emission current to the EL element;
A first switching transistor for supplying a signal corresponding to the video signal;
A capacitor for holding a signal corresponding to the video signal;
A second switching transistor for supplying a signal held in the capacitor to the driving transistor;
A first gate signal line and a second gate signal line are formed on the display screen,
A selection voltage or a non-selection voltage is applied to the first and second gate signal lines,
The first switching transistor is connected to the first gate signal line;
The second switching transistor is connected to the second gate signal line;
The gate driver circuit according to claim 1, wherein a selection voltage or a non-selection voltage is simultaneously applied to the plurality of second gate signal lines. The pixel is
The EL element;
A first switching transistor for supplying a signal corresponding to the video signal;
A first gate signal line is formed on the display screen,
The first switching transistor is connected to the first gate signal line;
3. The gate driver circuit according to claim 1, wherein a video signal is supplied corresponding to a pixel row in which the first gate signal line of the display screen is selected. 4. A display screen having a plurality of gate signal lines, a plurality of source signal lines, and pixels arranged at intersections of the plurality of gate signal lines and the plurality of source signal lines;
A gate driver circuit connected to the gate signal line;
A source driver circuit connected to the source signal line;
A control circuit,
The pixel is
An EL element;
A drive transistor for supplying current to the EL element;
A first capacitor;
A second capacitor;
A first switch transistor for supplying a video signal output from the source driver circuit to the first capacitor;
A second switching transistor for short-circuiting the second capacitor and the first capacitor;
The first switch transistor is connected to a first gate signal line of the plurality of gate signal lines,
The second switching transistor is connected to a second gate signal line of the plurality of gate signal lines,
The gate driver circuit includes a decoder circuit;
In the first period, the gate driver circuit selects an arbitrary first gate signal line from the plurality of first gate signal lines formed on the display screen based on the output of the decoder circuit. And operating the first switch transistor to supply the video signal output from the source driver circuit to the pixel row selected by the arbitrary first gate signal line,
In the second period, the gate driver circuit selects a plurality of second gate signal lines formed on the display screen to operate the second switch transistor, and is held by the first capacitor. An EL display device, wherein the second signal is supplied to the second capacitor. The control circuit includes:
Calculating an index value of a video signal applied to a pixel row of the display screen;
Using the index value, rearrange the order of the pixel rows,
Based on the result of the rearrangement of the order of the pixel rows,
The EL display device according to claim 6, wherein the first gate signal line is selected. The pixel further comprises:
A light-emitting current path supplied to the EL element has a third switching transistor;
The EL display device according to claim 6, wherein the third switching transistor is controlled to be non-operating in the second period. The control circuit includes:
Obtaining a square of a potential difference between a first voltage value of a video signal applied to an arbitrary pixel row and a second voltage of a pixel row applied to a pixel row other than the pixel row;
The EL display device according to claim 6, wherein the order of the pixel rows to be selected is rearranged so that a square value of the potential difference becomes smaller. The gate driver circuit further includes:
The EL display device according to claim 6, comprising a plurality of shift register circuits.