JP2016001694A - Multilayer capacitors, multilayer capacitor series comprising the same, and multilayer capacitor mounted body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce both of acoustic noise and ESL.SOLUTION: A distance tbetween a second principal plane 112 and an inner index internal electrode 142x which is closer to a first principal plane 111 of a pair of internal electrodes 140 holding an effective dielectric layer 133 closest to the second principal plane 112 in a distortion suppressing part 20 is less than or equal to a distance tbetween the inner index internal electrode 142x and an internal electrode 142y which is closest to the second principal plane 112 in a main capacitance part 10.

Description

  The present invention relates to a multilayer capacitor, a multilayer capacitor series including the multilayer capacitor, and a multilayer capacitor mounting body.

  Japanese Patent Laid-Open No. 2013-65820 (Patent Document 1) is a prior art document that discloses a multilayer capacitor mounting structure that aims to reduce noise called “acoustic noise”. In the multilayer capacitor mounting structure described in Patent Document 1, the land is provided on the substrate body and is connected to each of the external electrodes by solder. The height from the land electrode to the top of the solder is 1.27 times or less the height from the land electrode to the portion where the capacitor conductor located closest to the circuit board is exposed from the end face.

  Japanese Patent Laid-Open No. 2004-342846 (Patent Document 2) is a prior art document that discloses a multilayer ceramic capacitor in which ESL (Equivalent Series Inductance) is reduced. In the multilayer ceramic capacitor described in Patent Document 2, terminal electrodes are provided on both end faces in the longitudinal direction of the ceramic substrate. The electrode film is embedded in the ceramic substrate and laminated in the thickness direction of the ceramic substrate with the ceramic layer interposed therebetween. One of the adjacent electrode films has one end connected to one of the terminal electrodes, and the other of the adjacent electrode films has one end connected to the other of the terminal electrodes. When the distance from the bottom surface to the uppermost electrode film in the thickness direction of the ceramic substrate is e and the distance from the bottom surface to the lowermost electrode film is d1, d1 <e ≦ 400 μm and 0 <d1 ≦ 80 μm Meet.

JP2013-65820A JP 2004-342846 A

  The mounting structure of the multilayer capacitor described in Patent Document 1 has room for improvement from the viewpoint of reducing the equivalent series inductance (ESL). The multilayer ceramic capacitor described in Patent Document 2 has room for improvement from the viewpoint of reducing noise.

  The present invention has been made in view of the above problems, and an object thereof is to provide a multilayer capacitor, a multilayer capacitor series including the multilayer capacitor, and a multilayer capacitor mounting body that can further reduce noise while suppressing ESL. To do.

  The multilayer capacitor according to the first aspect of the present invention is configured by alternately laminating dielectric layers and internal electrodes, and has a first main surface and a second main surface that are located on opposite sides in the stacking direction. And a pair of external electrodes provided on a part of the surface of the laminate and electrically connected to the internal electrodes. The multilayer body includes an effective dielectric layer sandwiched between a pair of internal electrodes connected to different external electrodes, a main capacitance section in which the pair of internal electrodes are stacked, a main capacitance section, 2 including a plurality of effective dielectric layers positioned between the two main surfaces and a strain suppression unit having a plurality of internal electrodes that sandwich each of the plurality of effective dielectric layers. Since the capacitance per effective dielectric layer included in the strain suppression unit is smaller than the capacitance per effective dielectric layer included in the main capacitance unit, the strain suppression unit is Suppressing the distortion of the laminate due to the electrostriction of the effective dielectric layer of the capacitor portion. The number of effective dielectric layers included in the main capacitance portion is larger than the number of effective dielectric layers included in the strain suppression portion. The main capacitance part is thicker than the distortion suppression part. Of the pair of internal electrodes sandwiching the effective dielectric layer positioned closest to the second main surface in the distortion suppressing portion, between the inner indicator internal electrode positioned on the first main surface side and the second main surface The distance is equal to or less than the distance between the internal electrode located closest to the second main surface in the main capacitance portion and the inner indicator internal electrode.

  In one embodiment of the present invention, an outer indicator internal electrode positioned on the second main surface side of the pair of internal electrodes sandwiching the effective dielectric layer positioned closest to the second main surface side in the distortion suppressing portion; The shortest distance between the outer electrode connected to the inner indicator internal electrode is larger than the shortest distance between the outer indicator inner electrode and the inner indicator internal electrode.

  In one embodiment of the present invention, the center of the main capacitance portion is farther from the second main surface than the center of the stacked body in the stacking direction of the stacked body.

  In one form of this invention, a laminated body further contains the other distortion suppression part which is located between the main electrostatic capacitance part and the 1st main surface, and has a some effective dielectric material layer. Since the capacitance per each effective dielectric layer included in the other strain suppression unit is smaller than the capacitance per each effective dielectric layer included in the main capacitance unit, the other strain suppression unit Suppresses the distortion of the laminate due to the electrostriction of the effective dielectric layer. The number of effective dielectric layers included in the main capacitance portion is larger than the number of effective dielectric layers included in other strain suppression portions. The main capacitance part is thicker than other distortion suppression parts. Of the pair of internal electrodes sandwiching the effective dielectric layer positioned closest to the first main surface among the other strain suppression portions, the other inner indicator internal electrode and the first main surface positioned on the second main surface side Is less than or equal to the distance between the internal electrode located closest to the first main surface in the main capacitance portion and the other inner indicator internal electrode.

  In one form of this invention, the other outer side located in the 1st main surface side of a pair of internal electrodes which pinch | interpose the effective dielectric material layer located in the 1st main surface side most among other distortion suppression parts The shortest distance between the indicator internal electrode and the outer electrode connected to the other inner indicator internal electrode is larger than the shortest distance between the other outer indicator internal electrode and the other inner indicator internal electrode.

  In one aspect of the present invention, the laminate includes a first end surface and a second end surface that connect the first main surface and the second main surface and face each other, connect the first main surface and the second main surface, and the first main surface. It further has a first side surface and a second side surface that connect the end surface and the second end surface and face each other. The shortest distance between the first side surface and the second side surface is less than the shortest distance between the first end surface and the second end surface. One of the pair of internal electrodes is connected to one of the pair of external electrodes at the first end face. The other of the pair of internal electrodes is connected to the other of the pair of external electrodes at the second end face.

  In one aspect of the present invention, the laminate includes a first end surface and a second end surface that connect the first main surface and the second main surface and face each other, connect the first main surface and the second main surface, and the first main surface. It further has a first side surface and a second side surface that connect the end surface and the second end surface and face each other. The shortest distance between the first side surface and the second side surface is less than the shortest distance between the first end surface and the second end surface. One of the pair of internal electrodes is connected to one of the pair of external electrodes on the first side surface. The other of the pair of internal electrodes is connected to the other of the pair of external electrodes on the second side surface.

  In one embodiment of the present invention, the area where the internal electrodes sandwiching the effective dielectric layer included in the strain suppressing portion are opposed to each other is the internal electrode sandwiching the effective dielectric layer included in the main capacitance portion. It is smaller than the area where they face each other.

  In one embodiment of the present invention, the area where the internal electrodes that sandwich the effective dielectric layer included in the other strain suppression portion are opposed to each other sandwich the effective dielectric layer included in the main capacitance portion. The internal electrodes are smaller than the area facing each other.

  In one embodiment of the present invention, the dielectric constant of the effective dielectric layer included in the strain suppression portion is smaller than the dielectric constant of the effective dielectric layer included in the main capacitance portion.

  In one embodiment of the present invention, the dielectric constant of the effective dielectric layer included in the other strain suppression portion is smaller than the dielectric constant of the effective dielectric layer included in the main capacitance portion.

  In one embodiment of the present invention, the laminated body includes an internal electrode positioned on the first main surface side of the internal electrodes sandwiching the effective dielectric layer positioned closest to the first main surface, and the first main surface. It further includes an inner conductor positioned therebetween.

  In one embodiment of the present invention, the laminate includes an internal electrode positioned on the second main surface side of the internal electrodes sandwiching the effective dielectric layer positioned closest to the second main surface, and the second main surface. It further includes an inner conductor positioned therebetween.

  A multilayer capacitor series according to a second aspect of the present invention is a long capacitor in which a plurality of multilayer capacitors according to any one of the above and a plurality of recesses respectively storing the plurality of multilayer capacitors are provided at intervals. A carrier tape and a package including a cover tape that is attached to the carrier tape and closes the plurality of recesses. The plurality of multilayer capacitors are respectively housed in the plurality of recesses in a state where the second main surface is positioned on the bottom side of the plurality of recesses.

  A multilayer capacitor mounting body according to a third aspect of the present invention includes any of the multilayer capacitors described above and a mounted body on which the multilayer capacitor is mounted. The multilayer capacitor is mounted on the mounted body with the second main surface positioned on the mounted body side.

  According to the present invention, it is possible to further reduce squeal while suppressing ESL.

1 is a perspective view showing an appearance of a multilayer capacitor according to Embodiment 1 of the present invention. It is sectional drawing which looked at the multilayer capacitor of FIG. 1 from the II-II line arrow direction. It is sectional drawing which looked at the multilayer capacitor of FIG. 2 from the III-III line arrow direction. It is sectional drawing which looked at the multilayer capacitor of FIG. 2 from the IV-IV line arrow direction. FIG. 5 is a cross-sectional view of the multilayer capacitor of FIG. 2 as viewed from the direction of arrows VV. FIG. 3 is an enlarged cross-sectional view of an end portion on a second main surface side of the multilayer capacitor of FIG. 2. It is sectional drawing which shows the structure of the multilayer capacitor mounting body which concerns on Embodiment 1 of this invention. It is a top view which shows the structure of the multilayer capacitor | condenser series which concerns on Embodiment 1 of this invention. It is sectional drawing which looked at the multilayer capacitor | condenser series of FIG. 8 from the IX-IX line arrow direction. It is sectional drawing which shows the structure of the multilayer capacitor which concerns on Embodiment 2 of this invention. It is sectional drawing which looked at the multilayer capacitor of FIG. 10 from the XI-XI line arrow direction. It is sectional drawing to which the edge part by the side of the 1st main surface of the multilayer capacitor of FIG. 10 was expanded. It is a perspective view which shows the external appearance of the multilayer capacitor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the multilayer capacitor mounting body which concerns on Embodiment 3 of this invention seen from the XIV-XIV line arrow direction of FIG. It is a figure which shows an example of the enlarged image which observed the LT cross section of the multilayer capacitor with the scanning electron microscope.

  Hereinafter, a multilayer capacitor according to each embodiment of the present invention, a multilayer capacitor series including the multilayer capacitor, and a multilayer capacitor mounting body will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a perspective view showing the appearance of the multilayer capacitor in accordance with Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the multilayer capacitor of FIG. 1 as viewed from the direction of arrows II-II. FIG. 3 is a cross-sectional view of the multilayer capacitor of FIG. 2 as viewed from the direction of arrows III-III. 4 is a cross-sectional view of the multilayer capacitor of FIG. 2 as viewed from the direction of arrows IV-IV. FIG. 5 is a cross-sectional view of the multilayer capacitor of FIG. 2 as viewed from the direction of arrows VV. FIG. 6 is an enlarged cross-sectional view of the end portion on the second main surface side of the multilayer capacitor of FIG. In FIG. 1, the longitudinal direction L of the laminated body, the width direction W of the laminated body, and the thickness direction T of the laminated body, which will be described later, are illustrated.

  As shown in FIGS. 1 to 6, the multilayer capacitor 100 according to the first embodiment of the present invention includes a first main surface 111 and a first main surface 111 and dielectric layers 130 and internal electrodes 140 that are alternately stacked and positioned on opposite sides. The laminated body 110 having two main surfaces 112 and a pair of external electrodes 120 provided on a part of the surface of the laminated body 110 and electrically connected to the internal electrodes 140 are provided.

  The stacking direction of the dielectric layer 130 and the internal electrode 140 is orthogonal to the longitudinal direction L of the stacked body 110 and the width direction W of the stacked body 110. That is, the stacking direction of the dielectric layer 130 and the internal electrode 140 is parallel to the thickness direction T of the stacked body 110.

  The laminated body 110 connects the first main surface 111 and the second main surface 112, and the first end surface 115 and the second end surface 116 that face each other, connects the first main surface 111 and the second main surface 112, and the first end surface. The first side surface 113 and the second side surface 114 are further provided opposite to each other by connecting the first end surface 115 and the second end surface 116. The shortest distance between the first side surface 113 and the second side surface 114 is less than the shortest distance between the first end surface 115 and the second end surface 116. That is, the dimension of the laminated body 110 in the width direction W is smaller than the dimension of the laminated body 110 in the longitudinal direction L.

  In order to configure the multilayer capacitor mounting structure with the first main surface 111 or the second main surface 112 facing the mounted body 1 to be described later, in order to distinguish the main surface from the side surface, It is preferable that the dimension in the width direction W is different from the dimension in the thickness direction T by 20% or more. In this case, in the small multilayer capacitor 1 in which the dimension in the width direction W of the multilayer body 110 is less than 0.8 mm, in order to ensure both the capacitance and the thickness of the strain suppression unit 20 described later, The dimension in the height direction T of the stacked body 110 is preferably larger than the dimension in the width direction W. On the other hand, in the large multilayer capacitor 1 having a dimension of the multilayer body 110 in the width direction W of 0.8 mm or more, in order to suppress the height of the multilayer capacitor mounting structure, The dimension is preferably smaller than the dimension in the width direction W. The stacked body 110 has a rectangular parallelepiped outer shape, but may have roundness in at least one of the corner portion and the ridge line portion.

  In the present embodiment, the pair of external electrodes 120 are provided on both sides in the longitudinal direction L of the multilayer body 110. Specifically, the pair of external electrodes 120 includes a first external electrode 121 provided on the first end surface 115 side in the longitudinal direction L of the multilayer body 110 and a second end surface 116 in the longitudinal direction L of the multilayer body 110. The second external electrode 122 is provided on the side.

  The internal electrode 140 includes a plurality of first internal electrodes 141 electrically connected to the first external electrode 121 and a plurality of second internal electrodes 142 electrically connected to the second external electrode 122. Yes. Each of the first internal electrode 141 and the second internal electrode 142 has a substantially rectangular shape in plan view. The first internal electrode 141 and the second internal electrode 142 are disposed so as to face each other with an effective dielectric layer 133 described later interposed therebetween.

  In the present embodiment, the plurality of first internal electrodes 141 and the first external electrodes 121 are connected by the first end face 115. The plurality of second internal electrodes 142 and the second external electrode 122 are connected at the second end face 116.

  The dielectric layer 130 includes a first outer layer 131 constituting the first major surface 111, a second outer layer 132 constituting the second major surface 112, and a pair of inner electrodes 140 connected to different outer electrodes 120. It includes an effective dielectric layer 133 sandwiched. Specifically, the effective dielectric layer 133 is sandwiched between the first internal electrode 141 and the second internal electrode 142.

  The effective dielectric layer 133 includes a first effective dielectric layer 133a included in the main capacitance unit 10 described later, a second effective dielectric layer 133b and a third effective dielectric included in the strain suppression unit 20 described later. Layer 133c is included.

  The stacked body 110 is sandwiched between the main capacitance section 10 in which the first effective dielectric layer 133a is repeatedly stacked continuously to develop the main capacitance, and the main capacitance section 10 and the second main surface 112. And a strain suppression unit 20 having one second effective dielectric layer 133b and at least one third effective dielectric layer 133c.

  That is, in the main capacitance unit 10, a unit capacitor composed of three layers of the first internal electrode 141 and the second internal electrode 142 that sandwich the first effective dielectric layer 133a and the first effective dielectric layer 133a is continuous. Are stacked repeatedly. The main capacitance is the largest capacitance that is larger than half of the total capacitance of the multilayer capacitor 100.

  The capacitance per second effective dielectric layer 133 b included in the strain suppression unit 20 and the capacitance per each third effective dielectric layer 133 c are the first effective capacitances included in the main capacitance unit 10. It is smaller than the electrostatic capacity per dielectric layer 133a.

  That is, the capacitance of the unit capacitor including the second effective dielectric layer 133 b of the strain suppression unit 20 is smaller than the capacitance of the unit capacitor including the first effective dielectric layer 133 a of the main capacitance unit 10. The capacitances of the unit capacitors each including the third effective dielectric layer 133c of the strain suppression unit 20 are smaller than the capacitances of the unit capacitors each including the first effective dielectric layer 133a of the main capacitance unit 10.

  In the strain suppression unit 20, the capacitance of the unit capacitors each including the third effective dielectric layer 133c is less than or equal to the capacitance of the unit capacitors including the second effective dielectric layer 133b. Therefore, the comparison between the capacitance of the unit capacitor including the first effective dielectric layer 133a of the main capacitance unit 10 and the capacitance of the unit capacitor including the second effective dielectric layer 133b of the strain suppression unit 20 is made. Only will be described below. The capacitance of the unit capacitors each including the third effective dielectric layer 133c of the strain suppression unit 20 is appropriately set so as to be equal to or less than the capacitance of the unit capacitors including the second effective dielectric layer 133b of the strain suppression unit 20. Is done.

  In the present embodiment, the capacitance of the unit capacitor including the second effective dielectric layer 133b of the strain suppression unit 20 is equal to the capacitance of the unit capacitor including the first effective dielectric layer 133a of the main capacitance unit 10 respectively. 80% or less of the capacity.

  Here, the capacitance C of the capacitor is defined as C, where the dielectric constant of the effective dielectric layer 133 is ε, the area where the internal electrodes 140 are opposed to each other is s, and the interval between the internal electrodes 140 is d. = Εs / d is satisfied.

  As can be seen from the above formula, in order to change the capacitance C of the capacitor, the dielectric constant ε of the effective dielectric layer 133, the area s where the internal electrodes 140 face each other, and the internal electrodes 140 Any one of the intervals d may be changed.

  In the present embodiment, the area s where the internal electrodes 140 face each other is changed. Specifically, the area where the internal electrodes 140 sandwiching the second effective dielectric layer 133b of the strain suppression unit 20 are opposed to each other, and the first effective dielectric layer 133a included in the main capacitance unit 10 is respectively It is set to 80% or less of the area where the sandwiched internal electrodes 140 face each other.

  More specifically, as shown in FIG. 2, the length of the length of the internal electrodes 140 that sandwich the second effective dielectric layer 133b of the strain suppression unit 20 is opposed to the main capacitance unit 10. As shown in FIGS. 3 to 5, the second effective dielectric of the strain suppression unit 20 is made smaller than the length of the internal electrodes 140 that sandwich the first effective dielectric layer 133 a included. The width of the internal electrodes 140 sandwiching the layer 133b is opposed to each other, and the width of the internal electrodes 140 sandwiching the first effective dielectric layer 133a included in the main capacitance portion 10 is opposed to each other. It is smaller than the dimensions.

  Further, instead of changing the area s where the internal electrodes 140 are opposed to each other, the interval d between the internal electrodes 140 may be changed. Specifically, the dimension of the interval between the internal electrodes 140 sandwiching the second effective dielectric layer 133b of the strain suppression unit 20 is set to the internal electrode sandwiching the first effective dielectric layer 133a included in the main capacitance unit 10 respectively. It is good also as 125% or more of the dimension of the space | interval of 140.

  Furthermore, instead of changing the area s in which the internal electrodes 140 face each other, the dielectric constant ε of the second effective dielectric layer 133b may be changed. Specifically, the dielectric constant of the second effective dielectric layer 133b included in the strain suppression unit 20 may be 80% or less of the dielectric constant of the first effective dielectric layer 133a included in the main capacitance unit 10. .

  The second effective dielectric layer 133 b included in the strain suppression unit 20 is positioned adjacent to the main capacitance unit 10. Specifically, the second effective dielectric layer 133b is located adjacent to the second main surface 112 side of the main capacitance portion 10. The third effective dielectric layer 133c included in the strain suppression unit 20 is located on the second main surface 112 side of the second effective dielectric layer 133b.

In the present embodiment, the thickness of all the effective dielectric layers 133 included in the stacked body 110 is substantially uniform. As shown in FIG. 6, the thickness dimension of each effective dielectric layer 133 is t _a .

The number of first effective dielectric layers 133a included in the main capacitance unit 10 is larger than the number of second effective dielectric layers 133b and third effective dielectric layers 133c included in the strain suppression unit 20. The main capacitance unit 10 is thicker than the strain suppression unit 20. That is, as shown in FIG. 2, when the thickness dimension of the main capacitance portion 10 is t ₁₀ and the thickness dimension of the strain suppression portion 20 is t ₂₀ , t ₁₀ > t ₂₀ .

Of the pair of internal electrodes 140 sandwiching the third effective dielectric layer 133c positioned closest to the second main surface 112 side in the strain suppression unit 20, the inner indicator internal electrode 142x positioned on the first main surface 111 side; The distance dimension t ₁ between the second main surface 112 and the distance between the internal electrode 142y and the inner index internal electrode 142x located closest to the second main surface 112 in the main capacitance portion 10 is as follows. it is the dimension t ₂ below.

  In the present embodiment, in the stacking direction of the stacked body 110, the center 10 c of the main capacitance portion 10 is farther from the second main surface 112 than the center 110 c of the stacked body 110. That is, the main capacitance part 10 is located in a biased direction toward the first main surface 111 in the stacking direction of the stacked body 110.

As shown in FIG. 6, the distortion suppression unit 20 is positioned on the second main surface 112 side of the pair of internal electrodes 140 sandwiching the third effective dielectric layer 133 c positioned closest to the second main surface 112 side. The dimension t _c of the shortest distance between the outer index internal electrode 141x and the second external electrode 122 connected to the inner index internal electrode 142x is the distance between the outer index internal electrode 141x and the inner index internal electrode 142x. It is larger than the dimension t _a of the shortest distance between them.

Hereinafter, each configuration of the multilayer capacitor 100 will be described in detail.
As a material constituting the dielectric layer 130, dielectric ceramics mainly composed of BaTiO ₃ , CaTiO ₃ , SrTiO ₃ or CaZrO ₃ can be used. In addition, dielectric ceramics in which Mn compounds, Mg compounds, Si compounds, Co compounds, Ni compounds, rare earth compounds, or the like are added to these main components as subcomponents, are used as materials constituting the dielectric layer 130. Also good.

  As a material constituting the internal electrode 140, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd can be used. The thickness of each internal electrode 140 is preferably 0.3 μm or more and 2.0 μm or less after firing.

  The external electrode 120 includes a base layer provided so as to cover both end portions of the multilayer body 110 and a plating layer provided so as to cover the base layer. As a material constituting the underlayer, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd can be used. The thickness of the underlayer is preferably 10.0 μm or more and 50.0 μm or less.

  As the underlayer, one obtained by applying and baking a conductive paste on both ends of the laminate 110 or one fired simultaneously with the internal electrode 140 may be used. Other than that, as the underlayer, one formed by plating on both ends of the laminate 110 or a conductive resin containing a thermosetting resin applied to both ends of the laminate 110 was cured. It may be a thing.

  As a material constituting the plating layer, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd can be used.

  The plating layer may be composed of a plurality of layers. In this case, the plating layer preferably has a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. The Ni plating layer functions as a solder barrier layer. The Sn plating layer has good wettability with solder. The thickness of the plating layer per layer is preferably 1.0 μm or more and 10.0 μm or less.

Hereinafter, a method for manufacturing the multilayer capacitor 100 according to the present embodiment will be described.
First, a ceramic green sheet is produced by applying a ceramic paste containing a ceramic powder to a sheet by a screen printing method or the like and drying it.

  In a part of the produced ceramic green sheets, a conductive paste for forming internal electrodes is applied on the ceramic green sheets by a screen printing method or a gravure printing method so as to form a predetermined pattern. Thus, the ceramic green sheet in which the conductive pattern used as an internal electrode was formed, and the ceramic green sheet in which the conductive pattern was not formed are prepared. The ceramic paste and the conductive paste for forming the internal electrode may contain a known binder and solvent.

  A plurality of ceramic green sheets on which a conductive pattern is not formed are stacked in order to form the first outer layer 131, and a plurality of ceramic greens on which a conductive pattern is formed to form the main capacitance portion 10 thereon. A plurality of ceramic green sheets each having a conductive pattern formed thereon are sequentially stacked thereon to form the effective dielectric layer 133 of the strain suppression unit 20, and a second outer layer 132 is formed thereon. A mother laminate is produced by laminating a predetermined number of ceramic green sheets on which no conductive pattern is formed in order to form them. Thereafter, the mother laminate is pressed in the stacking direction by means such as isostatic pressing.

  Next, the mother laminated body is cut into a predetermined shape and divided to produce a plurality of rectangular parallelepiped soft laminated bodies. A rectangular parallelepiped soft laminate may be barrel-polished to round the corners of the soft laminate.

  The soft laminate is cured by firing to produce the laminate 110. The firing temperature is appropriately set according to the types of the ceramic material and the conductive material, and is set within a range of 900 ° C. or higher and 1300 ° C. or lower, for example.

  Next, a conductive paste for forming external electrodes is applied to both ends of the laminate 110 by various printing methods or dipping methods, and the laminate 110 coated with the conductive paste for forming external electrodes is heated to form a base layer. Provide. The temperature at which the laminate 110 coated with the conductive paste for forming external electrodes is preferably 700 ° C. or higher and 900 ° C. or lower.

  Next, a plating layer is provided on the underlayer by depositing a metal component by a plating method. As a method for providing the plating layer, an electrolytic plating method is preferable.

  The external electrode 120 can be provided at both ends of the stacked body 110 so as to be electrically connected to the internal electrode 140 by the step of providing the base layer and the step of providing the plating layer. Through the above steps, the multilayer capacitor 100 according to this embodiment can be manufactured.

  In the multilayer capacitor 100 according to the present embodiment, the capacitance per second effective dielectric layer 133b and the capacitance per each third effective dielectric layer 133c included in the strain suppression unit 20 are the main electrostatic capacitance. By being smaller than the electrostatic capacity per each first effective dielectric layer 133a included in the capacitor section 10, the distortion of the stacked body 110 due to the electrostriction of the effective dielectric layer 133 is suppressed.

  Specifically, when an AC voltage or a DC voltage on which an AC component is superimposed is applied to the multilayer capacitor 100, electrostriction occurs in the effective dielectric layer 133. By repeatedly generating electrostriction in accordance with the period of the AC voltage or AC component, vibration using the effective dielectric layer 133 as a vibration source is generated. In the main capacitance part 10 including the most effective dielectric layers 133, the largest strain vibration in the stacked body 110 occurs.

  As described above, the capacitance of the unit capacitor including the second effective dielectric layer 133b and the capacitance of the unit capacitor including the third effective dielectric layer 133c of the strain suppression unit 20 are expressed as the main capacitance unit 10. By making the capacitance smaller than the capacitance of the unit capacitors each including the first effective dielectric layer 133a, it is possible to reduce the strain vibration of the multilayer body 110 generated in the strain suppression unit 20.

  By positioning the strain suppression unit 20 on the second main surface 112 side of the main capacitance unit 10, propagation of strain vibration of the laminate 110 generated in the main capacitance unit 10 to the second main surface 112 side is prevented. It can be suppressed by the distortion suppression unit 20.

  Since the strain suppression unit 20 includes the second effective dielectric layer 133b and the third effective dielectric layer 133c, strain vibration of the stacked body 110 also occurs in the strain suppression unit 20. Nevertheless, due to the interaction between the strain vibration of the laminate 110 generated in the main capacitance unit 10 and the strain vibration of the laminate 110 generated in the strain suppression unit 20, the strain vibration of the laminate 110 causes the second main surface. As it approaches 112, it decays. As a result, distortion vibration propagating from the stacked body 110 to the mounted body 1 is suppressed, and noise is reduced.

  Hereinafter, a multilayer capacitor mounting body in which the multilayer capacitor 100 according to the present embodiment is mounted on a mounted body will be described with reference to the drawings.

  FIG. 7 is a cross-sectional view showing the configuration of the multilayer capacitor mounting body according to Embodiment 1 of the present invention. As shown in FIG. 7, the multilayer capacitor mounting body 100x according to the first embodiment of the present invention includes the multilayer capacitor 100 and a mounted body 1 such as a circuit board on which the multilayer capacitor 100 is mounted. The multilayer capacitor 100 is mounted on the mounted body 1 with the second main surface 112 positioned on the mounted body 1 side.

  Specifically, the mounted body 1 has a first land 21 and a second land 22 that are located at a distance from each other on the surface. The first external electrode 121 and the first land 21 of the multilayer capacitor 100 are electrically connected by a solder 31 that is a bonding agent. The second external electrode 122 and the second land 22 of the multilayer capacitor 100 are electrically connected by a solder 32 that is a bonding agent. The solders 31 and 32 are provided by reflow. Note that the bonding agent is not limited to solder, and may be any material that can mechanically and electrically bond the external electrode 120 and the first and second lands 21 and 22.

  When distortion vibration of the multilayer body 110 in the multilayer capacitor 100 propagates to the mounted body 1 through the solders 31 and 32 and the mounted body 1 vibrates at a frequency of 20 Hz to 20 kHz which is an audible frequency range, it is called squeal. Audible sound (noise) is generated.

  In the multilayer capacitor mounting body 100x, by suppressing the distortion of the multilayer body 110 by the distortion suppressing unit 20 in the multilayer capacitor 100, it is possible to reduce the distortion vibration propagating to the mounted body 1, and thus reduce the noise.

  Further, in the multilayer capacitor mounting body 100x, the main capacitance portion 10 of the multilayer capacitor 100 is mounted by mounting the multilayer capacitor 100 on the mounted body 1 with the second main surface 112 positioned on the mounted body 1 side. Since the strain suppression unit 20 can be positioned between the mounting body 1 and the mounted body 1, the strain suppression unit can suppress the propagation of the strain vibration of the stacked body 110 generated in the main capacitance unit 10 toward the second main surface 112. 20 can be suppressed.

  Further, in the multilayer capacitor 100, the main capacitance portion 10 is biased to the first main surface 111 side in the stacking direction of the multilayer body 110, so that the second main surface 112 is covered by the multilayer capacitor mounting body 100x. By mounting the multilayer capacitor 100 on the mounted body 1 while being positioned on the mounting body 1 side, the distance between the main capacitance portion 10 of the multilayer capacitor 100 and the mounted body 1 can be increased. Thereby, the propagation path of the distortion vibration of the laminated body 110 generated in the main capacitance unit 10 can be lengthened, the distortion vibration propagating to the mounted body 1 can be reduced, and the noise can be reduced.

  In order to reduce propagation of strain vibration of the laminate 110 generated in the main capacitance unit 10 to the mounted body 1, the solder 31 and 32 are arranged in the main capacitance in the stacking direction of the laminate 110. It is preferable to be located below the part 10. That is, in the stacking direction of the stacked body 110, it is preferable that the upper ends of the solders 31 and 32 are positioned below the internal electrode 142 y positioned closest to the second main surface 112 in the main capacitance portion 10.

  As shown in FIG. 7, in the multilayer capacitor mounting body 100x, the strain suppression unit 20 of the multilayer capacitor 100 includes the second effective dielectric layer 133b and the third effective dielectric layer 133c. A circuit loop 40 having the shortest path connecting the first land 21 and the second land 22, the solders 31 and 32, the outer index internal electrode 141x, and the inner index internal electrode 142x is formed. As the circuit loop 40 is made smaller, the ESL of the multilayer capacitor mounting body 100x can be reduced.

From the viewpoint of reducing noise, in order to increase the distance between the main capacitance portion 10 of the multilayer capacitor 100 and the mounted body 1, it is preferable that the thickness dimension t20 of the strain suppression portion ₂₀ is large. . From the viewpoint of reducing ESL, in order to reduce the circuit loop 40, it is preferable that the distance dimension t ₁ between the inner indicator internal electrode 142x and the second main surface 112 is small.

As described above, in the multilayer capacitor 100, the dimension t ₁ of the distance between the inner indicator internal electrode 142 x and the second main surface 112 is closest to the second main surface 112 side in the main capacitance portion 10. The distance t ₂ or less is between the internal electrode 142y located and the inner indicator internal electrode 142x. In order to reduce the sound pressure of the noise generated from the multilayer capacitor mounting body 100x, it is preferable that both the dimension t ₁ and the dimension t ₂ are large. However, in order to reduce squeal while suppressing ESL, the above dimension is required. It is more desirable to increase the dimension t ₂ than to increase t ₁ . Although the noise generated from the multilayer capacitor mounting body 100x increases as the dimension t ₁ decreases, the effect of reducing the noise works by increasing the dimension t ₂ . Therefore, variation of the sound pressure of the noise generated from the multilayer capacitor mounting body 100x by increasing the above dimensions t ₂ while reducing the dimension t ₁ is compressed, the effect on brake noise by reducing the dimension t ₁ Alleviated. Therefore, by satisfying the relationship of t ₁ ≦ t ₂ , it is possible to further reduce noise while suppressing ESL of the multilayer capacitor mounting body. Thus, in the multilayer capacitor mounting body 100x, t _10> while to reduce the circuit loop 40 in the range satisfying a relation of t ₂₀ to reduce ESL, by increasing the size t ₂₀ in the thickness of the distortion suppressing portion 20 The noise can be reduced.

However, if the dimension t ₁ of the distance between the inner indicator internal electrode 142x and the second main surface 112 is too small, the reliability of the multilayer capacitor 100 is lowered. Therefore, in the multilayer capacitor 100, as shown in FIG. The shortest distance dimension t _c between the outer index internal electrode 141x and the second external electrode 122 is preferably larger than the shortest distance dimension t _a between the outer index internal electrode 141x and the inner index internal electrode 142x.

  The reason is as follows. In the multilayer capacitor mounted body 100x, the portion of the external electrode 120 that covers the second main surface 112 located on the mounted body 1 side easily retains moisture from the outside.

When an AC voltage or a DC voltage on which an AC component is superimposed is applied to the multilayer capacitor 100, the outer index internal electrode 141x and the inner index internal electrode 142x, and the outer index internal electrode 141x and the second external electrode 122 A potential difference occurs both in between. When the second external electrode 122 holds moisture, a short circuit is likely to occur due to a potential difference between the outer index internal electrode 141x and the second external electrode 122, and the reliability of the multilayer capacitor 100 is reduced. Therefore, by satisfying the relation of t _c> t _a, it is possible to reduce the ESL while maintaining the reliability of the multilayer capacitor 100.

If the distance between the outer indicator internal electrode 141x and the second external electrode 122 is too narrow, electrostriction may occur in the dielectric layer between them, and the noise may increase. From this point of view, it is preferable to satisfy the relation of t _c> t _a.

  In the present embodiment, the multilayer body 110 includes at least one inner conductor 149 that is in contact with the first outer layer 131 and does not substantially contribute to the expression of capacitance. The internal conductor 149 is connected to the same external electrode 120 as the internal electrode 140 located closest to the first main surface 111 in the main capacitance portion 10. The inner conductor 149 in contact with the first outer layer 131 has a function of increasing the rigidity of the first outer layer 131 and restrains the distortion of the main capacitance portion 10. From the viewpoint of restraining the distortion of the main capacitance unit 10, the internal conductor 149 is preferably located near the main capacitance unit 10, and the first main surface 111 is the most in the main capacitance unit 10. The distance between the internal electrode 140 located on the side and the internal conductor 149 is preferably substantially the same as the thickness of the effective dielectric layer 133 included in the main capacitance portion 10.

  In the present embodiment, the multilayer body 110 includes at least one inner conductor 149 that is in contact with the second outer layer 132 and does not substantially contribute to the development of the capacitance. The inner conductor 149 is connected to the same outer electrode 120 as the outer index inner electrode 141x of the strain suppression unit 20. The inner conductor 149 in contact with the second outer layer 132 has a function of increasing the rigidity of the second outer layer 132, and the second main surface 112 side of the strain vibration of the multilayer body 110 generated in the main capacitance portion 10 (that is, the covered surface). Suppresses propagation to the mounting body 1).

  Hereinafter, a multilayer capacitor series including a plurality of multilayer capacitors 100 according to the present embodiment will be described with reference to the drawings.

  FIG. 8 is a plan view showing the configuration of the multilayer capacitor series according to Embodiment 1 of the present invention. FIG. 9 is a cross-sectional view of the multilayer capacitor series of FIG. 8 as viewed from the direction of arrows IX-IX.

  As shown in FIGS. 8 and 9, the multilayer capacitor string 100 s according to the first embodiment of the present invention is provided with a plurality of multilayer capacitors 100 and a plurality of recesses 5 h that respectively accommodate the plurality of multilayer capacitors 100. A long carrier tape 5 and a package 4 including a cover tape 6 that is attached to the carrier tape 5 and closes the plurality of recesses 5h. The plurality of multilayer capacitors 100 are respectively housed in the plurality of recesses 5h in a state where the second main surface 112 is positioned on the bottom 5b side of the plurality of recesses 5h.

  The plurality of multilayer capacitors 100 included in the multilayer capacitor series 100 s are taken out from the package 4 one by one and mounted on the mounted body 1. Specifically, with the cover tape 6 peeled off from the carrier tape 5, the multilayer capacitor 100 is taken out from the carrier tape 5 one by one by adsorbing and holding the first main surface 111 side of the multilayer capacitor 100. Mounted on the mount 1. As a result, the multilayer capacitor 100 is mounted on the mounted body 1 with the second main surface 112 of the multilayer capacitor 100 positioned on the mounted body 1 side.

  That is, the multilayer capacitor mounting body 100x according to Embodiment 1 of the present invention can be easily manufactured by using the multilayer capacitor string 100s according to Embodiment 1 of the present invention.

  Hereinafter, the multilayer capacitor according to the second embodiment of the present invention, the multilayer capacitor series including the multilayer capacitor, and the multilayer capacitor package will be described. In the following description of the embodiment, only the configuration different from the multilayer capacitor according to the first embodiment, the multilayer capacitor series including the multilayer capacitor, and the multilayer capacitor mounting body will be described, and the description of the same configuration will not be repeated.

(Embodiment 2)
FIG. 10 is a cross-sectional view showing the configuration of the multilayer capacitor in accordance with Embodiment 2 of the present invention. FIG. 11 is a cross-sectional view of the multilayer capacitor of FIG. 10 as viewed from the direction of the arrows XI-XI. 12 is an enlarged cross-sectional view of the end portion on the first main surface side of the multilayer capacitor of FIG. Note that FIG. 10 is shown in the same sectional view as FIG.

  As illustrated in FIGS. 10 to 12, in the multilayer capacitor 100 b according to the second embodiment of the present invention, the multilayer body 110 is positioned between the main capacitance portion 10 and the first main surface 111, and one It further includes another strain suppression unit 20 having another second effective dielectric layer 133b and at least one other third effective dielectric layer 133c.

  The capacitance per other second effective dielectric layer 133b and the capacitance per each other third effective dielectric layer 133c included in the other strain suppression unit 20 are included in the main capacitance unit 10. Less than the capacitance per each first effective dielectric layer 133a.

  That is, the capacitance of the unit capacitor including the other second effective dielectric layer 133b of the other strain suppression unit 20 is equal to the electrostatic capacitance of the unit capacitor including the first effective dielectric layer 133a of the main capacitance unit 10 respectively. Less than capacity. The capacitances of the unit capacitors each including the other third effective dielectric layer 133c of the other strain suppression unit 20 are the capacitances of the unit capacitors each including the first effective dielectric layer 133a of the main capacitance unit 10. Smaller than.

  In the other strain suppression units 20, the capacitances of the unit capacitors each including the other third effective dielectric layer 133c are not more than the capacitances of the unit capacitors including the other second effective dielectric layer 133b. Therefore, the electrostatic capacity of the unit capacitor including the first effective dielectric layer 133a of the main electrostatic capacity unit 10 and the electrostatic capacity of the unit capacitor including the other second effective dielectric layer 133b of the other strain suppression unit 20 are provided. Only the comparison with the capacity will be described below. The electrostatic capacity of the unit capacitor including the other third effective dielectric layer 133c of the other strain suppression unit 20 is equal to the electrostatic capacity of the unit capacitor including the other second effective dielectric layer 133b of the other strain suppression unit 20. It is set appropriately so as to be less than the capacity.

  In the present embodiment, the unit capacitor including the other second effective dielectric layer 133b of the other strain suppression unit 20 is a unit including the first effective dielectric layer 133a of the main capacitance unit 10, respectively. 80% or less of the capacitance of the capacitor.

  Specifically, the area in which the internal electrodes 140 sandwiching the other second effective dielectric layer 133 b of the other strain suppression unit 20 are opposed to each other is defined as the first effective dielectric included in the main capacitance unit 10. The area is set to 80% or less of the area where the internal electrodes 140 sandwiching the layers 133a face each other.

  Alternatively, the distance between the internal electrodes 140 sandwiching the other second effective dielectric layer 133b of the other strain suppression unit 20 is set to the inside of the first effective dielectric layer 133a included in the main capacitance unit 10 respectively. It is good also as 125% or more of the dimension of the space | interval between electrodes 140. FIG.

  Alternatively, the dielectric constant of the other second effective dielectric layer 133b included in the other strain suppression unit 20 may be 80% or less of the dielectric constant of the first effective dielectric layer 133a included in the main capacitance unit 10. Good.

  The other second effective dielectric layer 133 b included in the other strain suppression unit 20 is positioned adjacent to the main capacitance unit 10. Specifically, the other second effective dielectric layer 133b is located adjacent to the first main surface 111 side of the main capacitance portion 10. The other third effective dielectric layer 133c included in the other strain suppression unit 20 is located on the first main surface 111 side of the other second effective dielectric layer 133b.

In the present embodiment, the thickness of all the effective dielectric layers 133 included in the stacked body 110 is substantially uniform. As shown in FIG. 12, the thickness dimension of each effective dielectric layer 133 is t _a .

The quantity of the first effective dielectric layer 133a included in the main capacitance part 10 is the number of the other second effective dielectric layer 133b and the other third effective dielectric layer 133c included in the other distortion suppressing part 20. is more than. The main capacitance unit 10 is thicker than the other strain suppression units 20. That is, as shown in FIG. 10, when the thickness dimension of the main capacitance part 10 is t ₁₀ and the thickness dimension of the other strain suppression part 20 is t ₂₀ , t ₁₀ > t ₂₀ .

Among the other strain suppression units 20, other ones positioned on the second main surface 112 side of the pair of internal electrodes 140 sandwiching the other third effective dielectric layer 133 c positioned closest to the first main surface 111 side. The dimension t ₁ of the distance between the inner indicator internal electrode 141x and the first main surface 111 is determined so that the inner electrode 142y located closest to the first main surface 111 in the main capacitance portion 10 and the other inner indicator inside The distance t ₂ or less between the electrode 141x and the electrode 141x.

  In the present embodiment, the center 10 c of the main capacitance portion 10 overlaps the center 110 c of the stacked body 110 in the stacking direction of the stacked body 110. That is, the main capacitance unit 10 is located at the center of the stacked body 110 in the stacking direction of the stacked body 110.

As shown in FIG. 12, the first main surface 111 side of the pair of internal electrodes 140 sandwiching the third effective dielectric layer 133 c located closest to the first main surface 111 side among the other strain suppression units 20. The dimension t _c of the shortest distance between the other outer indicator internal electrode 142x located at the first outer electrode 121 connected to the other inner indicator internal electrode 141x is the other outer indicator internal electrode 142x. And the dimension t _a of the shortest distance between the inner indicator internal electrode 141x and the other inner indicator internal electrode 141x.

  In the multilayer capacitor 100b according to the present embodiment, the electrostatic capacity per other second effective dielectric layer 133b included in the other distortion suppressing unit 20 and the electrostatic capacity per each other third effective dielectric layer 133c. Since the capacitance is smaller than the capacitance per each first effective dielectric layer 133a included in the main capacitance portion 10, distortion of the stacked body 110 due to electrostriction of the effective dielectric layer 133 is suppressed.

  Specifically, when an AC voltage or a DC voltage on which an AC component is superimposed is applied to the multilayer capacitor 100b, electrostriction occurs in the effective dielectric layer 133. By repeatedly generating electrostriction in accordance with the period of the AC voltage or AC component, vibration using the effective dielectric layer 133 as a vibration source is generated. In the main capacitance part 10 including the most effective dielectric layers 133, the largest strain vibration in the stacked body 110 occurs.

  As described above, the capacitance of the unit capacitor including the other second effective dielectric layer 133b and the capacitance of the unit capacitor including the other third effective dielectric layer 133c are calculated as follows. By making the capacitance smaller than the capacitance of the unit capacitors each including the first effective dielectric layer 133a of the main capacitance portion 10, it is possible to reduce the strain vibration of the stacked body 110 generated in the other strain suppression portions 20. .

  By positioning the other strain suppression unit 20 on the first main surface 111 side of the main capacitance unit 10, distortion vibration of the laminate 110 generated in the main capacitance unit 10 toward the first main surface 111 side. Propagation can be suppressed by another distortion suppression unit 20.

  Since the other strain suppression unit 20 includes another second effective dielectric layer 133b and another third effective dielectric layer 133c, strain vibration of the stacked body 110 also occurs in the other strain suppression unit 20. When the strain vibration of the laminate 110 generated in the main capacitance unit 10 and the strain vibration of the laminate 110 generated in the other strain suppression unit 20 interfere with each other, the stack generated in the other strain suppression unit 20 When the phase of the distortion vibration of the body 110 and the phase of the distortion vibration of the stacked body 110 generated in the main capacitance unit 10 are opposite in phase, the absolute value of the amplitude of the strain vibration generated in the stacked body 110 becomes small. In this case, when the other strain suppression unit 20 includes a plurality of effective dielectric layers 133, the strain of the stacked body 110 can be suppressed.

  As described above, in the multilayer capacitor 100b according to the present embodiment, the distortion vibration of the multilayer body 110 generated in the main capacitance unit 10 propagates to the first main surface 111 side and to the second main surface 112 side. Both propagations can be suppressed. Therefore, when the multilayer capacitor 100b is mounted on the mounted body 1, either the first main surface 111 or the second main surface 112 of the multilayer capacitor 100b may be located on the mounted body 1 side.

  When the second main surface 112 of the multilayer capacitor 100b is positioned on the mounted body 1 side, the other distortion suppression unit 20 restrains the distortion of the main capacitance unit 10. The internal capacitance 140 of the other strain suppression unit 20 increases the rigidity of the other strain suppression unit 20, and the internal conductor 149 in contact with the first outer layer 131 increases the rigidity of the first outer layer 131. The effect of constraining 10 strains is increased. Further, the internal conductor 149 in contact with the second outer layer 132 increases the rigidity of the second outer layer 132, thereby suppressing the propagation of the distortion vibration of the multilayer body 110b generated in the main capacitance portion 10 to the mounted body 1. Can do.

  Conversely, when the first main surface 111 of the multilayer capacitor 100b is positioned on the mounted body 1 side, the distortion suppressing unit 20 restrains the distortion of the main capacitance unit 10. Further, the internal electrode 140 of the other strain suppression unit 20 increases the rigidity of the other strain suppression unit 20, and the internal conductor 149 in contact with the second outer layer 132 increases the rigidity of the second outer layer 132. The effect of constraining 10 strains is increased. Further, the inner conductor 149 in contact with the first outer layer 131 increases the rigidity of the first outer layer 131, thereby suppressing the propagation of distortion vibration of the multilayer body 110b generated in the main capacitance portion 10 to the mounted body 1. Can do.

  Therefore, in the multilayer capacitor series including the plurality of multilayer capacitors 100b according to the present embodiment, each of the plurality of multilayer capacitors 100b housed in the plurality of recesses 5h includes the first main surface 111 and the second main surface 112, respectively. Any of these may be located on the bottom 5b side of the plurality of recesses 5h.

  This eliminates the need to distinguish between the first main surface 111 and the second main surface 112 of the multilayer capacitor 100b when storing the plurality of multilayer capacitors 100b in the plurality of recesses 5h of the carrier tape 5, respectively. it can. Therefore, the multilayer capacitor series can be easily manufactured.

In the present embodiment, if the dimension t ₁ of the distance between the other inner indicator internal electrode 141x and the first main surface 111 is too small, the reliability of the multilayer capacitor 100b is lowered. As shown in FIG. 10, the dimension t _c of the shortest distance between the other outer index internal electrode 142x and the first external electrode 121 is between the other outer index internal electrode 142x and the other inner index internal electrode 141x. it is preferably greater than the dimension t _a of the shortest distance.

  The reason is as follows. When the first main surface 111 is positioned on the mounted body 1 side in the multilayer capacitor mounting body, the external electrode 120 in a portion covering the first main surface 111 easily retains moisture brought from the outside.

When an AC voltage or a DC voltage on which an AC component is superimposed is applied to the multilayer capacitor 100b, between the other outer index internal electrode 142x and the other inner index internal electrode 141x and between the other outer index internal electrode 142x A potential difference occurs between the first external electrode 121 and the first external electrode 121. When the first external electrode 121 holds moisture, a short circuit is likely to occur due to a potential difference between the other outer indicator internal electrode 142x and the first external electrode 121, and the reliability of the multilayer capacitor 100b is reduced. Therefore, by satisfying the relation of t _c> t _a, it is possible to reduce the ESL while maintaining the reliability of the multilayer capacitor 100b.

  Hereinafter, the multilayer capacitor according to the third embodiment of the present invention, the multilayer capacitor series including the multilayer capacitor, and the multilayer capacitor mounting body will be described.

(Embodiment 3)
FIG. 13 is a perspective view showing the appearance of the multilayer capacitor in accordance with Embodiment 3 of the present invention. FIG. 14 is a cross-sectional view showing the configuration of the multilayer capacitor mounting body according to Embodiment 3 of the present invention as viewed from the direction of the arrows XIV-XIV in FIG.

  As shown in FIGS. 13 and 14, in the multilayer capacitor 100 c according to the third embodiment of the present invention, the pair of external electrodes 120 are provided on both sides in the width direction W of the multilayer body 110. Specifically, the pair of external electrodes 120 includes a first external electrode 121 provided on the first side surface 113 side in the width direction W of the multilayer body 110 and a second side surface 114 in the width direction W of the multilayer body 110. The second external electrode 122 is provided on the side.

  The internal electrode 140 includes a plurality of first internal electrodes 141 electrically connected to the first external electrode 121 and a plurality of second internal electrodes 142 electrically connected to the second external electrode 122. Yes. Each of the first internal electrode 141 and the second internal electrode 142 has a substantially rectangular shape in plan view. The first internal electrode 141 and the second internal electrode 142 are disposed so as to face each other with the effective dielectric layer 133 interposed therebetween.

  In the present embodiment, the plurality of first internal electrodes 141 and the first external electrodes 121 are connected by the first side surface 113. The plurality of second internal electrodes 142 and the second external electrode 122 are connected by the second side surface 114.

  As a result, in the multilayer capacitor mounting body 100y according to Embodiment 3 of the present invention, the distance between the first external electrode 121 and the second external electrode 122 is shorter than in the multilayer capacitor mounting body 100x according to Embodiment 1. Become. Accordingly, the interval between the first land 21 and the second land 22 is shortened in the mounted body 1.

  When the mounted body 1 vibrates due to the distortion vibration of the stacked body 110 in the multilayer capacitor 100 c propagating to the mounted body 1, the mounted body 1 expands and contracts between the first land 21 and the second land 22. repeat. Therefore, by shortening the distance between the first land 21 and the second land 22, the stretchable length of the mounted body 1 can be shortened, so that the vibration of the mounted body 1 can be suppressed, and consequently the noise can be reduced.

  Further, by shortening the distance between the first land 21 and the second land 22, the first land 21 and the second land 22 of the mounted body 1, the solders 31 and 32, the outer index internal electrode 141 x, and the inner side The shortest circuit loop 40 connecting the index internal electrode 142x can be reduced. Therefore, the multilayer capacitor mounting body 100y according to the present embodiment can further reduce ESL compared to the multilayer capacitor mounting body 100x according to the first embodiment.

Hereinafter, a method for measuring the thickness and distance of the multilayer capacitor will be described.
First, the multilayer capacitor is filled with resin. By polishing the resin-embedded multilayer capacitor, an LT cross section passing through the center of the multilayer body and parallel to the side surface of the multilayer body is exposed. Ion milling is performed on the exposed LT cross section to remove sagging due to polishing. Thereafter, the exposed LT cross section is observed with a scanning electron microscope.

  FIG. 15 is a diagram illustrating an example of an enlarged image obtained by observing the LT cross section of the multilayer capacitor with a scanning electron microscope. In FIG. 15, a part of the second main surface 112 side in contact with the resin 9 in the multilayer capacitor is illustrated.

  When measuring the internal thickness or distance of the multilayer capacitor, first, as shown in FIG. 15, in an enlarged image obtained by observing the LT cross section of the multilayer capacitor with a scanning electron microscope, the multilayer capacitor extends in the stacking direction of the multilayer body. A straight line Lc passing through the center in the longitudinal direction L of the laminate is drawn. Next, a plurality of straight lines parallel to the straight line Lc are drawn at equal intervals (pitch S). The pitch S may be determined to be about 5 to 10 times the thickness or distance to be measured. For example, when measuring a dielectric layer having a thickness of 1 μm, the pitch S = 5 μm. Further, the same number of straight lines are drawn on both sides of the straight line Lc. That is, an odd number of straight lines are drawn by combining the straight lines Lc. In FIG. 15, five straight lines from a straight line La to a straight line Le are illustrated.

  Next, the thickness or distance is measured on each of the straight lines La to Le. However, on each of the straight lines La to Le, when the internal electrode is missing and the dielectric layers sandwiching the internal electrode are connected, or when the enlarged image of the measurement position is unclear, Further, the thickness or distance is measured on a straight line away from the straight line Lc.

For example, when measuring the thickness of the effective dielectric layer 133, as shown in FIG. 15, the thickness D ₁ on the straight line La, the thickness D ₂ on the straight line Lb, and the thickness D ₃ on the straight line Lc. Then, the thickness D ₄ on the straight line Ld and the thickness D ₅ on the straight line Le are measured, and the average value thereof is set as the thickness of the effective dielectric layer 133.

Similarly, when measuring the thickness of the second outer layer 132, as shown in FIG. 15, the thickness E ₁ on the straight line La, the thickness E ₂ on the straight line Lb, and the thickness E ₃ on the straight line Lc are measured. , The thickness E ₄ on the straight line Ld and the thickness E ₅ on the straight line Le are measured, and the average value thereof is taken as the thickness of the second outer layer 132.

  For example, when calculating the average thickness of the plurality of effective dielectric layers 133 of the main capacitance unit 10, the effective dielectric layer 133 positioned substantially at the center in the thickness direction T of the main capacitance unit 10 and The thickness of each of the five effective dielectric layers 133 including the two effective dielectric layers 133 positioned on both sides thereof is measured by the above-described method, and the average value is calculated as the main capacitance portion 10. The average thickness of the plurality of effective dielectric layers 133.

  When the number of effective dielectric layers 133 stacked is less than five, the thicknesses of all the effective dielectric layers 133 are measured by the above method, and the average value is calculated for the plurality of effective dielectric layers 133. Average thickness.

For example, when measuring the distance from the second main surface 112 to the inner indicator internal electrode 142x, as shown in FIG. 15, the distance L ₁ on the straight line La, the distance L ₂ on the straight line Lb, and the straight line Lc The distance L ₃ , the distance L ₄ on the straight line Ld, and the distance L ₅ on the straight line Le are measured, and the average value thereof is taken as the distance from the second major surface 112 to the inner indicator internal electrode 142x.

  It should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Mounted object, 4 Packaging body, 5 Carrier tape, 5b Bottom, 5h Recessed part, 6 Cover tape, 9 Resin, 10 Main electrostatic capacity part, 20 Distortion suppression part, 21 1st land, 22 2nd land, 31, 32 solder, 40 circuit loop, 100, 100b, 100c multilayer capacitor, 100s multilayer capacitor series, 100x, 100y multilayer capacitor mounting body, 110 multilayer body, 111 first main surface, 112 second main surface, 113 first side surface, 114 Second side surface, 115 First end surface, 116 Second end surface, 120 External electrode, 121 First external electrode, 122 Second external electrode, 130 Dielectric layer, 131 First outer layer, 132 Second outer layer, 133 Effective dielectric layer 133a First effective dielectric layer, 133b Second effective dielectric layer, 133c Third effective dielectric layer, 140, 141y, 14 y internal electrode, 141 a first internal electrode, 141x outer index internal electrodes, other inner index internal electrodes, 142x inner index internal electrodes, other outer index internal electrodes, 142 the second internal electrode, 149 the inner conductor.

Claims (15)

A laminate having a first principal surface and a second principal surface, which are configured by alternately laminating dielectric layers and internal electrodes, and located on opposite sides in the lamination direction;
A pair of external electrodes provided on a part of the surface of the laminate and electrically connected to the internal electrodes;
The laminate is
An effective dielectric layer sandwiched between a pair of internal electrodes connected to the different external electrodes, and a main capacitance section in which the pair of internal electrodes are laminated;
A strain suppression unit that includes a plurality of effective dielectric layers and a plurality of internal electrodes that sandwich each of the plurality of effective dielectric layers and is positioned between the main capacitance unit and the second main surface. ,
Since the capacitance per each effective dielectric layer included in the strain suppression portion is smaller than the capacitance per each effective dielectric layer included in the main capacitance portion, the strain suppression is performed. Part suppresses distortion of the laminate due to electrostriction of the effective dielectric layer of the main capacitance part,
The number of effective dielectric layers included in the main capacitance portion is greater than the number of effective dielectric layers included in the strain suppression portion,
The main capacitance part is thicker than the distortion suppression part,
The inner indicator internal electrode located on the first principal surface side of the pair of internal electrodes sandwiching the effective dielectric layer located closest to the second principal surface side in the strain suppressing portion and the second principal surface Is a multilayer capacitor that is equal to or shorter than the distance between the internal electrode located closest to the second main surface in the main capacitance portion and the inner indicator internal electrode.   Of the pair of internal electrodes sandwiching the effective dielectric layer located closest to the second main surface in the distortion suppressing portion, an outer index internal electrode positioned on the second main surface side, and the inner index internal 2. The multilayer capacitor according to claim 1, wherein a shortest distance between the external electrode connected to the electrode is larger than a shortest distance between the outer index internal electrode and the inner index internal electrode.   3. The multilayer capacitor according to claim 1, wherein in the stacking direction of the multilayer body, the center of the main capacitance portion is separated from the second main surface from the center of the multilayer body. The laminate further includes another strain suppression unit having a plurality of the effective dielectric layers positioned between the main capacitance unit and the first main surface,
The capacitance per each effective dielectric layer included in the other strain suppression portion is smaller than the capacitance per each effective dielectric layer included in the main capacitance portion. Another strain suppression unit suppresses distortion of the laminate due to electrostriction of the effective dielectric layer,
The number of the effective dielectric layers included in the main capacitance portion is larger than the number of the effective dielectric layers included in the other strain suppression portion,
The main capacitance part is thicker than the other distortion suppressing part,
The other inner indicator internal electrode positioned on the second main surface side of the pair of internal electrodes sandwiching the effective dielectric layer positioned closest to the first main surface side among the other strain suppression portions, and the The distance between the first main surface is equal to or less than the distance between the internal electrode located closest to the first main surface in the main capacitance portion and the other inner indicator internal electrode. The multilayer capacitor according to any one of claims 1 to 3.   Another outer index internal electrode positioned on the first main surface side of the pair of internal electrodes sandwiching the effective dielectric layer positioned closest to the first main surface side among the other strain suppression portions; The shortest distance between the external electrode connected to the other inner indicator internal electrode is larger than the shortest distance between the other outer indicator internal electrode and the other inner indicator internal electrode. Item 5. The multilayer capacitor according to Item 4. The laminate includes a first end surface and a second end surface that connect the first main surface and the second main surface and face each other, connect the first main surface and the second main surface, and the first end surface. A first side surface and a second side surface facing each other by connecting the second end surface;
The shortest distance between the first side surface and the second side surface is less than the shortest distance between the first end surface and the second end surface;
One of the pair of internal electrodes is connected to one of the pair of external electrodes at the first end face;
The laminated body according to any one of claims 1 to 5, wherein the other of the pair of internal electrodes is connected to the other of the pair of external electrodes at the second end face. Capacitor. The laminate includes a first end surface and a second end surface that connect the first main surface and the second main surface and face each other, connect the first main surface and the second main surface, and the first end surface. A first side surface and a second side surface facing each other by connecting the second end surface;
The shortest distance between the first side surface and the second side surface is less than the shortest distance between the first end surface and the second end surface;
One of the pair of internal electrodes is connected to one of the pair of external electrodes on the first side surface;
The laminated body according to any one of claims 1 to 5, wherein the other of the pair of internal electrodes is connected to the other of the pair of external electrodes on the second side surface. Capacitor.   The area where the internal electrodes sandwiching the effective dielectric layer included in the strain suppression portion are opposed to each other is that the internal electrodes sandwiching the effective dielectric layer included in the main capacitance portion are The multilayer capacitor according to any one of claims 1 to 7, wherein the multilayer capacitor is smaller than areas facing each other.   The area where the internal electrodes that sandwich the effective dielectric layer included in the other strain suppression portion are opposed to each other is the internal electrode that sandwiches the effective dielectric layer included in the main capacitance portion. The multilayer capacitor according to claim 4, wherein the multilayer capacitors are smaller than areas facing each other.   8. The dielectric constant according to claim 1, wherein a dielectric constant of the effective dielectric layer included in the strain suppression unit is smaller than a dielectric constant of the effective dielectric layer included in the main capacitance unit. The multilayer capacitor described.   The multilayer capacitor according to claim 4, wherein a dielectric constant of the effective dielectric layer included in the other strain suppression unit is smaller than a dielectric constant of the effective dielectric layer included in the main capacitance unit.   The laminated body is located between the internal electrode positioned on the first main surface side of the internal electrodes sandwiching the effective dielectric layer positioned closest to the first main surface and the first main surface. The multilayer capacitor according to any one of claims 1 to 11, further comprising an inner conductor.   The laminated body is located between the internal electrode located on the second principal surface side of the internal electrodes sandwiching the effective dielectric layer located closest to the second principal surface and the second principal surface. The multilayer capacitor according to any one of claims 1 to 12, further comprising an inner conductor. A plurality of multilayer capacitors according to any one of claims 1 to 13,
A package including a long carrier tape in which a plurality of recesses respectively storing the plurality of multilayer capacitors are provided at intervals, and a cover tape attached to the carrier tape to close the plurality of recesses; With
The multilayer capacitors are multilayer capacitor series, wherein the plurality of multilayer capacitors are respectively housed in the plurality of recesses in a state where the second main surface is located on the bottom side of the plurality of recesses. The multilayer capacitor according to any one of claims 1 to 13,
A mounted body on which the multilayer capacitor is mounted;
The multilayer capacitor is mounted on the mounted body in a state where the second main surface is located on the mounted body side.

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