JP2016058979A - Demodulator and radio device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator and a radio device, capable of stably establishing clock synchronization.SOLUTION: A demodulator includes a baseband conversion part, a zero cross detection part, a clock signal generation part, an asynchronous state detection part, and a reset part. The baseband conversion part converts a modulation signal into a baseband signal by sampling the modulation signal based on a clock signal. The zero cross detection part detects zero cross of the baseband signal. The clock signal generation part generates a clock signal and adjusts a frequency of the clock signal such that the clock signal synchronizes the modulation signal, according to a detection result of the zero cross detection part. The asynchronous state detection part detects an asynchronous state in which the clock signal is not synchronized with the modulation signal. The reset part sequentially resets the frequency of the clock signal, generated by the clock signal generation part, to a plurality of mutually different frequencies, if the asynchronous state is detected.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a demodulation device and a wireless device.

  In a demodulator for multilevel QAM (Quadrature Amplitude Modulation), in order to demodulate a received modulated wave and reproduce transmission data, a clock component of the modulated wave and a clock signal output from an oscillator provided in the demodulator By synchronizing these, the clock component of the modulated wave is reproduced as a clock signal output from the oscillator. A so-called zero cross method is used as a method of synchronizing the clock component of the modulated wave with the clock signal of the oscillator. According to the zero cross method, the frequency of the oscillator clock signal is feedback-controlled so that the zero cross point of the symbol of the modulated wave sampled at the period of the clock signal of the oscillator is located at the center between the symbols. Such feedback control is realized by configuring the signal path inside the demodulating apparatus involved in the generation of the clock signal as a PLL (Phase Locked Loop).

  In multi-level QAM, in order to suppress the deterioration of BER (Bit Error Rate) characteristics, the characteristics of a clock signal reproduced from a modulated wave are required to have low jitter (fluctuation) characteristics and stable frequency and phase characteristics. The On the other hand, in order to reduce costs, a clock oscillator that is not subjected to temperature compensation and that has a relatively large temperature fluctuation range may be used as a clock oscillator used on the transmitter side. In such a case, the frequency fluctuation of the clock component of the modulated wave becomes large, and it may be difficult on the receiving device side to synchronize the clock signal of the oscillator with the clock component of the modulated wave.

  As a technique for solving such a problem, there is a technique for improving the stability of the clock signal by reducing the response speed of the PLL for reproducing the clock signal used for the multilevel QAM. However, according to this method, when the frequency of the modulated wave greatly fluctuates, it takes time to establish synchronization between the modulated wave and the clock signal. In addition, according to this method, the synchronization range of the PLL is narrowed, and thus synchronization may not be established. On the contrary, if the response speed of the PLL is increased, the synchronization range of the PLL can be expanded, but the jitter of the clock signal increases, the stability of the clock signal is impaired, and the BER characteristic is deteriorated. obtain.

  Therefore, as a technique for making both the shortening of the time until the synchronization between the modulated wave and the clock signal is established and the stability of the clock signal, there is a technique for switching the response speed of the PLL before and after the establishment of synchronization. . Specifically, the response speed of the PLL is increased before the synchronization is established, and the response speed of the PLL is decreased after the synchronization is established. However, according to this method, it is necessary to add a circuit element (analog circuit) for switching the response speed of the PLL, which increases the circuit scale. Therefore, a method for switching the response speed of the PLL is not realistic.

Japanese Patent No. 52699751

  The problem to be solved by the present invention is to provide a demodulator and a radio apparatus capable of stably establishing synchronization when a clock signal is reproduced from a modulated wave.

The demodulator according to the embodiment includes a baseband conversion unit, a zero-cross detection unit, a clock signal generation unit, an asynchronous detection unit, and a reset unit. The baseband converter samples the modulation signal based on the clock signal and converts it into a baseband signal. The baseband converter detects a zero cross of the baseband signal. The clock signal generator generates the clock signal and adjusts the frequency of the clock signal based on the detection result of the zero cross detector so that the clock signal is synchronized with the modulation signal. The asynchronous detection unit detects an asynchronous state where the clock signal is not synchronized with the modulation signal. The reset unit sequentially resets the frequency of the clock signal generated by the clock signal generation unit to one of a plurality of different frequencies when the asynchronous state is detected by the asynchronous detection unit.
The wireless device of the embodiment includes the demodulation device.

The block diagram which shows the structural example of the demodulation apparatus of embodiment. It is a figure for demonstrating the detection method of the zero crossing in the demodulation apparatus of embodiment, (A) is a figure which shows the timing relationship in case the clock phase is ahead of the symbol clock of a modulation wave, (B) The figure which shows the timing relationship in case a clock phase is late | slower than a symbol clock. The figure for demonstrating operation | movement of the asynchronous detection part of the demodulator of embodiment. The figure for demonstrating operation | movement of the voltage control oscillation part of the demodulator of embodiment. The flowchart for demonstrating operation | movement of the reset part of the demodulator of embodiment. The figure which shows the waveform example of the pulse signal which the pulse signal generation part of the reset part of the demodulation apparatus of embodiment generates. FIG. 2 is a diagram illustrating a configuration example of a wireless device including the demodulation device according to the embodiment.

Hereinafter, a demodulator according to an embodiment will be described with reference to the drawings.
As an example, the demodulator of this embodiment is used in a receiving unit of a radio apparatus such as a QAM multilevel radio apparatus in the microwave band. The modulated wave received through the antenna of the wireless device is demodulated (or decoded) by the demodulating device of this embodiment.

[Description of configuration]
FIG. 1 is a block diagram illustrating an example of the overall configuration of a demodulation device 100 according to an embodiment.
The demodulator 1 includes a band-pass filter unit 101, a variable amplification unit 102, a frequency conversion unit 103, a local oscillation unit 104, a low-pass filter unit 105, a gain adjustment control unit 106, an analog / digital conversion unit 107, multiplication units 108 and 109, Numerical control oscillation unit 110, decimation filter unit 111, root roll-off filter unit 112, auto gain control unit 113, carrier wave removal unit 114, numerical control oscillation unit 115, transversal equalization unit 116, maximum likelihood decoding unit 117, phase error A detection unit 118, an asynchronous detection unit 119, a zero cross detection unit 120, a reset unit 121, and a clock signal generation unit 122 are provided. Among these, the reset unit 121 includes a pulse signal generation unit 1211 and a selection unit 1212, and the clock signal generation unit 122 includes a low-pass filter unit 1221 and a voltage controlled oscillation unit 1222.

A modulated wave IF including a carrier wave having a first intermediate frequency (for example, 140 MHz) is input to the bandpass filter unit 101. The band pass filter unit 101 is a filter for limiting the reception band, and is for removing external interference.
The variable amplifying unit 102 is for correcting the level of the received signal including the modulated wave IF that has passed through the bandpass filter unit 101. The gain of the variable amplifying unit 102 is feedback-controlled by the gain adjustment control unit 106 so that the reception intensity becomes substantially constant.
The frequency conversion unit 103 is for down-converting the frequency of the received signal including the modulated wave IF to the second intermediate frequency (for example, 21.4 MHz) by the local signal output from the local oscillation unit 104.

The low-pass filter unit 105 is an anti-aliasing filter for removing aliasing noise that occurs when the received signal including the down-converted modulated wave IF is converted from analog to digital.
The analog / digital conversion unit 107 is for sampling the received signal that has passed through the low-pass filter unit 105, for example, at a sampling rate that is eight times the frequency of the received signal and converting it into a digital signal.

  Multipliers 108 and 109 are for converting a digital signal (received signal) including the modulated wave IF output from analog / digital converter 107 into a baseband signal by quadrature detection. A multiplier 108 receives a cosine wave (cos) from the numerically controlled oscillator 110 and a multiplier 109 receives a sine wave (sin) from the numerically controlled oscillator 110. Multiplier 108 synchronously detects an in-phase component I (hereinafter referred to as I component) of the received signal, and multiplier 109 detects synchronously an orthogonal component Q (hereinafter referred to as Q component) of the received signal.

  Multipliers 108 and 109 together with analog / digital converter 107 constitute a baseband converter that converts a received signal including modulated wave IF into a baseband signal. The baseband conversion unit samples a received signal including the modulation signal IF and converts it into a baseband signal based on a clock signal CLK (described later) obtained by synchronizing with the symbol clock of the modulation wave IF in the demodulator 100. Here, the symbol clock means a clock component of the modulated wave IF, and is a virtual clock defined by the MSB (Most Significant Bit) of the symbol included in the modulated wave IF. Therefore, in this embodiment, the symbol clock of the modulated wave and the clock component of the modulated wave are synonymous.

  The numerically controlled oscillator 110 is an oscillator that oscillates at a frequency corresponding to a set value. The numerically controlled oscillator 110 generates a cosine wave (cos) and a sine wave (sin) having phases different from each other by 90 °, and supplies them to the multipliers 108 and 109, respectively. In addition, the numerically controlled oscillator 110 receives a carrier error CER based on the phase error detected by the phase error detector 118. When the carrier wave error CER exceeds the allowable value, the numerically controlled oscillator 110 stops the generation of the cosine wave (cos) and the sine wave (sin).

  The decimation filter unit 111 performs decimation processing (decimation processing) on the I component and Q component of the baseband signal output from the multiplication units 108 and 109, respectively, and reduces the sampling interval to about four times the symbol clock. Is. The decimation filter unit 111 operates in synchronization with the clock signal CLK. The baseband signal that has been subjected to the decimation processing is supplied to the root roll-off filter unit 112.

  The root roll-off filter unit 112 is a filter for performing waveform shaping by performing processing for removing intersymbol interference on each of the I component and Q component of the baseband signal supplied from the decimation filter unit 111. It is. The root roll-off filter unit 112 operates with a clock 4SCLK having a frequency that is four times the symbol clock of the baseband signal, for example. The I and Q components of the baseband signal whose waveform has been shaped are level-corrected by the auto gain control unit 113. The auto gain control unit 113 operates in synchronization with, for example, a clock 2SCLK having a frequency twice that of the symbol clock.

  The carrier wave removal unit 114 uses a cosine wave (cos) and a sine wave (sin) supplied from the numerically controlled oscillation unit 115 and uses a carrier wave component (included in the baseband signal output from the auto gain control unit 113). (Frequency offset). The carrier wave removal unit 114 operates in synchronization with, for example, a clock 2SCLK having a frequency twice that of the symbol clock.

  The numerically controlled oscillator 115 is an oscillator that oscillates at a frequency corresponding to a set value. The numerically controlled oscillation unit 115 generates a cosine wave (cos) and a sine wave (sin) whose phases are different from each other by 90 ° and supplies the generated cosine wave (sin) to the carrier wave removal unit 114. In addition, the numerically controlled oscillator 115 receives a carrier error CER based on the phase error detected by the phase error detector 118. When the carrier wave error CER exceeds the allowable value, the numerical control oscillation unit 115 stops the generation of the cosine wave (cos) and the sine wave (sin).

  Transversal equalization section 116 performs adaptive equalization processing for removing intersymbol interference due to frequency selective fading on each of the I component and Q component of the baseband signal output from carrier wave removal section 115. Is. The transversal equalization unit 116 operates in synchronization with a clock 1SCLK having the same frequency as the symbol clock, for example.

  Maximum likelihood decoding section 117 calculates the distance between the data sequence of the baseband signal output from transversal equalization section 116 and all possible encoded sequences, and the encoded sequence with the smallest distance is the most probable code sequence. For performing maximum likelihood decoding. The maximum likelihood decoding unit 117 outputs symbol data D indicating a code sequence obtained by the above maximum likelihood decoding. The maximum likelihood decoding unit 117 operates in synchronization with a clock 1SCLK having the same frequency as the symbol clock, for example.

  The phase error detection unit 118 detects a phase difference (phase error) between the I component and the Q component of the baseband signal output from the transversal equalization unit 116, and a numerically controlled oscillation unit based on the phase difference This is for detecting whether or not the carrier wave reproduced at 110 and 115 is out of synchronization with the carrier wave of the received signal. The carrier wave error CER indicating the phase error is supplied to the numerically controlled oscillators 110 and 115, and controls the operation (start and stop of oscillation) of these numerically controlled oscillators 110 and 115.

  Asynchronous detection section 119 detects a phase shift amount between the I component and Q component of the baseband signal output from transversal equalization section 116, and receives a received signal (including a modulated wave) based on the shift amount ( In order to detect the presence or absence of a state (hereinafter referred to as an asynchronous state) where the clock component of the baseband signal) and the clock signal CLK generated by the voltage controlled oscillator 1222 constituting the clock signal generator 122 are not synchronized. belongs to. As will be described later, the asynchronous detection unit 119 determines the position of the symbol on the constellation from the I component and the Q component of the baseband signal, and detects the asynchronous state from the position. A detection signal DER indicating the detection result of the asynchronous detection unit 119 is supplied to the reset unit 121.

  The zero-cross detector 120 is for detecting a zero-cross of a baseband signal (received signal), and operates in synchronization with a clock 2SCLK having a frequency twice as high as a symbol clock, for example. In the present embodiment, the zero cross detector 120 detects the zero cross by detecting whether or not the base band signal passes through the zero cross point. The zero cross detection unit 120 supplies a zero cross signal S120 indicating the detection result to the reset unit 121.

  When the asynchronous state is detected by the asynchronous detection unit 119, the reset unit 121 sets the frequency of the clock signal CLK generated by the voltage controlled oscillation unit 1222 included in the clock signal generation unit 122 to any one of a plurality of different frequencies. For resetting sequentially. The reset unit 121 selects a plurality of pulse signals having different generation ratios of the value “1” and the value “0” as a control signal for resetting the frequency of the clock signal CLK to any one of a plurality of different frequencies. To output automatically. As a result, the frequency pull-in operation start point of a PLL (Phase Locked Loop) described later is changed. Details thereof will be described later.

  The reset unit 121 includes a pulse signal generation unit 1211 and a selection unit 1212. The pulse signal generator 1211 generates a plurality of pulse signals having different generation ratios of logic value 1 and logic value 0 corresponding to a plurality of different frequencies. The selection unit 1212 selects a plurality of pulse signals generated by the pulse signal generation unit 1211 and a zero cross signal S120 indicating the detection result of the zero cross detection unit 120 based on the detection signal DER supplied from the asynchronous detection unit 119. Is for. In this embodiment, the selection unit 1212 sequentially selects a plurality of pulse signals generated by the pulse signal generation unit 1211 when an asynchronous state is detected, and when the asynchronous state is not detected, the selection unit 1212 The serocross signal S120 indicating the detection result is selected.

  The clock signal generation unit 122 generates a clock signal CLK and a zero cross signal indicating a detection result of the zero cross detection unit 120 so that the clock signal CLK is synchronized with a clock component (symbol clock) of the reception signal including the modulation signal IF. The frequency of the clock signal CLK is adjusted based on S120. The low-pass filter unit 1221 constituting the clock signal generation unit 122 integrates the pulse signal output from the reset unit 121 and converts it to a DC voltage signal. This DC voltage signal is supplied to the voltage controlled oscillator 1222. The voltage controlled oscillator 1222 oscillates at a frequency corresponding to the signal level of the DC voltage signal supplied from the low pass filter 1221 to generate the clock signal CLK. The clock signal CLK output from the voltage controlled oscillator 1222 is output from the demodulator 100 together with the symbol data D indicating the code sequence obtained by the maximum likelihood decoding of the maximum likelihood decoding unit 117 described above.

  In the present embodiment, among the above-described components, the analog / digital conversion unit 107, the multiplication units 108 and 109, the decimation filter unit 111, the root roll-off filter unit 112, the auto gain control unit 113, the carrier wave removal unit 114, and the zero cross detection. The unit 120, the reset unit 121, the low-pass filter unit 1221, and the voltage control oscillation unit 1222 constitute a feedback system and function as a kind of PLL. The PLL functions to establish synchronization between the clock signal CLK output from the voltage controlled oscillation unit 1222 and the clock component (symbol clock) included in the modulation wave IF, thereby clocking the clock component of the modulation wave IF. Output as signal CLK. In the following description, the synchronization between the clock signal CLK and the clock component of the modulation wave IF is referred to as “clock synchronization”.

[Description of operation]
Next, the operation of the demodulator 100 will be described focusing on the establishment of clock synchronization.
Here, after explaining the normal operation when the clock synchronization is established, the operation when the clock synchronization is not established will be explained.

(1) Operation when Clock Synchronization is Established The band of the modulation signal IF is limited by the bandpass filter unit 101. The received signal including the band-limited modulated signal is level-corrected by the variable amplification unit 102. The level-corrected received signal is down-converted by the frequency converter 103. The reception signal that has been down-converted has its aliasing noise removed by the low-pass filter unit 105 and is output from the low-pass filter unit 105 as a received signal S105. A baseband conversion unit (unsigned) including analog / digital conversion unit 107 and multiplication units 108 and 109 converts received signal S105 into a baseband signal including an I component and a Q component.

  For the baseband signal obtained by the baseband conversion unit, digitalization processing by the decimation filter unit 111, intersymbol interference removal processing by the route roll-off filter unit 112, level correction processing by the auto gain control unit 113, Carrier wave removal processing by the carrier wave removal unit 114 and adaptive equalization processing by the transversal equalization unit 116 are performed. Maximum likelihood decoding section 117 generates and outputs symbol data D by performing maximum likelihood decoding on the I component and Q component of the baseband signal (received signal) subjected to the above signal processing.

  In the process of performing a series of signal processing for generating the symbol data D from the modulated wave IF described above, the zero cross detector 120 synchronizes with the clock signal 2SCLK having a frequency twice as high as the symbol clock. Whether or not the reception signal output from 114 has passed through the zero cross point is sequentially detected, and a zero cross signal S120 indicating the detection result is output.

  In the present embodiment, the zero-cross detection unit 120 outputs a zero-cross signal S120 having a logical value “1” when a zero-cross is detected, and outputs a zero-cross signal S120 having a logical value “0” when no zero-cross is detected. Therefore, the zero cross signal S120 is a pulse signal including logical values “1” and “0” corresponding to the presence or absence of the detection of the zero cross. In the present embodiment, for simplification of description, in the state where the clock synchronization is established, the generation ratio of the logical values “1” and “0” included in the zero cross signal S120 is 50%, respectively. A circuit constant is set. However, the present invention is not limited to this example, and the generation ratio of the logical values “1” and “0” included in the zero-cross signal S120 can be arbitrarily set in a state where clock synchronization is established.

With reference to FIG. 2, a zero cross detection method will be described.
FIG. 2 is a diagram for explaining a zero-cross detection method in the demodulator 100 according to the embodiment. FIG. 2A shows a timing relationship when the phase of the clock 2SCLK is ahead of the symbol clock of the modulated wave. FIG. 2B shows the timing relationship when the phase of the clock 2SCLK is delayed from the symbol clock. In the example of FIG. 2, for ease of understanding, it is assumed that at the time t <b> 1, the change timing of the symbol coincides with the rise timing of the clock 2 SCLK and “1” is detected as the symbol value. Further, in FIG. 2, waveforms corresponding to symbols S1, S2, and S3 are representatively shown.

  As shown in FIG. 2A, at time t2A when a clock 2SCLK having a frequency twice that of the symbol clock first rises after time t1, the value of the symbol remains “1” and the value of the symbol is If it has not changed, it can be understood that the received signal has passed the zero-cross point by time t2A.

  On the other hand, as shown in FIG. 2B, after the time t1, at the first time t2B when the clock 2SCLK having a frequency twice as high as the symbol clock SCLK rises, the value of the symbol has changed to “0”. For example, it can be grasped that the received signal has passed the zero cross point by time t2B. Therefore, it is possible to detect whether or not the zero cross point has passed from the change in the value of the symbol.

  In parallel with the zero-cross detection operation by the above-described zero-cross detection unit 120, the asynchronous detection unit 119 performs clock synchronization from the I component and Q component of the baseband signal (reception signal) output from the transversal equalization unit 116. It is determined whether it is established. Here, since it is assumed that the clock synchronization is established, the asynchronous detection unit 119 outputs a detection signal DER indicating that the asynchronous state is not detected.

FIG. 3 is a diagram for explaining the operation (detection of an asynchronous state) of the asynchronous detection unit 119 of the demodulator 100 according to the embodiment, and illustrates a constellation in 4QAM for simplification of description.
Asynchronous detection section 119 identifies the position of the symbol on the constellation from the I component and Q component of the baseband signal output from transversal equalization section 116, and determines whether or not the position is within a predetermined region. To detect whether it is in an asynchronous state, in other words, whether clock synchronization is established.

  Here, when the clock synchronization is established, the symbols on the constellation in FIG. 3 exist in a predetermined area indicated by a dotted line. On the other hand, when clock synchronization is not established, the symbol on the constellation exists in the area indicated by the oblique line outside the predetermined area indicated by the dotted line. Therefore, it can be determined whether or not clock synchronization is established from the number of symbols existing outside a predetermined area on the constellation. In FIG. 3, the area indicated by the dotted line can be arbitrarily set based on whether or not the symbol value can be normally decoded.

  The reset unit 121 selects the zero cross signal S120 output from the zero cross detection unit 120 when the detection signal DER output from the asynchronous detection unit 119 does not indicate an asynchronous state, that is, when clock synchronization is established. This is selected by 1212 and output to the low-pass filter unit 1221. When clock synchronization is thus established, the zero-cross signal S120 output from the zero-cross detection unit 120 passes through the reset unit 121 and is supplied to the low-pass filter unit 1221.

  The low-pass filter unit 1221 integrates the zero-cross signal S120 and converts it into a DC voltage signal. Here, when the clock synchronization is established, the generation ratios of the logical values “1” and “0” included in the zero cross signal S120 are 50%, respectively, so that the amplitude of the pulse of the zero cross signal S120 is set to 5V. For example, by integrating the zero cross signal S120, a DC voltage signal of 2.5V corresponding to half of the maximum amplitude (5V) of the pulse can be obtained. This DC voltage signal is supplied from the low-pass filter unit 1221 to the voltage-controlled oscillation unit 1222. The voltage controlled oscillator 1222 oscillates at a frequency corresponding to the signal level (2.5 V) of the DC voltage signal supplied through the low pass filter 1221 and outputs the clock signal CLK.

FIG. 4 is a diagram for explaining the operation of the voltage controlled oscillator 1222 of the demodulator 100 according to the embodiment.
In FIG. 4, the horizontal axis represents the input voltage Vin of the voltage controlled oscillator 1222, and the vertical axis represents the oscillation frequency of the voltage controlled oscillator 1222, that is, the frequency f of the clock signal CLK output from the voltage controlled oscillator 1222. Represents. As shown in the example of FIG. 4, the frequency f of the clock signal CLK output from the voltage controlled oscillator 1222 changes in proportion to the input voltage Vin (0V to 5V).

  In the present embodiment, the input / output characteristics of the voltage controlled oscillator 1222 are that the frequency f of the clock signal CLK is a symbol when the signal level of the DC voltage signal supplied from the low-pass filter unit 1221 as the input voltage Vin is 2.5V. The frequency f0 is set to be synchronized with the clock. The input / output characteristics of the voltage controlled oscillator 1222 are such that when the signal level of the DC voltage signal supplied from the low-pass filter unit 1221 is higher than 2.5V, the frequency f of the clock signal CLK is set to a frequency higher than the frequency f0. Conversely, when the signal level of the DC voltage signal supplied from the low-pass filter unit 1221 is lower than 2.5 V, the frequency f of the clock signal CLK is set to be lowered to a frequency lower than the frequency f0. Yes.

  In this embodiment, three input voltages Vin of 0.5 V, 2.5 V, and 4.5 V are assumed as the input voltage Vin of the voltage controlled oscillator 1222, and the voltage controlled oscillator 1222 corresponds to these input voltages, Three (plural) frequencies of frequency f05, frequency f0, and frequency 45 are generated. Specifically, the voltage-controlled oscillator 1222 outputs a clock signal CLK having a frequency f0 when 2.5 V is input as the input voltage Vin, and the frequency f0 when 4.5 V is input as the input voltage Vin. When a clock signal CLK having a higher frequency f45 is output and 0.5V is input as the input voltage Vin, a clock signal CLK having a frequency f05 lower than the frequency f0 is output. The clock signal CLK output from the voltage controlled oscillator 1222 is supplied to the analog / digital converter 107.

  The analog / digital conversion unit 107 samples the reception signal S105 of the analog amount from the low-pass filter unit 105 at a sampling period synchronized with the clock signal CLK output from the voltage controlled oscillation unit 1222. As a result of this sampling, the zero-cross point of the baseband signal output from the carrier wave removal unit 114 is positioned at the center between symbols, and the clock synchronization by the PLL is established.

  As described above, the demodulating device 100 generates the clock signal CLK synchronized with the symbol clock included in the modulated wave IF based on the zero cross method, and modulates the symbol data D obtained by demodulating the modulated wave IF. The clock signal CLK reproduced from the wave IF is output. The symbol data D and the clock signal CLK are used for predetermined signal processing such as audio conversion, for example, in a radio apparatus described later provided with the demodulator 100.

(2) Operation when clock synchronization is not established As an example of the operation when clock synchronization is not established, for example, the clock component of the modulated wave generated on the transmission device side in addition to the operation immediately after power-on In some cases, the frequency of the signal fluctuates significantly.

  In the process of generating the symbol data D from the modulated wave IF described above, the asynchronous detection unit 119 establishes clock synchronization from the I component and Q component of the baseband signal (reception signal) output from the transversal equalization unit 116. It is determined whether or not. Here, since it is assumed that the clock synchronization is not established, the asynchronous detection unit 119 outputs a detection signal DER indicating that the asynchronous state is detected. When the detection signal DER output from the asynchronous detection unit 119 indicates an asynchronous state, the reset unit 121 sequentially selects and outputs a plurality of pulse signals having different generation ratios of the logical value 1 and the logical value 0.

  With reference to FIGS. 5 and 6, the operation of the reset unit 121 when the clock synchronization is not established will be described in detail. FIG. 5 is a flowchart for explaining the operation of the reset unit 121 of the demodulator according to the embodiment. FIG. 6 is a diagram illustrating a waveform example of a plurality of pulse signals generated by the pulse signal generation unit 1211 of the reset unit 121 of the demodulation device according to the embodiment.

  Here, FIG. 6A shows a waveform example of a pulse signal in which each generation ratio of the logical value “1” is 50%. FIG. 6B shows a waveform example of a pulse signal in which the generation ratio of the logical value “1” is 90% and the generation ratio of the logical value “0” is 10%. Further, FIG. 6C shows a waveform example of a pulse signal in which the generation ratio of the logical value “1” is 10% and the generation ratio of the logical value “0” is 90%.

  The reset unit 121 sequentially determines whether or not clock synchronization is established based on the detection signal DER output from the asynchronous detection unit 119 (step ST1). If clock synchronization is established (step ST1: YES), the determination process is repeated. Here, when the detection signal DER does not indicate the establishment of clock synchronization (step ST1: NO), that is, when the detection signal DER indicates that an asynchronous state has been detected, the reset unit 121 first generates the pulse signal generation unit 1211. Among the plurality of pulse signals, the selection unit 1212 selects a pulse signal with the generation ratio of the logic value “1” illustrated in FIG. 6A as 50%, and outputs it to the low-pass filter unit 1221 (step ST2).

  For example, as illustrated in FIG. 6A, the reset unit 121 indicates that the signal level is 5 V in a half period of the unit time T when one pulse width is T0, and in the remaining half period. A pulse signal having a signal level of 0V is output. In this case, the low-pass filter unit 1221 generates a DC voltage signal of 2.5 V by integrating the pulse signal supplied from the reset unit 121 (a pulse signal having a generation ratio of logic value “1” of 50%). The voltage control oscillation unit 1222 is supplied. The voltage controlled oscillating unit 1222 outputs a clock signal CLK having a frequency f0 corresponding to the DC voltage signal (2.5 V) supplied from the low pass filter unit 1221. As a result, when the asynchronous state is detected, the reset unit 121 resets the frequency f of the clock signal CLK to a frequency f0 among a plurality of different frequencies f0, f05, and f45.

  Subsequently, the reset unit 121 waits for a predetermined time, and determines whether or not clock synchronization is established based on the detection signal DER output from the asynchronous detection unit 119 (step ST3). At this time, the frequency f0 of the clock signal CLK output from the voltage controlled oscillator 1222 corresponds to the normal frequency of the clock component included in the modulated wave IF. Therefore, if the frequency of the clock component of the modulated wave does not vary significantly, the reset unit 121 selects a pulse signal having a logic value “1” generation ratio of 50%, and thus the PLL signal is generated with high probability. Frequency pull-in is performed and clock synchronization is established.

  When the detection signal DER indicates the establishment of clock synchronization (step ST3: YES), that is, when it indicates that the asynchronous state is not detected, the reset unit 121 outputs the zero cross signal S120 output from the zero cross detection unit 120 by the selection unit 1212. Is supplied to the low-pass filter unit 1221 (step ST8). Thus, the normal zero cross detection operation by the zero cross detection unit 120 is performed in a state where the clock synchronization is established.

  On the other hand, when the detection signal DER does not indicate the establishment of clock synchronization (step ST3: NO), that is, when the detection signal DER indicates that an asynchronous state is detected, the reset unit 121 generates a plurality of pulses generated by the pulse signal generation unit 1211. Among the pulse signals, a pulse signal having a generation ratio of logical value “1” of 90% is selected by the selection unit 1212 and output to the low-pass filter unit 1221 (step ST4). For example, as illustrated in FIG. 6B, the reset unit 121 indicates that the signal level is 5 V in the period of 90 percent of the unit time T when one pulse width is T0, and the remaining 10 percent. A pulse signal having a signal level of 0 V in the period is output. As a result, when the asynchronous state is detected, the reset unit 121 resets the frequency f of the clock signal CLK to a frequency f45 among a plurality of different frequencies f0, f05, and f45.

  The low-pass filter unit 1221 integrates the pulse signal supplied from the reset unit 121 (a pulse signal having a logic value “1” generation rate of 90%) to obtain a logic value “1” generation rate (90%). A corresponding DC voltage signal of, for example, 4.5 V is generated and supplied to the voltage controlled oscillator 1222. The voltage controlled oscillation unit 1222 outputs a clock signal CLK having a high frequency f45 corresponding to the signal level (4.5 V) of the DC voltage signal supplied from the low pass filter unit 1221. At this time, if the frequency of the clock component of the modulated wave IF input to the demodulator 100 has increased to a frequency higher than the normal frequency f0, the generation ratio of the logical value “1” is 90% in the reset unit 121. As a result, the PLL frequency is pulled in with high probability, and clock synchronization is established.

  Subsequently, the reset unit 121 waits for a predetermined time, and determines whether or not clock synchronization is established based on the detection signal DER output from the asynchronous detection unit 119 (step ST5). Here, when the detection signal DER indicates the establishment of clock synchronization (step ST5: YES), that is, when it indicates that the asynchronous state is not detected, the reset unit 121 outputs the zero cross signal S120 output from the zero cross detection unit 120. It selects with the selection part 1212 and supplies to the low-pass filter part 1221 (step ST8). Thus, the normal zero cross detection operation by the zero cross detection unit 120 is performed in a state where the clock synchronization is established.

  On the other hand, when the detection signal DER does not indicate the establishment of clock synchronization (step ST5: NO), that is, when the detection signal DER indicates that an asynchronous state is detected, the reset unit 121 generates a plurality of pulses generated by the pulse signal generation unit 1211. Among the pulse signals, a pulse signal having a generation ratio of logical value “1” of 10% is selected by the selection unit 1212 and output to the low-pass filter unit 1221 (step ST6). For example, as illustrated in FIG. 6C, the reset unit 121 indicates that the signal level is 5 V in the period of 10 percent of the unit time T when the single pulse width is T0, and the remaining 90 percent. A pulse signal having a signal level of 0 V in the period is output. As a result, when the asynchronous state is detected, the reset unit 121 resets the frequency f of the clock signal CLK to a frequency f05 out of a plurality of different frequencies f0, f05, and f45.

  The low-pass filter unit 1221 integrates the pulse signal supplied from the reset unit 121 (a pulse signal having a logic value “1” generation rate of 10%) to obtain a logic value “1” generation rate (10%). A corresponding DC voltage signal of, for example, 0.5 V is supplied to the voltage controlled oscillator 1222. The voltage controlled oscillation unit 1222 outputs a clock signal CLK having a low frequency f05 corresponding to the signal level (0.5 V) of the DC voltage signal supplied from the low pass filter unit 1221. At this time, if the frequency of the clock component of the modulated wave IF input to the demodulating device 100 is lowered to a frequency lower than the normal frequency f0, the generation ratio of the logical value “1” is 10% in the reset unit 121. As a result, the PLL frequency is pulled in with high probability, and clock synchronization is established.

  Subsequently, the reset unit 121 waits for a predetermined time, and determines whether or not clock synchronization is established based on the detection signal DER output from the asynchronous detection unit 119 (step ST7). Here, when the detection signal DER indicates the establishment of clock synchronization (step ST7: YES), that is, when it indicates that the asynchronous state is not detected, the reset unit 121 outputs the zero cross signal S120 output from the zero cross detection unit 120. It selects with the selection part 1212 and supplies to the low-pass filter part 1221 (step ST8). Thus, the normal zero cross detection operation by the zero cross detection unit 120 is performed in a state where the clock synchronization is established.

On the other hand, when the detection signal DER does not indicate the establishment of the clock synchronization (step ST7: NO), that is, when the detection signal DER indicates that the asynchronous state is detected, the reset unit 121 returns the process to the above-described step ST2, and The series of processes (steps ST2 to ST7) are repeated.
As described above, when the asynchronous detection unit 119 detects the asynchronous state, the reset unit 121 sets the frequency f of the clock signal CLK generated by the clock signal generation unit 122 to a plurality of different frequencies f0, f05, and f45. Reset sequentially to either.

  In this embodiment, three frequencies f0, f05, and f45 are set as a plurality of mutually different frequencies. However, the present invention is not limited to this example, and the number and value of the frequencies can be set arbitrarily. In this embodiment, the frequency f of the clock signal CLK is set to the frequency f0 corresponding to the symbol clock and then reset to the frequencies f05 and f45. However, the frequency f of the clock signal CLK is first set to any of the frequencies f05 and 45. It may be reset to the frequency f0 after being set, and the order may be arbitrarily set.

  According to the above-described embodiment, when the synchronization between the clock component of the baseband signal and the clock signal CLK generated by the voltage controlled oscillation unit 1222 is not established, the frequency of the clock signal CLK is forcibly sequentially changed to a plurality of frequencies. Change. When the frequency of the clock signal CLK changes, the analog / digital conversion unit 107 may perform sampling near the frequency synchronized with the frequency of the symbol clock of the modulation wave IF, and the start frequency of the PLL pull-in operation is changed. The For this reason, it is possible to stably establish clock synchronization even when the clock component of the modulated wave IF varies significantly.

  Further, according to the above-described embodiment, the reset unit 121 sequentially generates a plurality of pulse signals having different generation ratios of the logical value “1”, and based on the DC voltage signal obtained by integrating the pulse signals. Thus, since the oscillation frequency of the voltage controlled oscillator 1222 is controlled, the oscillation frequency of the voltage controlled oscillator 1222 can be controlled without using an analog circuit. Therefore, it is possible to stably establish clock synchronization while suppressing the circuit scale.

  Further, according to the above-described embodiment, even if the frequency of the clock component of the modulation wave IF greatly fluctuates, clock synchronization can be stably established without changing the PLL circuit constant, and the clock Jitter of the signal CLK can be suppressed. Therefore, in the radio apparatus provided with the demodulating apparatus 100, it is possible to suppress the deterioration of the BER, and it is possible to stably perform data demodulation in data transmission using multi-level QAM such as 128QAM.

  Further, according to the above-described embodiment, the clock component of the modulated wave is obtained on the transmitting device side by using, for example, a crystal oscillator that does not perform temperature compensation as the clock oscillator that defines the clock component of the modulated wave IF. Even if the frequency of the clock signal fluctuates, clock synchronization can be established on the receiving device side in accordance with the frequency fluctuation of the clock component of the modulated wave IF, and the clock signal CLK synchronized with the clock component of the modulated wave IF can be reproduced.

Next, an example of a wireless device provided with the above-described demodulation device 100 will be described.
FIG. 7 is a diagram illustrating a configuration example of the wireless device 1 including the demodulation device 100 according to the embodiment.
The wireless device 1 is, for example, a multi-level QAM wireless device, has two transmission / reception systems, an external connection connector 10, interface units 20A and 20B, signal processing units 30A and 30B, transmission units 40A and 40B, and a reception unit 50A. , 50B, a switching unit 60, and an antenna 70. Each of the receiving units 50A and 50B includes the demodulation device 100 according to the present embodiment described above.

  The interface unit 20A, the signal processing unit 30A, the transmission unit 40A, and the reception unit 50A constitute a first transmission / reception system, and the interface unit 20B, the signal processing unit 30B, the transmission unit 40B, and the reception unit 50B constitute a second transmission / reception system. However, in this example, the interface unit 20A can also function as a second transmission / reception system interface, and the interface unit 20B can also function as a first transmission / reception system interface. As a configuration of such a wireless device 1, a known configuration can be used except for the demodulating device 100 of the present embodiment provided in the receiving units 50A and 50B.

  The external connection connector 10 is for connecting a cable for transmitting a signal between the wireless device 1 and the external device. The interface unit 20A is a first transmission / reception system interface, and the interface unit 20B is a second transmission / reception system interface. The signal processing unit 30A is for performing signal processing of the first transmission / reception system, and the signal processing unit 30B is for performing signal processing of the second transmission / reception system.

  The transmission unit 40A is for performing transmission processing of the first transmission / reception system, and the transmission unit 40B is for performing transmission processing of the second transmission / reception system. The receiving unit 50A is for performing reception processing of the first transmission / reception system, and the reception unit 50B is for performing reception processing of the second transmission / reception system. The switching unit 60 is for sharing the antenna 70 between the first transmission / reception system and the second transmission / reception system.

  In each of the receiving units 50A and 50B, the received signal of the modulated wave received by the antenna 70 is down-converted to the first intermediate frequency, and after unnecessary wave removal processing and level diagram correction processing are performed, the demodulation device 100 Is input. As described above, the demodulation device 100 provided in each of the receiving units 50A and 50B generates and outputs the symbol data D and the clock signal CLK from the received signal of the modulated wave IF. The symbol data D and the clock signal CLK are subjected to error correction processing in the receiving units 50A and 50B, and then subjected to predetermined signal processing in the signal processing units 30A and 30B, and converted into, for example, audio data. Data subjected to the predetermined signal processing is output through the interface units 20A and 20B and the external connection connector 10.

  According to the demodulating device of at least one embodiment described above, synchronization when the clock signal is reproduced from the modulated wave can be stably established.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 100 ... Demodulator, 101 ... Band pass filter part, 102 ... Variable amplification part, 103 ... Frequency conversion part, 104 ... Local oscillation part, 105 ... Low pass filter part, 106 ... Gain adjustment control part, 107 ... Analog / digital conversion part , 108, 109 ... multiplication unit, 110 ... numerical control oscillation unit, 111 ... decimation filter unit, 112 ... root roll-off filter unit, 113 ... auto gain control unit, 114 ... carrier wave removal unit, 115 ... numerical control oscillation unit, 116 ... transversal equalization unit, 117 ... maximum likelihood decoding unit, 118 ... phase error detection unit, 119 ... asynchronous detection unit, 120 ... zero cross detection unit, 121 ... reset unit, 122 ... clock signal generation unit, 1221 ... low pass filter unit , 1222... Voltage controlled oscillator, 1211... Pulse signal generator, 1212 The selection unit.

Claims (4)

A baseband converter that samples the modulation signal based on the clock signal and converts it to a baseband signal;
A zero-cross detector for detecting a zero-cross of the baseband signal;
A clock signal generator that generates the clock signal and adjusts the frequency of the clock signal based on the detection result of the zero-cross detector so that the clock signal is synchronized with the modulation signal;
An asynchronous detector for detecting an asynchronous state in which the clock signal is not synchronized with the modulation signal;
A reset unit that sequentially resets the frequency of the clock signal generated by the clock signal generation unit to any one of a plurality of different frequencies when the asynchronous detection unit detects the asynchronous state;
A demodulator comprising: The reset unit
A pulse signal generator for generating a plurality of pulse signals having different generation ratios of logic value 1 and logic value 0 corresponding to the plurality of different frequencies;
When the asynchronous state is detected, a plurality of pulse signals generated by the pulse signal generation unit are sequentially selected, and when the asynchronous state is not detected, a signal indicating a detection result of the zero cross detection unit is selected. A selection section;
The demodulator according to claim 1, comprising: The clock signal generator is
A low-pass filter unit for integrating the pulse signal output from the reset unit;
A voltage-controlled oscillation unit that generates the clock signal by oscillating at a frequency according to a signal level supplied from the low-pass filter unit;
The demodulator according to claim 2, comprising:   A wireless device comprising the demodulator according to claim 1.

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