JP2016058773A - Semiconductor device and wireless communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting an amplitude level of a harmonic wave.SOLUTION: A semiconductor device 10 includes: an in-phase detection circuit 11 for performing in-phase detection on an AC signal; and a detection circuit 12 for detecting an amplitude level of an even-order harmonic wave outputted from the in-phase detection circuit 11. The in-phase detection circuit 11 cancels an odd-order harmonic wave by combining the AC signal that is a differential signal, in an in-phase mode and obtains a direct current and the even-order harmonic wave. The detection circuit 12 performs detection to obtain the amplitude level of the even-order harmonic wave from the in-phase detected signal, and outputs the detected amplitude level.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a wireless communication device, and for example, relates to a semiconductor device and a wireless communication device that perform calibration for suppressing second-order harmonics.

  In recent years, there has been an increasing demand for computer equipment using wireless communication such as Bluetooth, and since there is a demand for one-chip wireless circuit for mounting on wearable devices, microcomputers and SoCs (System on a The mounting of wireless circuits on semiconductor devices such as chips is increasing.

  A wireless circuit mounted on a semiconductor device is connected to a chip resistor and a chip inductor provided on a substrate together with the semiconductor device to constitute a wireless device. In these wireless devices, the power of the transmission signal is amplified and transmitted as a wireless signal from the antenna. The class D amplifier used for amplification of the transmission signal applies pulse width modulation and pulse density modulation, and power is amplified by a switching circuit. When performing transmission, harmonics are generated when the power of the transmission signal is amplified.

  Patent Document 1 is known as a technique for suppressing this harmonic. In Patent Document 1, a harmonic signal having a frequency higher than that of the transmission signal is suppressed by passing the amplified transmission signal through an LPF (Low Pass Filter).

US Pat. No. 5,973,568

  In the conventional apparatus, an LPF that passes a transmission signal with a large electric power is required. When this LPF is not provided, there is a problem that it is impossible to know how much harmonics are generated.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes an in-phase detection circuit and a detection circuit, the in-phase detection circuit detects an in-phase AC signal, and the detection circuit outputs even-order harmonics output from the in-phase detection circuit. Detect amplitude level.

  According to the one embodiment, the amplitude level of the harmonic can be detected.

It is a block diagram which shows schematic structure of the semiconductor device which concerns on embodiment. FIG. 3 shows a configuration of a semiconductor device according to the first embodiment. Diagram showing an example of a pulse waveform Figure showing the relationship between the duty ratio of the amplifier and the amplitude level of the harmonics Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection Diagram showing the relationship between the duty ratio of the amplifier and the DC signal after common-mode detection Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection 1 is a block diagram showing a configuration of a detection circuit according to a first embodiment. Circuit diagram showing a configuration of a detection circuit according to the first embodiment. The figure which shows the signal input into the detector 112 Diagram showing the signal after detection The figure which shows the example of the signal after alternating current suppression Diagram showing an example of the amplified signal Circuit diagram showing a configuration of a detection circuit according to the second embodiment. The figure which shows the example of the signal input into the amplifier circuit 114 FIG. 6 is a diagram illustrating a configuration of a semiconductor device according to a third embodiment. Circuit diagram showing the configuration of the detection circuit of the third embodiment FIG. 9 shows a configuration of a semiconductor device according to a fourth embodiment. Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the comparison signal The figure which shows the structure of the radio | wireless communication apparatus which concerns on Embodiment 5. FIG. Diagram showing an example of a mounting board The figure which shows an example of the circuit of the conventional radio | wireless communication apparatus 1 is a diagram illustrating an example of a circuit of a wireless communication device of an embodiment

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).
(Outline of the embodiment)

  FIG. 1 is a configuration diagram illustrating a schematic configuration of a semiconductor device according to an embodiment. As shown in FIG. 1, a semiconductor device 10 according to the embodiment includes an in-phase detection circuit 11 that detects an AC signal in phase, and a detection circuit 12 that detects an amplitude level of an even-order harmonic output from the in-phase detection circuit. It has.

  The in-phase detection circuit 11 cancels out the odd-order harmonics and obtains direct-current and even-order harmonics by synthesizing the AC signals that are differential signals in the same phase. Then, the common-mode detection circuit outputs the obtained signal to the detection circuit 12.

  The detection circuit 12 obtains the amplitude level of even-order harmonics from the signal after in-phase detection by detection, and outputs the detected amplitude level.

As shown in FIG. 1, the amplitude level of the harmonic can be detected by detecting the in-phase AC signal and detecting the in-phase detected signal.
(Embodiment 1)

  The first embodiment will be described below with reference to the drawings. FIG. 2 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor device 100 includes an AC output circuit 101, a balun 102, an in-phase detection circuit 103, a detection circuit 104, and a control circuit 105.

  The AC output circuit 101 amplifies the input AC signal, which is a differential signal, and outputs the amplified AC signal to the balun 102 and the in-phase detection circuit 103. For example, the AC output circuit amplifies an AC signal using a class D amplifier. In a class D amplifier, power amplification is performed by a switching circuit using pulse width modulation.

  The balun 102 converts the AC signal, which is a differential signal, from balanced to unbalanced and transmits it as a radio signal via the antenna.

  The in-phase detection circuit 103 synthesizes alternating-current signals that are differential signals in the same phase, thereby canceling out odd-order harmonics and obtaining direct-current and even-order harmonics. Then, the common-mode detection circuit 103 outputs the obtained signal to the detection circuit 104. For example, the in-phase detection circuit 103 may be configured by a circuit that synthesizes differential signals through resistors.

  The detection circuit 104 detects the signal after the in-phase detection to obtain the amplitude level of the even-order harmonic. Then, the detection circuit 104 outputs the detected amplitude level to the control circuit 105.

  The control circuit 105 controls the parameters of the AC output circuit, and determines the parameters so that the amplitude level obtained from the detection circuit 104 is minimized. For example, the control circuit 105 changes the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101 to obtain the relationship between the duty ratio and the amplitude level of the even-order harmonics. Then, the control circuit 105 instructs the AC output circuit 101 of a duty ratio that minimizes the amplitude level of the even-order harmonics.

  In the class D amplifier, when the duty ratio changes, the amplitude level of the generated harmonics also changes. FIG. 3 is a diagram illustrating an example of a pulse waveform. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates voltage. In FIG. 3, π represents a half-cycle time, and α represents the time from the center of the pulse waveform until the voltage changes.

In FIG. 3, the voltage of the pulse waveform is represented by the following equation (1).
In Equation (1), ω represents the frequency of the pulse signal, and t represents time. K means a natural number.

Here, when the duty ratio is 0.5, α = π / 2, and the voltage of the pulse waveform is expressed by the following equation (2).

On the other hand, when the duty ratio deviates from 0.5, α = β + π / 2 (beta is an arbitrary value), and the voltage of the pulse waveform is expressed by the following approximate expression (3).

In the formula (3), the direct current component is represented by 1/2 + β / 2, and the second harmonic is represented by the following formula (4).

  Here, when the value of β is small, since Sinβ can be approximated by β, the second harmonic is approximated by β / π. That is, the second harmonic becomes larger as the duty ratio deviates from 0.5. Semiconductor device 100 according to the first embodiment detects the deviation of the duty ratio from the relationship between the duty ratio and the amplitude level of the harmonic.

Specifically, the differential signal input to the AC output circuit 101 is defined by the following expressions (5) and (6).

The in-phase detection circuit 103 arithmetically averages the voltages of the differential signals. Therefore, the output of the common-mode detection circuit 103 is expressed by the following equation (7).

Here, when α is rewritten as D (time of “H” in one cycle / time of one cycle MAX = 1), the output of the common-mode detection circuit 103 is expressed by the following equation (8). In the formula (8), D is in the range of 0 <D <1.

In the output signal represented by Expression (8), the third-order or higher-order components can be ignored by natural attenuation. Therefore, if attention is given to only the first two terms of Expression (8), Expression (9) is obtained.

Here, the coefficient (e1) of the first term and the coefficient (e2) of the second term are expressed by the equations (10) and (11), and both are monotonically increasing and monotonically decreasing factors.

The signal VCMDET_O is input to the detection circuit 104 next. The detection circuit 104 is configured by a circuit having a function of removing a DC component and a function of mainly detecting a peak value of amplitude for the purpose of preventing malfunction, and a coefficient in the peak detection circuit output waveform (VDET_O) is a coefficient e1. / E2 is calculated, and Equations (12) and (13) are obtained.

Here, the e2 component is detected by the detection circuit 104, and VLPF_O from which the high frequency is removed by the LPF in the detection circuit 104 can be expressed by the following equation (14).

  In Equation (14), the value at which D = 0.5 is the duty ratio that can most suppress the second harmonic. FIG. 4 is a diagram showing the relationship between the duty ratio of the amplifier and the amplitude level of the harmonics. In FIG. 3, the horizontal axis indicates the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis indicates the amplitude of the second harmonic obtained by the detection in the in-phase detection circuit 103.

  As shown in FIG. 4, the amplitude of the second harmonic is minimized at the point where the duty ratio is P0. In addition, the value of the amplitude of the second harmonic takes a symmetrical value about the point where the duty ratio is P0.

  The semiconductor device 100 detects even-order harmonic signals including second-order harmonics and searches for a duty ratio that minimizes the amplitude of the second-order harmonics. Here, an example of search will be described with reference to FIG. FIG. 5 is a diagram illustrating the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. In FIG. 5, the horizontal axis represents the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis represents the amplitude of the second harmonic obtained by the detection in the detection circuit 104.

  As shown in FIG. 5, the voltage of the second harmonic after detection is similar to the amplitude level of the second harmonic before detection shown in FIG. 4 at the point where the duty ratio is P0. Be minimized. Further, the voltage of the signal after detection takes a symmetrical value around the point where the duty ratio is P0.

The control circuit 105 searches for the duty ratio that minimizes the voltage of the signal after detection from the relationship between the duty ratio shown in FIG. 5 and the voltage of the second harmonic after detection. The minimum point of the signal voltage after detection may be simply determined, or the minimum point of the voltage of the signal after detection is determined by obtaining the midpoint of the duty ratio where the voltage of the signal after detection is equal. Also good. In FIG. 5, the duty ratios P1 and P2 at which the voltage of the signal after detection is equal to the threshold voltage 0V are searched, and the middle point P0 is obtained from the equation P0 = (P1 + P2) / 2. . Note that the threshold voltage may not be 0 V and may be an arbitrary voltage. When the threshold value is VCMP_REF, the duty ratios D1 and D2 at two points where VLPF_O = VCMP_REF are expressed by Expression (15) and Expression (16), respectively.

Here, when the midpoint between D1 and D2 is Dc = 0.5 × (D1 + D2), Expression (17) is obtained.

  In Equation (17), Dc = 0.5 is the solution because of the constraint of 0 <{Dc, D1, D2} <1. A variable related to the duty ratio may be controlled by a digital bit such as TXDUTY_P / N to search for an optimum point.

  The method of obtaining the optimum duty ratio from the midpoint has the effect of being resistant to noise. For example, when the detection level of the second harmonic is low, the low voltage portion of the signal after detection is buried in noise due to the influence of the noise floor. FIG. 6 is a diagram illustrating the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. As in FIG. 5, in FIG. 6, the horizontal axis indicates the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis indicates the amplitude of the second harmonic obtained by the detection in the detection circuit 104.

  In FIG. 6, the signal is buried in noise near the duty ratio P0. Therefore, in the method of searching for the point where the voltage is minimum, the minimum point is buried in noise, and the point where the voltage is minimum cannot be found.

  On the other hand, in the method of obtaining the optimum duty ratio from the midpoint of two points at a predetermined voltage, the duty ratio is calculated from the signal of the part not buried in the noise, so the optimum duty ratio is not affected by the noise. Can be sought.

  In addition, the semiconductor device of the first embodiment has an effect that an optimum duty ratio can be obtained without being affected by the offset of the signal voltage.

  For example, a method of obtaining an optimum duty ratio from a direct current component among signals amplified by the alternating current output circuit 101 can be considered. FIG. 7 is a diagram illustrating the relationship between the duty ratio of the amplifier and the DC signal after in-phase detection. As shown in FIG. 7, since the duty ratio of the amplifier and the DC signal after in-phase detection are in a linear relationship, a search is made for a point where the optimum duty ratio is equal to a predetermined threshold voltage (for example, 0 V). .

  However, when a voltage offset is applied to the DC signal due to variations in the components that make up the device, the duty ratio at which the voltage is 0 V is P0 ′ as shown by the slanted line shown by the broken line, and should be the optimum duty ratio. There is a possibility that a point different from P0 is erroneously recognized as the optimum duty ratio.

  On the other hand, in the semiconductor device of the first embodiment, since the second harmonic has a line-symmetric characteristic centered on the optimum duty ratio, the optimum duty ratio is obtained even if the signal has a voltage offset. Can do. FIG. 8 is a diagram illustrating the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. 5 and 6, the horizontal axis indicates the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis indicates the amplitude of the second harmonic obtained by the detection in the detection circuit 104. In FIG. 8, the broken line is a signal after detection with an offset in voltage. The point at which the voltage becomes equal to the threshold value of 0 V due to the voltage offset is shifted to P1 ′ and P2 ′, but the midpoint of P1 and P2 is the same P0 as the midpoint of P1 ′ and P2 ′. The duty ratio can be determined.

  Next, the internal configuration of the detection circuit 104 according to the first embodiment will be described. FIG. 9 is a block diagram illustrating a configuration of the detection circuit according to the first embodiment. In FIG. 9, the detection circuit 104 includes a reference voltage generation circuit 111, a detector 112, an LPF 113, an amplifier circuit 114, and a comparator 115.

  The reference voltage generation circuit 111 generates a reference voltage used by the detector 112. For example, the reference voltage generation circuit 111 generates two types of reference voltages VREF1 and VREF2. The amplitude level of the second harmonic to be detected is determined by the difference voltage between the reference voltages VREF1 and VREF2. That is, the voltages corresponding to P1 and P2 in FIG. 5 are determined by the difference voltage between the voltages VREF1 and VREF2.

  The detector 112 adds a voltage of VREF2 to the signal detected in-phase by the in-phase detection circuit 103, and detects the DC signal with the amplitude level of the second-harmonic signal detected in-phase detected as a DC voltage by detecting it together with VREF1. obtain. Then, the detector 112 outputs the obtained amplitude level to the LPF 113.

  The LPF 113 suppresses the high-frequency component contained in the obtained DC signal having the amplitude level and outputs it to the amplifier circuit 114.

  The amplifier circuit 114 amplifies the DC signal and outputs it to the comparator 115.

  The comparator 115 compares the voltages of the amplified DC signals. The difference between the voltages of the two signals to be compared reflects the difference between the amplitude level of the second harmonic signal and the two reference voltages. As described above, the voltage corresponding to P1 and P2 in FIG. 5 is determined by the difference voltage between the reference voltages VREF1 and VREF2. That is, the comparator 115 outputs a result indicating whether the voltage of the detection signal of the second harmonic signal is higher or lower than a predetermined voltage.

  The control circuit 105 changes the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101, and detects the duty ratio at which the result of the comparator 115 changes as P1 or P2 in FIG. Then, the control circuit 105 reflects the midpoint P0 of P1 and P2 as the optimum duty ratio in the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101.

  Next, a specific circuit example of the detection circuit 104 according to the first embodiment will be described. FIG. 10 is a circuit diagram showing a configuration of the detection circuit according to the first embodiment.

  The detection circuit 104 includes resistors R1-1, R1-2, R2-1, R2-2, R3, R4, R5, R6, R7, R8, R9, capacitors C1, C2, C3, C4, and field effect transistors. FET1, FET2, FET3, FET4, variable resistance VR1-1, VR1-2, switch SW1, and current source CS1 are provided. The field effect transistors FET1 and FET2 are, for example, pMOS-FETs, and the field effect transistors FET3 and FET4 are, for example, nMOS-FETs. The switch SW1 can detect when it is closed, and does not detect when it is opened.

  In FIG. 10, a resistor R1-1, a fixed resistor of a variable resistor VR1, and a resistor R2-1 are connected in series between a power supply potential and a ground potential, the variable resistor terminal of the variable resistor VR1, and the field effect transistor FET1. A resistor R3 is connected to the gate. A resistor R1-2, a variable resistor VR12 fixed resistor, and a resistor R2-2 are connected in series between the power supply potential and the ground potential, and the variable resistance terminal of the variable resistor VR2 and the gate of the field effect transistor FET2 are connected. It is connected. A capacitor C1 is connected between the second harmonic input terminal and the field effect transistor FET1.

  In the circuit configuration in the detector 112, a resistor R4 and a capacitor 2 are connected in parallel between the power supply potential and the source of the field effect transistor FET1. A resistor R5 is connected between the power supply potential and the field effect transistor FET2. A switch SW1 is connected between the drain of the field effect transistor FET1, the drain of the FET2, and the ground potential.

  The LPF 113 includes resistors R6 and R7 and capacitors C3 and C4. A resistor R6 is connected between the source of the field effect transistor FET1, the source of the field effect transistor FET2, and the gate of the field effect transistor FET4. A resistor R7 is connected between the gate of the field effect transistor FET3. A capacitor C3 is connected between the terminal of the resistor R6 on the amplifier circuit 114 side and the terminal of the resistor R7 on the amplifier circuit 114 side. A capacitor C4 is connected between the terminal of the resistor R7 on the amplifier circuit 114 side and the ground potential.

  In the circuit configuration in the amplifier circuit 114, a resistor R8 is connected between the power supply potential and the source of the field effect transistor FET3. A resistor R9 is connected between the power supply potential and the source of the field effect transistor FET4. A current source is connected between the drain of the field effect transistor FET3 and the ground potential. A current source is connected between the drain of the field effect transistor FET4 and the ground potential. The source of the field effect transistor FET3 and the source of the field effect transistor FET4 are each connected to the output terminal.

  Next, signal processing of the detection circuit 104 will be described below.

  The second harmonic HD2 input from the input terminal is suppressed in DC component in the capacitor C1. Then, a signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 in which the DC component is suppressed is input to the gate of the field effect transistor FET1. Further, the signal of the reference voltage VREF1 is input to the gate of the field effect transistor FET2. FIG. 11 is a diagram illustrating a signal input to the detector 112. In FIG. 11, the vertical axis represents voltage, and the horizontal axis represents time. In FIG. 11, a broken line indicates a signal of the reference voltage VREF2, and a solid line indicates a signal to be detected. As shown in FIG. 11, a signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 and a signal of the reference voltage VREF1 are input to the detector 112.

  In the detector 112, the signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 is detected and becomes a signal obtained by converting the amplitude of the second harmonic HD2 into a DC voltage. Here, when the difference voltage between the two reference voltages is Vrf and the voltage after detecting the amplitude level of the second harmonic is VDC1, the detection potential obtained from the source of the field effect transistor FET1 is obtained by Vo2 = VDC1 + Vrf. . Further, assuming that the detection potential obtained from the source of the field effect transistor FET2 is Vo1 = VDC, the amplitude level of the second harmonic in the potential difference between the field effect transistors FET1 and FET2 has a relationship of ΔVd = VDC1−VDC. FIG. 12 is a diagram illustrating a signal after detection. In FIG. 12, the vertical axis represents voltage and the horizontal axis represents time. In FIG. 12, the broken line indicates the signal of the reference voltage VREF2 and the signal before detection, and the solid line indicates the signal after detection. As shown in FIG. 12, some AC components remain in the signal after detection.

  The LPF 113 suppresses the AC component of the signal after detection. FIG. 13 is a diagram illustrating an example of a signal after AC suppression. In FIG. 13, the vertical axis represents voltage, and the horizontal axis represents time. In FIG. 13, the broken line indicates the signal of the reference voltage VREF2 and the AC component, and the solid line indicates the signal after AC suppression. Then, after passing through the LPF 113, the signal potentials are Vo2 ′ = VDC1 + a × Vrf and Vo1 ′ = VDC, respectively. Here, a is a predetermined constant.

  Then, the amplifier circuit 114 amplifies the signal after AC suppression. FIG. 14 is a diagram illustrating an example of the amplified signal. In FIG. 14, the vertical axis represents voltage, and the horizontal axis represents time. In FIG. 14, the solid line indicates the amplified signal. The potential difference between the signals output from the amplifier circuit 114 is V (OUT_N) −V (OUT_P) = Av × (ΔVd + a × Vrf). Here, Av is an amplification factor in the amplifier circuit 114. The potential difference between the two signals means a difference between a voltage indicating the amplitude of the second harmonic HD2 and a threshold voltage.

  Therefore, when the comparator 115 determines that the voltages of the two signals are equal, it means that the voltage indicating the amplitude of the second harmonic HD2 is equal to the threshold value. Based on the comparison result, search is made for duty ratios P1 and P2 at which the voltage of the signal after detection becomes equal to the threshold voltage, and P0 = (P1 + P2) / 2 is used as the optimum duty P0. It can be obtained as a ratio.

  The optimal duty ratio determination timing is changed so that the control circuit 105 sweeps a settable duty ratio range at a predetermined timing such as a stable timing after power-on. Then, the control circuit 105 searches for the duty ratios P1 and P2 at which the voltage of the second harmonic signal after detection is equal to the threshold voltage from the relationship between the output obtained from the comparator 115 and the duty ratio. The duty ratio of the AC output circuit 101 is set with P0, which is the middle point between P1 and P2, as an optimum duty ratio. With the above operation, calibration of the AC output circuit 101 for obtaining an optimum duty ratio can be executed.

As described above, the first embodiment can obtain the amplitude level of the harmonic by detecting the AC signal output from the AC output circuit in phase and detecting even-order harmonics of the signal after the in-phase detection. Thus, the AC output circuit can be controlled to suppress the amplitude level of the harmonics.
(Embodiment 2)

  The second embodiment will be described below with reference to the drawings. In the first embodiment, the second harmonic signal after detection is output to the amplifier circuit via the LPF, but in this embodiment, the connection lines between the detector and the amplifier circuit are connected by a capacitor. To do.

  FIG. 15 is a circuit diagram showing a configuration of the detection circuit according to the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 15, the capacitor connection circuit 201 includes a capacitor C21. A capacitor C21 is connected between a line connecting the source of the field effect transistor FET1 and the gate of the field effect transistor FET3 and a line connecting the source of the field effect transistor FET2 and the gate of the field effect transistor FET4. ing.

  Inserting a capacitor is equivalent to short-circuiting the connection lines between the detector 112 and the amplifier circuit 114 in an AC manner. A high-frequency component originally present only in one of the signals from which harmonics have been detected is input to the amplifier circuit 114 at the same level on the signal side of the reference voltage. FIG. 16 is a diagram illustrating an example of a signal input to the amplifier circuit 114. In FIG. 16, the vertical axis represents voltage, and the horizontal axis represents time. In FIG. 16, a broken line indicates a signal before detection, and a solid line indicates a signal in which a high frequency component is reflected on both by the capacitor connection circuit 201.

  For this high frequency component, the CMRR (Common Mode Rejection Ratio) of the amplifier circuit 114 is effectively used, and the high frequency component of the same level of each signal is removed at the output of the amplifier circuit 114. The amount to be removed is determined by the cut-off frequency of the RC filter and the CMRR characteristics of the amplifier circuit 114, respectively.

According to the semiconductor device of the second embodiment, the harmonic components are removed using the CMRR of the amplifier circuit, and the LPF is not used. Therefore, the parts of the LPF circuit can be reduced, and the area of the semiconductor device can be reduced. The effect can be expected.
(Embodiment 3)

  The second embodiment will be described below with reference to the drawings. In the first embodiment, the voltage of the second harmonic signal after detection is compared with the threshold voltage using a comparator, but in this embodiment, an analog-digital conversion circuit is provided, The potential difference between the voltage of the second harmonic signal and the threshold voltage is converted into a digital signal.

  FIG. 17 is a diagram showing a configuration of the semiconductor device according to the third embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 17, the semiconductor device 300 includes a detection circuit 301, an AD conversion circuit 302, and a control circuit 303.

  The detection circuit 301 detects the signal after in-phase detection to obtain the amplitude level of the even-order harmonics. Then, the detection circuit 301 outputs the detected amplitude level to the control circuit 105. In addition, the detection circuit 301 outputs the signal after the in-phase detection and the reference voltage signal to the AD conversion circuit 302.

  The AD conversion circuit 302 performs analog-to-digital conversion on the potential difference between the signal after the in-phase detection and the reference voltage signal, and outputs the converted digital signal to the control circuit 303.

  The control circuit 303 controls the parameters of the AC output circuit, and determines the parameters so that the amplitude level obtained from the detection circuit 301 is minimized. For example, the control circuit 303 changes the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101, and obtains the relationship between the duty ratio and the amplitude level of the even-order harmonics. Then, the control circuit 303 instructs the AC output circuit 101 of a duty ratio that minimizes the amplitude level of the even-order harmonics.

  Further, the control circuit 303 monitors the fluctuation of the second harmonic based on the digital signal converted by the AD conversion circuit 302. Detailed operation will be described later.

  Next, the internal configuration of the detection circuit 301 will be described. FIG. 18 is a circuit diagram showing a configuration of the detection circuit according to the third embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 18, the detection circuit 301 includes switches SW31, SW32, SW33, and SW34.

  As shown in FIG. 18, a switch SW31 is connected between the variable resistance terminal of the variable resistor VR1 and the resistor R6. A switch SW31 is connected between the variable resistor terminal of the variable resistor VR2 and the resistor R7.

  A switch SW33 is connected between the source of the field effect transistor FET2 and the resistor R6. A switch SW34 is connected between the source of the field effect transistor FET1 and the resistor R7.

  SW31 and SW32 open and close in conjunction, and similarly SW33 and SW34 open and close. When SW31 and SW32 are in an open state, SW33 and SW34 are in a closed state, and a signal after detection is input to the LPF 113.

  When SW31 and SW32 are in the closed state, SW33 and SW34 are in the open state, bypassing the detector 112, and inputting the second harmonic signal and the reference voltage signal directly into the LPF 113.

The operation will be described below. After performing the calibration using the second harmonic in the first or second embodiment, the signal path is switched so that the output of the amplifier circuit 114 is monitored by the AD converter circuit. Here, the detector 112 is bypassed, and a DC voltage (e1 component described in the first embodiment) that changes monotonically according to the second harmonic is input to the AD converter circuit. At the end of calibration, the output of the amplification circuit 114 is a voltage (Vopt) at which the second harmonic is minimized, and the output of the amplification circuit 114 at this time is temporarily stored in the memory. If the secondary harmonic fluctuates for some reason (for example, temperature), the output of the amplifier circuit 114 changes following the change.
(1) Adjust the duty so that it approaches Vopt.
(2) If it is not significantly different from Vopt, either one of the calibration operations is not selected is selected.

  As a criterion for judging that it is not significantly different from Vopt, it is conceivable that it is the level of the second harmonic allowed by the Radio Law.

As described above, according to the semiconductor device of the third embodiment, either a correction is performed again even for a sudden environmental change, or a calibration operation is not selected according to the degree of the second harmonic fluctuation. Can be reduced based on the output of the analog-digital conversion circuit.
(Embodiment 4)

  The fourth embodiment will be described below with reference to the drawings. In the first embodiment, the optimum duty ratio is searched using the amplitude level of the second harmonic, but in the present embodiment, the phase of the second harmonic is used.

  FIG. 19 is a diagram illustrating a configuration of a semiconductor device according to the fourth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 19, the semiconductor device 400 includes an in-phase detection circuit 401, a phase comparator 402, an LPF 403, a comparator 404, and a control circuit 405.

  The common-mode detection circuit 401 cancels out the odd-order harmonics and obtains direct-current and even-order harmonics by synthesizing the differential signals input to the AC output circuit 101 in the same phase. Then, the common-mode detection circuit 401 outputs the obtained signal to the phase comparator 402.

  The phase comparator 402 compares the phase of the signal output from the in-phase detection circuit 103 and the signal output from the in-phase detection circuit 401, and outputs a comparison signal using the comparison result as a voltage. The LPF 403 suppresses the AC component of the comparison signal and outputs it to the comparator 404.

  The comparator 404 compares the comparison signal with a predetermined threshold value and outputs the comparison result to the control circuit 405. The control circuit 405 controls the AC output circuit 101 based on the comparison result.

  Next, the operation of the semiconductor device of the fourth embodiment will be described. FIG. 20 is a diagram illustrating the relationship between the duty ratio of the amplifier and the voltage of the comparison signal. In FIG. 20, the horizontal axis represents the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis represents the voltage of the comparison signal obtained in the phase comparator 402.

  The control circuit 405 searches for a duty ratio in which the voltage of the comparison signal is equal to the threshold voltage shown in FIG. 20, and instructs the AC output circuit 101 of the obtained duty ratio.

As described above, according to the semiconductor device of the fourth embodiment, the optimum duty ratio can be detected by comparing the phase differences before and after amplification of the differential signal.
(Embodiment 5)

  The fifth embodiment will be described below with reference to the drawings. The fifth embodiment is an example in which the semiconductor device of the first to fourth embodiments is applied to BLE (Bluetooth (registered trademark) Low Energy).

  FIG. 21 is a diagram illustrating a configuration of a wireless communication apparatus according to the fifth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 21, the wireless communication system 500 includes a wireless communication device 501 and an MCU 502. In FIG. 21, the wireless communication device 501 includes a modem 50, a local oscillator 51, a power amplifier 52, a matching 53, an antenna 54, a low noise amplifier 55, a frequency divider 56, and a down converter 57-1. 57-2, LPFs 58-1, 58-2, and AD converters 59-1, 59-2.

  The modem 50 modulates the transmission data output from the MCU 502 to obtain a transmission signal and outputs it to the local oscillator 51. Also, the modem 50 demodulates the reception signals output from the AD converters 59-1 and 59-2 and outputs the demodulated signals to the MCU 502.

  The local oscillator 51 generates a signal having a frequency to be transmitted wirelessly, and outputs the signal to the power amplifier 52 by superimposing it on the modulated transmission signal.

  The power amplifier 52 is a power amplifier including any one of the semiconductor devices according to the first to fourth embodiments. The power amplifier 52 amplifies the power of the transmission signal and outputs it to the matching 53.

  The matching 53 matches the impedance between the power amplifier 52 and the antenna 54. The matching 53 matches the impedance between the antenna 54 and the low noise amplifier 55.

  The antenna 54 transmits a transmission signal as a radio signal, and outputs the received radio signal to the matching 53 as a reception signal.

  The low noise amplifier 55 amplifies the power of the received signal and outputs it to the down converters 57-1 and 57-2.

  The frequency divider 56 divides the frequency signal generated by the local oscillator 51 and outputs it to the down converters 57-1 and 57-2.

  The down converters 57-1 and 57-2 perform frequency conversion on the received signals and output them to the LPFs 58-1 and 58-2, respectively.

  LPFs 58-1 and 58-2 suppress high-frequency components of the received signal and output the signals to AD converters 59-1 and 59-2, respectively.

  The AD converters 59-1 and 59-2 convert the received signal from an analog signal to a digital signal and output it to the modem 50.

  As described above, according to the wireless communication device of the fifth embodiment, the detection of the optimum duty ratio using the second harmonic can be applied to the wireless communication device, so that unnecessary harmonics can be transmitted wirelessly. It is suppressed.

  In addition, when mounted on a wireless communication device, the number of external components connected to the semiconductor device can be reduced.

  FIG. 22 is a diagram illustrating an example of a mounting substrate. In FIG. 22, a substrate 600 is a substrate on which a conventional wireless communication device is mounted, and the substrate 600 includes a semiconductor 601 including an integrated circuit and an LPF 602. On the other hand, the substrate 610 is a substrate on which the wireless communication device of this embodiment is mounted, and the substrate 610 includes the semiconductor 611 of this embodiment. As shown in FIG. 22, the substrate 610 has a smaller number of components other than the semiconductor mounted on the substrate compared to the substrate 600.

  A specific reduction in the number of parts will be described with reference to FIGS. FIG. 23 is a diagram illustrating an example of a circuit of a conventional wireless communication device. FIG. 24 is a diagram illustrating an example of a circuit of the wireless communication apparatus of this embodiment. In FIG. 23, a conventional wireless communication apparatus 700 includes an amplifier circuit 701, an LPF 702, and an antenna 703. On the other hand, in FIG. 24, radio communication apparatus 800 of the present embodiment includes an amplifier circuit 701 and an antenna 703.

Comparing FIG. 23 and FIG. 24, the number of components connected to the outside of the semiconductor device is fewer in FIG. 24 than in FIG. That is, as described in the first to fifth embodiments, radio communication apparatus 800 according to the present embodiment obtains harmonic amplitude levels by detecting even-order harmonics of signals after in-phase detection. Therefore, since the AC output circuit can be controlled to suppress the harmonic amplitude level, a configuration for suppressing the harmonic amplitude level with respect to the amplified high-frequency signal becomes unnecessary. An LPF circuit for a high-frequency signal after amplification has a larger capacitor and resistor size than an LPF circuit for a weak signal. Therefore, making this LPF circuit unnecessary greatly contributes to miniaturization of the wireless communication device.

  The wireless communication device can also be applied to a wireless communication device commission using BLE and wireless communication devices other than BLE.

  As a specific application example, the wireless communication device according to the present embodiment is used when a heart rate monitor, a blood pressure monitor, or a pedometer used in the fitness and healthcare fields communicates with a computer device such as a smartphone by a wireless signal. Can be mounted on individual devices.

  Further, the present invention can be applied to a device that records the traveling content of a bicycle. For example, when a sensor provided on a wheel and a handle of a bicycle and a recording computer provided on the handle are communicated with each other by a wireless signal, they can be mounted on individual devices.

  In addition, an NTP server, a mail server, or a computer terminal that receives mail and a clock that communicates with a clock that has a mail arrival notification function on the clock or the clock are mounted on individual devices. be able to.

  Moreover, when communicating between apparatuses, such as a keyless entry apparatus and iBeacon (trademark), by radio | wireless signal, it can mount in each apparatus. It can also be mounted on a wearable device.

  The semiconductor device according to each of the above embodiments may have a configuration in which the conductivity type (p-type or n-type) such as a semiconductor substrate, a semiconductor layer, or a diffusion layer (diffusion region) is inverted. Therefore, when one of n-type and p-type conductivity is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type is p-type and the second conductivity type is The first conductivity type may be n-type and the second conductivity type may be p-type.

  In addition, what is expressed by replacing the device of the above embodiment with a method or system, a program that causes a computer to execute processing of the device or a part of the device, a wireless communication device including the device, and the like are also included in the present embodiment. It is effective as a form.

  In addition, the control operation and the program for realizing the control operation in the control circuit described above can be stored using various types of non-transitory computer readable media and supplied to the computer. . Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROM (Read Only Memory) CD-R, CD -R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

10, 100, 300, 400 Semiconductor device 11 In-phase detection circuit 12 Detection circuit 101 AC output circuit 102 Balun 103, 401 In-phase detection circuit 104, 301 Detection circuit 105, 405 Control circuit 111 Reference voltage generation circuit 112 Detector 113 LPF
114 Amplifier circuit 115, 404 Comparator 201 Capacitor connection circuit 302 Conversion circuit 303 Control circuit 402 Phase comparator 500 Wireless communication system 501 Wireless communication devices C1-C4, C21 Capacitor CS1 Current sources FET1-FET4 Field effect transistors R1-R9 Resistance SW1 , SW31 to SW34 switch VR1, VR2 variable resistance

Claims (13)

An in-phase detection circuit for detecting an AC signal in phase,
And a detection circuit that detects the amplitude level of the even-order harmonics output from the common-mode detection circuit. The detection circuit includes:
A detector for detecting the amplitude level of the even harmonics output from the common-mode detection circuit;
An LPF circuit that suppresses a high-frequency component of an amplitude level signal of an even-order harmonic detected by the detector;
An amplifying circuit for amplifying a signal of an even-order harmonic amplitude level in which a high-frequency component is suppressed in the LPF circuit;
The semiconductor device according to claim 1, further comprising: a comparator that compares a signal having an amplitude level of even harmonics after amplification with a reference voltage. A reference voltage generation circuit for generating a first reference voltage and a second reference voltage;
The detector includes: a first transistor that detects a signal obtained by adding the even-order harmonics and the second reference voltage; and a second transistor that detects the first reference voltage. 2. The semiconductor device according to 2. The LPF circuit includes a resistor and a capacitor connected in parallel between a power supply potential and the first transistor,
The semiconductor device according to claim 3, wherein a resistor is connected between a power supply potential and the second transistor.   The comparator compares the voltage of a signal obtained by detecting a signal obtained by adding the even-order harmonics and the second reference voltage with the voltage of a signal obtained by detecting the first reference voltage. The semiconductor device described. An AC output circuit that amplifies an AC signal by changing a duty ratio and outputs the amplified signal to the common-mode detection circuit;
Control for instructing the AC output circuit of a duty ratio at which the amplitude of the even-order harmonics of the AC signal is a minimum value based on the comparison result of the comparator based on the relationship between the duty ratio of the AC signals and the even-order harmonics A semiconductor device according to claim 2, comprising: a circuit.   The control circuit instructs the AC output circuit to set the midpoint of the two duty ratios at which the two voltages in the comparator are equal to each other as the duty ratio at which the amplitude of the even-order harmonics of the AC signal becomes a minimum value. The semiconductor device according to claim 6. An AC output circuit for changing the duty ratio and outputting an AC signal to the common-mode detection circuit;
Based on a signal detected by the detection circuit, a duty ratio at which the amplitude of the even-order harmonic of the AC signal becomes a minimum value is set in the AC output circuit from the relationship between the duty ratio of the AC signal and the even-order harmonic. The semiconductor device according to claim 1, further comprising a control circuit for instructing. A reference voltage generation circuit for generating a first reference voltage and a second reference voltage;
The LPF circuit includes a first resistor for a signal obtained by adding the even-order harmonics and the second reference voltage, a second resistor for a signal having the first reference voltage, the first resistor, and the second resistor. The semiconductor device according to claim 2, comprising a capacitor connected between the resistors and a capacitor connected between one of the resistors and the ground potential. A reference voltage generation circuit for generating a first reference voltage and a second reference voltage;
3. The semiconductor according to claim 2, wherein the LPF circuit includes a capacitor that forms a capacitance between a signal obtained by adding the even-order harmonics and the second reference voltage and the signal of the first reference voltage. apparatus.   The semiconductor device according to claim 1, further comprising an AD conversion circuit that performs analog-to-digital conversion on a potential of an even-order harmonic signal detected by the detection circuit. An AC output circuit for changing the duty ratio and outputting an AC signal to the common-mode detection circuit;
The semiconductor device according to claim 11, further comprising: a control circuit that determines whether or not to search again for an optimum value of the duty ratio based on a signal that has been analog-digital converted in the AD conversion circuit. A modem that modulates the transmitted data;
A local oscillator that generates a radio frequency signal and converts the modulated transmission data to a radio frequency to obtain a transmission signal;
A semiconductor device comprising: an in-phase detection circuit that detects an AC signal in-phase; and a detection circuit that detects an amplitude level of an even-order harmonic output from the in-phase detection circuit;
An antenna for wireless transmission of the amplified transmission signal;
A wireless communication device comprising: