JP2016058661A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce on-resistance and suppress a decrease in breakdown voltage.SOLUTION: A semiconductor device comprises a JFET region provided in a second n type silicon carbide epitaxial layer 2b on a source side of an n type drift region, where an impurity concentration is higher than that of a first n type silicon carbide epitaxial layer 2a on a drain side of the n type drift region. On a part of the JFET region, sandwiched by p type base regions 4, an n type well region 8 having an impurity concentration higher than that of the second n type silicon carbide epitaxial layer 2b is provided. On a part of the JFET region, sandwiched by ptype base regions 3, an n type high-concentration region 2c having an impurity concentration higher than that of the n type well region 8 is provided. A thickness t2 of the n type high-concentration region 2c is thinner than a thickness t3 of the ptype base region 3. That is, an impurity concentration of a part of the JFET region other than an underside corner part of the ptype base region 3 on the JFET region side is higher than that of the JFET region on the drain side of the n type drift region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  Conventionally, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is known as a switching device using a silicon carbide (SiC) semiconductor. For example, in order to manufacture (manufacture) a vertical MOSFET, first, an impurity concentration higher than that of a semiconductor substrate is provided on the front surface of a semiconductor substrate made of a first conductivity type silicon carbide semiconductor (hereinafter referred to as a silicon carbide substrate). A low first conductivity type silicon carbide semiconductor layer is formed. Next, a general MOS gate (insulating gate made of metal-oxide film-semiconductor) structure and source electrode are formed on the surface side of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side. To do. Thereafter, a drain electrode is formed on the back surface of the silicon carbide substrate, thereby completing a vertical MOSFET.

In such a vertical MOSFET, a high electric field concentrates on the MOS gate side surface of the first conductivity type silicon carbide layer, which is the drift region, during operation. For this reason, on the MOS gate side of the first conductivity type silicon carbide layer, it is possible to withstand a high electric field by making the impurity concentration of the region sandwiched between the base regions immediately below the gate electrode higher than the impurity concentration of the drift region. A JFET (Junction FET) region is formed. However, since the JFET region has a large resistance component, the on-resistance increases, causing an increase in loss during switching. As a device for reducing the on-resistance, the length of the JFET region is 3 μm or less, and the impurity density of the JFET region is equal to or higher than the impurity density of the drift region and is 1 × 10 ¹⁶ / cm ³ or higher. An apparatus has been proposed (see, for example, Patent Document 1 below).

JP 2011-159797 A

  However, when the impurity concentration of the JFET region is increased to reduce the on-resistance as in Patent Document 1, the decrease in breakdown voltage can be suppressed to some extent by making the impurity concentration of the JFET region uniform in the depth direction. However, it is inevitable that the breakdown voltage decreases with increasing impurity concentration in the JFET region.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reduce the on-resistance and suppress a decrease in breakdown voltage in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A first conductive type first semiconductor layer made of a silicon carbide semiconductor having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate made of a silicon carbide semiconductor. A first conductive type second semiconductor layer made of a silicon carbide semiconductor having an impurity concentration higher than that of the first semiconductor layer is provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. . A second conductivity type first semiconductor region is selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side. A second conductivity type second semiconductor region having an impurity concentration lower than that of the first semiconductor region is provided on a surface of the second semiconductor layer opposite to the semiconductor substrate side. A third semiconductor region of the first conductivity type is selectively provided inside the second semiconductor region. A fourth semiconductor region that penetrates through the second semiconductor region and reaches a portion of the second semiconductor layer sandwiched between the first semiconductor regions is provided. A fifth semiconductor region having an impurity concentration higher than that of the second semiconductor layer and the fourth semiconductor region is provided in a portion of the second semiconductor layer sandwiched between the first semiconductor regions. A gate electrode provided via a gate insulating film is provided on the surface of the portion of the second semiconductor region sandwiched between the third semiconductor region and the fourth semiconductor region. The first electrode is electrically connected to the second semiconductor region and the third semiconductor region. The second electrode is provided on the back surface of the semiconductor substrate.

  In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the fifth semiconductor region is thinner than the thickness of the first semiconductor region.

The semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor layer is 1 × 10 ¹⁶ / cm ³ or more.

The semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor layer is less than 4 × 10 ¹⁶ / cm ³ .

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the thickness of the second semiconductor layer is 1 μm or more.

  In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the second semiconductor layer is 4 μm or less.

  In the semiconductor device according to the present invention as set forth in the invention described above, the second semiconductor layer is an epitaxial layer formed by epitaxial growth.

  In the semiconductor device according to the present invention as set forth in the invention described above, the front surface of the semiconductor substrate is inclined at 10 degrees or less with respect to a plane parallel to the (000-1) plane or the (000-1) plane. It is characterized by a flat surface.

  In the semiconductor device according to the present invention, in the above-described invention, the front surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane tilted to 10 degrees or less with respect to the (0001) plane. It is characterized by that.

According to the above-described invention, since the n-type impurity concentration in the JFET region can be made higher than the impurity concentration on the drain side of the n-type drift region, the on-resistance can be reduced. Further, according to the above-described invention, the n-type impurity concentration in the portion sandwiched between adjacent p ⁺ -type base regions in the JFET region is further increased, so that the p ⁺ -type base region where the electric field is most concentrated is obtained. Since the electric field near the lower corner portion (drain side corner portion) on the JFET region side can be relaxed, the on-resistance can be further reduced.

  According to the semiconductor device of the present invention, it is possible to reduce the on-resistance and to suppress the decrease in breakdown voltage.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is a characteristic view which shows the pressure | voltage resistance characteristic and on-resistance characteristic of the silicon carbide semiconductor device concerning an Example. It is a characteristic view which shows the pressure | voltage resistance characteristic and on-resistance characteristic of the silicon carbide semiconductor device concerning an Example.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment)
The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than a silicon (Si) semiconductor (hereinafter referred to as a wide band gap semiconductor). In the embodiment, a configuration of a silicon carbide semiconductor device using, for example, a silicon carbide (SiC) semiconductor as a wide band gap semiconductor will be described by taking a MOSFET (hereinafter referred to as a silicon carbide MOSFET) as an example. FIG. 1 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment includes first and second n-type silicon carbide epitaxial layers (first and second semiconductor layers) on a main surface of an n ⁺ -type silicon carbide substrate (semiconductor substrate) 1. ) 2a and 2b are stacked in this order to form a silicon carbide epitaxial substrate (semiconductor chip).

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N), and constitutes an n ⁺ type drain layer. The main surface (front surface) of n ⁺ -type silicon carbide substrate 1 has, for example, a (000-1) plane or an off angle of about 10 degrees or less in the <11-20> direction (000-1). It may be a surface. First n-type silicon carbide epitaxial layer 2a is an n-type drift region formed by doping, for example, nitrogen with an impurity concentration lower than that of n ⁺ -type silicon carbide substrate 1. Second n-type silicon carbide epitaxial layer 2b is an n-type drift region formed by doping, for example, nitrogen with a higher impurity concentration than first n-type silicon carbide epitaxial layer 2a.

  The reason why the n-type drift region composed of the first and second n-type silicon carbide epitaxial layers 2a and 2b having different impurity concentrations is configured is as follows. By making the impurity concentration of second n-type silicon carbide epitaxial layer 2b higher than the impurity concentration of first n-type silicon carbide epitaxial layer 2a, the impurity concentration on the source side of the n-type drift region is made higher than the impurity concentration on the drain side. can do. This is because the n-type impurity concentration in a region (JFET region) sandwiched between base regions described later in the n-type drift region can be increased, and the on-resistance can be reduced.

  The reason why second n-type silicon carbide epitaxial layer 2b is formed by epitaxial growth is as follows. As will be described later, n-type high concentration region 2c is formed in the JFET region of second n-type silicon carbide epitaxial layer 2b. This is because the n-type high concentration region 2c is formed by ion implantation, and thus the thickness (depth) t2 of the n-type high concentration region 2c is limited and limited to the impurity concentration of the n-type high concentration region 2c. . Therefore, the second n-type silicon carbide epitaxial layer 2b is formed by epitaxial growth, and the JFET region is arranged with high dimensional accuracy. Thereby, the n-type high concentration region 2c can be formed with a predetermined depth with respect to the depth of the JFET region. In addition, when ions are implanted at several MeV, crystallinity is destroyed by impact due to large energy, and the characteristics are affected.

The impurity concentration of second n-type silicon carbide epitaxial layer 2b is preferably about 1 × 10 ¹⁶ / cm ³ or more and less than 4 × 10 ¹⁶ / cm ³ . The reason is as follows. This is because by setting the impurity concentration of the second n-type silicon carbide epitaxial layer 2b to 1 × 10 ¹⁶ / cm ³ or more, complete depletion of the JFET region can be prevented and an increase in on-resistance can be prevented. This is because the lowering of the breakdown voltage can be suppressed as the impurity concentration of the second n-type silicon carbide epitaxial layer 2b is lower than 4 × 10 ¹⁶ / cm ³ .

Thickness t0 of second n-type silicon carbide epitaxial layer 2b is preferably about 1 μm to 4 μm. This is because the on-resistance increases when the thickness t0 of the second n-type silicon carbide epitaxial layer 2b is less than 1 μm, and the breakdown voltage decreases when the thickness is greater than 4 μm. Hereinafter, the silicon carbide epitaxial substrate formed by laminating the n ⁺ type silicon carbide substrate 1 alone or the first and second n type silicon carbide epitaxial layers 2a and 2b in this order on the n ⁺ type silicon carbide substrate 1 will be referred to as a silicon carbide semiconductor substrate. Here, an example will be described in which a silicon carbide epitaxial substrate formed by laminating first and second n-type silicon carbide epitaxial layers 2a and 2b on n ⁺ type silicon carbide substrate 1 is used as a silicon carbide semiconductor substrate.

On the silicon carbide semiconductor substrate, an active region 101 and a pressure-resistant structure portion 102 surrounding the periphery of the active region 101 are provided. The active region 101 is a region through which current flows when in the on state. The breakdown voltage structure portion 102 is a region that relaxes the electric field on the front surface side of the silicon carbide semiconductor substrate and maintains the breakdown voltage. In the active region 101, for example, a planar gate type MOS gate structure (element structure) is provided on the front surface side (the second n-type silicon carbide epitaxial layer 2b side) of the silicon carbide semiconductor substrate. The MOS gate structure includes a p ⁺ type base region (first semiconductor region) 3, a p type base region (second semiconductor region) 4, an n ⁺ type source region (third semiconductor region) 6, a p ⁺ type contact region 7, It consists of a gate insulating film 9 and a gate electrode 10.

Specifically, the surface layer of the second n-type silicon carbide epitaxial layer 2b opposite to the n ⁺ -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate) has a p ⁺ -type base. Region 3 is selectively provided. The p ⁺ type base region 3 is doped with, for example, aluminum (Al). An n-type high concentration region (fifth semiconductor region) 2c is provided in a region (that is, a JFET region) sandwiched between adjacent p ⁺ -type base regions 3 of second n-type silicon carbide epitaxial layer 2b. N-type high concentration region 2c constitutes an n-type drift region together with first and second n-type silicon carbide epitaxial layers 2a and 2b.

The impurity concentration of n type high concentration region 2c is higher than the impurity concentration of second n type silicon carbide epitaxial layer 2b and n type well region (fourth semiconductor region) 8 described later. By providing the n-type high-concentration region 2c, (p-type base region 4 below 3 and the p ⁺ -type base region) base region adjacent of the JFET region sandwiched between, the p ⁺ -type base for most field concentration The n-type impurity concentration in the portion on the region 3 side can be increased. Thereby, the fall of a proof pressure can be suppressed. The thickness (depth from the substrate front surface) t2 of the n-type high concentration region 2c is preferably smaller than the thickness t3 of the p ⁺ -type base region 3 (t2 <t3). The reason is that when the thickness t2 of the n-type high concentration region 2c is made thicker than the thickness t3 of the p ⁺ -type base region 3, the effect of suppressing a decrease in breakdown voltage cannot be obtained.

Specifically, when the thickness t2 of the n-type high concentration region 2c is made larger than the thickness t3 of the p ⁺ -type base region 3, the following problem occurs. The n-type high concentration region 2c is formed by ion implantation as will be described later. Thus, n-type if the thickness t2 of the high concentration region 2c made thicker than the thickness t3 of the p ⁺ -type base region 3, the lateral p ⁺ type base region 3 by diffusion of (direction perpendicular to the depth direction) An n-type high concentration region 2c is formed so as to go around to the drain side. As a result, the lower corner portion (drain side corner portion) of the p ⁺ type base region 3 where the electric field is most concentrated is covered with the n type high concentration region 2c, so that the impurity concentration of the n type high concentration region 2c is covered. As the voltage increases, the withstand voltage decreases rapidly.

A p-type silicon carbide epitaxial layer serving as p-type base region 4 is deposited on the surface of second n-type silicon carbide epitaxial layer 2b opposite to the n ⁺ -type silicon carbide substrate 1 side. The p-type base region 4 extends from the active region 101 to the vicinity of the boundary between the active region 101 and the breakdown voltage structure 102. The impurity concentration of the p-type base region 4 is lower than the impurity concentration of the p ⁺ -type base region 3. For example, the p-type base region 4 is doped with aluminum. An n ⁺ type source region 6 and a p ⁺ type contact region 7 are selectively provided in a portion of the p type base region 4 facing the p ⁺ type base region 3.

The n ⁺ -type source region 6 is arranged near the n-type well region 8 described later in the p-type base region 4. The p ⁺ type contact region 7 is arranged near the center of the p type base region 4 than the n ⁺ type source region 6. The n ⁺ type source region 6 and the p ⁺ type contact region 7 are in contact with each other. The p ⁺ -type contact region 7 may be provided at a depth that penetrates the p-type base region 4 in the depth direction and reaches the p ⁺ -type base region 3. An n-type well region 8 that penetrates the p-type base region 4 in the depth direction and reaches the second n-type silicon carbide epitaxial layer 2b is provided in a portion of the p-type base region 4 that faces the n-type high concentration region 2c. It has been.

That is, the n-type well region 8 is provided in a region sandwiched between adjacent p-type base regions 4 (that is, a JFET region). Therefore, by providing the n-type well region 8, the n-type impurity concentration of the JFET region sandwiched between adjacent base regions (p ⁺ -type base region 3 and p-type base region 4) can be further increased. Further, the on-resistance can be further increased. The width (width in the direction in which the main current flows) w1 of the n-type well region 8 may be wider than, for example, the width w2 of the n-type high concentration region 2c. N type well region 8 forms an n type drift region together with first and second n type silicon carbide epitaxial layers 2a and 2b. The n-type well region 8 may be in contact with the n-type high concentration region 2c.

The impurity concentration of n type well region 8 is higher than the impurity concentration of second n type silicon carbide epitaxial layer 2b and lower than the impurity concentration of n type high concentration region 2c. When the impurity concentration is distributed, the average impurity concentration of the n-type well region 8 may be lower than the maximum value of the impurity concentration of the n-type high concentration region 2c. The reason is as follows. By providing the n-type high concentration region 2c, it is sandwiched between the p ⁺ -type base regions 3 among the JFET regions sandwiched between the adjacent base regions (p ⁺ -type base region 3 and p-type base region 4). The impurity concentration of the portion becomes high. This is because a decrease in breakdown voltage can be suppressed while maintaining the low on-resistance obtained by providing the n-type well region 8.

A gate electrode 10 is provided on the surface of the portion of the p-type base region 4 sandwiched between the n ⁺ -type source region 6 and the n-type well region 8 via a gate insulating film 9. The gate electrode 10 may be provided over the surface of the n-type well region 8 via the gate insulating film 9. FIG. 1 shows one MOS gate structure constituting one unit cell (functional unit of an element) of the active region 101. A plurality of unit cells (not shown) are arranged in parallel so as to be adjacent to this unit cell. It may be arranged. On gate electrode 10, interlayer insulating film 11 is provided on the entire front surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10. In the contact hole that penetrates the interlayer insulating film 11 in the depth direction, the n ⁺ type source region 6 and the p ⁺ type contact region 7 are exposed.

The source electrode (first electrode) 12 is provided in the contact hole, and is in contact with the n ⁺ type source region 6 and the p ⁺ type contact region 7 exposed in the contact hole. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A front electrode pad 13 is provided on the source electrode 12 and the interlayer insulating film 11. The front surface electrode pad 13 is provided on almost the entire active region 101. The end portion of the front electrode pad 13 extends on the interlayer insulating film 11 of the breakdown voltage structure portion 102 and terminates in the vicinity of the boundary between the breakdown voltage structure portion 102 and the active region 101.

In the breakdown voltage structure 102, the first p ⁻ is formed on the surface layer of the second n-type silicon carbide epitaxial layer 2 b opposite to the n ⁺ -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate). A mold region 5a and a second p ^- type region 5b are provided. The first p ⁻ type region 5a and the second p ⁻ type region 5b constitute a double zone JTE (Junction Termination Extension) structure. The double zone JTE structure is a JTE structure having a configuration in which two p-type regions having different impurity concentrations are arranged in parallel so as to contact each other.

Specifically, the first p ⁻ type region 5 a is in contact with the p ⁺ type base region 3 that constitutes the unit cell closest to the breakdown voltage structure 102, and surrounds the active region 101. The 2p ^- type region 5b is a 1p ^- contact with the outer end of the mold region 5a (chip outer peripheral side), the 1p ^- surround type region 5a. That is, the p ⁺ type base region 3, the first p ⁻ type region 5 a, and the second p ⁻ type region 5 b are arranged in parallel from the active region 101 side toward the breakdown voltage structure 102 side. The impurity concentration of the first p ⁻ type region 5 a is lower than the impurity concentration of the p ⁺ type base region 3. The 2p ^- impurity concentration type region 5b is a 1p ^- lower than the impurity concentration type region 5a.

An interlayer insulating film 11 is provided on the first p ⁻ type region 5a and the second p ⁻ type region 5b. The first p ⁻ type region 5 a and the second p ⁻ type region 5 b are electrically insulated from the element structure of the active region 101 by the interlayer insulating film 11. A protective film 14 such as a passivation film made of polyimide, for example, is provided on the interlayer insulating film 11 so as to cover almost the entire breakdown voltage structure 102. The protective film 14 has a function of preventing discharge. The end portion of the protective film 14 extends on the front electrode pad 13 and covers the end portion of the front electrode pad 13.

A back electrode (second electrode) 15 is provided on the surface of n ⁺ type silicon carbide substrate 1 opposite to the n type silicon carbide epitaxial layer 2 side (the back surface of the silicon carbide semiconductor substrate). The back electrode 15 constitutes a drain electrode. A back electrode pad 16 is provided on the surface of the back electrode 15.

Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described by taking as an example the case of creating a MOSFET with a withstand voltage class of 1200 V, for example. FIGS. 2-6 is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment. First, an n ⁺ type silicon carbide substrate (semiconductor wafer) 1 doped with nitrogen at an impurity concentration of about 2 × 10 ¹⁸ / cm ³ is prepared. The main surface of n ⁺ type silicon carbide substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction.

Next, on the (000-1) plane of the n ⁺ -type silicon carbide substrate 1, for example, a first n-type carbonization having a thickness of about 8 μm doped with nitrogen at an impurity concentration of about 8.0 × 10 ¹⁵ / cm ³ is performed. A silicon epitaxial layer 2a is grown. Further, on the surface of the first n-type silicon carbide epitaxial layer 2a, for example, a second n-type silicon carbide epitaxial layer 2b having a thickness of about 2 μm doped with nitrogen at an impurity concentration of about 3.0 × 10 ¹⁶ / cm ³ is formed. Grow. The state up to this point is shown in FIG.

Next, an oxide film (not shown) is deposited (formed) on n-type silicon carbide epitaxial layer 2. Next, a portion of the oxide film corresponding to the formation region of the p ⁺ type base region 3 is removed by photolithography and etching. Next, ion implantation is performed using the remaining portion of the oxide film as a mask to selectively form p ⁺ -type base region 3 on the surface layer of second n-type silicon carbide epitaxial layer 2b. In the ion implantation for forming the p ⁺ -type base region 3, for example, the dopant is aluminum and the dose is set so that the impurity concentration of the p ⁺ -type base region 3 is about 3.0 × 10 ¹⁸ / cm ^3. May be. For example, the width w3 and the thickness t3 of the p ⁺ -type base region 3 may be about 13 μm and about 0.5 μm, respectively. The distance between adjacent p ⁺ -type base regions 3 (the width w2 of the n-type high concentration region 2c formed in a later process) may be about 1.6 μm, for example.

Next, a p-type silicon carbide epitaxial layer to be the p-type base region 4 is grown on the surface of the second n-type silicon carbide epitaxial layer 2b with a thickness t1 of 0.5 μm, for example. At this time, for example, a p-type silicon carbide epitaxial layer doped with aluminum may be grown so that the impurity concentration of the p-type base region 4 is 5.0 × 10 ¹⁵ / cm ³ . Hereinafter, the silicon carbide semiconductor substrate including the p-type silicon carbide epitaxial layer on the silicon carbide epitaxial substrate composed of the n ⁺ type silicon carbide substrate 1 and the first and second n-type silicon carbide epitaxial layers 2a and 2b is used. The state up to here is shown in FIG.

  Next, a resist mask (not shown) that covers active region 101 is formed on the p-type silicon carbide epitaxial layer. Next, etching is performed using this resist mask as a mask, and the p-type silicon carbide epitaxial layer (p-type base region 4) in the pressure-resistant structure 102 is removed at a depth of, for example, about 0.7 μm, and the second n-type silicon carbide epitaxial is removed. Layer 2b is exposed. Then, the resist mask used for etching the second n-type silicon carbide epitaxial layer 2b is removed. The state up to this point is shown in FIG.

Next, first p ⁻ -type region 5a is selectively formed on the surface layer of second n-type silicon carbide epitaxial layer 2b exposed by etching by photolithography and ion implantation. In the ion implantation for forming the first p ⁻ -type region 5a, for example, the dopant may be aluminum and the dose may be 2.0 × 10 ¹³ / cm ² . Next, the second p ⁻ -type region 5b is selectively formed on the surface layer of the second n-type silicon carbide epitaxial layer 2b exposed by etching by photolithography and ion implantation. The 2p ^- ion implantation for forming the mold region 5b is, for example, the dopant is aluminum, the dose may be 1.0 × 10 ¹³ / cm ^2.

  Next, the n-type well region 8 is selectively formed by inverting the conductivity type of the portion of the p-type base region 4 facing the second n-type silicon carbide epitaxial layer 2b by photolithography and ion implantation. At this time, simultaneously with the formation of the n-type well region 8, the n-type high concentration region 2c is formed immediately below the n-type well region 8 (a portion of the second n-type silicon carbide epitaxial layer 2b facing the n-type well region 8). To do. The n-type high concentration region 2c may be formed by ion implantation with higher acceleration energy than ion implantation for forming the n-type well region 8. Specifically, for example, the n-type well region 8 and the n-type high concentration region 2c are formed by controlling the impurity concentration distribution in the depth direction by multiple-stage ion implantation (multi-stage ion implantation) with different acceleration energies. Also good.

More specifically, in the multi-stage ion implantation for forming the n-type well region 8 and the n-type high concentration region 2c, for example, the dopant is nitrogen and the impurity concentration of the n-type well region 8 is 3.0 × 10. ^The dose may be set to be ¹⁶ / cm ³ . In this case, although not particularly limited, for example, nine stages of multi-stage ion implantation may be used, and the acceleration energy and doping concentration of each of the nine stages of ion implantation may be set as follows. The acceleration energy and doping concentration of the first-stage ion implantation are 600 keV and 5.5 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and doping concentration of the second-stage ion implantation are set to 460 keV and 3.7 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and doping concentration of the third-stage ion implantation are set to 360 keV and 2.7 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and the doping concentration of the fourth-stage ion implantation are 300 keV and 2.2 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and the doping concentration of the fifth-stage ion implantation are 240 keV and 2.7 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and doping concentration of the sixth-stage ion implantation are 180 keV and 2.5 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and doping concentration of the seventh-stage ion implantation are 130 keV and 3 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and doping concentration of the eighth stage ion implantation are set to 80 keV and 2.5 × 10 ¹¹ ions / cm ² , respectively. The acceleration energy and the doping concentration of the ninth stage ion implantation are 40 keV and 2 × 10 ¹¹ ions / cm ² , respectively. The order of performing these nine stages of ion implantation can be variously changed. The width w1 and the thickness t1 of the n-type well region 8 may be, for example, 2.0 μm and 0.5 μm, respectively. The width w2 of the n-type high concentration region 2c may be 1.6 μm, for example.

In the above-described nine-stage multi-stage ion implantation example, the impurity concentration distribution increases in the depth direction from the surface of the p-type base region 4 and has an average impurity concentration of 3.5 × 10 ¹⁶ / cm ^3. The n-type region is formed with a thickness (depth) of 0.75 μm from the surface of the p-type base region 4. Therefore, the impurity concentration and the thickness t2 of the n-type high concentration region 2c are 6.5 × 10 ¹⁶ / cm ³ and 0.25 μm, respectively. That is, the portion corresponding to the second n-type silicon carbide epitaxial layer 2b of the n-type region formed by nine-stage multi-stage ion implantation (with a depth of 0.5 μm to 0.75 μm from the surface of the p-type base region 4). (Part) becomes the n-type high concentration region 2c.

Next, an n ⁺ type source region 6 is selectively formed on the surface layer of the p type base region 4 at a portion facing the p ⁺ type base region 3 by photolithography and ion implantation. Next, a p ⁺ -type contact region 7 is selectively formed on the surface layer of the p-type base region 4 at a portion facing the p ⁺ -type base region 3 by photolithography and ion implantation. Next, p ⁺ type base region 3, n ⁺ type source region 6, p ⁺ type contact region 7, n type well region 8, n type high concentration region 2c, first p ⁻ type region 5a and second p ⁻ type region A heat treatment (annealing) for activating 5b is performed. The heat treatment temperature and heat treatment time at this time may be, for example, about 1620 ° C. and about 2 minutes, respectively.

The order of forming the n ⁺ type source region 6, p ⁺ type contact region 7, n type well region 8, n type high concentration region 2c, first p ⁻ type region 5a and second p ⁻ type region 5b is variously changed. Is possible. Further, the ion implantation step for forming the first p ⁻ type region 5a and the second p ⁻ type region 5b may be performed before the p type base region 4 is deposited. In this case, the order of forming the p ⁺ type base region 3, the first p ⁻ type region 5a, and the second p ⁻ type region 5b can be variously changed. Further, the n-type well region 8 and the n-type high concentration region 2c may be formed separately. In this case, before depositing the p-type silicon carbide epitaxial layer to be the p-type base region 4 on the second n-type silicon carbide epitaxial layer 2b, the n-type high concentration region 2c is formed on the surface layer of the second n-type silicon carbide epitaxial layer 2b. It may be formed.

Next, the front side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 9 having a thickness of about 100 nm, for example. This thermal oxidation may be performed, for example, by a heat treatment at a temperature of about 1000 ° C. in an oxygen (O ₂ ) atmosphere. Thereby, the gate insulating film 9 covers each region formed in the surface layer of the p-type base region 4 and the surface layer of the second n-type silicon carbide epitaxial layer 2b exposed at the breakdown voltage structure 102.

Next, a polycrystalline silicon layer doped with, for example, phosphorus (P) is formed on the gate insulating film 9 as the gate electrode 10. Next, this polycrystalline silicon layer is selectively removed by patterning, and a polycrystalline silicon layer is formed on the portion of the p-type base region 4 sandwiched between the n ⁺ -type source region 6 and the n-type well region 8. leave. At this time, a polycrystalline silicon layer may be left over the p-type base region 4 and the n-type well region 8. The polycrystalline silicon layer remaining on the p-type base region 4 and the n-type well region 8 becomes the gate electrode 10.

Next, an interlayer insulating film 11 having a thickness of, for example, about 1 μm is formed (formed) on the entire surface of the base so as to cover the gate electrode 10. The interlayer insulating film 11 may be a silicon oxide (SiO ₂ ) film made of phosphorous glass such as PSG (Phospho Silicate Glass) and BPSG (Boro Phospho Silicate Glass), or a non-doped silicon oxide film (NSG: Non-doped). (Silicate Glass). Alternatively, it may be formed of a plurality of layers of any combination of two or more of PSG, BPSG, and NSG. The state up to here is shown in FIG.

Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed to form contact holes, thereby exposing the n ⁺ -type source region 6 and the p ⁺ -type contact region 7. Next, heat treatment (reflow) for planarizing the interlayer insulating film 11 is performed. Next, the source electrode 12 is formed (formed) on the surface of the interlayer insulating film 11. At this time, the source electrode 12 is buried also in the contact hole, and the n ⁺ type source region 6 and the p ⁺ type contact region 7 are brought into contact with the source electrode 12. Next, the source electrode 12 on the interlayer insulating film 11 is removed, and the source electrode 12 is left inside the contact hole. Further, the source electrode 12 may have a shape larger than the contact hole so as to correspond to the misalignment at the time of patterning, and a part of the source electrode 12 may be left on the interlayer insulating film 11.

Next, a nickel (Ni) film, for example, is formed as the back electrode 15 on the back surface of the n ⁺ type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate). Then, for example, heat treatment is performed at a temperature of 970 ° C. to form an ohmic junction (electrical contact) between the n ⁺ -type silicon carbide substrate 1 and the back electrode 15. Next, a front electrode pad 13 is deposited (formed) on the entire front surface of the silicon carbide semiconductor substrate so as to cover the source electrode 12 and the interlayer insulating film 11 by, for example, sputtering. The thickness of the portion of the front electrode pad 13 on the interlayer insulating film 11 may be 5 μm, for example. The front electrode pad 13 may be formed of, for example, aluminum containing silicon (Al—Si) at a rate of 1%. The state up to this point is shown in FIG.

  Next, the front electrode pad 13 is selectively removed, leaving the front electrode pad 13 on the source electrode 12 and the interlayer insulating film 11 in the active region 101. Next, protective film 14 is formed on the entire front surface of the silicon carbide semiconductor substrate. Next, the protective film 14 is patterned to expose the surface electrode pad 13, and the protective film 14 is covered on the interlayer insulating film 11 of the breakdown voltage structure 102 so as to cover the end of the front electrode pad 13. Leave. Next, for example, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film are sequentially formed on the surface of the back electrode 15 as the back electrode pad 16. Thereafter, the silicon wafer MOSFET shown in FIG. 1 is completed by dicing (cutting) the semiconductor wafer into chips.

(Example)
Next, the breakdown voltage and on-resistance of the semiconductor device according to the example were verified. 7 and 8 are characteristic diagrams showing a breakdown voltage characteristic and an on-resistance characteristic of the silicon carbide semiconductor device according to the example. In FIG. 7, the horizontal axis represents the impurity concentration (nitrogen implantation concentration) of the n-type high concentration region 2c, and the vertical axis represents the breakdown voltage and the on-resistance RonA. The numerical value in the parentheses in FIG. 7 is the thickness of the n-type high concentration region 2c. In FIG. 8, the horizontal axis represents the impurity concentration of the second n-type silicon carbide epitaxial layer 2b, and the vertical axis represents the breakdown voltage and the on-resistance RonA. The numerical value in the parentheses in FIG. 8 is the impurity concentration (nitrogen implantation concentration) of the n-type high concentration region 2c.

First, the configuration of the above-described various conditions (hereinafter referred to as examples) exemplified in the semiconductor device (FIG. 1) according to the above-described embodiment was simulated, and the breakdown voltage and on-resistance were calculated. The simulation structure of the example is designed on the assumption that the n-type well region 8 and the n-type high-concentration region 2c are formed at the same time in order to match the manufacturing method of the semiconductor device according to the above-described embodiment. Specifically, as the simulation conditions of the example, the average impurity concentration and implantation depth of the n-type region formed by multi-stage ion implantation for forming the n-type well region 8 and the n-type high concentration region 2c are 3 respectively. And 5 × 10 ¹⁶ / cm ³ and 0.75 μm. That is, the impurity concentration of the n-type well region 8 is 3.0 × 10 ¹⁶ / cm ³ , and the impurity concentration of the n-type high concentration region 2 c is 6.5 × 10 ¹⁶ / cm ³ .

Conditions other than the n-type high concentration region 2c in the simulation structure of the example are the same as the various conditions exemplified in the method for manufacturing the semiconductor device according to the first embodiment. The simulation results of the example are shown in FIG. 7 shows that the thickness t2 of the n-type high concentration region 2c is 0.25 μm, and the impurity concentration (nitrogen implantation concentration) of the n-type high concentration region 2c is 1.5 × 10 ¹⁶ / cm ³ to 2. The simulation result variously changed in the range of 05 × 10 ¹⁷ / cm ³ is shown (hereinafter referred to as the first sample). The configuration other than the impurity concentration of the n-type high concentration region 2c of the first sample is the same as that of the example. Among the first samples, the simulation results of the example are the results when the thickness t2 of the n-type high concentration region 2c and the impurity concentration are 0.25 μm and 6.5 × 10 ¹⁶ / cm ³ , respectively. In the examples, it was confirmed that the breakdown voltage and the on-resistance were 1367 V and 8.21 mΩcm ² , respectively.

Further, FIG. 7 shows the impurity concentration of the n-type high concentration region 2c when the thickness t2 of the n-type high concentration region 2c is 0.45 μm and 0.65 μm (hereinafter referred to as second and third samples). The results of calculating the withstand voltage and the on-resistance are shown with various changes in the range of 1.5 × 10 ¹⁶ / cm ³ to 2.05 × 10 ¹⁷ / cm ³ . The configurations of the second and third samples other than the thickness t2 of the n-type high concentration region 2c are the same as those of the first sample. From the results shown in FIG. 7, it was confirmed that both the first and second samples showed a gradual decrease in breakdown voltage with increasing impurity concentration in the n-type high concentration region 2c. That is, it is possible to suppress a decrease in breakdown voltage by appropriately adjusting the impurity concentration of the n-type high concentration region 2c. In addition, it was confirmed that the on-resistance can be lowered as the impurity concentration of the n-type high concentration region 2c is increased in both the first to third samples.

On the other hand, in the third sample in which the thickness t2 of the n-type high concentration region 2c exceeds 0.65 μm, it was confirmed that the breakdown voltage sharply decreases as the impurity concentration of the n-type high concentration region 2c increases. (The results when the thickness t2 of the n-type high concentration region 2c is larger than 0.65 μm are not shown). This is because the thickness t2 of the n-type high-concentration region 2c exceeds 0.5 μm, which is the thickness t3 of the p ⁺ -type base region 3, and thus the J ⁺ region side of the p ⁺ -type base region 3 where the electric field is most concentrated. It is presumed that this is because the lower corner portion is also covered with the n-type high concentration region 2c having a higher impurity concentration than the second n-type silicon carbide epitaxial layer 2b. From these results, it can be said that in the present invention, the thickness t2 of the n-type high concentration region 2c is smaller than the thickness t3 of the p ⁺ -type base region 3 and the effect of suppressing the decrease in breakdown voltage is obtained. On the condition that the thickness t2 of the n-type high concentration region 2c is thinner than the thickness t3 of the p ⁺ -type base region 3, the concentration of the n-type high concentration region 2c is less than 1.5 × 10 ¹⁷ / cm ^3. It can be said that there is an effect of suppressing the decrease in the amount.

Next, the thickness t2 of the n-type high concentration region 2c is set to 0.45 μm, and the impurity concentration (nitrogen implantation concentration) of the n-type high concentration region 2c is 1.5 × 10 ¹⁶ / cm ³ and 8.5 × 10, respectively. ^{The structure of 16} / cm ³ (hereinafter referred to as the fourth and fifth samples) was simulated, and the withstand voltage and on-resistance were calculated. In the fourth and fifth samples, the thickness t0 of the second n-type silicon carbide epitaxial layer 2b is 2 μm, and the impurity concentration of the second n-type silicon carbide epitaxial layer 2b is 2 × 10 ¹⁶ / cm ³ to 4 × 10 ¹⁶ / cm. Various changes were made within the range of ³ . The configurations of the fourth and fifth samples other than the n-type high concentration region 2c and the second n-type silicon carbide epitaxial layer 2b are the same as those of the first sample. The simulation results of the fourth and fifth samples are shown in FIG.

As shown in FIG. 8, in both the fourth and fifth samples, as with the first to third samples, it was confirmed that the decrease in the breakdown voltage accompanying the increase of the impurity concentration in the n-type high concentration region 2c was gradual. . In addition, it was confirmed that the on-resistance can be lowered in both the fourth and fifth samples as the impurity concentration in the n-type high concentration region 2c is increased. In addition, it was confirmed that the breakdown voltage becomes the target 1200 V or less when the impurity concentration of the n-type high concentration region 2c is 4 × 10 ¹⁶ / cm ³ . From this result, it can be said that as the impurity concentration of the second n-type silicon carbide epitaxial layer 2b is lower than 4 × 10 ¹⁶ cm / ³ , there is an effect of suppressing a decrease in breakdown voltage.

As described above, according to the embodiment, the n-type well region and the n-type high concentration region are provided in the JFET region sandwiched between the adjacent base regions (p-type base region and p ⁺ -type base region). Thus, the n-type impurity concentration in the JFET region can be made higher than the impurity concentration on the drain side of the n-type drift region. Thereby, the on-resistance can be reduced. Further, by providing the n-type high concentration region is sandwiched between adjacent p ⁺ -type base region portion, of the JFET region, the n-type impurity concentration of sandwiched between adjacent p ⁺ -type base region portions It can be even higher. Thereby, the fall of a proof pressure can be suppressed. Further, according to the embodiment, by providing an n-type high concentration region having a thickness smaller than that of the p ⁺ type base region in a portion sandwiched between adjacent p ⁺ type base regions, the p having the highest electric field concentration is provided. The lower corner portion (drain side corner portion) of the ⁺ type base region on the JFET region side is not covered with the n-type high concentration region. Therefore, the n-type impurity concentration in the region other than the lower corner portion of the p ⁺ -type base region on the JFET region side in the JFET region can be increased. As a result, it is possible to avoid a sudden drop in breakdown voltage due to a high impurity concentration in the n-type high concentration region.

In the present invention, the case where the main surface (front surface) of the n ⁺ type silicon carbide substrate is a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction is described as an example. However, the present invention is not limited to this, and the plane orientation of the main surface of the n ⁺ -type silicon carbide substrate can be variously changed according to the design conditions and the like. For example, the main surface of the n ⁺ -type silicon carbide substrate may be a (0001) plane or a (0001) plane having an off angle of about 10 degrees or less in the <11-20> direction. In the above-described embodiment, the case where a silicon carbide semiconductor is used as the wide band gap semiconductor has been described as an example. However, the present invention is not limited to this, and in other wide band gap semiconductors such as gallium nitride (GaN) and diamond. The same effect can be obtained. In each of the above-described embodiments, the MOSFET is described as an example. However, the present invention is an IGBT (Insulated Gate Bipolar Transistor) having a MOS gate structure on the front surface side of the substrate. It is applicable to MOS type semiconductor devices such as.

  In the present invention, a case where a double-zone JTE structure is provided as the breakdown voltage structure is described as an example. However, a multi-zone JTE structure or a FLR (Field Limiting Ring) structure may be applied to the breakdown voltage structure portion. The multi-zone JTE structure is a structure in which three or more p-type regions having different impurity concentrations are arranged in parallel and in contact with each other in the direction from the active region side to the breakdown voltage structure portion side. The FLR structure is a structure in which a plurality of p-type regions are arranged in parallel at a predetermined interval in the direction from the active region side to the pressure-resistant structure side, and can be applied regardless of the difficulty of manufacturing. In the first embodiment described above, a case where a silicon carbide epitaxial substrate in which a silicon carbide epitaxial layer is deposited on a silicon carbide substrate is described as an example. However, the present invention is not limited to this, and a MOS gate structure, for example, is configured. It is good also as a diffusion area | region which formed all the area | regions to perform inside the silicon carbide bulk substrate. In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is similarly established when the first conductivity type is p-type and the second conductivity type is n-type. .

  As described above, the semiconductor device according to the present invention is useful for a high voltage semiconductor device used for a power conversion device, a power supply device such as various industrial machines and the like.

1 n ⁺ -type silicon carbide substrate 2a second 1n-type silicon carbide epitaxial layer 2b first 2n-type silicon carbide epitaxial layer 2c n-type high-concentration region 3 p ⁺ -type base region 4 p-type base region 5a first 1p ^- -type region 5b the 2p ^{- -} type region 6 n ⁺ -type source region 7 p ⁺ -type contact region 8 n-type well region 9 gate insulating film 10 gate electrode 11 interlayer insulating film 12 source electrode 13 front surface electrode pad 14 protective layer 15 rear surface electrode 16 back-surface electrode Pad 101 Active region 102 Withstand voltage structure

Claims (9)

A first conductivity type semiconductor substrate made of a silicon carbide semiconductor;
A first semiconductor layer of a first conductivity type formed of a silicon carbide semiconductor having a lower impurity concentration than the semiconductor substrate, provided on the front surface of the semiconductor substrate;
A second semiconductor layer of a first conductivity type made of a silicon carbide semiconductor having an impurity concentration higher than that of the first semiconductor layer, provided on a surface opposite to the semiconductor substrate side of the first semiconductor layer;
A first semiconductor region of a second conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the semiconductor substrate;
A second conductivity type second semiconductor region having a lower impurity concentration than the first semiconductor region, provided on a surface of the second semiconductor layer opposite to the semiconductor substrate side;
A third semiconductor region of a first conductivity type selectively provided inside the second semiconductor region;
A fourth semiconductor region passing through the second semiconductor region and reaching a portion of the second semiconductor layer sandwiched between the first semiconductor regions;
A fifth semiconductor region having a higher impurity concentration than the second semiconductor layer and the fourth semiconductor region, provided in a portion of the second semiconductor layer sandwiched between the first semiconductor regions;
A gate electrode provided on a surface of a portion of the second semiconductor region sandwiched between the third semiconductor region and the fourth semiconductor region via a gate insulating film;
A first electrode electrically connected to the second semiconductor region and the third semiconductor region;
A second electrode provided on the back surface of the semiconductor substrate;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a thickness of the fifth semiconductor region is thinner than a thickness of the first semiconductor region. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor layer is 1 × 10 ¹⁶ / cm ³ or more. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor layer is less than 4 × 10 ¹⁶ / cm ³ .   The semiconductor device according to claim 1, wherein a thickness of the second semiconductor layer is 1 μm or more.   The semiconductor device according to claim 1, wherein a thickness of the second semiconductor layer is 4 μm or less.   The semiconductor device according to claim 1, wherein the second semiconductor layer is an epitaxial layer formed by epitaxial growth.   The front surface of the semiconductor substrate is a plane parallel to the (000-1) plane or a plane inclined at 10 degrees or less with respect to the (000-1) plane. The semiconductor device according to any one of the above.   The front surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane inclined at 10 degrees or less with respect to the (0001) plane. A semiconductor device according to 1.

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