JP2016040875A - Semiconductor device and control method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which simplifies measurement of a delay time of a delay element inside a DLL (Delay Locked Loop).SOLUTION: A semiconductor device comprises: an output terminal; a first delay circuit DL1/REP1 which receives a first clock signal PCLK and delays the first clock signal PCLK depending on a delay control signal C_DELAY in a variable manner to generate a second clock signal RCLK; a delay control circuit DLC which holds delay control information relevant to the first delay circuit DL1/REP1 and supplies the delay control signal C_DELAY corresponding to the delay control information to the first delay circuit DL1/REP1; a delay time measurement circuit NV_DET which measures a delay time between the first clock signal PCLK and the second clock signal RCLK and holds the measurement result as delay time information; and an output path which connects the delay control circuit DLC and the delay time measurement circuit NV_DET to an output terminal to transmit the delay control information and the delay time information to the output terminal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a delay element and a control method thereof.

  A large number of delay elements are arranged in the semiconductor device for timing adjustment between signals. For these delay elements, the delay time may change from the design value due to process variations during the manufacture of the semiconductor device. For this reason, it is necessary to measure the timing difference between the signals (internal signals) of the internal circuit of the semiconductor device and the delay time of the delay element.

  As a technique for accurately measuring the timing difference between internal signals of a semiconductor device, for example, Patent Document 1 discloses that a delay time measuring circuit such as a ring oscillator on a chip oscillates with main signals and / or clocks used on the chip A configuration is disclosed in which the timing of main signals can be measured for each chip by stopping, counting the number of oscillations with a counter, and outputting the count result from a data output circuit.

JP 2010-109154 A

  In a semiconductor device having a delay element, there is a demand for a new technique (technology) that can measure the delay time of the delay element by a simpler method.

  According to one aspect of the present invention, an output terminal and a first clock signal that receives a first clock signal, variably delays the first clock signal in response to a delay control signal, and generates a second clock signal. A delay circuit, a delay control circuit that holds delay control information related to the first delay circuit, and supplies the delay control signal corresponding to the delay control information to the first delay circuit; and the first clock signal A delay time measuring circuit for measuring a delay time between the second clock signal and holding a measurement result as delay time information, and connecting the delay control circuit and the delay time measuring circuit to the output terminal, An output path for transmitting control information and the delay time information to the output terminal is provided.

  According to another aspect of the present invention, a delay control circuit that supplies a delay control signal corresponding to the delay control information to the first delay circuit, a first clock signal is received, and the first control signal is received in response to the delay control signal. A first delay circuit that variably delays one clock signal and generates a second clock signal, and a delay time provided in the semiconductor device based on a test control signal In a measurement circuit, a delay time between the first clock signal and the second clock signal is measured and held as delay time information, and the delay control circuit and the delay time measurement circuit are connected to an output circuit. There is provided a method for controlling a semiconductor device, wherein the delay control information and the delay time information are controlled to be output from an output terminal.

  According to the present invention, the measurement of the delay time of the delay element inside the semiconductor device is simplified.

It is a figure which illustrates the whole structure of the semiconductor device of the 1st Embodiment of this invention. It is a figure which illustrates the structure of the DLL circuit of the 1st Embodiment of this invention. It is a figure which illustrates the structure of the delay circuit of the DLL circuit of the 1st Embodiment of this invention. (A) thru | or (C) is a figure which illustrates the structure of the delay circuit of the 1st Embodiment of this invention. (A) is a figure which illustrates the structure of the delay time measuring circuit of the DLL circuit of the 1st Embodiment of this invention, (B) is a timing diagram. It is a figure which illustrates the structure of the data input / output part of the 1st Embodiment of this invention. It is a figure which illustrates the structure of the test system of the 1st Embodiment of this invention. It is a flowchart for demonstrating the test procedure of the 1st Embodiment of this invention. It is a figure which illustrates the structure of the DLL circuit of the modification of the 1st Embodiment of this invention. It is a figure which illustrates the structure of the DLL circuit of the 2nd Embodiment of this invention. It is a flowchart for demonstrating the test procedure of the 2nd Embodiment of this invention. It is a figure which illustrates the whole structure of the semiconductor device of the 3rd Embodiment of this invention. It is a figure which illustrates the structure of the DLL circuit of the 3rd Embodiment of this invention. It is a figure which illustrates the structure of the data input / output part of the 3rd Embodiment of this invention. It is a figure which illustrates the structure of the DLL circuit of the 4th Embodiment of this invention. It is a figure which illustrates the structure of the delay time measurement circuit of the DLL circuit of the 4th Embodiment of this invention. FIG. 14 is a timing diagram illustrating the operation of the delay time measurement circuit of the DLL circuit according to the fourth embodiment of the invention.

  First, the basic concept of the present invention will be described, followed by embodiments.

According to the semiconductor device of the present invention, the phase adjustment circuit includes a DLL (Delay Locked Loop) circuit,
-Number information of delay elements used in the variable delay circuit in the delay circuit of the DLL circuit,
A delay time (delay time difference information) between the clock signal before delay (first clock signal) and the clock signal after delay (second clock signal) input to the delay circuit when the DLL circuit is locked Is characterized in that it can be output from the output terminal of the semiconductor device to the outside of the semiconductor device.

  The number information (delay control information) of the delay elements used in the variable delay circuit of the DLL circuit is held and output as the count value (first count value) of the first counter that controls the variable delay circuit of the DLL circuit. The On the other hand, the delay time information is a count of a second counter that counts the number of clocks between the clock signal before the delay (first clock signal) and the corresponding edge of the clock signal after the delay (second clock signal). It is held and output as a value (second count value). The count value of the second counter corresponds to information indicating at which edge of the first clock signal the second clock signal is locked by the delay circuit.

  According to the present invention, the delay control information and the delay time information are measured and output using the frequency of the external clock signal supplied to the semiconductor device to be tested as the first frequency, and then the frequency of the external clock signal is set to the second frequency. The delay control information and the delay time information may be measured and output after changing to (Embodiment 1). Alternatively, without changing the frequency of the external clock signal supplied to the semiconductor device to be tested, before changing (shifting) the edge of the clock signal to be locked and after changing (shifting) the edge of the clock signal to be locked The delay control information and the delay time information may be measured and output under different conditions (second embodiment).

  Then, from the delay control information and the delay time information output from the output terminal of the semiconductor device to be tested, the absolute value of the delay time per delay element of the DLL circuit can be obtained using simple calculation. . Hereinafter, some embodiments will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram for explaining the overall configuration of the semiconductor device according to the first embodiment of the present invention. In the present embodiment, the semiconductor device is composed of a DRAM (Dynamic Random Access Memory). Referring to FIG. 1, a semiconductor device 1 is composed of, for example, a clock synchronous DRAM that performs input / output from a data terminal DQ in synchronization with a clock signal, and includes a command input circuit (Input Buffer1: IB1) 11, Input Buffer2: IB2) 12, clock input circuit (Input Buffer3: IB3) 13, operation control unit (Operation Control Unit: OCU) 14, test control unit (Test Control Unit: TCU) 15, row decoder (Row Decoder: XDEC) 16, a column decoder (YDEC) 17, a memory array (MA) 18, a data input / output unit (I / O Unit) 19, and a DLL (Delay Locked Loop) circuit 20. Hereinafter, each part will be outlined.

  The command input circuit 11 generates an internal command signal PCMD in response to the external command signal CMD.

  Address input circuit 12 generates internal address signal PADD in response to external address signal ADD.

  The clock input circuit 13 generates an internal clock signal PCLK in response to the external clock signal ExCLK (third clock signal).

  The operation control unit 14 controls the operation of the memory array 18 according to the internal command signal PCMD, the internal address signal PADD, and the internal clock signal PCLK, the column control signal CCTL, and the input / output Various control signals of the control signal I / O CTL are generated and output.

  The row control signal RCTL includes, for example, a row address and a sense amplifier drive signal. The column control signal CCTL includes, for example, a column address and a Y switch drive timing signal. The input / output control signal I / O CTL includes, for example, various timing signals related to data transfer between the memory array (MA) 18 and the data input / output unit 19. The I / O CTL includes an output enable signal OE (not shown) that controls the output of an output buffer (not shown) of the data input / output unit 19.

  Further, the operation control unit 14 supplies the test signal TEST to the test control unit 15 when the internal command signal PCMD indicates a test operation.

  When the test signal TEST from the operation control unit 14 is activated, the test control unit 15 generates various internal test signals according to the test code supplied as the internal address signal PADD.

  The internal test signals include, for example, a DLL test enable signal TDEN for starting the test operation of the DLL circuit 20, a test DLL reset signal TDRST for resetting the DLL circuit 20 during the test operation, output mode selection signals TOMODE1, TOMODE2, and data input / output A DLL information read signal DLL_R supplied to the unit 19 is included.

  The memory array (MA) 18 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. In FIG. 1, one word line WL, one bit line BL, and one memory cell MC are shown for simplicity.

  A row decoder circuit (XDEC) 16 is disposed at the end of the word line WL of the memory array 18, and a column decoder circuit (YDEC) 17 is disposed at the end of the bit line BL. The row decoder circuit (XDEC) 16 selectively activates a desired word line WL specified by a row address from the plurality of word lines WL. The column decoder circuit (YDEC) 17 makes a Y switch (column selection switch) (not shown) of a column designated by a column address conductive, and selectively selects the bit line BL of the column from the plurality of bit lines BL. Connect to the data input / output unit 19.

  The data input / output unit 19 is disposed between the memory array 18 and the data terminal DQ. The data input / output unit 19 operates according to the input / output control signal I / O CTL supplied from the operation control unit 14 and the output clock signal LCLK supplied from the DLL circuit 20. During the read operation, the data input / output unit 19 receives data DATA (read data) read from the memory array 18 and outputs the data DATA to the outside via the data terminal DQ. During the write operation, the data input / output unit 19 receives data DATA (write data) supplied from the outside via the data terminal DQ and supplies it to the memory array 18.

  Further, the data input / output unit 19 outputs the DLL state information DLL_INF supplied from the DLL circuit 20 to the outside through the data terminal DQ during the test operation. Details of the configuration of the data input / output unit 19 will be described later.

  The DLL circuit 20 delays the internal clock signal PCLK and generates an output clock signal LCLK synchronized with the external clock signal ExCLK. Further, the DLL circuit 20 outputs DLL state information DLL_INF, which is information related to the delay of the DLL circuit 20, during the test operation.

The DLL status information DLL_INF is
Information on the number of delay elements of the variable delay circuit in the delay circuit of the DLL circuit 20,
・ Delay time difference information between the clock signal before delay and the clock signal after delay,
Including both.

  Here, the clock signal before the delay is the internal clock signal PCLK input to the delay circuit (not shown) of the DLL circuit 20 of FIG. 1, and the delayed clock signal is the delay circuit (not shown) of the DLL circuit 20. ) Output from the clock signal (RCLK in FIG. 2 to be described later).

  FIG. 2 is a diagram illustrating a detailed configuration of the DLL circuit 20 of FIG. Referring to FIG. 2, a DLL circuit 20 includes a variable delay circuit (Delay Line 1: DL1) 21, a delay circuit counter (Delay Line Counter: DLC) (first delay control circuit) 22, and a DLL control circuit (DLL). CTL) 23, a phase detector (PD) 24, a register (Register: REG) 25, a first replica circuit (replica1: REP1) 26, a delay time measuring circuit (NV_DET) 27, 1 selection circuit (multiplexer: MUX1) 28. Hereinafter, each part will be described. Here, the variable delay circuit 21 and the first replica circuit 26 constitute a first delay circuit.

  The variable delay circuit 21 receives the internal clock signal PCLK and outputs a signal obtained by delaying the internal clock signal PCLK as an output clock signal LCLK. The variable delay circuit 21 varies the delay time (the delay time between the output clock signal LCLK and the internal clock signal PCLK) according to the delay control signal C_DELAY supplied from the delay circuit counter 22.

  In the present embodiment, as shown in FIG. 3, the variable delay circuit 21 includes a coarse adjustment delay circuit (Coarse Delay Line 1: CDL1) 211 that performs coarse adjustment of delay, and a fine adjustment delay circuit that performs fine adjustment of delay ( Fine Delay Line 1: FDL1) 212. The coarse adjustment delay circuit 211 is supplied with the delay control signal C_CDELAY from the delay circuit counter 22, and the fine adjustment delay circuit 212 is supplied with the delay control signal C_FDELAY from the delay circuit counter 22. In the present invention, however, the DLL variable delay circuit is not limited to the configuration including the coarse adjustment delay circuit and the fine adjustment delay circuit.

  As shown in FIG. 4A, the coarse adjustment delay circuit 211 includes a plurality of coarse adjustment delay elements (Coarse Delay Elements: CDE) 213-1 to 213-m (where m is a predetermined positive integer). )including. As shown in FIG. 4B, the fine adjustment delay circuit 212 includes a plurality of fine adjustment delay elements (FDE) 214-1 to 214-8.

  Each of the coarse adjustment delay element 213 and the fine adjustment delay element 214 has a configuration in which, for example, inverter circuits are connected in two stages in cascade. The inverter circuit may be composed of a CMOS (Complementary MOS) inverter. It is assumed that the transistor included in the inverter circuit constituting the coarse adjustment delay element 213 has a larger current driving capability than the transistor included in the inverter constituting the fine adjustment delay element 214.

  However, the configurations of the coarse adjustment delay element 213 and the fine adjustment delay element 214 are not limited to the two-stage configuration of the inverter circuit. For example, the inverter circuit may be composed of one stage. Alternatively, instead of the inverter circuit, a NAND circuit (for example, one input terminal of a two-input NAND circuit is used as a power supply potential and a signal is input to the other input terminal) may be used. Similarly, the difference between the delay time of the coarse adjustment delay element 213 and the delay time of the fine adjustment delay element 214 is not limited to the transistor size. For example, the delay time may be different by making the power supply voltages of the coarse adjustment delay element (CDE) 213 and the fine adjustment delay element (FDE) 214 different from each other. Alternatively, the delay time may be different by changing the threshold voltage Vth of the corresponding MOS transistor between the coarse adjustment delay element 213 and the fine adjustment delay element 214.

  When the coarse adjustment delay element 213 and the fine adjustment delay element 214 transmit signals differentially, the inverter circuit may be configured by a differential circuit (differential inverter). In this case, the delay time of the coarse adjustment delay element 213 and the fine adjustment delay element 214 may be differentiated by making the tail currents of the differential pair constituting the differential amplifier different.

  Here, the delay times of the plurality of coarse adjustment delay elements 213-1 to 213-m are substantially equal to each other. The delay times of the plurality of fine adjustment delay elements 214-1 to 214-8 are also substantially equal to each other. It is assumed that the delay time of one coarse adjustment delay element 213 is larger than the delay time of one fine adjustment delay element 214 and is n times. However, n is a predetermined number determined in advance, and is not limited to an integer.

  The coarse adjustment delay circuit 211 changes the utilization radix of the coarse adjustment delay element (CDE) 213 in the coarse adjustment delay circuit (CDL1) in accordance with the coarse adjustment control signal C_CDELAY (changes the number of stages of cascaded CDEs). ) To change its own delay time. Similarly, the fine adjustment delay circuit 212 also performs fine adjustment of the delay time according to the fine adjustment control signal C_FDELAY.

  There are various types of fine adjustment delay circuit 212. Although not particularly limited, the example shown in FIG. 4B illustrates a fine adjustment delay element (FDE) in which 1/8 of the coarse adjustment delay element (CDE) is used as a delay time as one unit. . The fine adjustment delay element (FDE) 214 in the fine adjustment delay circuit 212 corresponds to an increase of one value of the coarse adjustment delay element (CDE) 213 in the coarse adjustment delay circuit 211 when the maximum eight delays are used. Return to the 0 unit usage state. For example, when the utilization base of the coarse adjustment delay element (CDE) 213 in the coarse adjustment delay circuit 211 is X (X is a non-negative integer), the utilization base of the fine adjustment delay element (FDE) 214 in the fine adjustment delay circuit 212 is 8. Then, carry (carry) occurs, the utilization base of the coarse adjustment delay element (CDE) 213 becomes X + 1, and the utilization base of the fine adjustment delay element (FDE) 214 becomes zero.

That is, regarding the delay time,
1 x CDE = 8 x FDE
Thus, the FDE mounting radix is suppressed. Each of the above operations is performed by the delay circuit counter 22.

  The delay circuit counter 22 holds the utilization radix of the delay elements (CDE, FDE) of the coarse adjustment delay circuit (CDL1) 211 and the fine adjustment delay circuit (FDL) 212. As shown in FIG. 4A, the lower bits of the delay circuit counter 22 are assigned to the FDL counter, and the carry (carry) of the FDL counter is reflected in the least significant bit (Least Significant Bit: LSB) of the count value of the CDL counter. I am letting.

  The “coarse adjustment delay control signal C_CDELAY” and the “fine adjustment delay control signal C_FDELAY” may be simply referred to as “delay control signal C_DELAY”. For example, in FIG. 2 and the like, the signal C_DELAY from the delay circuit counter 22 includes a coarse adjustment delay control signal C_CDELAY and a fine adjustment delay control signal C_FDELAY.

  FIG. 4C is a diagram for explaining the outline of the configuration of the coarse adjustment delay element (CDE) 213 in FIG. The coarse adjustment delay element (CDE) 213 selects a unit delay element 215 (for example, two stages of inverters as described above) that delays the input signal, and selects one bit corresponding to the delay control signal C_CDELAY from the delay circuit counter 22. When the selection control signal is “0”, the input signal is selected and output. When the selection control signal is “1”, the signal delayed by the unit delay element 215 is selected and output. To do. The fine adjustment delay element (FDE) 214 is different from the delay circuit counter 22 in that the corresponding delay bit of the delay control signal C_FDELAY is input as a selection control signal and the delay amount of the unit delay element 215 is different. It is good also as the same structure. The variable delay circuit 21 configured as shown in FIG. 3 and FIG. 4 is configured to select the use radix (number) of the coarse adjustment delay element (CDE) 213 by the delay control signal C_CDELAY from the delay circuit counter 22. Is provided with a selection circuit that receives the output signal of the coarse adjustment delay element (CDE) 213 at each stage in the coarse adjustment delay circuit (CDL1) 211 of FIG. 4A as an input. Alternatively, one output signal of the coarse adjustment delay element (CDE) 213 corresponding to the value of the delay control signal C_CDELAY may be selected and output. The same applies to the fine adjustment delay circuit 212.

  Referring to FIG. 2 again, the delay control signal C_DELAY output from the delay circuit counter 22 is supplied to the variable delay circuit (DL1) 21 as described above, and further, the delay time measurement circuit (NV_DET) 27 And the register (REG) 25 is also supplied.

  The delay circuit counter 22 increases or decreases its count value according to the delay count clock signal DC_CLK supplied from the DLL control circuit 23. When the up / down signal UP / DWN supplied from the DLL control circuit 23 indicates a count up, the delay circuit counter 22 counts up its own count value by one in response to the rising of the delay count clock signal DC_CLK ( Increment), when the up / down signal UP / DWN indicates a countdown, the count value thereof is counted down (decremented) by one in response to the rising of the delay count clock signal DC_CLK.

  The first replica circuit (REP1) 26 reproduces the delay time of the data input / output unit 19 shown in FIG. The first replica circuit 26 simulates the transmission path from the DLL circuit 20 of FIG. 1 to the output buffer (not shown) of the data input / output unit 19 and the output buffer (not shown). The output clock signal LCLK of (DL1) 21 is delayed by the delay time of the output buffer of the data input / output unit 19 and output as a replica clock signal RCLK. Here, the timing of the replica clock signal RCLK is substantially equal to the timing at which data DATA (read data) is output from the output terminal DQ during the read operation.

  The phase comparator (PD) 24 compares the phase of the external clock signal ExCLK with the phase of the replica clock signal RCLK, and outputs the comparison result to the DLL control circuit 23 as the phase comparison result signal PCR.

  The DLL control circuit 23 generates various signals that control the operation of the DLL circuit 20. The DLL control circuit 23 is activated according to a DLL test enable signal TDEN supplied from the test control unit 15 during a test operation. The DLL control circuit 23 resets the setting of each circuit in the DLL circuit 20 to the initial state according to the DLL reset signal TDRST supplied from the test control unit 15 during the test operation.

  The DLL control circuit 23 changes the logic level of the selection signal SEL according to the output mode selection signals TOMODE 1 and 2 supplied from the test control unit 15 during the test operation. The DLL control circuit 23 performs a desired operation according to various control signals (not shown) even during a normal operation other than the test operation.

  The DLL control circuit 23 generates a delayed count clock signal DC_CLK according to the internal clock signal PCLK.

  The DLL control circuit 23 generates an up / down signal UP / DWN according to the phase comparison result signal PCR (in accordance with the phase advance or phase delay).

  Furthermore, the DLL control circuit 23 generates a lock signal LOCK according to the phase comparison result signal PCR. Specifically, when the phase comparison result signal PCR indicates a phase mismatch, the lock signal is maintained at a low level of the inactive level, and when the phase comparison result signal PCR indicates a phase match, for example, When the high level and the low level are repeated, the lock signal LOCK is changed to the active high level. That is, the lock signal LOCK is a signal indicating that the DLL circuit 20 has completed the delay adjustment operation.

  The register (REG) 25 holds both the delay control signal C_DELAY supplied from the delay circuit counter (DLC) 22 and the delay time information C_NVAL supplied from the delay time measurement circuit (NV_DET) 27, and the delay control signal C_DELAY And delay time information C_NVAL is output as a register output signal REG_OUT. Preferably, the register 25 serially outputs the delay control signal C_DELAY and the delay time information. The register 25 receives, for example, the delay control signal C_DELAY and the delay time information C_NVAL in parallel bits, stores and holds them, and outputs them from the most significant bit (MSB) or the least significant bit (LSB) side at the time of output. Output serially in order.

  The first selection circuit (MUX1) 28 outputs either the lock signal LOCK or the register output signal REG_OUT as DLL state information DLL_INF in accordance with the logic level of the selection control signal SEL from the DLL control circuit 23.

  The delay time measurement circuit (NV_DET) 27 receives the lock signal LOCK and the delay control signal C_DELAY, and measures the propagation delay time of the internal clock signal PCLK and the replica clock RCLK. Specifically, the delay time measurement circuit 27 counts how many periods of the internal clock signal PCLK the delay time between the internal clock signal PCLK and the replica clock signal RCLK, and outputs the count value as C_NVAL. .

  FIG. 5A is a diagram illustrating a configuration of the delay time measurement circuit (NV_DET) 27 in FIG. FIG. 5B is a timing chart schematically showing an operation example of the delay time measurement circuit 27. FIG. 5B schematically shows the voltage waveforms of PCLK, LOCK, MSK1, MSK2, and NC_CLK in FIG. 5A and the transition of the count value C_NVAL.

  Referring to FIG. 5A, the delay time measuring circuit 27 includes a flip-flop 271, a second variable delay circuit (DL2) 272, a second replica circuit (REP2) 273, an AND circuit (3-input AND circuit). ) 275 and a time difference counting circuit (NVC) 276.

  The flip-flop 271 captures the value of the lock signal LOCK input to the data terminal D in response to the rising edge of the internal clock signal PCLK, and outputs the captured lock signal from the output terminal Q as the mask signal MSK1.

  The second variable delay circuit (DL2) 272 has substantially the same configuration as the variable delay circuit (DL1) 21 described with reference to FIGS. The second variable delay circuit 272 delays the mask signal MSK1 from the flip-flop 271 by a delay time defined by the delay control signal C_DELAY supplied from the delay circuit counter (DLC) 22.

  The second replica circuit (REP2) 273 has substantially the same configuration as the first replica circuit (REP1) 26 of FIG. The second replica circuit 273 further delays the mask signal MSK1 output from the second variable delay circuit 272.

  The inverter 274 receives the mask signal MSK1 output from the second replica circuit 273, and outputs a signal obtained by inverting the mask signal MSK1 as the mask signal MSK2.

  AND circuit 275 receives mask signals MSK1, MSK2 and internal clock signal PCLK as inputs. The AND circuit 275 supplies the internal clock signal PCLK to the time difference count circuit (NVC) 276 as the time difference count clock signal NC_CLK only during a period when both the mask signals MSK1 and MSK2 are at a high level. The AND circuit 275 sets the time difference count clock signal NC_CLK to a low level (stops the output of the time difference count clock signal NC_CLK) when at least one of the mask signals MSK1 and MSK2 is at a low level.

  The time difference count circuit (NVC) 276 counts up its count value in accordance with, for example, the rising edge of the time difference count clock signal NC_CLK. The time difference count circuit (NVC) 276 is constituted by a known ripple counter (asynchronous counter), for example. However, it goes without saying that the time difference count circuit (NVC) 276 may be composed of a synchronous counter. The time difference count circuit (NVC) 276 outputs its count value as delay time information C_NVAL.

  As schematically shown in the timing waveform diagram of FIG. 5B, when the lock signal LOCK has a low level, the mask signal MSK1 is at a low level, and the time difference count clock signal NC_CLK is inactivated.

  When the lock signal LOCK changes to high level and the flip-flop 271 sets the mask signal MSK1 to high level, the AND circuit 275 passes the input internal clock signal PCLK and outputs it as the time difference count clock signal NC_CLK, and the time difference count circuit 276. The counting operation of the time difference count clock signal NC_CLK starts at.

  After that, when the total delay time of the variable delay circuit 272 and the replica circuit 273 elapses after the mask signal MSK1 transits to the high level, the mask signal MSK2 transits to the low level, and the output of the AND circuit 275 becomes the low level. The time difference count clock signal NC_CLK is deactivated (fixed to a low level), and the count operation in the time difference count circuit 276 is stopped.

  Accordingly, C_NVAL, which is the count value of the time difference count circuit 276 at the end of the count operation, represents how many clocks of the internal clock signal PCLK the total delay time of the variable delay circuit 272 and the replica circuit 273 is. In the example of FIG. 5B, the delay time information C_NVAL is “0110” (decimal display 6) in 4-bit binary display.

  As described above, the variable delay circuit 272 and the replica circuit 273 have substantially the same configurations as the variable delay circuit 21 and the replica circuit 26 of FIG.

  Therefore, the total delay time of the variable delay circuit 272 and the replica circuit 273 is substantially equal to the delay time difference between the internal clock signal PCLK and the replica clock signal RCLK.

  FIG. 6 is a diagram illustrating a configuration of the data input / output unit 19 of FIG. Referring to FIG. 6, the data input / output unit 19 outputs, as output signals, data input / output that outputs data from the memory array (18 in FIG. 1) and DLL state information supplied from the DLL circuit (20 in FIG. 2). A circuit 191 and a data input / output circuit 192 that outputs only data from the memory array 18 as output signals are included. The data input / output circuits 192 are arranged in parallel by the number obtained by subtracting 1 from the number of data terminals DQ. Both the data input / output circuit 191 and the data input / output circuit 192 input data to the memory array 18 in the same manner. That is, data from input buffer circuits 195-1 and 195-2 that receive signals from two data input / output terminals DQ are input to data control circuits (Data CTL) 193-1 and 193-2, respectively. It is transferred to the memory array 18. When data is input from the data terminal DQ, the output enable signal OE is set in an inactive state, and the output buffers (tri-state buffers) 194-1 and 194-2 are in an output disabled state (output is high impedance ( Hi-Z) state).

  The data input / output circuit 191 includes a selection circuit (MUX) 196. The selection circuit 196 is one of data DATA (read data) from the memory array 18 supplied via the data control circuit (Data CTL) 193-1 and DLL state information DLL_INF supplied from the DLL circuit 20. Is selected based on the DLL information read signal DLL_R from the test control unit (15 in FIG. 1) and supplied to the output buffer 194-1 set to the output enable state by the output enable signal OE in the active state. That is, when the DLL information read signal DLL_R is at a high level, the selection circuit 196 selects the DLL state information DLL_INF and supplies it to the output buffer 194-1, and the DLL state information DLL_INF is serially output from the data terminal DQ. . On the other hand, when the DLL information read signal DLL_R is at a low level, the selection circuit 196 selects the data DATA (read data) from the memory array 18 and supplies the data DATA to the output buffer 194-1, and the data DATA ( Read data) is output serially.

  The data input / output circuit 191 and the data input / output circuit 192 have substantially the same configuration except that the selection circuit 196 is included. That is, the data control circuit 193, the output buffer 194, and the input buffer 195 are included. The data control circuit 193 operates in accordance with the input / output control signal I / O CTL from the operation control unit 14 in FIG. 1 and the output clock signal LCLK from the DLL circuit 20. Note that the data input / output circuit 191 is not limited to the configuration connected to the end (for example, the least significant bit DQ0) of the plurality of data terminals DQ, and may be connected to any data terminal DQ. Of course.

  FIG. 7 is a diagram schematically illustrating the configuration of the test system in the present embodiment. The semiconductor device (semiconductor memory) 1 is the semiconductor device (DRAM) 1 described with reference to FIGS.

  The test apparatus 2 includes a control unit 202 including a CPU for executing a program, a holding unit 203 including a memory for holding a program and test results, an input buffer 204 for connection to the semiconductor device 1 to be tested, A test processing device 201 having an interface unit 206 for connection to the output buffer 205 and the peripheral device 207, a monitor 208, an external storage device 209, and a peripheral device 207 such as a keyboard 210 are included. Note that the test apparatus 2 may use an automatic test apparatus such as a memory tester. In this case, the output buffer 205 is connected to an external terminal of the semiconductor device 1 and represents a pin electronic driver that applies a test pattern to the external terminal, and the input buffer 204 is connected to an external terminal of the semiconductor device 1, It represents a pin etronics comparator that compares an output signal from the external terminal with an expected value pattern. The control unit 202 includes a pattern generator that generates a pattern sequence to be supplied to a device under test (DUT), a timing generator that sets an edge of a signal to be supplied to the device under test, and the like. It is good also as a structure. The holding unit 203 may be configured to include a pattern memory that holds a test pattern.

  The test apparatus 2 executes processing corresponding to the test program stored in the holding unit 203 by the control unit 202 and supplies the test command TCMD, the test code TCODE, and the test clock signal TCLK to the semiconductor device 1 that is a device under test. To do.

  The semiconductor device 1 receives the test command TCMD, the test code TCODE, and the test clock signal TCLK from the test device 2 as a command signal CMD, an address signal ADD, and an external clock signal ExCLK, respectively, at corresponding terminals.

  In addition, the test apparatus 2 holds the DLL state signal DLL_INF read from the semiconductor memory 1 and performs an operation based on the description below on the DLL state signal DLL_INF. The delay times of the fine adjustment delay element (FDE) 214 and the coarse adjustment delay element (CDE) 213 are calculated, and the calculation results are held in the holding unit 203 and displayed on the monitor 208. This series of calculations is also held in the holding unit 203 as a program.

  FIG. 8 is a flowchart for explaining a test procedure by the test system of the present embodiment described with reference to FIG. The test procedure in this embodiment will be described with reference to FIG. 8 and FIGS.

  When the semiconductor device 1 is in a test state, that is, in a state where the test signal TEST in FIG. 1 is activated and the test control unit 15 is activated, the following flow is executed. At this time, the test apparatus 2 issues a test clock signal TCLK having a first period (tCK = 1500 ps (pico second)). The test clock signal TCLK is supplied as the external clock signal ExCLK of the semiconductor device 1, and the internal clock signal PCLK has a first period tCK (= 1500 ps).

  The test apparatus 2 issues a test code TCODE1 indicating test DLL enable (step S1). In response to this, in the semiconductor device 1, the test control unit 15 outputs the DLL test enable signal TDEN, and the DLL circuit 20 is activated. Further, the test control unit 15 of the semiconductor device 1 activates the DLL information read signal DLL_R.

  The test apparatus 2 issues a test code TCODE2 indicating a test DLL reset as a test command (step S2). In response to this, the test control unit 15 in the semiconductor device 1 outputs a DLL reset signal TDRST to reset the DLL circuit 20.

  The test apparatus 2 issues a test code TCODE3 indicating the output of the lock signal LOCK (step S3). In response to this, in the semiconductor device 1, the test control unit 15 outputs the output mode selection signal TOMODE1, and the DLL control circuit 23 sets the selection signal SEL to high level. As a result, in the DLL circuit 20 of the semiconductor device 1, the selection circuit 28 selectively outputs the lock signal LOCK and outputs it as DLL state information DLL_INF.

  After detecting that the lock signal LOCK has changed from the low level to the high level (step S4), the test apparatus 2 performs the following processing.

  The test apparatus 2 issues a test code TCODE4 indicating the output of the lock signal LOCK (step S5).

  In response to this, in the semiconductor device 1, the test control unit 15 outputs the output mode selection signal TOMODE2, and the DLL control circuit 23 sets the selection signal SEL to low level. As a result, in the DLL circuit 20 of the semiconductor device 1, the selection circuit 28 selects and outputs the register output REG_OUT and outputs it as the first DLL state information DLL_INF.

The test apparatus 2 uses the first DLL state information DLL_INF as
A first delay control signal (delay circuit counter (DLC) 22 count values: C_FDELAY, C_CDELAY), and
First delay time information (count value of time difference count circuit (NVC) 276: C_NVAL is received (step S6).

  The test apparatus 2 stores and holds the first DLL state information received from the semiconductor device 1 in the holding unit 203 (step S7).

Here, as the first delay control signal stored and held in the holding unit 203 of the test apparatus 2,
The coarse adjustment control signal C_CDELAY has a count value of 1,
Fine adjustment control signal C_FDELAY has a count value of 6,
As the first delay time information,
C_NVAL of the time difference count circuit (NVC) 276 is a count value: 3,
Is shown.

  Next, the test apparatus 2 switches the cycle of the test clock ExTCLK from the first cycle to the second cycle (tCK = 1000 ps) (step S8).

  Then, steps S9 to S13, which are operations corresponding to the steps S1 to S7, are executed in the second period (tCK = 1000 ps).

As a result, the test apparatus 2 uses the second DLL state information DLL_INF as
A second delay control signal (counter values C_FDELAY and C_CDELAY of the delay circuit counter 22), and
The second delay time information (count value C_NVAL of the time difference count circuit 276) is received (step S14).

  The test apparatus 2 stores and holds the second DLL state information DLL_INF received from the semiconductor device 1 in the holding unit 203 (step S15).

Here, as the second delay control signal stored and held in the holding unit 203 of the test apparatus 2,
The coarse adjustment control signal C_CDELAY has a count value of 1,
Fine adjustment control signal C_FDELAY has a count value of 1,
As the second delay time information,
C_NVAL of the time difference count circuit (NVC) 276 has a count value of 4,
Is shown.

  The test apparatus 2 reads the first DLL state information and the second DLL state information from the holding unit 203, performs a predetermined calculation in the control unit 202, and outputs a calculation result.

  When the variable delay circuit 21 is locked (the phase detection circuit 24 detects the coincidence of the phases of ExCLK and RCLK), the phase of the transition edge (for example, the rising edge) of the output RCLK of the replica circuit 26 in FIG. Match the phase of the transition edge (eg rising edge). When the period of the external lock signal ExCLK is tCK, the time obtained by adding these inherent delays to the delays of the variable delay circuit 21 and the replica circuit 26 is n × tCK (n = C_NVAL).

  The delay times of the fine adjustment delay element (FDE) 214 and the coarse adjustment delay element (CDE) 213 are tPDY_f and tPDY_c, respectively, and dX is the inherent delay information of the variable delay circuit 21 and the replica circuit 26.

From the first DLL state information of tCK = 1500 ps, when the DLL circuit 20 is locked, the delay time of the variable delay circuit 21 and the replica circuit 26 is 3 × tCK, and the delay time of the coarse adjustment delay circuit (CDL) 211 is 1 × The delay time of tPDY_c and fine adjustment delay circuit (FDL) 212 is 6 × tPDY_f. However, tPDY_c = 8 × tPDY_f.
Therefore, the following expression (1) is established.

3 × 1500 = 4500 = dX + 1 × tPDY_c + 6 × tPDY_f = dX + 14 × tPDY_f
... (1)

  From the second DLL state information of tCK = 1000 ps, when the DLL circuit 20 is locked, the delay time of the variable delay circuit 21 and the replica circuit 26 is 4 × tCK, and the delay time of the coarse adjustment delay circuit (CDL) 211 is 1 × tPDY_c The delay time of the fine adjustment delay circuit (FDL) 212 is 1 × tPDY_f. Therefore, the following equation (2) is established.

4 × 1000 = 4000 = dX + 1 × tPDY_c + 1 × tPDY_f = dX + 9 × tPDY_f
... (2)

From Expressions (1) and (2), 5 × tPDY_f = 500 ps holds. Therefore,
tPDY_f = 100 ps,
tPDY_c = 800 ps,
dX = 3100 ps,
It becomes.

<Modification of First Embodiment>
FIG. 9 is a diagram illustrating a modification of the DLL circuit according to the first embodiment. Referring to FIG. 9, in the DLL circuit 20 ′ of this modification, a second selection circuit (MUX2) 29 is newly added to the DLL circuit 20 having the configuration of FIG.

  In the second selection circuit 29, one input node is connected to the output (C_DELAY) of the delay circuit counter (DLC) 22, and the other input node is connected to the output C_NVAL of the time difference detection circuit (NV_DET) 27. Is connected to the register 25.

  The second selection circuit 29 supplies either the delay control signal C_DELAY or the delay time information C_NVAL to the register REG 25 according to a control signal (not shown) supplied from the DLL control circuit 23.

  According to this modification, the size (storage capacity) of the register REG25 can be reduced by adopting a configuration in which the delay control signal C_DELAY and the delay time information C_NVAL are alternately transferred to the register REG in time series.

<Embodiment 2>
Next, a second embodiment of the present invention will be described. In the first embodiment, as described with reference to FIG. 8, two sets of DLL state information DLL_INF obtained by changing the cycle of the test clock signal TCLK generated by the test apparatus 2 of FIG. The delay times tPDY_f and tPDY_c of the delay elements (CDE and FDE) of the delay circuit 21 are calculated.

  In the second embodiment, two types of DLL state information corresponding to the two sets of DLL state information DLL_INF of the first embodiment can be obtained without changing the cycle of the test clock signal TCLK generated by the test apparatus 2. It is configured as follows.

  According to the second embodiment, for example, an effect equivalent to that of the first embodiment can be obtained by using an inexpensive test apparatus that does not have a function of changing the cycle of the test clock signal TCLK. The basic configuration of the entire semiconductor device 1 according to the second embodiment is the same as that shown in FIG. FIG. 10 is a diagram illustrating the configuration of the DLL circuit 20A of the second embodiment. Referring to FIG. 10, as compared with the DLL circuit 20 of the first embodiment shown in FIG. 2, a DLL test is performed as an internal test signal supplied from the test control unit 15 of FIG. 1 to the DLL control circuit 23. In addition to the enable signal TDEN, the test DLL reset signal TDRST, and the output mode selection signals TOMODE1, TOMODE2, a lock forward signal LFWD is further included.

  In the second embodiment, the lock advance signal LFWD is generated by the test control unit 15 according to a desired test code TCODE supplied from the outside of the semiconductor device 1, and is supplied to the DLL control circuit 23 of the DLL circuit 20A. The

  When the lock advance signal LFWD supplied from the test control unit 15 is activated, the DLL control circuit 23 skips the first lock determination. That is, when the phase comparison result signal PCR from the phase comparator 24 first indicates phase matching (exCLK matching between RCLK and RCLK) after the start of the phase adjustment operation, the DLL control circuit 23 outputs the UP / DWN signal. Are kept in the previous state indicating phase match. That is, the DLL control circuit 23 also maintains the lock signal LOCK in the inactive state (non-locked state).

  Thereafter, again, when the phase comparison result signal PCR from the phase comparator 24 indicates that the phases match, the DLL control circuit 23 activates the lock signal LOCK and ends the phase adjustment.

  With such a configuration, two delay time differences between the internal clock signal PCLK and the replica clock signal RCLK are different even if the test clock signal TCLK is not changed on the test apparatus 2 side as in the first embodiment. Can create a state. As a result, two types of DLL state information corresponding to the two sets of DLL state information of the first embodiment are obtained.

  FIG. 11 is a flowchart for explaining a test procedure according to the second embodiment. In FIG. 8, the cycle tCK of the test clock signal TCLK is changed in step S8. In FIG. 11, instead of changing the cycle tCK of the test clock signal TCLK, the test code TCODE5 is issued in step S8A. The lock advance signal LFWD is activated.

  The test apparatus 2 reads the first DLL state information and the second DLL state information from the holding unit 203 (step S16), performs a predetermined calculation in the control unit 202 (step S17), and outputs the calculation result (step S16). S18).

As the first delay control signal of the first DLL state information received by the test apparatus 2 from the semiconductor device 1 in step S6 in FIG. 11, the cycle tCK of the test clock signal TCLK is set to 1000 ps.
The coarse adjustment control signal C_CDELAY has a count value of 1,
Fine adjustment control signal C_FDELAY has a count value of 1,
As the first delay time information,
C_NVAL of the time difference count circuit (NVC) 276 has a count value of 4,
Is shown.

As the second delay control signal of the second DLL state information received from the semiconductor device 1 by the test apparatus 2 in step S14 of FIG. 11 while the cycle tCK = 1000 ps of the test clock signal TCLK,
The coarse adjustment control signal C_CDELAY has a count value of 2,
The fine adjustment control signal C_FDELAY has a count value of 3,
As the second delay time information,
C_NVAL of the time difference count circuit (NVC) 276 has a count value of 5,
Suppose that

  When the delay times of the fine adjustment delay element (FDE) 214 and the coarse adjustment delay element (CDE) 213 are tPDY_f and tPDY_c, respectively, and dX is the inherent delay information of the DLL and the replica circuit, the first DLL state of tCK = 1000 ps From the information, when the DLL is locked, the delay time of the DLL and the replica circuit is 4 × tCK, the delay time of the coarse adjustment delay circuit (CDL) 211 is 1 × tPDY_c, and the delay time of the fine adjustment delay circuit (FDL) 212 is 1. XtPDY_f. However, tPDY_c = 8 × tPDY_f. Therefore, the following equation (3) is established.

4 × 1000 = 4000 = dX + 1 × tPDY_c + 1 × tPDY_f = dX + 9 × tPDY_f
... (3)

  From the second DLL state information of tCK = 1000 ps, when the DLL is locked, the delay time of the DLL and the replica circuit is 5 × tCK, the delay time of the coarse adjustment delay circuit (CDL) 211 is 1 × tPDY_c, and the fine adjustment delay circuit ( The delay time of (FDL) 212 is 1 × tPDY_f. Therefore, the following expression (4) is established.

5 x 1000 = 5000 = dX + 2 x tPDY_c + 3 x tPDY_f = dX + 19 x tPDY_f
... (4)

From Expressions (3) and (4), 10 × tPDY_f = 1000 ps holds. Therefore,
tPDY_f = 100 ps,
tPDY_c = 800 ps,
dX = 3100ps
It becomes.

<Embodiment 3>
Next, a third embodiment of the present invention will be described. In the first and second embodiments, the DLL state information DLL_INF from the DLL circuit is output from one DQ terminal. In the third embodiment, the DLL state information DLL_INF is output from a plurality of DQ terminals. It is configured to do. FIG. 12 is a diagram for explaining the third embodiment, and illustrates the entire configuration of the semiconductor device 1.

  As shown in FIG. 12, in the third embodiment, the DLL circuit 20B outputs the first DLL state information DLL_INF1 and the second DLL state information DLL_INF2 to the data input / output unit (I / O Unit) 19B. Yes. In FIG. 12, other configurations are the same as those in FIG. The description of the same part as FIG. 1 is omitted to avoid duplication.

  FIG. 13 is a diagram illustrating the configuration of the DLL circuit 20B of the third embodiment. In the DLL circuit 20 of the first embodiment, as shown in FIG. 2, the output C_NVAL of the delay time measurement circuit (NV_DET) 27 is connected to the register (REG) 25, but in the third embodiment, The output C_NVAL of the delay time measurement circuit (NV_DET) 27 (the count value of the time difference count circuit (NVC) 276 in FIG. 5A) is connected to the second register (REG2) 30. The delay time information C_NVAL is output from the second register (REG2) 30 to the data input / output unit 19B as the second DLL state information DLL_INF2. On the other hand, the delay control information C_DELAY stored in the register (REG1) (first register) 25 is output as first DLL state information DLL_INF1 via the selection circuit 28.

  FIG. 14 is a diagram illustrating a configuration of the data input / output unit (I / O Unit) 19B of FIG. Referring to FIG. 14, the data input / output unit (I / O Unit) 19B outputs, as output signals, data from the memory array 18 and first and second DLL state information DLL_INF1 and DLL_INF2 supplied from the DLL circuit 20B. Includes two data input / output circuits 191-1 and 191-2 that output data from the data terminal DQ, and a data input / output circuit 192 that outputs only data from the memory array 18 as output signals. In any circuit, data input from each data terminal DQ is similarly input to the memory array 18. That is, data from the input buffer circuits 195-1, 195-2, and 195-3 that receive signals from the data terminal DQ are input to the data control circuits 193-1, 193-2, and 193-3, respectively, and the memory array 18 is transferred.

  The two data input / output circuits 191-1 and 191-2 include selection circuits (MUX) 196-1 and 196-2, respectively.

  The selection circuit 196-1 includes data DATA (read data) from the memory array 18 supplied via the data control circuit 193-1 and first DLL state information DLL_INF1 (delay control information C_DELAY) supplied from the DLL circuit 20B. ) Is selected based on the DLL information read signal DLL_R from the test control unit (15 in FIG. 12) and supplied to the output buffer 194-1.

  The selection circuit 196-2 includes data DATA (read data) from the memory array 18 supplied via the data control circuit 193-2 and second DLL state information DLL_INF2 (delay time information C_NVAL) supplied from the DLL circuit 20B. ) Is selected based on the DLL information read signal DLL_R from the test control unit (15 in FIG. 12) and supplied to the output buffer 194-2.

  That is, the selection circuit 196-1 (196-2) selects the first DLL state information DLL_INF1 (second DLL state information DLL_INF2) and selects the output buffer 194- when the DLL information read signal DLL_R is at a high level. 1 (194-2), and first DLL state information DLL_INF1 (second DLL state information DLL_INF2) is serially output from the data terminal DQ. On the other hand, when the DLL information read signal DLL_R is at the low level, the selection circuit 196-1 (196-2) selects the data DATA (read data) from the memory array 18 and outputs the output buffer 194-1 (194-2). ) And data DATA (read data) is serially output from the data terminal DQ.

  The data input / output circuits 191-1 and 191-2 and the data input / output circuit 192 have substantially the same configuration except that the selection circuits 196-1 and 196-2 are included. That is, each data input / output circuit 191-1, 191-2, 192 includes data control circuits 193-1 to 193-2, output buffers 194-1 to 194-3, and input buffers 195-1 to 195-3. including. The data control circuits 193-1 to 193-3 operate according to the input / output control signal I / O CTL from the operation control unit 14 of FIG. 12 and the output clock signal LCLK from the DLL circuit 20B.

<Embodiment 4>
Next, a fourth embodiment of the present invention will be described. The overall basic configuration of the semiconductor device 1 of the fourth embodiment is the same as that of FIG. 1, but the delay described below is used as an internal test signal output from the test control unit 15 of FIG. 1 to the DLL circuit 20. A time measurement start signal NC_STR is included.

  In the first to third embodiments, as shown in FIG. 5A, the delay time measurement circuit (NV_DET) 27 of the DLL circuit 20 includes the first variable delay circuit (DL1) 21 and the first replica. The second variable delay circuit (DL2) 272 and the second replica circuit (REP2) 273 each having substantially the same configuration as the circuit (REP1) 26 are provided. In the fourth embodiment, the delay time is The measurement circuit (NV_DET) 27 includes a second variable delay circuit (DL2) 272 and a second replica having substantially the same configuration as the first variable delay circuit (DL1) 21 and the first replica circuit (REP1) 26. The configuration of the delay time measurement circuit (NV_DET) 27 capable of providing substantially the same operation and effect as the first to third embodiments without arranging the circuit (REP2) 273 is presented. That.

  FIG. 15 is a diagram illustrating a configuration of a DLL circuit 20C according to the fourth embodiment. Referring to FIG. 15, in the DLL circuit 20C of the fourth embodiment, as a change from the DLL circuit 20 of the first embodiment shown in FIG. 2, a gate circuit (GATE that receives the internal clock signal PCLK) is used. ) 31 and the DLL control circuit (DLL_CTL) 23C and the delay time measurement circuit (NV_DET) 27C are changed.

  The delay time measurement start signal NC_STR is a signal generated by the test control unit (TCU) 15 in FIG. The test control unit 15 controls the logic level of the delay time measurement start signal NC_STR according to the test code TCODE from the outside.

  When the delay time measurement start signal NC_STR is activated, the DLL control circuit 23C activates the clock stop signal PCLKSUS and supplies it to the gate circuit 31.

  The gate circuit 31 stops outputting the internal clock signal PCLK as the internal clock signal PCLK1 while the clock stop signal PCLKSUS is activated.

  On the other hand, the gate circuit 31 outputs the internal clock signal PCLK as the internal clock signal PCLK1 while the clock stop signal PCLKSUS is inactive.

  FIG. 16 is a diagram illustrating the configuration of the delay time measurement circuit 27C of the fourth embodiment of FIG. Referring to FIG. 16, the delay time measurement circuit 27C of the fourth embodiment includes a flip-flop 2711, a flip-flop 2712 with a reset terminal, an AND circuit 2713, and a time difference count circuit (NVC) 2714.

  The flip-flop 2711 inputs the delay time measurement start signal NC_STR signal to the data terminal D, samples the signal NC_STR of the data terminal D in response to the falling edge of the internal clock signal PCLK, and outputs the reset signal NC_RST from the output terminal Q. Output. Note that the flip-flop 2711 may be a flip-flop with a reset terminal and may be reset by a DLL reset signal TDRST or the like.

  The flip-flop 2712 has the data terminal D connected to the power supply line VDD, samples the power supply potential of the data terminal D in response to the falling edge of the replica clock signal RCLK from the replica circuit 26, and outputs the inverted output terminal QB (QB is output). Q is inverted output), and a low level stop signal NC_STPB (active state at low level) is output, and when the reset signal NC_RST input to the reset terminal R is set to the activation level (high level), it is reset and inverted A high level stop signal NC_STPB is output from the output terminal QB.

  The AND circuit 2713 receives the clock signal PCLK1 from the gate circuit 31 and the output NC_STPB from the flip-flop 2712, and outputs an AND operation result as a time difference count clock signal NC_CLK.

  The time difference count circuit 2714 receives the reset signal NC_RST from the flip-flop 2711 to the reset terminal R, and is reset when the reset signal NC_RST is at the active level (high level). When the reset signal NC_RST is at an inactive level (low level), the time difference count clock signal NC_CLK from the AND circuit 2713 is counted, and the count value is output as C_NVAL.

  FIG. 17 is a timing chart for explaining the operation of the delay time measurement circuit 27C of FIG. With reference to FIG. 17, the operation of the delay time measuring circuit 27C of FIG. 16 will be described.

  In response to activation of the delay time measurement start signal NC_STR from the test control unit 15 in FIG. 1, the gate circuit 31 in FIG. 15 stops the internal clock signal PCLK1. In the example of FIG. 17, the delay time measurement start signal NC_STR transitions to the high level that is the activation level in response to the falling edge of the internal clock signal PCLK.

  When the delay time measurement start signal NC_STR is activated, the gate circuit 31 in FIG. 15 stops the internal clock signal PCLK1 (low level) until the delay time measurement start signal NC_STR again becomes the inactivation level low level. And

  The flip-flop 2711 samples the delay time measurement start signal NC_STR at the falling edge of the internal clock signal PCLK and outputs the sampled signal from its output terminal Q. That is, the flip-flop 2711 delays the delay time measurement start signal NC_STR by one clock cycle and outputs it as an active state (high level) reset signal NC_RST.

  The flip-flop 2712 and the time difference count circuit 2714 enter a reset state in response to activation (high level) of the reset signal NC_RST. When the flip-flop 2712 is reset, the inverting output terminal QB of the flip-flop 2712 becomes a high level (power supply potential). Therefore, in response to the activation of the reset signal NC_RST, the stop signal NC_STPB (active state is low level) is reset to the inactive high level.

  In response to the transition to the inactivation level (low level) of the delay time measurement start signal NC_STR from the test control unit 15 in FIG. 1, the gate circuit 31 in FIG. 15 reactivates the internal clock signal PCLK1 (PCLK1 Is output again). At this time, as described above, since the flip-flop 2712 maintains the stop signal NC_STPB at the high level which is the inactive level, the AND circuit 2713 outputs the internal clock signal PCLK1 as the time difference count clock signal NC_CLK. In the example of FIG. 17, the delay time measurement start signal NC_STR transitions from the high level to the low level in response to the falling edge of the internal clock signal PCLK.

  The flip-flop 2711 sets the reset signal NC_RST to a low level, which is an inactive level, with a delay of one clock cycle from the inactivation timing of the delay time measurement start signal NC_STR. Therefore, the time difference count circuit 2714 counts up its own count value according to the time difference count clock signal NC_CLK.

  When the replica clock RCLK from the replica circuit 26 of the DLL circuit 20C in FIG. 15 is activated, the flip-flop 2712 sets the stop signal NC_STPB to the low level of the active level in response to the first falling edge of the replica clock RCLK. .

  As a result, the AND circuit 2713 stops outputting the time difference count clock signal NC_CLK. That is, in response to the low level of the stop signal NC_STPB, the AND circuit 2713 sets NC_CLK to a low level. The count value C_NVAL of the time difference count circuit (NVC) 2714 at this time is the number of clocks of the internal clock signal PCLK1 from when the internal clock signal PCLK1 is first supplied to when the replica clock RCLK is first supplied (see FIG. In 17, the number of clocks corresponds to 3). That is, this corresponds to the delay time difference between the internal clock signal PCLK1 and the replica clock signal RCLK. The count value C_NVAL of the time difference count circuit (NVC) 2714 of the delay time measurement circuit 27C is output to the register 25, and then output as DLL state information DLL_INF via the selection circuit 28, and the DLL information read from the test control unit 15 is performed. Based on the signal DLL_R, the data input / output unit 19 outputs the signal to the data terminal DQ.

  In the above embodiment, the semiconductor device 1 is not limited to the DRAM, but other semiconductor memories such as SRAM (Static Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random). For various semiconductor memories such as Access Memory (resistance change memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory: Ferroelectric Memory), NAND flash memory, NOR flash memory, etc. Is also applicable. Furthermore, the semiconductor device is not limited to a semiconductor memory, and can be applied to various semiconductor devices such as a logic IC, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), and an ASIC (Application Specific Integrated Circuit). .

  Each embodiment can be realized not only independently but also by combining components in different embodiments.

  The disclosure of the above patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Test apparatus 11 Command input circuit (IB1)
12 Address input circuit (IB2)
13 Clock input circuit (IB3)
14 Operation control unit (OCU)
15 Test control unit (TCU)
16 Row decoder (XDEC)
17 Column decoder (YDEC)
18 Memory array 19, 19B Data input / output unit (I / O Unit)
20, 20 ', 20A, 20B, 20C DLL circuit 21 Variable delay circuit (DL1)
22 Delay circuit counter (DLC)
23, 23C DLL control circuit (DLL CTL)
24 Phase detector (PD)
25 Register 26 First replica circuit 27, 27C Delay time measurement circuit (NV_DET)
28 Selection circuit (MUX1)
29 Selection circuit (MUX2)
30 registers (REG2)
31 Gate circuit 191, 191-1, 191-2, 192 Data input / output circuit 193 Data control circuit (Data CTL)
194 output buffer 195 input buffer 196 selection circuit 201 processing device 202 control unit 203 holding unit 204 input buffer 205 output buffer 206 interface unit 207 peripheral device 208 monitor 209 external storage device 210 keyboard 211 coarse adjustment delay circuit (CDL1)
212 Fine adjustment delay circuit (FDL1)
213-1 to 213-m Coarse adjustment delay element (CDE)
214-1 to 214-8 Fine adjustment delay element (FDE)
215 Unit delay element 216 selection circuit 271 flip-flop 272 variable delay circuit (DL2)
273 Replica circuit (REP2)
274 Inverter 275 AND circuit 276 Time difference count circuit (NVC)
2711, 2712 Flip-flop 2713 AND circuit 2714 Time difference count circuit (NVC)

Claims (17)

An output terminal;
A first delay circuit that receives a first clock signal and variably delays the first clock signal in response to a delay control signal to generate a second clock signal;
A delay control circuit that holds delay control information and supplies the delay control signal corresponding to the delay control information to the first delay circuit;
A delay time measuring circuit for measuring a delay time between the first clock signal and the second clock signal and holding a measurement result of the delay time as delay time information;
The delay control circuit and the delay time measurement circuit are connected to the output terminal, and the delay control information held by the delay control circuit and the delay time information held by the delay time measurement circuit are transmitted to the output terminal. Output path to
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the output path includes a circuit that serially transmits the delay control information and the delay time information to the output terminal.   The semiconductor device according to claim 1, wherein the delay control circuit includes a first counter circuit that holds the delay control information as a first count value. An input terminal for receiving a third clock signal;
An input circuit connected to the input terminal and outputting the first clock signal in response to the third clock signal;
A phase detection circuit that detects a phase difference between the second clock signal and the third clock signal and outputs a phase detection signal;
Further including
4. The semiconductor device according to claim 1, wherein the delay control circuit updates the held delay control information in accordance with the phase detection signal. 5. The delay control circuit takes a first logic level when the phase of the second clock signal and the phase of the third clock signal substantially coincide with each other according to the phase detection signal. When the phase of the second clock signal is different from the phase of the third clock signal, a lock signal that takes a second logic level is output;
The delay time measurement circuit includes:
A first circuit that captures the lock signal in response to the first clock signal and generates a first mask signal;
A second delay circuit that receives the first mask signal output from the first circuit and variably delays the first mask signal according to the delay control signal to generate a second mask signal; When,
A delay time count clock signal generation circuit that receives the first mask signal, the second mask signal, and the first clock signal and generates a delay time count clock signal based on the first clock signal; A delay time count clock signal generation circuit for controlling whether to generate the delay time count clock signal according to the values of the first and second mask signals;
A second counter circuit that updates a second count value representing the delay time information in response to the delay time count clock signal;
The semiconductor device according to claim 4, further comprising: The delay control circuit receives a lock advance signal for controlling the lock advance, and when the lock advance signal is activated, skips at least the first lock determination, and the phase detection circuit Maintaining the lock signal at the second logic level also when it is detected that the phase of the clock signal and the phase of the third clock signal substantially match,
Next, when it is detected that the phase of the second clock signal and the phase of the third clock signal substantially coincide with each other, control is performed to set the lock signal to the first logic level. The semiconductor device according to claim 5, wherein the semiconductor device is performed.   The output path outputs the lock signal from the output terminal based on a selection signal from the delay control circuit, or controls to output the delay control information and the delay time information from the output terminal. The semiconductor device according to claim 5, further comprising a selection circuit.   The semiconductor device according to claim 5, wherein the first delay circuit and the second delay circuit have substantially the same configuration. The delay control circuit receives a first control signal and generates a third mask signal in response to the first control signal;
The semiconductor device includes:
A first gate circuit that receives the first clock signal and supplies the first clock signal to the first delay circuit, wherein the first mask signal is activated when the third mask signal is activated; A first gate circuit for stopping the output of the clock signal of 1;
The delay time measurement circuit includes:
A mask control circuit for generating a fourth mask signal in response to the second clock signal;
A delay time count clock generation circuit which receives the fourth mask signal and the first clock signal and generates a delay time count clock signal based on the first clock signal, wherein the fourth mask signal In response, a delay time count clock signal generation circuit that controls whether to generate the delay time count clock signal;
A second counter circuit that updates a second count value indicating the delay time information in response to the delay time count clock signal;
The semiconductor device according to claim 1, further comprising: A memory cell array,
The output path is
An output circuit that includes first and second input nodes and an output node connected to the output terminal, and selectively connects the first or second input node to the output node;
The first input node of the output circuit is commonly connected to the delay control circuit and the delay time measurement circuit;
The semiconductor device according to claim 1, wherein the second input node of the output circuit is connected to the memory cell array. The output terminal includes a first output terminal and a second output terminal,
The output path is
A first switching circuit connected between the delay control circuit and the first output terminal and supplying the delay control information to the first output terminal;
A second switching circuit connected between the delay time measuring circuit and the second output terminal and supplying the delay time information to the second output terminal;
The semiconductor device according to claim 1, further comprising: A memory cell array,
The first switching circuit includes:
First and second input nodes;
A first output node connected to the first output terminal;
Including
The second switching circuit includes:
A third and fourth input node;
A second output node connected to the second output terminal;
Including
The first input node of the first switching circuit is connected to the delay control circuit;
The second input node of the first switching circuit is connected to the memory cell array;
The third input node of the second switching circuit is connected to the delay time measuring circuit;
12. The semiconductor device according to claim 11, wherein the fourth input node of the second switching circuit is connected to the memory cell array. The first delay circuit varies the number of delay elements included in the delay path according to the delay control signal, thereby varying and outputting the delay time of the first clock signal. A delay circuit;
A replica circuit simulating the transmission path from the first variable delay circuit to the output buffer and the output buffer;
With
13. The semiconductor device according to claim 1, wherein the replica circuit receives an output signal of the first variable delay circuit and outputs the second clock signal. A delay control circuit that supplies a delay control signal corresponding to the delay control information to the first delay circuit; a second clock signal that receives the first clock signal and variably delays the first clock signal according to the delay control signal; A first delay circuit for generating a clock signal of the semiconductor device, comprising:
During the test, the delay time measurement circuit provided in the semiconductor device measures the delay time between the first clock signal and the second clock signal and holds it as delay time information.
A control method of a semiconductor device, wherein the delay control circuit and the delay time measurement circuit are connected to an output circuit, and the delay control information and the delay time information are controlled to be output from an output terminal. The first clock signal is generated according to a third clock signal input to the semiconductor device,
In response to a phase detection result in a phase detection circuit that detects a phase difference between the second clock signal and the third clock signal, the delay control circuit updates the delay control information,
Further, the delay control circuit, based on the phase detection result in the phase detection circuit, when the phase of the second clock signal and the phase of the third clock signal substantially match, When the lock signal is determined to be activated and the lock signal is activated, and the phase of the second clock signal is different from the phase of the third clock signal, the lock signal is deactivated,
15. The semiconductor device according to claim 14, wherein the delay control information in the locked state and the delay time information measured in the locked state are controlled to be output from the output terminal. Control method. During the test, the first clock signal is set to a first period, the delay control information and the delay time information are output from the output terminal,
Next, after changing the first clock signal to the second period, control to output the delay control information and the delay time information from the output terminal,
In a test apparatus that has acquired the two sets of the delay control information and the delay time information, which are output from the output terminal of the semiconductor device, per stage of a plurality of delay elements constituting the first delay circuit 16. The method of controlling a semiconductor device according to claim 14, wherein the delay time can be derived. The delay control circuit of the semiconductor device receives a lock advance signal that controls lock advance, and when the lock advance signal is activated, skips at least the first lock determination and deactivates the lock signal. And then, when it is detected that the phase of the second clock signal and the phase of the third clock signal substantially coincide with each other, the control to activate the lock signal is performed. Done
When the lock advance signal is in an inactive state, the lock determination is not skipped, and it is detected that the phase of the second clock signal and the phase of the third clock signal substantially match. The lock signal is activated,
During the test, the lock advance signal is set to one of an active state and an inactive state, the first clock signal is set to a first period, and the delay control information and the delay time information are sent from the output terminal. Output
Next, the lock forward signal is changed to the active state or the inactive state, the first clock signal remains in the first period, and the delay control information and the delay time information are transmitted to the output terminal. Output from
In a test apparatus that has acquired the two sets of the delay control information and the delay time information, which are output from the output terminal of the semiconductor device, per stage of a plurality of delay elements constituting the first delay circuit 16. The method of controlling a semiconductor device according to claim 15, wherein the delay time can be derived.

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