JP2015138960A - semiconductor device - Google Patents

Abstract

A semiconductor device having excellent pressure resistance and capable of being manufactured with a high yield is provided. A p-type body region is formed in a surface layer portion of a SiC epitaxial layer at a distance from each other, and a surface layer portion of each p-type body region is spaced from the periphery of the p-type body region. N + type source region 19 formed with a gap between each other and p − type body region 17, and gate insulation is performed on channel region 22 between the periphery of each p − type body region 17 and n + type source region 19. A gate electrode 10 that is opposed to and sandwiched by the cavity portion 25 in the JFET region 18 between the adjacent p − type body regions 17 across the film 21, is formed in the cavity portion 25, and is formed from the gate insulating film 21. The semiconductor device 1 including the thick intermediate insulating film 30 is manufactured. [Selection] Figure 3

Description

  The present invention relates to a semiconductor device using SiC.

Patent Document 1 discloses an n ⁺ -type SiC substrate, an n ⁻ -type SiC epi layer formed on the SiC substrate, and a p-type base formed on the surface layer portion of the n ⁻ -type SiC epi layer at intervals. A semiconductor device including a region and an N ⁺ type source region formed in a surface layer portion of each base region is disclosed. The gate insulating film in the semiconductor device is formed across adjacent base regions, and a gate electrode is formed on the gate insulating film. The gate electrode is opposed to each body region with the gate insulating film interposed therebetween. A source electrode is electrically connected to the source region. On the other hand, the drain electrode is formed on the back side of the SiC substrate. Thereby, a power device having a vertical structure in which the source electrode and the drain electrode are arranged in the vertical direction perpendicular to the main surface of the SiC substrate is configured.

  In a state where a voltage is applied between the source electrode and the drain electrode (between the source and the drain), a voltage higher than a threshold value is applied to the gate electrode, so that an electric field from the gate electrode causes a contact with the gate insulating film in the body region. A channel is formed near the interface. Thereby, a current flows between the source electrode and the drain electrode, and the power device is turned on.

JP 2003-347548 A

In a semiconductor device such as Patent Document 1, when the semiconductor device is in an off state (that is, in a state where the gate voltage is 0 V), a voltage at which the SiC substrate is on the (+) side of the SiC substrate functioning as a source region and a drain. Is applied, equipotential surfaces with a high potential are distributed between the adjacent body regions with reference to the gate electrode (0 V).
Since the equipotential surface is narrower than the equipotential surface in other regions, a large electric field is applied to the gate insulating film interposed between the gate electrode and the SiC substrate. Therefore, if a voltage as high as the device breakdown voltage is continuously applied between the source and the drain, the gate insulating film cannot withstand the electric field concentration and may cause a dielectric breakdown.

Such a problem also causes a decrease in yield in a high temperature reverse bias (HTRB) test for inspecting the device breakdown voltage in a high temperature environment.
Therefore, an object of the present invention is to provide a semiconductor device that has excellent pressure resistance and can be manufactured with high yield.

  In order to achieve the above object, the invention according to claim 1 is the first conductivity type SiC semiconductor layer and the plurality of second conductivity type bodies formed on the surface layer portion of the SiC semiconductor layer at intervals from each other. A first conductivity type source region formed on the surface layer of each body region at a distance from the periphery of the body region, and a periphery of each of the body regions. And a gate electrode that is opposed to the channel region between the source region and the gate region, and is selectively divided by a cavity in an intermediate region between adjacent body regions, and formed in the cavity A semiconductor device including an intermediate insulating film thicker than the gate insulating film.

According to this configuration, the semiconductor device has a vertical structure in which the source region and the region that can function as the drain in the SiC semiconductor layer are arranged in the vertical direction with the body region interposed therebetween.
According to this configuration, the gate electrode is divided by the cavity, and the intermediate insulating film thicker than the gate insulating film is formed in the cavity. Therefore, even when a voltage (for example, 1200 V) at which the source region and the SiC semiconductor layer are on the (+) side is applied in a state where the semiconductor device is off (that is, a state where the gate electrode is 0 V), Since the gate electrode does not exist, the cavity does not become the reference position of the equipotential surface. Thereby, the distribution of the equipotential surface of the potential in the intermediate region can be changed. As a result, it is possible to mitigate the application of a high electric field to the intermediate region. Furthermore, since the thick intermediate insulating film is formed in the region where the electric field can be relaxed, the dielectric breakdown in the intermediate region can be effectively suppressed. As a result, a semiconductor device that has excellent pressure resistance and can be manufactured with high yield can be provided.

  In addition, according to this configuration, since the gate electrode is formed on the channel region, the MISFET (Metal Insulator Field Effect Transistor) does not hinder the on operation. Furthermore, the area of the gate electrode (more specifically, the facing area where the surface of the gate electrode and the surface of the SiC semiconductor layer face each other) can be reduced by the cavity. Thereby, the capacity | capacitance between a SiC semiconductor layer and a gate electrode can be reduced.

The invention according to claim 2 is the semiconductor device according to claim 1, wherein the hollow portion of the gate electrode is formed on a central portion of the intermediate region.
According to this configuration, the intermediate insulating film is formed on the central portion of the intermediate region. The equipotential surface of the potential tends to be highest at the center of the intermediate region. Therefore, by forming the intermediate insulating film on the central portion of the intermediate region where the electric field is most likely to be highest, the dielectric breakdown in the intermediate region can be effectively suppressed.

According to a third aspect of the present invention, the plurality of body regions are formed in a stripe shape having one end and the other end, and the gate electrode is formed at the one end and / or the other end of the body region. The semiconductor device according to claim 1, wherein the semiconductor device straddles adjacent body regions.
According to this configuration, the intermediate insulating film is formed along the stripe direction of the body region (intermediate region). Therefore, the equipotential surface distribution of the potential in the intermediate region can be changed along the stripe direction of the intermediate region. This can alleviate the application of an electric field in a wide range along the stripe direction of the intermediate region. As a result, dielectric breakdown in the intermediate region can be further suppressed.

According to a fourth aspect of the present invention, the cavity of the gate electrode is formed so as to be inward of the intermediate region at a distance from a boundary between the body region and the intermediate region. It is a semiconductor device as described in any one of Claims 1-3.
According to this configuration, the gate electrode can be reliably opposed to the source region, the body region, and the SiC semiconductor layer. Therefore, since the gate electrode and the channel region can be reliably opposed to each other, the ON operation of the MISFET can be further improved.

The invention according to claim 5 is the semiconductor device according to claim 1, wherein the intermediate region has a width of 0.1 μm to 50 μm.
As the width of the intermediate region increases, high potential equipotential surfaces tend to be distributed in the intermediate region. On the other hand, if the intermediate region is too narrow, the resistance value of the intermediate region becomes high. Therefore, according to this configuration, it is possible to realize a good resistance value while suppressing the equipotential surface having a high potential from being distributed in the intermediate region.

A sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the intermediate insulating film has a thickness twice or more that of the gate insulating film.
According to this configuration, dielectric breakdown in the intermediate region can be further suppressed.
A seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the intermediate insulating film includes a SiO ₂ film.

According to this configuration, the SiO ₂ film melts satisfactorily at the time of reflow, and therefore the SiO ₂ film can be satisfactorily embedded in the cavity.
In the invention according to claim 8, the SiO ₂ film preferably contains P (phosphorus) ions.
According to this configuration, the intermediate insulating film includes a PSG (Phosphorus Silicon Glass) film. The PSG film melts well during reflow (for example, about 1000 ° C.). Therefore, the PSG film can be satisfactorily embedded in the cavity.

The invention according to claim 9 is the semiconductor device according to claim 8, wherein the SiO ₂ film further contains B (boron) ions.
According to this configuration, the intermediate insulating film includes a BPSG (Boron Phosphorus Silicon Glass) film. The BPSG film melts at a lower temperature (for example, about 800 ° C.) than the PSG film. Therefore, the BPSG film can be embedded more satisfactorily in the cavity.

A tenth aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the intermediate insulating film includes an insulating material film having a dielectric constant higher than that of SiO ₂ .
According to this configuration, dielectric breakdown in the intermediate region can be further suppressed.
As in the eleventh aspect of the present invention, the intermediate insulating film is preferably made of Al ₂ O ₃ or SiN.

The invention according to claim 12 is the semiconductor according to any one of claims 1 to 6, wherein the insulating material film includes a stacked structure in which an SiO ₂ film and an Al ₂ O ₃ film are stacked in this order. Device.
According to this configuration, the portion where the SiC semiconductor layer and the intermediate insulating film are in contact (connection interface) is formed of the SiO ₂ film, so that the channel mobility of carriers flowing in the channel region can be improved. Meanwhile, since the on the SiO ₂ film _{an Al} 2 _{O 3} film having a dielectric constant higher than that of the SiO ₂ film is formed, a high dielectric constant can be secured in the _{the Al} 2 _{O 3} film. Thereby, the dielectric breakdown in the intermediate region can be further suppressed. Note that the SiO ₂ film and the Al ₂ O ₃ film may be laminated over a plurality of periods.

The invention according to claim 13 is the semiconductor device according to any one of claims 1 to 6, wherein the intermediate insulating film includes a laminated structure in which an SiO ₂ film and an SiN film are laminated in this order. .
According to this configuration, the portion where the SiC semiconductor layer and the intermediate insulating film are in contact (connection interface) is formed of the SiO ₂ film, so that the channel mobility of carriers flowing in the channel region can be improved. Meanwhile, since the on SiO ₂ film are formed SiN film having a dielectric constant higher than that of the SiO ₂ film can ensure a high dielectric constant in the SiN film. Thereby, the dielectric breakdown in the intermediate region can be further suppressed. Note that the SiO ₂ film and the SiN film may be stacked over a plurality of periods.

Preferably, the gate electrode is made of polysilicon.
The invention according to claim 15 is the semiconductor device according to claim 14, wherein the polysilicon includes B (boron) ions.
According to this configuration, the threshold voltage (V _{GS (th)} ) of the gate voltage necessary for forming the channel can be lowered.

The invention according to claim 16 is the semiconductor device according to any one of claims 1 to 13, wherein the gate electrode is made of a metal material.
According to this configuration, the resistance value of the gate electrode can be made smaller than when the gate electrode is formed using polysilicon. Thereby, since the film thickness of the gate electrode can be further reduced, the intermediate insulating film can be satisfactorily embedded in the cavity.

Preferably, the metal material is made of Al, Cu, or AlCu.
The invention according to claim 18 is the semiconductor device according to claim 1, wherein the gate electrode has a thickness of 2 μm or less.
According to this configuration, the intermediate insulating film can be satisfactorily embedded in the cavity.

As in the nineteenth aspect of the present invention, each body region is preferably formed along the <11-20> axial direction.
According to a twentieth aspect of the present invention, the gate insulating film has a first thickness on the channel region, and a second thickness larger than the first thickness on the source region. A semiconductor device according to any one of claims 1 to 19.

According to this configuration, when an electric field is applied to the gate insulating film, the electric field in the gate insulating film in contact with the source region can be effectively reduced. Thereby, the dielectric breakdown of the gate insulating film on the source region can be effectively suppressed.
The invention according to claim 21 is the semiconductor device according to claim 20, wherein the second thickness of the gate insulating film is 2.03 times or more of the first thickness.

According to this configuration, the long-term reliability of the gate insulating film in contact with the source region can be improved. Thereby, the long-term reliability of the entire gate insulating film can be further improved by the long-term reliability of the gate insulating film in contact with the source region.
Preferably, the gate insulating film formed on the channel region has a thickness of 1 μm or less.

The invention according to claim 23 further includes an interlayer insulating film formed on the SiC semiconductor layer so as to cover the gate electrode and embedded in the cavity, wherein the intermediate insulating film is formed of the interlayer insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is formed using a buried portion.
According to this configuration, the intermediate insulating film can be formed using the step of forming the interlayer insulating film. Therefore, a semiconductor device that can be easily manufactured can be provided.

The invention according to claim 24 is the semiconductor device according to claim 23, wherein an amount of the interlayer insulating film embedded in the cavity is substantially equal to a thickness of a portion of the interlayer insulating film on the gate electrode. .
The invention according to claim 25 is the semiconductor device according to any one of claims 1 to 24, wherein a taper angle of 5 degrees or more is formed at an upper end portion of the gate electrode.

  According to this configuration, the insulating film can be satisfactorily embedded in the cavity.

FIG. 1 is a schematic plan view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is an enlarged view showing the arrangement of gate electrodes and unit cells of the semiconductor device according to FIG. 3A is a cross-sectional view seen from the section line IIIa-IIIa in FIG. 2, and FIG. 3B is a cross-sectional view seen from the section line IIIb-IIIb in FIG. FIG. 4 is a table showing the relationship between the electric field strengths at the time of dielectric breakdown of SiO ₂ , SiC and Si. FIG. 5 is a schematic view of the SiC substrate and the SiC epitaxial layer in the wafer state. FIG. 6 is a schematic diagram illustrating a unit cell having a crystal structure of 4H—SiC. FIG. 7 is a view of the unit cell of FIG. 6 as viewed from directly above the (0001) plane. FIG. 8 is a flowchart for explaining an example of the manufacturing process of the semiconductor device shown in FIG. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic enlarged plan view of a semiconductor device according to a modification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to the first embodiment of the present invention.
The semiconductor device 1 includes a planar gate type VDMISFET (Vertical double diffused Metal Insulator Field Effect Transistor) 2 in which SiC having a withstand voltage of, for example, 600 V to 10000 V is employed.

The semiconductor device 1 is formed in a substantially rectangular shape including a pair of long sides 1a and a pair of short sides 1b in a plan view of FIG. A gate pad 3 having a substantially rectangular shape in plan view is formed at one end in the longitudinal direction along the long side 1 a of the semiconductor device 1, and an active region 4 including the VDMISFET 2 is formed so as to surround the periphery of the gate pad 3. ing.
The gate pad 3 includes a pair of long sides 3 a formed along the short side 1 b of the semiconductor device 1 and a pair of short sides 3 b formed along the long side 1 a of the semiconductor device 1. A plurality of contacts 5 are formed on the gate pad 3 at intervals along the periphery of the gate pad 3. The contacts 5 are formed at both ends in the longitudinal direction of the long sides 3 a of the gate pad 3 and at the central portion in the longitudinal direction of the short sides 3 b, respectively, and the gate wiring 6 is electrically connected to the contacts 5. .

  The gate wiring 6 includes a first wiring 7 connected to each contact 5 on each long side 3 a of the gate pad 3 and a second wiring 8 connected to each contact 5 on each short side 3 b of the gate pad 3. . The first wires 7 are formed so as to run in parallel with each other in the direction orthogonal to the short side 1 b of the semiconductor device 1 from each contact 5. On the other hand, each second wiring 8 is formed along each short side 3 b of the gate pad 3. A plurality of gate electrodes 10 are integrally formed on the first wiring 7 and the second wiring 8.

  The plurality of gate electrodes 10 are formed in a direction perpendicular to the gate wiring 6, and are arranged in a stripe pattern with a space between each other. Hereinafter, the direction in which the gate electrodes 10 are arranged is referred to as “the stripe direction of the gate electrodes 10”. A VDMISFET 2 formed along the stripe direction of the gate electrode 10 is electrically connected to the gate electrode 10. That is, in the present embodiment, a striped VDMISFET 2 is formed. Hereinafter, the structure of the VDMISFET 2 will be described more specifically with reference to FIG. 2 and FIG.

FIG. 2 is an enlarged view showing the arrangement of the gate electrodes 10 and the unit cells 11 of the semiconductor device 1 according to FIG. 3A is a cross-sectional view seen from the section line IIIa-IIIa in FIG. 2, and FIG. 3B is a cross-sectional view seen from the section line IIIb-IIIb in FIG. In FIG. 2, for convenience of explanation, the gate wiring 6 and the gate electrode 10 are indicated by hatching.
As shown in FIG. 3, the semiconductor device 1 includes a SiC semiconductor layer 12. SiC semiconductor layer 12 includes an ^{n +} -type SiC substrate 13, is stacked on ^{the n +} -type SiC substrate 13, than ^{the n +} -type SiC substrate 13 and the low concentration of the SiC epitaxial layer 14. The SiC epitaxial layer 14 is formed by epitaxially growing SiC on the surface of the n ⁺ -type SiC substrate 13 and functions as a drift layer (drain layer) of the semiconductor device 1.

The impurity concentration of n ⁺ type SiC substrate 13 is, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of SiC epitaxial layer 14 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 ×. 10 ¹⁷ cm ⁻³ . As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic) or the like can be used (hereinafter the same). A p ⁻ type body connection region 16 and a p ⁻ type body region 17 are integrally formed on the surface layer portion of SiC epitaxial layer 14.

The p ⁻ type body connection region 16 is formed along the gate wiring 6 as shown in FIG. 2 and FIG. The p ⁻ type body connection region 16 is formed wider than the gate wiring 6 and is formed so as to cover the gate wiring 6 from below.
On the other hand, as shown in FIGS. 2 and 3B, a plurality of p ⁻ type body regions 17 are formed at intervals from each other along the stripe direction of the gate electrode 10. One end and / or the other end in the longitudinal direction of each p ⁻ type body region 17 is formed so as to be integrated with the p ⁻ type body connection region 16 as shown in FIG. The SiC epitaxial layer 14 between the p ^- type body regions 17 adjacent to each other is a JFET (Junction Field Effect Transistor) region 18 as an intermediate region.

  The width WJ of the JFET region 18 is preferably 0.1 μm to 50 μm (in this embodiment, 2.6 μm), for example. As the JFET region 18 becomes wider, high potential equipotential surfaces tend to be distributed in the JFET region 18 when the gate electrode 10 is in the OFF state. On the other hand, if the JFET region 18 is too narrow, the resistance value of the JFET region 18 increases. Therefore, within this numerical value range, it is possible to realize a good resistance value while suppressing the distribution of a high potential equipotential surface in the JFET region 18.

The depth of p ⁻ type body connection region 16 and p ⁻ type body region 17 (which refers to the depth from the surface of SiC epitaxial layer 14 in the thickness direction; the same applies hereinafter) is, for example, 0.1 μm to 10 μm. It is. The impurity concentration of p ⁻ type body connection region 16 and p ⁻ type body region 17 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . As the p-type impurity, for example, B (boron), Al (aluminum), or the like can be used (hereinafter the same). An n ⁺ type source region 19 and a p ⁺ type body contact region 20 are formed in the surface layer portion of the p ⁻ type body region 17.

The n ⁺ type source region 19 is formed along the stripe direction of the gate electrode 10 as shown in FIGS. 2 and 3B, and is viewed in plan view with a gap from the periphery of the p ⁻ type body region 17. It is formed in a rectangular ring shape. The n ⁺ type source region 19 is formed shallower than the p ⁻ type body region 17 and has a depth of 0.05 μm to 5 μm, for example. Further, the impurity concentration of the n ⁺ -type source region 19 is, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

As shown in FIGS. 2 and 3B, the p ⁺ type body contact region 20 is formed along the stripe direction of the gate electrode 10, and is formed in an inner part surrounded by the n ⁺ type source region 19 ( The p ⁻ -type body region 17 is formed in a substantially rectangular shape in plan view on the center portion of the surface layer portion. The p ⁺ type body contact region 20 is shallower than the p ⁻ type body region 17 and deeper than the n ⁺ type source region 19. The depth of p ⁺ type body contact region 20 is, for example, 0.06 μm to 6 μm. Further, the impurity concentration of the p ⁺ type body contact region 20 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . A unit cell 11 extending in the stripe direction of the gate electrode 10 is defined by a boundary line passing through the center of the p ⁺ type body contact region 20. A gate insulating film 21 is formed on the surface of the SiC epitaxial layer 14 along the p ⁻ type body connection region 16 and the unit cells 11.

In the present embodiment, the gate insulating film 21 is a silicon oxide film made of SiO ₂ (silicon oxide). The gate insulating film 21 formed on the p ⁻ type body connection region 16 is formed wider than the gate wiring 6 as shown in FIG. That is, the entire gate wiring 6 faces the p ⁻ type body connection region 16 with the gate insulating film 21 interposed therebetween. On the other hand, the gate insulating film 21 formed on each unit cell 11 is formed so as to straddle adjacent p ⁻ type body regions 17 as shown in FIG. More specifically, the gate insulating film 21 is formed so as to cover a portion surrounding each n ⁺ type source region 19 in each p ⁻ type body region 17 and an outer peripheral portion of the n ⁺ type source region 19. The gate insulating film 21 is formed with a uniform thickness, and the film thickness is preferably, for example, 1 μm or less.

The gate electrode 10 faces the channel region 22 with the gate insulating film 21 interposed therebetween. More specifically, the gate electrode 10 is a region straddling the SiC epitaxial layer 14, the p ⁻ type body region 17 and the n ⁺ type source region 19 outside the p ⁻ type body region 17 with the gate insulating film 21 interposed therebetween. Opposite to. In plan view, gate electrode 10 includes an overlap portion that protrudes from the boundary between n ⁺ type source region 19 and p ⁻ type body region 17 toward n ⁺ type source region 19. In the direction orthogonal to the stripe direction, the width of the overlap portion of the gate electrode 10 is, for example, 0.05 μm to 1 μm.

The gate electrode 10 (and the gate wiring 6) has a film thickness of 2 μm or less, for example. The gate electrode 10 (and the gate wiring 6) is formed of an electrode material made of polysilicon or a metal material. When polysilicon is employed for the gate electrode 10, the polysilicon preferably contains B (boron) ions. Thereby, the threshold voltage (V _{GS (th)} ) of the gate voltage necessary for forming the channel can be lowered.

On the other hand, when a metal material is employed for the gate electrode 10, the metal material is preferably made of Al (aluminum), Cu (copper), or AlCu (aluminum copper). According to these metal materials, the resistance value of the gate electrode 10 can be reduced as compared with the case where polysilicon is employed as the electrode material. Therefore, the thickness of the gate electrode 10 can be further reduced (for example, 0.1 μm to 1 μm). A cavity 25 is formed in each gate electrode 10 on a region (JFET region 18) between adjacent p ⁻ type body regions 17.

The cavity 25 is a region where the electrode material of the gate electrode 10 is removed and the gate electrode 10 does not face the JFET region 18 with the gate insulating film 21 interposed therebetween. As shown in FIG. 2, each cavity 25 is formed in a substantially rectangular shape along the stripe direction of the gate electrode 10. Each cavity portion 25 is formed at a position crossing a boundary line passing through the center between the p ⁻ type body regions 17 in a direction orthogonal to the stripe direction. More specifically, each cavity 25 is formed to be inward of JFET region 18 at a distance from the boundary between each p ⁻ type body region 17 and JFET region 18. Each cavity 25 is preferably formed on the central part of p ⁻ type body regions 17 adjacent to each other. One end and / or the other end in the stripe direction of each cavity 25 is formed to reach the gate wiring 6.

As shown in FIG. 3B, each cavity 25 is formed to be narrower than the width WJ (= 2.6 μm) of the JFET region 18, and the width WD is, for example, 0.1 μm to 2.. 4 μm (in this embodiment, 1.6 μm). Due to the hollow portion 25, the gate electrode 10 further includes an overlap portion that protrudes from the boundary line between the p ⁻ type body region 17 and the JFET region 18 toward the JFET region 18 in a plan view. As a result, the gate electrode 10 can be reliably opposed to the p ⁻ type body region 17 between the n ⁺ type source region 19 and the JFET region 18, so that the channel formation in the p ⁻ type body region 17 can be performed. It can be reliably controlled. That is, when the gate electrode 10 is turned on, a current can be passed through the JFET region 18 in each unit cell 11. More specifically, it can flow from SiC epitaxial layer 14 to n ⁺ type source region 19 through channel region 22 in p ⁻ type body region 17. The channel length L of the channel region 22 is defined by the width of the p ⁻ type body region 17 directly below the gate electrode 10 and is, for example, 0.05 μm to 2 μm (in this embodiment, 0.65 μm).

On the SiC epitaxial layer 14, an interlayer insulating film 26 is formed so as to cover the gate electrode 10 by filling the cavity 25 back from the gate insulating film 21. The interlayer insulating film 26 formed on the gate insulating film 21 in the cavity 25 has a film thickness substantially equal to that of the interlayer insulating film 26 formed so as to cover the gate electrode 10. As an insulating material of the interlayer insulating film 26, an insulating material having a dielectric constant higher than that of SiO ₂ or SiO ₂ such as Al ₂ O ₃ or SiN can be employed. In FIG. 3, the thickness of the interlayer insulating film 26 on the gate insulating film 21 is increased from the viewpoint of more clearly showing the configuration of the cavity 25 (intermediate insulating film 30).

An intermediate insulating film 30 as an example of the intermediate insulating film of the present invention is defined by the laminated structure of the gate insulating film 21 in the hollow portion 25 and the interlayer insulating film 26 embedded in the hollow portion 25.
When SiO ₂ is adopted as the insulating material of the interlayer insulating film 26, the interlayer insulating film 26 is preferably a PSG (Phosphorus Silicon Glass) film in which P (phosphorus) ions are included in the SiO ₂ . According to the PSG film, the interlayer insulating film 26 having a flat surface can be formed. Further, the PSG film melts well during reflow (for example, about 1000 ° C.). Therefore, the PSG film can be satisfactorily embedded in the cavity portion 25. The interlayer insulating film 26 is more preferably a BPSG (Boron Phosphorus Silicon Glass) film in which B (boron) ions are contained in the SiO ₂ in addition to P (phosphorus) ions. The BPSG film melts at a lower temperature (for example, about 800 ° C.) than the PSG film. Therefore, the BPSG film can be more satisfactorily embedded in the cavity portion 25, and the interlayer insulating film 26 having a more flat surface can be formed.

On the other hand, when Al ₂ O ₃ or SiN is adopted as the insulating material of the interlayer insulating film 26, the intermediate insulating film 30 has a stacked structure in which Al ₂ O ₃ or SiN is stacked on the gate insulating film 21 (SiO ₂ ). including. According to this configuration, since the portion (connection interface) where SiC epitaxial layer 14 and intermediate insulating film 30 are in contact is formed by gate insulating film 21, the channel mobility of carriers flowing in channel region 22 can be improved. On the other hand, since the interlayer insulating film 26 having a dielectric constant higher than that of SiO ₂ is formed on the gate insulating film 21, the interlayer insulating film 26 can increase the dielectric constant of the intermediate insulating film 30.

The intermediate insulating film 30 formed in this way has a thickness that is twice or more (more specifically, two to 25 times or more) the thickness of the gate insulating film 21, thereby A portion of the insulating film 21 where an electric field is easily applied (that is, a central portion between the p ⁻ type body regions 17 adjacent to each other) is formed thicker than the other portions.
FIG. 4 is a table showing the relationship between the electric field strengths at the time of dielectric breakdown of SiO ₂ , SiC and Si.

Referring to the table of FIG. 4, SiO ₂ of the electric field at the time of semiconductor breakdown of SiC (= 6.4MV / cm) is provided with a SiO ₂ field at the semiconductor breakdown of Si (= 0.77MV / cm) In comparison, the value is close to the electric field (= 8 MV / cm to 11 MV / cm) at the time of dielectric breakdown of SiO ₂ . From this, it can be seen that in the case of a SiC semiconductor device, the gate insulating film (SiO ₂ ) is more easily broken than in the Si semiconductor device. Therefore, as in the present embodiment, the gate insulating film 30 is formed by forming the intermediate insulating film 30 thicker than the gate insulating film 21 while forming the cavity 25 on the central portion of the JFET region 18 where the electric field tends to be the highest. It can be seen that the destruction of the film 21 (SiO ₂ ) can be effectively suppressed. Further, it can be seen that such an intermediate insulating film 30 is particularly effective in the SiC semiconductor device.

The electric field of SiO ₂ at the time of SiC (or Si) semiconductor breakdown is calculated by (dielectric constant of SiC / dielectric constant of SiO ₂ ) × dielectric breakdown voltage of SiC (or Si).
Referring again to FIG. 3A and FIG. 3B, a contact hole 33 is formed in the interlayer insulating film 26. In the contact hole 33, the entire p ⁺ type body contact region 20 and the inner periphery of the n ⁺ type source region 19 are exposed.

A source electrode 34 is formed on the interlayer insulating film 26. The source electrode 34 is collectively connected to the p ⁺ type body contact region 20 and the n ⁺ type source region 19 of all the unit cells 11 through the contact holes 33. That is, the source electrode 34 is a common wiring for all the unit cells 11. The source electrode 34 may have a structure in which a Ti / TiN layer 35 and an Al layer are stacked in order from the contact side with the SiC epitaxial layer 14. The Ti / TiN layer 35 is a laminated film in which a Ti layer as an adhesion layer is provided on the SiC epitaxial layer 14 side, and a TiN layer as a barrier layer is laminated on the Ti layer. The barrier layer prevents constituent atoms (Al atoms) of the Al layer from diffusing toward the SiC epitaxial layer 14 side. A passivation film (not shown) is partially formed on the source electrode 34, and a portion without the passivation film is a source pad (not shown).

A drain electrode 36 is formed on the back surface of the n ⁺ -type SiC substrate 13 so as to cover the entire area thereof. The drain electrode 36 is a common wiring for all the unit cells 11. As the drain electrode 36, for example, a stacked structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au, and Ag are stacked in order from the n ⁺ type SiC substrate 13 can be employed.
Next, the relationship between the off direction of the n ⁺ -type SiC substrate 13 and the unit cell 11 formation direction will be described with reference to FIGS. FIG. 5 is a schematic view of the n ⁺ -type SiC substrate 13 and the SiC epitaxial layer 14 in a wafer state.

The SiC crystal constituting the n ⁺ -type SiC substrate 13 and the SiC epitaxial layer 14 of the semiconductor device 1 is a material showing crystal polymorphism (polytype) having various laminated structures with the same composition, and several hundred types or more Polytype exists. Examples of the polytype include 4H—SiC, 3CSiC, 6H—SiC, and 15R—SiC. Among these, 4H—SiC is preferable. In the following description, it is assumed that a 4H—SiC wafer is used as the n ⁺ -type SiC substrate 13.

The thickness t1 of the n ⁺ type SiC substrate 13 is, for example, 200 μm to 500 μm, and the thickness t2 of the SiC epitaxial layer 14 is thinner than the n ⁺ type SiC substrate 13, for example, 5 μm to 100 μm (for example, about 10 μm) ).
In this embodiment, the n ⁺ type SiC substrate 13 has an off angle θ of 2 ° to 8 ° (preferably about 4 °). For example, the surface of the n ⁺ -type SiC substrate 13 is a surface inclined at an off angle θ in the <11-20> direction (off direction) with respect to the (0001) plane. Expressions such as (0001) and <11-20> are so-called Miller indices, and are used to describe the lattice plane and lattice direction of the SiC crystal. The Miller index can be described with reference to FIGS.

FIG. 6 is a schematic diagram illustrating a unit cell having a crystal structure of 4H—SiC. FIG. 7 is a view of the unit cell of FIG. 6 viewed from directly above the (0001) plane. In the perspective view of the SiC crystal structure shown in the lower part of FIG. 6, only two layers are extracted from the four layers of the SiC laminated structure shown on the side.
As shown in FIG. 6, the crystal structure of 4H—SiC can be approximated by a hexagonal system, and four carbon atoms are bonded to one silicon atom. Four carbon atoms are located at four vertices of a regular tetrahedron having a silicon atom arranged at the center. Of these four carbon atoms, one silicon atom is positioned in the <0001> direction with respect to the carbon atom, and the other three carbon atoms are positioned on the <000-1> side with respect to the silicon atom.

<0001> and <000-1> are along the axial direction of the hexagonal column, and the surface (the top surface of the hexagonal column) having this <0001> as a normal line is the (0001) plane (Si plane). On the other hand, the surface (the lower surface of the hexagonal column) whose normal is <000-1> is the (000-1) surface (C surface).
Further, when viewed from directly above the (0001) plane and passing through vertices that are not adjacent to each other, the directions of the hexagonal note are a1 axis <2-1-10> and a2 axis <-12-10> and a3 axis <-1-120>.

As shown in FIG. 7, the direction passing through the apex between the a1 axis and the a2 axis is <11-20>, and the direction passing through the apex between the a2 axis and the a3 axis is <-2110>, The direction passing through the apex between the a3 axis and the a1 axis is <1-210>.
Between each of the six axes passing through each vertex of the hexagonal note, the axis which is inclined at an angle of 30 ° with respect to each axis on both sides thereof, and which is the normal line of each side surface of the hexagonal note, is a1. <10-10>, <1-100>, <0-110>, <-1010>, <-1100> and <01-10> in order clockwise from between the axis and <11-20> is there. Each plane (side surface of the hexagonal column) having these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

Here, in the n ⁺ -type SiC substrate 13 (4H—SiC wafer), basal plane dislocations may exist on the (0001) plane (Si plane) that is a plane perpendicular to the <0001> axial direction. . The basal plane dislocation is a dislocation on the (0001) plane and is a complete dislocation having a Burgers vector in the <11-20> axial direction. As described above, the n ⁺ type SiC substrate 13 is given a predetermined off angle from the viewpoint of favorably growing the SiC epitaxial layer 14. Accordingly, the basal plane dislocations in the ^{n +} -type SiC substrate 13, the basal plane dislocation structurally converted into threading edge dislocation near the interface between the SiC epitaxial layer 14 and the ^{n +} -type SiC substrate 13, as SiC epitaxial layer It is succeeded according to the step flow direction (that is, the <11-20> axial direction) which is the growth direction of 14.

  Such a basal plane dislocation generates a planar stacking fault along the <11-20> axial direction during forward operation (that is, in the on state), particularly in a device including a pn junction, and thus the forward direction. There is a risk of degrading characteristics (deterioration in forward direction). In addition, when a current flows in a direction perpendicular to the planar stacking fault, the forward current flow is inhibited by the stacking fault. As a result, the electrical resistance when the device is turned on increases and the power consumption increases. Therefore, in order to improve the reliability of the semiconductor device, it is necessary to reduce such defects.

  The VDMISFET 2 in the semiconductor device 1 has a body diode (parasitic diode) between the source electrode 34 and the drain electrode 36 (between the source and drain). For example, in the case where the unit cell 11 is formed along the <0001> axis direction, if a forward current flows through the body diode, a stacking fault occurs due to a basal plane dislocation, and the forward current flows due to the stacking fault. Be inhibited. As a result, the characteristics of the body diode fluctuate, leading to a decrease in reliability.

  Therefore, the unit cell 11 is preferably formed along the <11-20> axial direction (step flow direction which is the growth direction of the SiC epitaxial layer 14). According to this configuration, generation of stacking faults due to basal plane dislocations can be suppressed. Even if a stacking fault occurs, a forward current can flow in the direction along the stacking fault (that is, the <11-20> axial direction), so that deterioration of the body diode can be suppressed. Thus, a semiconductor device that exhibits good forward characteristics can be provided.

As described above, according to the semiconductor device 1, the n ⁺ type source region 19 and the SiC epitaxial layer 14 have a vertical structure in which the p ⁻ type body region 17 is disposed in the vertical direction. . In addition, the gate electrode 10 in the semiconductor device 1 is divided by the cavity 25, and an intermediate insulating film 30 thicker than the gate insulating film 10 is formed in the cavity 25.
Therefore, a voltage (for example, 1200 V) is applied so that n ⁺ -type source region 19 and SiC epitaxial layer 14 are on the (+) side in a state where semiconductor device 1 is off (that is, gate electrode 10 is at 0 V). Even so, since the gate electrode 10 and the JFET region 18 do not face each other with the gate insulating film 21 interposed therebetween, the cavity 25 does not become the reference position of the equipotential surface. For this reason, it is possible to effectively suppress the distribution of a relatively high potential equipotential surface in the JFET region 18 immediately below the cavity 25. In particular, since the equipotential surface of this potential is likely to be distributed so that the central portion of the JFET region 18 is the highest, the cavity 25 (intermediate insulating film 30) is formed on the central portion of the JFET region 18 as in the semiconductor device 1. ) Can effectively mitigate the application of a high electric field to the JFET region 18.

Furthermore, since the intermediate insulating film 30 thicker than the gate insulating film 21 is formed in addition to the gate insulating film 21 on the region where the electric field can be relaxed, the dielectric breakdown in the JFET region 18 can be effectively suppressed. As a result, it is possible to provide the semiconductor device 1 that has excellent pressure resistance and can be manufactured with high yield.
In addition, according to this configuration, since the gate electrode 10 is formed on the channel region 22, the ON operation of the VDMISFET 2 is not hindered. Furthermore, the cavity 25 can reduce the area of the gate electrode 10 (more specifically, the facing area where the surface of the gate electrode 10 and the surface of the SiC epitaxial layer 14 face each other). Thereby, the capacity | capacitance between the gate electrode 10 and the SiC epitaxial layer 14 can be reduced.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG. FIG. 8 is a flowchart for explaining an example of the manufacturing process of the semiconductor device 1 shown in FIG.
To manufacture the semiconductor device 1, first, an n ⁺ type SiC substrate 13 is prepared. The n ⁺ -type SiC substrate 13 is a 4H—SiC wafer provided with a predetermined off angle. Next, on the surface (Si surface) of the n ⁺ -type SiC substrate 13 by an epitaxial growth method such as a CVD (Chemical Vapor Deposition) method or an LPE (Liquid Phase Epitaxy) method, An SiC crystal is grown while introducing an n-type impurity (for example, N (nitrogen)) (step S1). As a result, n ⁻ type SiC epitaxial layer 14 is formed on n ⁺ type SiC substrate 13.

Next, using a mask having an opening in a portion where p ⁻ type body region 17 (p ⁻ type body connection region 16) is to be formed, p type impurities (for example, Al (aluminum)) are applied to the surface of SiC epitaxial layer 14. (Step S2). Thereby, p ⁻ type body region 17 (p ⁻ type body connection region 16) is formed in the surface layer portion of SiC epitaxial layer 14. In addition, a drift region that maintains the state after epitaxial growth is formed in the base layer portion of SiC epitaxial layer 14.

Next, an n-type impurity (for example, P (phosphorus)) is implanted into the p ⁻ -type body region 17 using a mask having an opening in a region where the n ⁺ -type source region 19 is to be formed (step S3). As a result, an n ⁺ type source region 19 is formed in the surface layer portion of the p ⁻ type body region 17. Next, a p-type impurity (for example, Al) is implanted into the p ⁻ -type body region 17 using a mask having an opening in a region where the p ⁺ -type body contact region 20 is to be formed (step S4). Thereby, the p ⁺ type body contact region 20 is formed.

  Next, for example, SiC epitaxial layer 14 is annealed (heat treated) at 1400 ° C. to 2000 ° C. for 2 to 10 minutes (step S5). Thereby, ions of n-type impurity and p-type impurity implanted into the surface layer portion of SiC epitaxial layer 14 are activated. Annealing treatment of SiC epitaxial layer 14 can be performed, for example, by controlling a resistance heating furnace and a high frequency induction heating furnace at an appropriate temperature.

  Next, the surface of SiC epitaxial layer 14 is thermally oxidized to form gate insulating film 21 that covers the entire surface of SiC epitaxial layer 14 (step S6). Next, a polysilicon material is deposited on SiC epitaxial layer 14 by introducing a p-type impurity (for example, B (boron)) by CVD (step S7). Of course, the introduction of impurities into the polysilicon material may be performed by ion implantation. Next, unnecessary portions of the deposited polysilicon material are removed by dry etching (step S8). As a result, the gate electrode 10 having the cavity 25 is formed.

Then, for example, depositing a SiO ₂ containing SiO ₂ or P (phosphorus) ions and B (boron) ions, including P (phosphorus) ions on the SiC epitaxial layer 14 (step S9). Next, SiO ₂ is melted by reflow (for example, 800 ° C. to 1000 ° C.) (step S 10) to refill the cavity 25 of the gate electrode 10 and cover the surface of the gate electrode 10 with the interlayer insulating film 26 (PSG). Film or BPSG film).

  Next, the interlayer insulating film 26 and the gate insulating film 21 are successively patterned to form the contact hole 33 (step S11). Next, for example, Ti, TiN, and Al are sequentially sputtered on the interlayer insulating film 26 to form the source electrode 34 (step S12). Further, Ti, Ni, Au, and Ag are sequentially sputtered on the back surface of the SiC substrate to form the drain electrode 36. Thereafter, the gate pad 3 and the like are formed, whereby the semiconductor device 1 shown in FIG. 1 is obtained.

FIG. 9 is a schematic cross-sectional view of a semiconductor device 51 according to the second embodiment of the present invention.
The semiconductor device 51 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment described above in that an n ⁺ -type source region 59 is formed instead of the n ⁺ -type source region 19, and An n ⁺ -type impurity region 52 is formed between adjacent p ⁻ -type body regions 17, and a gate insulating film 50 is formed instead of the gate insulating film 21. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment described above. 9, parts corresponding to those shown in FIGS. 1 to 8 are given the same reference numerals, and description thereof is omitted.

The n ⁺ type source region 59 according to the second embodiment is formed with the same shape and depth as the n ⁺ type source region 19 according to the first embodiment described above. The n type impurity concentration of the n ⁺ type source region 59 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²² cm ⁻³ , more preferably 1 × 10 ²⁰ cm ⁻³ to 1 × 10 ²² cm ⁻³ . is there.
The n ⁺ -type impurity region 52 is formed in the surface layer portion of the JFET region 18. More specifically, the n ⁺ -type impurity region 52 is formed in a substantially rectangular shape along the stripe direction of the gate electrode 10 in the central portion of the JFET region 18. N ⁺ -type impurity region 52 is formed at a position spaced from the boundary between p ⁻ -type body region 17 and JFET region 18. The n ⁺ type impurity region 52 is formed with the same depth and concentration as the n ⁺ type source region 59.

The gate insulating film 50 according to the second embodiment includes a first region 53 that covers the entire area of the JFET region 18, a portion that surrounds the n ⁺ -type source region 59 in each p ⁻ -type body region 17, and the n ⁺ -type source region 59. 2nd area | region 54 which covers an outer peripheral part. Both the first and second regions 53 and 54 of the gate insulating film 50 are selectively formed thick on the region into which a high concentration impurity is implanted. That is, the gate insulating film 50 includes a first portion 50 a in contact with the n ⁺ -type impurity region 52, a second portion 50 b in contact with the p ⁻ -type body region 17, and a third portion 50 c in contact with the n ⁺ -type source region 59.

The lower interface (interface with the n ⁺ -type impurity region 52) of the first portion 50a and the lower interface (interface with the n ⁺ -type source region 59) of the third portion 50c are both below the second portion 50b. It is located below the interface (interface with p ⁻ type body region 17) (n ⁺ type SiC substrate 13 side, deeper from the surface of SiC epitaxial layer 14). The upper interface (interface with the interlayer insulating film 26) of the first portion 50a and the upper interface (interface with the gate electrode 10) of the third portion 50c are both the upper interface (gate electrode 10 and the second electrode 50b). Is located above the gate electrode 10 side (position farther from the surface of the SiC epitaxial layer 14).

  Accordingly, the film thickness T1 of the first portion 50a and the film thickness T3 of the third portion 50c in the gate insulating film 50 are both larger than the film thickness T2 of the second portion 50b. More specifically, the film thickness T2 of the second portion 50b is, for example, 30 nm or more (for example, about 40 nm). On the other hand, the film thicknesses T1 and T3 of the first part 50a and the third part 50c are preferably 2.03 times or more the film thickness T1 of the first part 50a, for example, about 90 nm. . In this embodiment, the gate insulating film 50 is made of an oxide film containing nitrogen, for example, a silicon nitride oxide film formed by thermal oxidation using a gas containing nitrogen and oxygen.

  In the direction perpendicular to the stripe direction of the gate electrode 10, bird's beaks are formed at both ends of the first portion 50a and at the end of the third portion 50c on the JFET region 18 side, respectively. On the other hand, no bird's beak is formed at the end of the third portion 50c opposite to the JFET region 18 side in the direction perpendicular to the stripe direction, and the thick portion is flush with the side surface of the interlayer insulating film 26. Thus, the contact hole 33 is exposed.

For such a gate insulating film 50, the process of step S3 may be changed as follows. That is, the mask having an opening in the region where the n ⁺ -type source region 19 is to be formed is changed to a mask having openings in the regions where the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 are to be formed. Next, when an n-type impurity (for example, P (phosphorus)) is implanted into SiC epitaxial layer 14, the temperature of SiC epitaxial layer 14 is maintained at 150 ° C. or lower (for example, room temperature). The reason for maintaining the temperature of SiC epitaxial layer 14 at 150 ° C. or lower during ion implantation is to prevent crystallization of n ⁺ -type source region 59 and n ⁺ -type impurity region 52. Thereby, the thick gate insulating film 50 can be formed on the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 during the thermal oxidation process in step S6.

That is, in the thermal oxidation process of step S6, the gate insulating film 50 made of a silicon nitride oxide (SiN) film is formed by thermal oxidation (for example, about 1200 ° C. for half a day to two days) in an atmosphere containing nitrogen and oxygen. It is formed. As described above, the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 are implanted with n-type impurity ions so as to have a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. , N ⁺ type source region 59 and n ⁺ type impurity region 52 are performed at a low temperature (150 ° C. or lower) at which crystallization does not occur. Therefore, when the gate insulating film 50 is formed by thermal oxidation, the film thicknesses T1 and T3 of the first portion 50a and the third portion 50c in contact with the n ⁺ type source region 59 and the n ⁺ type impurity region 52 are locally increased. . Thereby, the film thicknesses T1 and T3 of the first part 50a and the third part 50c are larger than the film thickness T2 of the second part 50b in contact with the p ⁻ type body region 17.

As described above, in the semiconductor device 51, the film thicknesses T1 and T3 of the first portion 50a in contact with the n ⁺ -type impurity region 52 and the third portion 50c in contact with the n ⁺ -type source region 59 in the gate insulating film 50 are p ^- greater than the thickness T2 of the second portion 50b in contact with the mold body region 17. Thereby, since the film thickness of the intermediate insulating film 30 can be formed much thicker, the dielectric breakdown in the JFET region 18 can be further suppressed.

Further, in the semiconductor device 51, when an electric field is applied to the gate insulating film 50, the electric field in the third portion 50c in contact with the n ⁺ -type source region 59 can be relaxed, so that the leakage current in the third portion 50c can be suppressed. Therefore, since the dielectric breakdown in the third portion 50c in contact with the n ⁺ -type source region 59 can be suppressed, the long-term reliability of the entire gate insulating film 50 can be easily ensured. Thereby, the reliability of the whole semiconductor device can be easily secured.

Further, according to the semiconductor device 51, the gate insulating film 50 includes a SiN higher dielectric constant than SiO _2. Therefore, the intermediate insulating film 30 containing Al ₂ O ₃ or SiN can be formed. According to this configuration, since the dielectric constant is higher than when the intermediate insulating film 30 includes SiO ₂ , it is possible to further alleviate that a high electric field is applied to the gate insulating film 21.
Moreover, since such a gate insulating film 50 can be formed only by devising a mask layout, the manufacturing process is not complicated.

FIG. 10 is a schematic cross-sectional view of a semiconductor device 61 according to the third embodiment of the present invention.
The semiconductor device 61 according to the third embodiment is different from the semiconductor device 1 according to the first embodiment described above in that a gate electrode 60 is employed instead of the gate electrode 10. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment described above. 10, parts corresponding to those shown in FIGS. 1 to 9 are given the same reference numerals, and description thereof will be omitted.

The gate electrode 60 according to the third embodiment has a chamfered corner at its upper end, and has a taper angle of 5 degrees or more. Such a taper angle can be formed simply by changing the etching method in step S8. Thereby, in step S <b> 9, the interlayer insulating film 26 can be embedded more satisfactorily in the cavity 25 of the gate electrode 60.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.

  For example, in each of the above-described embodiments, an example in which the cavity 25 is formed in the gate electrodes 10 and 60 along the stripe direction of the gate electrodes 10 and 60 has been described. May be formed in the stripe direction at intervals. Further, a plurality of stripe-shaped cavities 25 may be formed along the stripe direction at intervals.

In each of the above-described embodiments, the gate electrodes 10 and 60 are formed in a stripe shape. However, the gate electrodes 10 and 60 are arranged in a lattice shape (ladder shape) as shown in FIG. It may be.
FIG. 11 is a schematic enlarged plan view of a semiconductor device 81 according to a modification.
The semiconductor device 81 according to the modification differs from the semiconductor device 1 according to the first embodiment described above in that a matrix-like (lattice-like) VDMISFET 72 is formed instead of the stripe-like VDMISFET 2, and the stripe Instead of the gate electrode 10, a grid (ladder) gate electrode 70 is formed.

Since semiconductor device 81 has a cross-sectional structure equivalent to the cross-sectional structure shown in FIG. 3, only the arrangement of gate electrode 70 and p ⁻ -type body region 77 constituting VMISFET 72 is shown in FIG. The illustration and description of other configurations are omitted.
As shown in FIG. 11, a plurality of p ⁻ type body regions 77 are formed in the surface layer portion of SiC epitaxial layer 14. The plurality of p ⁻ -type body regions 77 are formed in a square matrix with equal intervals in the row direction and the column direction.

Gate electrode 70 is formed so as to straddle the boundary line between each p ⁻ type body region 77 and SiC epitaxial layer 14. A first cavity 75 that divides the gate electrode 70 in the column direction is formed in the gate electrode 70 between the p ⁻ type body regions 77 adjacent to each other in the row direction. On the other hand, a second cavity 76 that selectively divides the gate electrode 70 in the row direction is selectively formed in the gate electrode 70 between the p ⁻ type body regions 77 adjacent to each other in the column direction. As a result, the gate electrode 70 is formed in a substantially square ring shape in plan view. The gate electrodes 70 adjacent to each other in the column direction are electrically connected to each other via a gate electrode connection portion 70a.

  The gate electrode connection portion 70a is formed integrally with each gate electrode 70 adjacent in the column direction at the positions of both ends in the longitudinal direction where the second cavity portion 76 extends in the row direction. Thus, a ladder-like gate electrode 70 is formed along the column direction. One end and / or the other end in the longitudinal direction of the gate electrode 70 is connected to the gate wiring 6 (see FIG. 1), as in the first embodiment. The intermediate insulating film 30 is formed in the first and second cavities 75 and 76 with the same configuration as that of the first embodiment described above.

  In this modification, the gate electrode connection portions 70a are formed at the positions of both end portions in the longitudinal direction of the second cavity portion 76. However, the second cavity portion 76 is not formed and the second cavity portion 76 is formed in the column direction. Adjacent gate electrodes 70 may be directly connected to each other. Further, in this modification, an example is shown in which the first cavity portion 75 that divides the gate electrode 70 in the column direction is formed. However, the first cavity portion 75 has the same configuration as the second cavity portion 76. A lattice-like gate electrode 70 may be formed by forming the structure.

Here, when the first and second cavities 75 and 76 are formed so as to extend in the entire row direction and the column direction without forming the gate electrode connection part 70a, the closed ring gate electrode 70 is formed. Therefore, as a result of the electrical isolation between the gate electrode 70 and the gate wiring 6, the VDMSET 72 cannot operate. On the other hand, according to the semiconductor device 81 of the present modification, each annular gate electrode 70 is electrically connected to the gate wiring 6 through the gate electrode connection portion 70a. Therefore, unlike the case of the first embodiment described above, it is possible to relax the electric field in the entire region between the p ⁻ type body regions 77 adjacent to each other in the row direction and the column direction (that is, the JFET region 18 (see FIG. 3)). However, the electric field can be relaxed in the JFET region 18 in the entire column direction and part of the row direction. That is, in the aspect in which the gate electrode 70 and the gate wiring 6 are electrically connected, if the first and second cavities 75 and 76 (intermediate insulating film 30) are formed in the JFET region 18 where an electric field is easily applied. The dielectric breakdown in the JFET region 18 can be suppressed.

In the first and third embodiments described above, the example in which the gate insulating film 21 made of a silicon oxide film (SiO ₂ ) is formed is shown. However, the gate insulating film 21 is replaced with SiO ₂ by Al ₂ O. ₃ or SiN. When the gate insulating film 21 is made of Al ₂ O ₃ or SiN, the intermediate insulating film 30 can be formed of Al ₂ O ₃ or SiN. According to this configuration, since the dielectric constant is higher than when the intermediate insulating film 30 is made of SiO ₂ , the electric field in the JFET region 18 can be more effectively relaxed.

In the first and third embodiments described above, the intermediate insulating film 30 may be formed separately from the gate insulating film 21. That is, the gate insulating film 21 in the region outside the cavity 25 of the gate electrode 10 is formed of SiO ₂ , while the connection portion with the JFET region 18 in the intermediate insulating film 30 is formed of Al ₂ O ₃ or SiN. Good.
In the first and third embodiments described above, the connecting portion of the intermediate insulating film 30 with the JFET region 18 is formed by the gate insulating film 21, while the cavity 25 of the gate electrode 10 is formed by SiO ₂ , Al ₂ O. ₃ , or after being backfilled with SiN, an interlayer insulating film 26 may be further formed.

In each of the above-described embodiments, the example in which the interlayer insulating film 26 composed of only one layer is described has been described. However, the interlayer insulating film 26 is, of course, a plurality of insulating material films (SiO ₂ , Al ₂ O ₃ , Alternatively, SiN) may have a laminated structure in which a plurality of periods are laminated.
In each of the above-described embodiments, the interlayer insulating film 26 formed on the gate insulating film 21 in the cavity 25 has a film thickness substantially equal to the interlayer insulating film 26 formed so as to cover the gate electrode 10. However, it may be formed with a different thickness.

In each of the above-described embodiments, the p-type VDCMISFET can be configured by inverting the conductivity type of each semiconductor portion of the semiconductor device 1. That is, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
In each of the above-described embodiments, the example in which the VDMISFET 2 is formed in the active region 4 has been described. However, instead of the n ⁺ type SiC substrate 13 (drain region), a p ⁺ type SiC substrate (p ⁺ type collector region) is used. By adopting it, an IGBT (Insulated Gate Bipolar Transistor) may be formed. In this case, the source electrode 34 of the VDMISFET 2 corresponds to the emitter electrode of the IGBT.

  The semiconductor devices 1, 51, 61, 81 of the present invention constitute a drive circuit for driving an electric motor used as a power source for an electric vehicle (including a hybrid vehicle), a train, an industrial robot, etc., for example. It can be incorporated in a power module used in an inverter circuit. It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 Semiconductor Device 10 Gate Electrode 12 SiC Semiconductor Layer 17 p ⁻ Type Body Region 18 JFET Region 19 n ⁺ Type Source Type Region 21 Gate Insulating Film 22 Channel Region 25 Cavity 26 Interlayer Insulating Film 30 Intermediate Insulating Film 50 Gate Insulating Film 51 Semiconductor Device 59 n ⁺ type source type region 60 Gate electrode 61 Semiconductor device 70 Gate electrode 75 First cavity portion 76 Second cavity portion 77 p ⁻ type body region 81 Semiconductor device L Channel length T1 Film thickness T2 Film thickness T3 Film thickness WD Width WJ Width θ Off angle

Claims (25)

A first conductivity type SiC semiconductor layer;
A plurality of second conductivity type body regions formed on the surface layer portion of the SiC semiconductor layer at intervals,
A source region of a first conductivity type formed in a surface layer portion of each of the body regions spaced from the periphery of the body region;
A cavity portion is formed across the plurality of body regions, is opposed to a channel region between a periphery of each body region and the source region with a gate insulating film interposed therebetween, and is an intermediate region between adjacent body regions. A gate electrode selectively separated by
A semiconductor device including an intermediate insulating film formed in the cavity and thicker than the gate insulating film.   The semiconductor device according to claim 1, wherein the hollow portion of the gate electrode is formed on a central portion of the intermediate region. The plurality of body regions are formed in a stripe shape having one end and the other end,
The semiconductor device according to claim 1, wherein the gate electrode straddles adjacent body regions at the one end and / or the other end of the body region.   The cavity of the gate electrode is formed so as to be inward of the intermediate region at a distance from a boundary between each body region and the intermediate region. The semiconductor device according to item.   The semiconductor device according to claim 1, wherein the intermediate region has a width of 0.1 μm to 50 μm.   The semiconductor device according to claim 1, wherein the intermediate insulating film has a thickness that is twice or more that of the gate insulating film. The semiconductor device according to claim 1, wherein the intermediate insulating film includes a SiO ₂ film. The semiconductor device according to claim 7, wherein the SiO ₂ film contains P (phosphorus) ions. The semiconductor device according to claim 8, wherein the SiO ₂ film further contains B (boron) ions. The semiconductor device according to claim 1, wherein the intermediate insulating film includes an insulating material film having a dielectric constant higher than that of SiO ₂ . The semiconductor device according to claim 10, wherein the insulating material film is made of Al ₂ O ₃ or SiN. The semiconductor device according to claim 1, wherein the insulating material film includes a stacked structure in which an SiO ₂ film and an Al ₂ O ₃ film are stacked in this order. The semiconductor device according to claim 1, wherein the intermediate insulating film includes a stacked structure in which a SiO ₂ film and a SiN film are stacked in this order.   The semiconductor device according to claim 1, wherein the gate electrode is made of polysilicon.   The semiconductor device according to claim 14, wherein the polysilicon includes B (boron) ions.   The semiconductor device according to claim 1, wherein the gate electrode is made of a metal material.   The semiconductor device according to claim 16, wherein the metal material is made of Al, Cu, or AlCu.   The semiconductor device according to claim 1, wherein the gate electrode has a thickness of 2 μm or less.   19. The semiconductor device according to claim 1, wherein each of the body regions is formed along a <11-20> axial direction.   20. The gate insulating film according to claim 1, wherein the gate insulating film has a first thickness on the channel region, and has a second thickness on the source region that is thicker than the first thickness. The semiconductor device as described in any one.   21. The semiconductor device according to claim 20, wherein the second thickness of the gate insulating film is 2.03 times or more of the first thickness.   The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 1 μm or less on the channel region. An interlayer insulating film formed on the SiC semiconductor layer so as to cover the gate electrode and embedded in the cavity;
The semiconductor device according to claim 1, wherein the intermediate insulating film is formed using a buried portion of the interlayer insulating film.   24. The semiconductor device according to claim 23, wherein an amount of the interlayer insulating film embedded in the cavity is substantially equal to a thickness of a portion of the interlayer insulating film on the gate electrode.   The semiconductor device according to any one of claims 1 to 24, wherein a taper angle of 5 degrees or more is formed at an upper end portion of the gate electrode.

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