JP2015191677A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read information held in an anti-fuse element with high sensitivity.SOLUTION: A semiconductor device comprises: a first inverter circuit 133 generating a determination signal AFBLB based on the potential of a sense node AFBL; a bias transistor 134 connected between VPERI wiring and the sense node AFBL and causing bias current IBIAS to flow to the sense node AFBL according to a bias potential BIAS; an anti-fuse element AF1 connected between power supply wiring VBBSV and the sense node AFBL; and a bias generation circuit generating the bias potential BIAS. The bias generation circuit controls the level of the bias potential BIAS in accordance with reference current flowing through the anti-fuse element (replica of AF1). According to the invention, a reading sensitivity can be improved because the bias current changes according to a resistance variation of the anti-fuse element.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an antifuse element.

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective memory cell is replaced with a redundant memory cell, whereby the defective memory cell is relieved. The address of the defective memory cell is programmed in a nonvolatile memory element such as an antifuse element in the manufacturing stage (see Patent Document 1).

  Examples of the nonvolatile memory element include a fuse circuit, a fuse element, and an antifuse element. In particular, the anti-fuse element is insulated between both ends in the initial state, and transitions to a conductive state if dielectric breakdown is caused by applying a high voltage between both ends. And after dielectric breakdown, since it cannot return from a conduction | electrical_connection state to an insulation state, memory | storage of irreversible and non-volatile information is attained.

  Here, it is known that the resistance value of the antifuse element after dielectric breakdown is not necessarily constant and has a large variation. That is, the resistance value may be sufficiently low due to dielectric breakdown, or the resistance value may remain relatively high even after dielectric breakdown. For this reason, the sense circuit that reads out information stored in the antifuse element is a highly sensitive circuit so that it can correctly determine whether or not the breakdown is present even when there is such a variation in resistance value. It is necessary to adopt a configuration.

JP 2007-80302 A

  In order to read the information stored in the antifuse element with high sensitivity, it is effective to control the bias current flowing through the sense circuit to an optimum value. However, since the optimum value of the bias current varies depending on the resistance variation of the antifuse element, the logic threshold value of the sense circuit, etc., when the bias current is set to a fixed value, it is not always possible to sufficiently increase the read sensitivity. could not.

  A semiconductor device according to an aspect of the present invention includes first and second power supply lines to which first and second potentials are supplied, a determination circuit that generates a determination signal based on a potential of a sense node, and the first A bias circuit connected between one power supply line and the sense node, and passing a bias current corresponding to a bias potential to the sense node; and a second circuit connected between the second power supply line and the sense node. An antifuse element, and a bias generation circuit that generates the bias potential, the bias generation circuit including a second antifuse element connected between the first and second power supply lines, And an amplifier circuit that controls the level of the bias potential in accordance with a reference current flowing through the second antifuse element.

  A semiconductor device according to another aspect of the present invention includes first and second power supply lines to which first and second potentials are supplied, a first inverter circuit having an input node connected to a sense node, A bias circuit that is connected between the first power supply line and the sense node, and that supplies a bias current corresponding to a bias potential to the sense node, and is connected between the second power supply line and the sense node. A first inverter circuit, a second inverter circuit that outputs a reference potential from the output node, a bias generation circuit that outputs the bias potential according to the reference potential; It is characterized by providing.

  According to the present invention, since the bias current changes according to the resistance variation of the antifuse element and the actual logic threshold value of the sense circuit, it is possible to increase the read sensitivity.

1 is a block diagram showing a configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. FIG. 2 is a block diagram for explaining a configuration of antifuse circuits 51a and 52a and a pump circuit 100 according to the first embodiment. 2 is a circuit diagram of a load circuit 110, a connect circuit 120, and a sense circuit 130 according to the first embodiment. FIG. 3 is a circuit diagram of a logical threshold monitor 140. FIG. 3 is a circuit diagram of a bias generation circuit 150. FIG. 3 is a circuit diagram of a differential circuit 152. FIG. FIG. 6 is a timing chart for explaining the operation of the first embodiment. 5 is a circuit diagram of a load circuit 110, a connect circuit 120, and a sense circuit 130 according to a modification of the first embodiment. It is a circuit diagram of a reference potential generation circuit 140X that can be used in place of the logic threshold value monitor 140. FIG. 3 is a circuit diagram of a bias generation circuit 150X that can be used in place of the bias generation circuit 150. FIG. 5 is a block diagram for explaining a configuration of antifuse circuits 51a and 52a and a pump circuit 100 according to a second embodiment. FIG. 6 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a verify bit selection circuit 160 according to a second embodiment. FIG. 10 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a verify bit selection circuit 160 according to a modification of the second embodiment. FIG. 6 is a circuit diagram of a bias generation circuit 150 according to a second embodiment. It is a timing diagram for demonstrating operation | movement of 2nd Embodiment. It is a block diagram for demonstrating the structure of the antifuse circuits 51a and 52a and the pump circuit 100 by 3rd Embodiment. 3 is a circuit diagram of an antifuse array 170. FIG. 3 is a circuit diagram of a driver circuit 191. FIG. It is a circuit diagram of the load circuit 110 in 3rd Embodiment. It is a circuit diagram of the connection circuit 120 in 3rd Embodiment. It is a circuit diagram of the sense circuit 130 in 3rd Embodiment. 3 is a circuit diagram of a latch block 180. FIG. 2 is a circuit diagram of a latch circuit 200. FIG. FIG. 6 is a circuit diagram of a bias generation circuit 150 according to a third embodiment. It is a timing diagram for demonstrating operation | movement of 3rd Embodiment. FIG. 10 is a circuit diagram of a bias generation circuit 150 according to a fourth modification example of the first embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to each of the first to third preferred embodiments of the present invention.

  The semiconductor device 10 is a DDR4 (Double Data Rate 4) type synchronous DRAM. As external terminals, clock terminals 11a and 11b, command terminals 12a to 12d, an address terminal 13, a data input / output terminal 14 and a power supply terminal 15v, 15s at least.

  Complementary external clock signals CK and CKB are supplied to the clock terminals 11a and 11b, respectively. The external clock signals CK and CKB are supplied to the internal clock generation circuit 21. The internal clock generation circuit 21 generates an internal clock signal ICLK and supplies it to the DLL circuit 22 and various internal circuits. The DLL circuit 22 receives the internal clock signal ICLK, generates an internal clock signal LCLK for output, and supplies it to the data input / output circuit 80.

  The command terminals 12a to 12d are supplied with a command signal CMD including a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a chip select signal CS, and the like. These command signals CMD are supplied to the command decoder 31. The command decoder 31 generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock signal ICLK.

  The address terminal 13 is supplied with an address signal ADD composed of a plurality of bits. Address signal ADD is supplied to address latch circuit 41 and latched in synchronization with internal clock signal ICLK. Of the address signal ADD latched by the address latch circuit 41, the row address XA is supplied to the row decoder 51, and the column address YA is supplied to the column decoder 52. Further, the redundant address RA is supplied to the redundant address decoder 55 at the time of programming to the antifuse element described later.

  The row decoder 51 selects one of the word lines WL included in the memory cell array 60 based on the row address XA.

  The row decoder 51 includes an antifuse circuit 51a and an address comparison circuit 51b. However, the antifuse circuit 51a is not limited to being configured in the row decode, and may be configured in a different area in the chip.

  The antifuse circuit 51a is a non-volatile storage element that stores information in a non-volatile manner, and may be, for example, a fuse circuit, a fuse element, or an antifuse element. In particular, the antifuse circuit 51a stores information such as a defective address. When the row address XA corresponding to the defective word line WL is input, the redundant word line RWL is selected instead of the word line WL. As a result, the redundant memory cell RMC can be accessed instead of the defective memory cell MC.

  The row address XA of the defective word line WL is stored in the antifuse circuit 51a, and the row address XA requested to be accessed and the row address XA stored in the antifuse circuit 51a are compared by the address comparison circuit 51b. . The operation of the antifuse circuit 51 a is controlled by the antifuse control circuit 54 and the redundant address decoder 55.

  The memory cell array 60 includes intersecting word lines WL and bit lines BL, and the memory cells MC are arranged at the intersections. The bit line BL is connected to the corresponding sense amplifier SA in the sense amplifier array 53.

  The column decoder 52 selects the bit line BL based on the column address YA.

  The column decoder 52 includes an antifuse circuit 52a and an address comparison circuit 52b. The antifuse circuit 52a is not limited to being configured in the column decode, but may be configured in a different region in the chip. Further, the antifuse circuits 51a and 52a may be configured by a plurality of antifuses arranged in an array.

  The anti-fuse circuit 52a is a non-volatile storage element that stores information in a non-volatile manner, and may be, for example, a fuse circuit, a fuse element, or an anti-fuse element. In particular, the antifuse circuit 52a stores defective address information and the like. When the column address YA corresponding to the defective bit line BL is input, the redundant bit line RBL is selected instead of the bit line BL. As a result, the redundant memory cell RMC can be accessed instead of the defective memory cell MC.

  The column address YA of the defective bit line BL is stored in the antifuse circuit 52a, and the column address YA requested to be accessed is compared with the column address YA stored in the antifuse circuit 52a by the address comparison circuit 52b. . The operation of the antifuse circuit 52 a is controlled by the antifuse control circuit 54 and the redundant address decoder 55.

  The bit line BL or redundant bit line RBL selected by the column decoder 52 is connected to the main amplifier 70 via the sense amplifier SA and the main I / O wiring MIO. The main amplifier 70 amplifies the read data read from the memory cell via the main I / O wiring MIO during the read operation and supplies the read data to the read / write bus RWBS, and the read / write bus RWBS during the write operation. Is supplied to the main I / O wiring MIO.

  The read / write bus RWBS is connected to the data input / output circuit 80. The data input / output circuit 80 serially outputs the read data DQ read in parallel via the read / write bus RWBS from the data input / output terminal 14 and the write input serially input via the data input / output terminal 14. Data DQ is supplied in parallel to the read / write bus RWBS.

  The power supply terminals 15v and 15s are supplied with the power supply potential VDD and the ground potential VSS, respectively. These power supply terminals 15v and 15s are connected to a power supply circuit 90. The power supply circuit 90 generates various internal potentials based on the power supply potential VDD and the ground potential VSS.

  The internal potential generated by the power supply circuit 90 includes internal potentials VPP, VARY, VPERI, and the like. The internal potential VPP is a potential generated by boosting the power supply potential VDD, and is mainly used in the row decoder 51. The internal potential VARY is a potential generated by stepping down the power supply potential VDD, and is mainly used in the sense amplifier row 53. The internal potential VPERI is a potential generated by stepping down the power supply potential VDD, and is used as a power supply potential in most circuit blocks.

  The internal potential VPP is also supplied to the pump circuit 100. The pump circuit 100 is a circuit that generates various potentials used during a connection operation and a load operation with respect to the antifuse circuits 51a and 52a. Here, the “connect operation” is a programming operation in which dielectric breakdown is caused by applying a high voltage across the antifuse element. Whether or not the antifuse element is broken down is determined by a “load operation”.

<First Embodiment>
FIG. 2 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the first embodiment.
As shown in FIG. 2, the antifuse circuits 51 a and 52 a include a load circuit 110, a connect circuit 120, and a sense circuit 130.
The load circuit 110 is a circuit block including an antifuse element, and is used during a connect operation and a load operation. The connect circuit 120 and the sense circuit 130 are used during a connect operation and a load operation, respectively.

  The load operation is controlled by a precharge signal PREB and a load signal LOADT supplied from the antifuse control circuit 54. The antifuse control circuit 54 is controlled by a reset signal RSTB that is activated when the semiconductor device 10 is initialized and a verify signal VRFY that is activated when the connect operation is verified.

  The connect operation is controlled by a select signal RSET and a redundant address RA supplied from the redundant address decoder 55. The redundant address decoder 55 is supplied with a redundant address RA (address of the defective word line WL or defective bit line BL) during the connection operation, and by decoding this, the antifuse circuit 51a, The redundant address RA is supplied to 52a.

  The sense circuit 130 senses information read from the antifuse element during the load operation and latches the sensed information to generate defective address information AFBLB that is a determination signal. The defective address information AFBLB is supplied to the address comparison circuits 51b and 52b. The address comparison circuits 51b and 52b compare the defective address information AFBLB with the row address XA or the column address YA, and if they do not match (mis-hit), the word line WL or the bit line based on the row address XA or the column address YA. Select BL. On the other hand, if the defective address information AFBLB matches the row address XA or the column address YA (hits), the redundant word line RWL or the redundant bit line RBL is selected.

  The pump circuit 100 includes a positive pump 101, a negative pump 102, and power switches 104 and 105.

  The positive pump 101 is a circuit that generates a high potential VPPC by a pumping operation using the internal potential VPP. The high potential VPPC is, for example, 5.0V. The high potential VPPC generated by the positive pump 101 is supplied to the power switch 104. The power switch 104 supplies either the high potential VPPC or the power supply potential VDD to the power supply wiring VPPSV based on the program signal PGPT. The power supply wiring VPPSV is connected to the connect circuit 120.

  The negative pump 102 is a circuit that generates a negative potential VBBC by a pumping operation using the internal potential VPP. The negative potential VBBC is, for example, −1.0V. The negative potential VBBC generated by the negative pump 102 is supplied to the power switch 105. The power switch 105 supplies either the negative potential VBBC or the ground potential VSS to the power supply wiring VBBSV based on the program signal PGNT. The power supply wiring VBBSV is connected to the load circuit 110. As an example, the power supply wiring VBBSV may be configured to be commonly connected to a plurality of antifuse elements AF in a configuration in which one antifuse element AF stores one bit.

  Here, the semiconductor device 10 according to the present embodiment further includes a logic threshold value monitor 140 and a bias generation circuit 150. A logic threshold monitor 140 generates a reference potential VREF.

  The bias generation circuit 150 generates a bias potential BIAS and supplies the generated bias potential BIAS to the antifuse circuits 51a and 52a.

  The reference potential VREF generated by the logic threshold monitor 140 is supplied to the bias generation circuit 150. The bias generation circuit 150 includes an amplifier circuit 151, a load circuit 210, and a connection circuit 220, and generates a bias potential BIAS. The bias potential BIAS is supplied to the sense circuit 130 and used during the load operation. Details of the logic threshold monitor 140 and the bias generation circuit 150 will be described later.

  FIG. 3 is a circuit diagram of the load circuit 110, the connect circuit 120, and the sense circuit 130 according to the first embodiment.

  As shown in FIG. 3, the load circuit 110 includes a first antifuse element AF1 connected between the connection node AFN1 and the power supply wiring VBBSV, and an N inserted between the connection node AFN1 and the sense node AFBL. A channel-type MOS transistor 111. Sense circuit 130 includes a sense node AFBL.

  The anti-fuse element AF1 is insulated in the initial state, and when a high voltage is applied between both ends by the connecting operation, the dielectric breakdown is brought about and the conductive state is established. The circuit shown in FIG. 3 is a circuit portion corresponding to one antifuse element AF1, and therefore, the circuits shown in FIG. 3 are provided in the semiconductor device 10 by the number of antifuse elements AF1. The required number of antifuse elements AF1 is the number of storable redundant addresses × the number of bits of redundant addresses. In addition, the antifuse element AF1 may be required for the enable bit.

  The transistor 111 is a switch for controlling the connection between the antifuse element AF1 and the sense node AFBL, and a load signal LOADT is supplied to the gate electrode. The substrate of the transistor 111 is connected to the power supply wiring VBBSV.

  The load signal LOADT is a signal that is activated to a high level during the load operation. During the load operation, the sense node AFBL is connected to the power supply wiring VBBSV via the antifuse element AF1.

  The connect circuit 120 includes a P-channel MOS transistor 121 connected between the power supply line VPPSV and the connection node AFN1. The gate electrode of transistor 121 receives the output signal of NAND gate circuit 122 that receives select signal RSET and the corresponding bit of redundant address RA. The select signal RSET is a signal assigned for each redundant address. When there are M + 1 redundant addresses that can be stored, the M + 1 bit select signal RSET is used. In the connect operation corresponding to the predetermined select signal RSET, if the logical level of the bit corresponding to the redundant address RA is high, the antifuse element AF1 is connected to the power supply wiring VPPSV.

  The sense circuit 130 includes a latch circuit in which an inverter circuit composed of a P-channel MOS transistor 131 and an N-channel MOS transistor 132 and a first inverter circuit 133 serving as a determination circuit are connected in a circulating manner. An input node of inverter circuit 133 is connected to sense node AFBL. The source of the transistor 131 is supplied with the internal potential VPERI, and the source of the transistor 132 is supplied with the ground potential VSS. The internal potential VPERI is, for example, 1.0V. A voltage (1.0 V) between the internal potential VPERI and the ground potential VSS is also used for the operation power supply of the inverter circuit 133.

  Here, the P-channel bias transistor 134 is connected between the transistor 131 and the sense node AFBL. The gate electrode of bias transistor 134 receives bias potential BIAS. The bias potential BIAS is supplied to the gate electrode of the bias transistor 134 from the bias generation circuit 150 shown in FIG.

  A current control circuit including the transistors 131 and 134 controls the amount of sense current flowing through the sense node AFBL in accordance with the bias potential BIAS.

  The P-channel type precharge transistor 135 is connected between the power supply line to which the internal potential VPERI is supplied and the sense node AFBL. The gate electrode of precharge transistor 135 receives precharge signal PREB. When the precharge signal PREB is activated to the low level, the sense node AFBL is precharged to the VPERI level (1.0 V).

  FIG. 4 is a circuit diagram of the logical threshold monitor 140.

  As shown in FIG. 4, the logic threshold monitor 140 includes a second inverter circuit 141 in which an input node and an output node are short-circuited, and a voltage supply circuit 142 that supplies an operating voltage to the inverter circuit 141. When the bias control signal BIASCONT is activated, the voltage supply circuit 142 supplies VPERI as an operation voltage to the inverter circuit 141. When the bias control signal BIASCONT is deactivated, the operating voltage supplied to the inverter circuit 141 is cut off, so that the current consumption by the logic threshold value monitor 140 is cut.

  The inverter circuit 141 is a replica of the inverter circuit 133 shown in FIG. Therefore, when the bias control signal BIASCONT is activated, the level of the reference potential VREF output from the output node of the inverter circuit 141 exactly matches the logic threshold value of the inverter circuit 133. The reference potential VREF generated in this way is supplied to the bias generation circuit 150.

  FIG. 5 is a circuit diagram of the bias generation circuit 150.

  As shown in FIG. 5, the bias generation circuit 150 includes an amplifier circuit 151, a load circuit 210, and a connect circuit 220. The load circuit 210 and the connect circuit 220 have a circuit configuration similar to that of the load circuit 110 and the connect circuit 120 shown in FIG.

  More specifically, the load circuit 210 includes a second antifuse element AF2 connected between the connection node AFN2 and the power supply wiring VBBSV, and an N channel inserted between the connection node AFN2 and the monitor node MN. Type MOS transistor 211. The antifuse element AF2 of the load circuit 210 is shown as one element in FIG. 5, but is not limited to this, and may be a plurality of antifuse elements as disclosed and detailed in FIG.

  The anti-fuse element AF2 is a replica of the anti-fuse element AF1 included in the load circuit 110, and the connect operation is executed in the manufacturing stage to be in a conductive state. Therefore, the resistance value of the antifuse element AF2 is a reproduction of the resistance value of the antifuse element AF1 after connection.

  The transistor 211 is a switch for controlling the connection between the antifuse element AF2 and the monitor node MN, and a bias control signal BIASCONT is supplied to its gate electrode. The bias control signal BIASCONT is a signal for activating the logic threshold value monitor 140 and the bias generation circuit 150, and becomes a high level during the load operation. Therefore, during the load operation, monitor node MN is connected to power supply wiring VBBSV via antifuse element AF2.

  The connect circuit 220 includes a P-channel MOS transistor 221 connected between the power supply line VPPSV and the connection node AFN2. The inverted bias program signal BIASPGT is supplied to the gate electrode of the transistor 221. The bias program signal BIASPGT is a signal for dielectric breakdown of the antifuse element AF2, and when this is activated to a high level, the antifuse element AF2 is connected to the power supply wiring VPPSV.

  The amplifier circuit 151 includes a differential circuit 152. One input node of the differential circuit 152 is connected to the monitor node MN, and a reference potential VREF is supplied to the other input node. As a result, the differential circuit 152 compares the potential of the monitor node MN with the reference potential VREF, and generates the bias potential BIAS based on the result.

  The amplifier circuit 151 further includes a P-channel MOS transistor 153 and an N-channel MOS transistor 154 connected in series between a wiring to which the internal potential VPERI is supplied and a wiring to which the ground potential VSS is supplied. An N-channel MOS transistor 155 connected between the output node of the circuit 152 and a wiring to which the ground potential VSS is supplied is provided.

  The transistor 153 has a gate electrode to which the bias potential BIAS is supplied, and the transistor 154 has a gate electrode to which the reference potential VREF is supplied. The transistor 155 has a gate electrode to which an inverted bias control signal BIASCONT is supplied. The monitor node MN is a connection point between the transistors 153 and 154.

  When the transistor 155 is turned off, the reference current IREF flows from the VPERI terminal to the VBBSV terminal via the transistor 153, the monitor node MN, the transistor 211, the connection node AFN2, and the antifuse element AF2. The reference current IREF corresponds to the bias current IBIAS flowing through the sense circuit 130.

  Here, the transistor 154 functions as a current sink for preventing the reference current IREF from becoming zero even before the antifuse element AF2 is programmed. This is because it is necessary to perform a load operation on the anti-fuse element for internal voltage adjustment before programming the anti-fuse element AF2, and at this time, the bias potential BIAS is prevented from being saturated to the VPERI level. It is to do.

  FIG. 6 is a circuit diagram of the differential circuit 152 shown in FIG.

  As shown in FIG. 6, the differential circuit 152 includes a pair of input transistors 157 and 158 having a common source connected to a constant current source 156, a current mirror circuit CM1 to which a current I1 flowing through the transistor 157 is input, a transistor A current mirror circuit CM2 to which a current I2 flowing through 158 is input; and a current mirror circuit CM3 to which a current I1 output from the current mirror circuit CM1 is input.

  A reference potential VREF is supplied to the gate electrode of the input transistor 157, and the gate electrode of the input transistor 158 is connected to the monitor node MN. Then, the output current paths of the current mirror circuits CM2 and CM3 are short-circuited, and the potential at the connection point is output as the bias potential BIAS.

  With this configuration, the bias potential BIAS (the level of the gate electrode of the transistor 153) is determined by the current difference ΔI (= I2−I1) between the current I1 and the current I2. Therefore, when the level of the monitor node MN is lower than the reference potential VREF, that is, when the resistance value of the anti-fuse element AF2 is relatively low, the current difference ΔI changes in the positive direction, so that the bias potential BIAS Will decline. As a result, the bias current IBIAS flowing through the sense circuit 130 increases. On the other hand, when the level of the monitor node MN is higher than the reference potential VREF, that is, when the resistance value of the antifuse element AF2 is relatively high, the current difference ΔI changes in the negative direction. BIAS goes up. As a result, the bias current IBIAS flowing through the sense circuit 130 decreases.

  By such a mechanism, the bias current IBIAS flowing through the sense circuit 130, that is, the amount of current flowing through the antifuse element AF1 is controlled according to the resistance value of the antifuse element AF2 included in the bias generation circuit 150.

  FIG. 7 is a timing chart for explaining the operation of the first embodiment.

  In the standby period T10, the program signals PGPT and PGNT are both at a low level, and therefore the power supply potential VDD is supplied to the power supply wiring VPPSV, and the ground potential VSS (0 V) is supplied to the power supply wiring VBBSV.

  In the connection period T11, the program signals PGPT and PGNT change to high level. Thus, the high potential VPPC (5.0 V) is supplied to the power supply wiring VPPSV, and the negative potential VBBC (−1.0 V) is supplied to the power supply wiring VBBSV. In this state, the select signal RSET sequentially changes to the high level, and each bit of the redundant address RA corresponding thereto is input to the connect circuit 120. The example shown in FIG. 7 shows a case where the select signal RSET is M + 1 bits (RSET <0> to RSET <M>) and the redundant address RA is n + 1 bits (RA <0> to RA <N>). .

  As a result, if the bit of the redundant address RA is at a high level, a connect voltage of about 6 V is applied to both ends of the antifuse element AF1 shown in FIG. 3, whereby the insulating film included in the antifuse element AF1 is formed. Breaks down. This operation is repeatedly executed until all redundant addresses RA are programmed by sequentially switching the select signal RSET to be activated.

  In the standby period T12, the program signal PGNT returns to the low level, and when the precharge period T13 is reached, the verify signal VRFY is activated to the high level and the precharge signal PREB is activated to the low level. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the verify period T14, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VBBSV via the antifuse element AF1. Therefore, a bias current IBIAS determined by the bias potential BIAS flows through the anti-fuse element AF1, and the potential of the sense node AFBL changes according to the amount of the current.

  Here, when the anti-fuse element AF1 is not connected (in an insulated state), the bias current IBIAS hardly flows through the anti-fuse element AF1, so that the potential of the sense node AFBL is pre-set as indicated by the symbol A. Maintain charge state.

  On the other hand, when the anti-fuse element AF1 is connected (when the anti-fuse element AF1 is in a conductive state), the bias current IBIAS flows through the anti-fuse element AF1, so that the potential of the sense node AFBL greatly decreases as indicated by the symbol B. To do.

  Further, when the antifuse element AF is connected (when it is in a conductive state), there are cases where the resistance value is relatively high and the resistance value is sufficiently low.

  When the anti-fuse element AF1 is connected (is in a conductive state) but its resistance value is relatively high, that is, in the half-connected state, the bias current IBIAS flowing through the anti-fuse element AF1 is small. In addition, as indicated by the symbol C, the decrease in the potential of the sense node AFBL becomes gradual. When the potential of the sense node AFBL falls below the logic threshold value of the sense circuit 130, the inverter circuit 133 is inverted and the level of the sense node AFBL is rapidly lowered via the transistor 132. Thereby, the information read from the antifuse element AF1 is latched.

  In the present embodiment, the bias current IBIAS flowing through the antifuse element AF1 is reproduced as the reference current IREF by the bias generation circuit 150, and the level of the bias potential BIAS changes accordingly.

  In the reconnect period T16, if there is an antifuse element AF1 that is not correctly connected as a result of the verify operation, the reconnect operation is performed on the antifuse element AF1 after the standby period T15 has elapsed. .

  In the waiting period T17, a series of programming is completed.

  Next, after the programming is completed, information is read from the antifuse element AF1 every time the semiconductor device 10 is reset.

  In the reset period T18, the reset signal RSTB is activated to a low level.

  In the precharge period T19, the precharge signal PREB is activated to a low level. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the load period T20, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VBBSV via the antifuse element AF1.

  The operation in the load period T20 is the same as the operation in the verify period T14 described above, and a difference occurs in the potential of the sense node AFBL depending on whether or not the antifuse element AF1 is connected.

  In the present embodiment, since the bias current IBIAS flowing through the antifuse element AF1 in the load period T20 is optimized according to the resistance value of the antifuse element AF1, the potential of the sense node AFBL is set even in the half-connected state. It can be sufficiently reduced.

  In addition, in this embodiment, since the reference potential VREF used in the bias generation circuit 150 is generated by the logic threshold monitor 140, the reference potential VREF corresponding to the actual logic threshold of the sense circuit 130 is set. Can be used. As described above, the load operation of the antifuse element AF1 can be executed with higher sensitivity.

<First Modification of First Embodiment>
FIG. 8 is a circuit diagram of the load circuit 110, the connect circuit 120, and the sense circuit 130 according to a modification of the first embodiment.

  The modification shown in FIG. 8 is the same as the circuit shown in FIG. 3 except that the polarities are all reversed with respect to the circuit shown in FIG. That is, P-channel MOS transistors 112 and 137 are used instead of the N-channel MOS transistors 111 and 132, and N-channel MOS transistors 123, 136, and 136 are used instead of the P-channel MOS transistors 121, 131, 134, and 135. 138, 139 are used.

  In this case, although not shown, the polarity of the bias generation circuit 150 may be reversed from that of the configuration shown in FIG. Thus, even when the polarity is reversed, the same effect can be obtained.

  In the first embodiment described above, the reference potential VREF is generated using the logic threshold value monitor 140 shown in FIG. 4, and the bias potential BIAS is generated using the bias generation circuit 150 shown in FIG. One of the logic threshold value monitor 140 and the bias generation circuit 150 may be simplified.

<Second Modification of First Embodiment>
FIG. 9 is a circuit diagram of a reference potential generation circuit 140X that can be used in place of the logical threshold monitor 140.

  The reference potential generation circuit 140X shown in FIG. 9 generates the reference potential VREF based on the band gap reference potential VBGR. The band gap reference potential VBGR is a constant potential that does not depend on process variations, temperature changes, voltage changes, and the like. The band gap reference potential VBGR is supplied to the non-inverting input node (+) of the operational amplifier 141X. The output node of the operational amplifier 141X is connected to the gate electrode of the P-channel MOS transistor 142X, and the inverting input node (−) is connected to the drain of the transistor 142X. An external voltage is applied to the transistor 142X and the resistor 143X, and the reference potential VREF is extracted from a predetermined tap of the resistor 143X.

  When the reference potential generation circuit 140X having such a configuration is used, it is possible to obtain the reference potential VREF corresponding to the actual logic threshold value of the sense circuit 130 as in the case where the logic threshold value monitor 140 is used. However, by using the bias generation circuit 150 shown in FIG. 5, the level of the bias potential BIAS can be adjusted according to the resistance value of the antifuse element AF1.

<Third Modification of First Embodiment>
FIG. 10 is a circuit diagram of a bias generation circuit 150X that can be used in place of the bias generation circuit 150.

  The bias generation circuit 150X shown in FIG. 10 includes P-channel MOS transistors 152X, 153X, and 154X connected in series between the operational amplifier 151X and a wiring to which the internal potential VPERI is supplied and a wiring to which the ground potential VSS is supplied. And a variable resistor 155X and an N-channel MOS transistor 156X that resets a node to which the bias potential BIAS is output.

  An inverted signal of the bias control signal BIASCONT is supplied to the gate electrodes of the transistors 152X and 156X. The transistor 153X has a gate electrode and a drain that are short-circuited. Furthermore, the gate electrode of the transistor 154X is connected to the output node of the operational amplifier 151X, and the drain of the transistor 154X is connected to the inverting input node (−) of the operational amplifier 151X. The reference potential VREF is supplied to the non-inverting input node (+) of the operational amplifier 151X.

  With this configuration, a current mirror circuit is formed in which the transistor 153X is an input transistor and the transistor 134 shown in FIG. 3 is an output transistor. It will flow to the element AF1.

  When the bias generation circuit 150X having such a configuration is used, the level of the bias potential BIAS cannot be adjusted according to the resistance value of the anti-fuse element AF1, but the logic threshold value monitor 140 shown in FIG. Since the reference potential VREF corresponding to the actual logic threshold value of the sense circuit 130 can be used, the level of the bias potential BIAS is adjusted according to the actual logic threshold value of the sense circuit 130. Is possible.

<Fourth Modification of First Embodiment>
FIG. 26 is a circuit diagram of a bias generation circuit 150 according to a fourth modification.

  A bias generation circuit 150 shown in FIG. 26 includes M + 1 antifuse elements AF2-0 to AF2-M connected in parallel. Accordingly, the transistor 211 also includes M + 1 transistors 211-0 to 211-M, and the transistor 221 also includes M + 1 transistors 221-0 to 221-M. In the example shown in FIG. 26, the bias program signal BIASPGT has an M + 1 bit configuration, whereby the transistors 221-0 to 221-M can be individually turned on / off, but these transistors 221-0 to 221-M May be collectively controlled by a 1-bit bias program signal BIASPGT.

  The transistor 153 includes M + 1 transistors 153-0 to 153-M, and the transistor 154 includes M + 1 transistors 154-0 to 154-M.

  According to the fourth modification, the level of the bias potential BIAS reflects the average value of the connected M + 1 antifuse elements AF2-0 to AF2-M, and the second antifuse element after connection The variation in the resistance value of AF2 can be reduced to 1 / √M + 1. For this reason, the readable margin for the first antifuse element AF1 can be made substantially constant.

  Furthermore, in the fourth modified example, the following effects can be obtained by changing the size of each transistor.

  The size of each of the transistors 153-0 to 153-M and 154-0 to 154-M is designed to be larger (n times) than the size of the transistors 153 and 154 shown in FIG. The

  As a result, the ratio of the bias current IBIAS flowing through the first antifuse element AF1 to the reference current IREF flowing through the second antifuse element AF2 is 1: n (> 1). In this example, the ratio is 1:10. It becomes. Even when the resistance value of the first antifuse element AF1 in the connected state is n times higher than the average resistance value of the plurality of antifuse elements AF2 in the connected state (in this example, 10 times) Even if it is high, the sensing operation can be performed correctly.

  That is, if the average resistance value of the antifuse element AF2 in the connected state is 1 MΩ, the antifuse element AF1 having a resistance value of 10 MΩ can be determined to be in the connected state. If the average resistance value of the anti-fuse element AF2 in the connected state is 10 KΩ, the anti-fuse element AF1 having a resistance value of 100 KΩ can be determined to be in the connected state. Thus, even if the resistance value of the antifuse element AF1 in the connected state varies depending on the process, temperature, and voltage, the sensing operation can be performed correctly, and a readable margin with respect to the first antifuse element AF1 is reduced to, for example, one. Can be expanded by digits.

<Second Embodiment>
FIG. 11 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the second embodiment.

  As shown in FIG. 11, in the present embodiment, the negative pump 102 is deleted from the pump circuit 100, and power switches 107 and 108 are used instead of the power switches 104 and 105. Further, a verify bit selection circuit 160 is added to the antifuse circuits 51a and 52a.

  The power switch 107 selects the high potential VPPC (6.0 V) or the ground potential VSS (0 V) in response to the program signal PGT and outputs it to the power supply wiring VPPSV. The power switch 108 selects the internal potential VPP (3.0 V) or the ground potential (0 V) in response to the program signal PGT and outputs it as the connect signal AFREF. Since the other configuration is basically the same as that of the first embodiment shown in FIG. 2, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 12 is a circuit diagram of the load circuit 110, the connect circuit 120, the sense circuit 130, and the verify bit selection circuit 160 according to the second embodiment.

  As shown in FIG. 12, the load circuit 110 according to the second embodiment is inserted between the power supply line VPPSV and the connection node AFN1 and between the connection node AFN1 and the sense node AFBL. N-channel MOS transistors 113 and 111 are provided. The gate electrode of the transistor 113 is fixed to the internal potential VPP.

  The connection circuit 120 according to the second embodiment includes N-channel MOS transistors 124 and 125 connected between a connection node AFN1 and a wiring to which a ground potential VSS is supplied. A connect signal AFREF activated during the connect operation is supplied to the gate electrode of the transistor 124. Further, the output signal of the NAND gate circuit 126 receiving the select signal RSET and the corresponding bit of the redundant address RA is supplied to the gate electrode of the transistor 125.

  As shown in FIG. 12, the sense circuit 130 according to the second embodiment includes a transistor 134 having a gate electrode to which a bias potential BIAS is supplied.

  In the sense circuit 130 according to the second embodiment, an N-channel type enable transistor 231 is added. A precharge signal PREB is supplied to the gate electrode of the enable transistor 231. With this configuration, the current control circuit including the transistors 132 and 231 is activated during a period in which the precharge signal PREB is at a high level.

  The verify bit selection circuit 160 includes a P-channel MOS transistor 161 connected between the wiring to which the internal potential VPERI is supplied and the sense circuit 130, and a P-channel MOS transistor 162 connected in series between them. , 163. The bit corresponding to the redundant address RA is supplied to the gate electrode of the transistor 162, and the enable signal ENB and its inverted signal are supplied to the gate electrodes of the transistors 161 and 163, respectively. With this configuration, when the enable signal ENB is activated at a low level, or when the enable signal ENB is deactivated at a high level and the corresponding bit of the redundant address RA is at a low level, the verify is performed. The bit selection circuit 160 supplies the internal potential VPERI to the sense circuit 130.

  FIG. 13 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a verify bit selection circuit 160 according to a modification of the second embodiment.

  The modification shown in FIG. 13 is shown in FIG. 12 in that an N-channel MOS transistor 127 is added to the connect circuit 120 and the connection order of the transistors 132 and 231 included in the sense circuit 130 is reversed. It is different from the circuit. Since other configurations are the same as those of the circuit shown in FIG. 12, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  The source of the transistor 127 is connected to the source of the transistor 124, and the connect signal AFREF and its inverted signal are supplied to the drain and gate electrodes, respectively. With this configuration, the source of the transistor 124 is fixed at the low level (the ground potential VSS) during the period in which the connect signal AFREF is inactivated to the low level. The operation of the sense circuit 130 is the same as that of the circuit shown in FIG.

  FIG. 14 is a circuit diagram of the bias generation circuit 150 according to the second embodiment.

  As shown in FIG. 14, the bias generation circuit 150 according to the second embodiment is different from the bias generation circuit 150 shown in FIG. 5 in the configuration of the load circuit 210 and the connection circuit 220. Specifically, the antifuse element AF2 included in the load circuit 210 is connected between the power supply line VPPSV and the connection node AFN2, and an N-channel MOS transistor 212 is added between the connection node AFN2 and the monitor node MN. It has a configuration. An internal potential VPP is supplied to the gate electrode of the transistor 212.

  14 includes N-channel MOS transistors 222 and 223 connected in series between a connection node AFN2 and a wiring to which a ground potential VSS is supplied. A connect signal AFREF is supplied to the gate electrode of the transistor 222, and a bias program signal BIASPGT is supplied to the gate electrode of the transistor 223.

  Thus, in the second embodiment, the load circuit 210 and the connect circuit 220 have a circuit configuration corresponding to the load circuit 110 and the connect circuit 120 shown in FIG. The operation is as described with reference to FIG.

  FIG. 15 is a timing chart for explaining the operation of the second embodiment.

  In the standby period T21, the program signal PGT is at a low level, and thus the ground potential VSS (0 V) is supplied to the power supply wiring VPPSV.

  In the connection period T22, the program signal PGT changes to a high level. As a result, the high potential VPPC (6.0 V) is supplied to the power supply wiring VPPSV. The level of the connect signal AFREF is the internal potential VPP (3.0 V). In this state, the select signal RSET sequentially changes to the high level, and each bit of the redundant address RA corresponding thereto is input to the connect circuit 120. The example shown in FIG. 15 also shows a case where the select signal RSET is M + 1 bits (RSET <0> to RSET <M>) and the redundant address RA is n + 1 bits (RA <0> to RA <N>). ing.

  As a result, if the bit of the redundant address RA is at a high level, a connection voltage of about 6 V is applied to both ends of the antifuse element AF1 shown in FIG. 12 or FIG. 13, thereby being included in the antifuse element AF1. The insulation film breaks down. This operation is repeatedly executed until all redundant addresses RA are programmed by sequentially switching the select signal RSET to be activated.

  The above operation may be repeatedly performed on the antifuse element AF1 that is not correctly connected after the verify operation. The verify operation is performed by activating the sense circuit 130 by setting the enable signal ENB to a low level.

  In the waiting period T23, a series of programming is completed.

  After the programming is completed, information is read from the antifuse element AF1 every time the semiconductor device 10 is reset.

  In the reset period T24, when the reset signal RSTB is activated to the low level, the precharge signal PREB is activated to the low level in the subsequent precharge period T25. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the load period T26, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VPPSV via the antifuse element AF1. Therefore, the bias current IBIAS flows through the antifuse element AF1, and the potential of the sense node AFBL changes according to the amount of the current.

  When the antifuse element AF1 is not connected (in an insulated state), the bias current IBIAS hardly flows through the antifuse element AF1, so that the potential of the sense node AFBL is precharged as indicated by symbol A. Maintain state. On the other hand, when the anti-fuse element AF1 is connected (when the anti-fuse element AF1 is in a conductive state), the bias current IBIAS flows through the anti-fuse element AF1, so that the potential of the sense node AFBL greatly decreases as indicated by the symbol B. To do.

  In addition, when the antifuse element AF1 is in the half-connected state, since the bias current IBIAS flowing through the antifuse element AF1 is small, the potential drop of the sense node AFBL is moderate as shown by reference C. Also in the embodiment, since the bias potential BIAS changes according to the resistance value of the antifuse element AF1, it is possible to perform a sensing operation with higher sensitivity.

  The load operation of the antifuse element AF1 can also be performed in bit units. In this case, after the sense node AFBL is precharged to the VPERI level (1.0 V) in the precharge period T27, the redundant address RA corresponding to the target bit is set to the low level in the load period T28. At this time, if the enable signal ENB is set to the high level, the transistors 162 and 163 shown in FIG. 12 or FIG. 13 are turned on, so that the load operation is selectively performed with respect to the antifuse element AF1 corresponding to the target bit. Can be executed.

<Third Embodiment>
FIG. 16 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the third embodiment.

  As shown in FIG. 16, in this embodiment, the antifuse circuits 51 a and 52 a are constituted by an antifuse array 170 and a latch block 180. In addition, a driver circuit 240 is added to the bias generation circuit 150. Since the other configuration is basically the same as that of the second embodiment shown in FIG. 11, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 17 is a circuit diagram of the antifuse array 170.

  As shown in FIG. 17, the antifuse array 170 includes a plurality of load circuits 110 arranged in an array. In the example shown in FIG. 17, a plurality of load circuits 110 constitutes an array of N + 1 rows × M + 1 columns. Each row corresponds to each bit of the redundant address RA, and each column corresponds to one redundant address RA.

  The antifuse array 170 includes a plurality of connect circuits 120 and sense circuits 130 that are commonly assigned to a plurality of load circuits 110 arranged in the row direction, and a plurality of load circuits 110 arranged in the column direction. The driver circuits 191 assigned in common are provided.

  Among the plurality of load circuits 110, the plurality of load circuits 110 arranged in the row direction are commonly connected to the corresponding sense nodes AFBL, respectively. As a result, the plurality of load circuits 110 arranged in the row direction are commonly connected to the corresponding sense circuits 130. In FIG. 17, N + 1 sense nodes AFBL are denoted as AFBL <0> to AFBL <N>.

  The driver circuit 191 selects a plurality of load circuits 110 arranged in the column direction among the plurality of load circuits 110. The driver circuit 191 generates a program signal WLP and a read signal WLR based on the corresponding select signal RSET and main word signal MWLR, and supplies these signals in common to the plurality of load circuits 110 arranged in the column direction. In FIG. 17, M + 1 select signals RSET are expressed as RSET <0> to RSET <M>, and M + 1 main word signals MWLR are expressed as MWLR <0> to MWLR <M>.

  The main word signal MWLR is generated by an AND gate circuit 193 that receives the load signal LOADT and the output signal of the corresponding register circuit 192. The register circuit 192 is provided corresponding to each column, and constitutes a shift register by being cascaded as shown in FIG. The load clock signal LOADCLK is supplied to the clock node of the register circuit 192, whereby the latch data is sequentially shifted in synchronization with the clocking of the load clock signal LOADCLK. These register circuits 192 are reset when the load signal LOADT is inactivated to a low level.

  FIG. 18 is a circuit diagram of the driver circuit 191.

  As shown in FIG. 18, the driver circuit 191 includes an OR gate circuit 194 that receives the main word signal MWLR and the select signal RSET, and an AND gate circuit 195 that receives the select signal RSET and the program signal PGT.

  The output signal of the OR gate circuit 194 is output as a read signal WLR via the buffer circuit 196. Since the buffer circuit 196 is supplied with the internal potential VPP (3.0 V) and the ground potential VSS (0 V) as operation power supplies, the activation level of the read signal WLR becomes the internal potential VPP (3.0 V).

  On the other hand, the output signal of the AND gate circuit 195 is output as the program signal WLP via the buffer circuit 197. Since the buffer circuit 197 is connected to the power supply wiring VPPSV, the level of the program signal WLP during the connection operation is the high potential VPPC (6.0 V) on the power supply wiring VPPSV, and the level of the program signal WLP during the load operation is The ground potential is VSS (0 V).

  FIG. 19 is a circuit diagram of the load circuit 110 in the third embodiment.

  As shown in FIG. 19, the load circuit 110 according to the third embodiment includes an antifuse element AF1 and a transistor 111 connected in series. The program signal WLP is supplied to one end of the antifuse element AF1, and the read signal WLR is supplied to the gate electrode of the transistor 111. A ground potential VSS is supplied to the substrate of the transistor 111.

  The drain of the transistor 111 is connected to the corresponding sense node AFBL. As shown in FIG. 17, the sense nodes AFBL are commonly connected in a plurality of load circuits 110 arranged in the row direction.

  FIG. 20 is a circuit diagram of the connect circuit 120 according to the third embodiment.

  As shown in FIG. 20, the connection circuit 120 in the third embodiment includes transistors 124 and 125 connected in series between a sense node AFBL and a wiring to which a ground potential VSS is supplied. A connect signal AFREF is supplied to the gate electrode of the transistor 124, and a bit corresponding to the redundant address RA is supplied to the gate electrode of the transistor 125. The ground potential VSS is supplied to the substrate of the transistor 124.

  FIG. 21 is a circuit diagram of the sense circuit 130 in the third embodiment.

  As shown in FIG. 21, the sense circuit 130 in the third embodiment is different from the sense circuit 130 shown in FIG. 3 in that an N-channel MOS transistor 232 is added. Since the other points are the same as those of the sense circuit 130 shown in FIG. 3, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The transistor 232 is inserted between the sense node AFBL and the input node of the inverter circuit 133, and a load signal LOADT is supplied to its gate electrode. Therefore, when the load signal LOADT is activated to a high level, the sense node AFBL and the input node of the inverter circuit 133 are short-circuited.

  The circuit configuration of the antifuse array 170 has been described above. When programming the antifuse array 170 having such a configuration, one or more antifuse elements are used using a plurality of connect circuits 120 in a state where any column is selected using the driver circuit 191. A high voltage is applied across the AF1. Thereby, programming is performed in units of columns. When reading information from the antifuse array 170, the driver circuit 191 activates the load signal LOADT in a state where any column is selected, thereby causing the bias current IBIAS to flow through the plurality of antifuse elements AF1. As a result, a loading operation is performed in units of columns.

  The defective address information AFBLB read by the load operation is supplied to the latch block 180 shown in FIG.

  FIG. 22 is a circuit diagram of the latch block 180.

  As shown in FIG. 22, the latch block 180 includes a plurality of latch circuits 200 arranged in an array. In the example shown in FIG. 22, a plurality of latch circuits 200 constitutes an array of N + 1 rows × M + 1 columns. Each row corresponds to each bit of the redundant address RA, and each column corresponds to one redundant address RA.

  Among the plurality of latch circuits 200, a plurality of latch circuits 200 arranged in the row direction are commonly supplied with corresponding bits of the defective address information AFBLB. In FIG. 22, N + 1-bit defective address information AFBLB is expressed as AFBLB <0> to AFBLB <N>.

  The selection of the plurality of latch circuits 200 arranged in the column direction among the plurality of latch circuits 200 is performed by the main word signal MWLR. The circuit for generating the main word signal MWLR has already been described.

  FIG. 23 is a circuit diagram of the latch circuit 200.

  As shown in FIG. 23, the latch circuit 200 includes two inverter circuits 201 and 202 that are circulated, a transistor 203 for inputting a corresponding bit of the defective address information AFBLB, and a transistor that outputs the latched information. 204.

  A corresponding main word signal MWLR is supplied to the gate electrode of the transistor 203. As a result, each bit of the defective address information AFBLB read from the antifuse array 170 is transferred to the corresponding latch circuit 200.

  The output signal REDX is supplied to the gate electrode of the transistor 204. The transistor 204 is connected between the inverter circuits 201 and 202 and the output line RX. Thus, when the output signal REDX is activated, the information held in the latch circuit 200 is output to the output line RX. . As shown in FIG. 22, the plurality of latch circuits 200 arranged in the row direction share an output line RX. In FIG. 22, N + 1 output lines RX are represented as RX <0> to RX <N>. The M + 1-bit output signal REDX is expressed as REDX <0> to REDX <M>.

  With this configuration, when a load operation is performed on the antifuse array 170, the defective address information AFBLB read from the array-shaped load circuit 110 is successively transferred to the array-shaped latch circuit 200. The defective address information AFBLB transferred to the latch circuit 200 is supplied to the address comparison circuits 51b and 52b via the output line RX.

  FIG. 24 is a circuit diagram of the bias generation circuit 150 according to the third embodiment.

  As shown in FIG. 24, in the bias generation circuit 150 according to the third embodiment, the transistor 155 is deleted from the amplifier circuit 151, and the configuration of the load circuit 210 is different from the bias generation circuit 150 shown in FIG. Yes. A driver circuit 240 that drives the load circuit 210 is also added.

  Specifically, the antifuse element AF2 included in the load circuit 210 is connected between the driver circuit 240 and the connection node AFN2, and an N-channel MOS transistor 213 is connected between the connection node AFN2 and the monitor node MN. It has a configuration. The gate electrode of the transistor 213 is also connected to the driver circuit 240.

  The driver circuit 240 has a configuration similar to that of the driver circuit 191 shown in FIG. That is, the driver circuit 240 includes an OR gate circuit 244 that receives the bias control signal BIASCONT and the bias program signal BIASPGT, and the output signal is supplied to the gate electrode of the transistor 213 through the buffer circuit 246. Since the buffer circuit 246 is supplied with the internal potential VPP (3.0 V) and the ground potential VSS (0 V) as an operation power supply, when one of the bias control signal BIASCONT and the bias program signal BIASPGT is activated, the transistor 213 An internal potential VPP (3.0 V) is applied to the gate electrode.

  Further, the bias program signal BIASPGT is supplied to the antifuse element AF2 via the buffer circuit 247. Since the buffer circuit 247 is connected to the power supply wiring VPPSV, a voltage of 6.0 V is applied to both ends of the antifuse element AF2 during the connection operation.

  FIG. 25 is a timing chart for explaining the operation of the third embodiment.

  In the standby period T31, the program signal PGT is at a low level, and thus the ground potential VSS (0 V) is supplied to the power supply wiring VPPSV.

  In the connection period T32, the program signal PGT changes to a high level. As a result, the high potential VPPC (6.0 V) is supplied to the power supply wiring VPPSV. The level of the connect signal AFREF is the internal potential VPP (3.0 V). Then, while the predetermined main word signal MWLR is activated, the select signal RSET is sequentially set to the high level, and each bit of the redundant address RA corresponding thereto is input to the plurality of connect circuits 120. As a result, the redundant address RA is programmed in the plurality of load circuits 110 constituting the selected column.

  Such an operation is performed for all the columns by switching the selection of the main word signal MWLR. Thereby, each column of the antifuse array 170 is programmed with a corresponding redundant address RA. The above operation may be repeatedly performed on the antifuse element AF1 that is not correctly connected after the verify operation.

  After the programming is completed, information is read from the antifuse element AF1 every time the semiconductor device 10 is reset.

  In the reset period T34 after the waiting period T33, the reset signal RSTB is activated to a low level.

  In the precharge period T35, the precharge signal PREB is activated to a low level. As a result, the sense nodes AFBL in all the sense circuits 130 are precharged to the VPERI level (1.0 V).

  In the load period T36, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VPPSV via the antifuse element AF1. Therefore, the bias current IBIAS flows through the antifuse element AF1, and the potential of the sense node AFBL changes according to the amount of the current.

  When the antifuse element AF1 is not connected (in an insulated state), the bias current IBIAS hardly flows through the antifuse element AF1, so that the potential of the sense node AFBL is precharged as indicated by symbol A. Maintain state. On the other hand, when the anti-fuse element AF1 is connected (when the anti-fuse element AF1 is in a conductive state), the bias current IBIAS flows through the anti-fuse element AF1, so that the potential of the sense node AFBL greatly decreases as indicated by the symbol B. To do.

  Further, when the anti-fuse element AF1 is in the half-connected state, since the bias current IBIAS flowing through the anti-fuse element AF1 is small, the decrease in the potential of the sense node AFBL becomes gradual as indicated by the symbol C. However, also in this embodiment, since the bias potential BIAS changes according to the resistance value of the antifuse element AF1, it is possible to perform a sensing operation with higher sensitivity.

  The defective address information AFBLB read in this way is written in a predetermined latch circuit 200 included in the latch block 180. Therefore, if the above operation is sequentially performed on each column, the defective address information AFBLB written on each column is transferred to the latch block 180 one after another. In the example shown in FIG. 25, all transfer operations are completed in the precharge period T37 and the load period T38 by repeating the load operation M + 1 times.

  Even when the load circuit 110 including the antifuse element AF1 is arranged in an array as in the third embodiment described above, the same effect as in the first and second embodiments can be obtained. Become.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the case where the present invention is applied to a DRAM (Dynamic Random Access Memory) has been described as an example. However, the application target of the present invention is not limited to this, and PCM (Phase Change Memory), ReRAM (Resistive Random Access Memory), MRAM (Magnetrogenic Random Access Memory), STT-RAM (Spin Transfer Torque Memory), and other types of semiconductor devices that can be used as a semiconductor memory such as flash memory The present invention can also be applied to logic semiconductor devices.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11a, 11b Clock terminal 12a-12d Command terminal 13 Address terminal 14 Data input / output terminal 15v, 15s Power supply terminal 21 Internal clock generation circuit 22 DLL circuit 31 Command decoder 41 Address latch circuit 51 Row decoder 51a, 52a Antifuse circuit 51b, 52b Address comparison circuit 52 Column decoder 53 Sense amplifier row 54 Antifuse control circuit 55 Redundant address decoder 60 Memory cell array 70 Main amplifier 80 Data input / output circuit 90 Power supply circuit 100 Pump circuit 101 Positive pump 102 Negative pumps 104, 105, 107 , 108 Power switch 110 Load circuit 111, 113, 123-125, 127, 132, 136, 142, 154, 155, 156X, 20 , 204, 211 to 213, 222, 223, 232 N channel type MOS transistors 112, 121, 131, 134, 137, 141, 142X, 152X to 154X, 153, 161 to 163, 221 P channel type MOS transistors 120 Connect circuit 122 NAND gate circuit 126 AND gate circuit 130 Sense circuit 133 First inverter circuit 134, 138 Bias transistor 135, 139 Precharge transistor 140 Threshold monitor 140X Reference potential generation circuit 141 Second inverter circuit 141X Operational amplifier 142 Voltage supply circuit 143X resistors 150 and 150X bias generation circuit 151 amplifier circuit 151X operational amplifier 152 differential circuit 155X variable resistor 156 constant current source 157 and 158 input transistor Star 160 Verify bit select circuit 170 Antifuse array 180 Latch block 191 Driver circuit 192 Register circuit 193, 195 AND gate circuit 194 OR gate circuit 196, 197 Buffer circuit 200 Latch circuit 201, 202 Inverter circuit 210 Load circuit 220 Connect circuit 231 Enable Transistor 240 Driver circuit 244 OR gate circuits 246 and 247 Buffer circuit AF1 First antifuse element AF2 Second antifuse element AFBL Sense node AFBLB Defective address information AFN1, AFN2 Connection node BL Bit lines CM1 to CM3 Current mirror circuit MC Memory Cell MN monitor node RBL redundant bit line RMC redundant memory cell RWBS read / write bus RWL redundant word Line RX output line SA sense amplifier VPPSV, VBBSV power wiring WL word line

Claims (20)

First and second power supply lines to which first and second potentials are respectively supplied;
A determination circuit that generates a determination signal based on the potential of the sense node;
A bias circuit connected between the first power supply line and the sense node, and causing a bias current corresponding to a bias potential to flow to the sense node;
A first antifuse element connected between the second power supply wiring and the sense node;
A bias generation circuit for generating the bias potential,
The bias generation circuit controls a level of the bias potential in accordance with a second antifuse element connected between the first and second power supply lines and a reference current flowing through the second antifuse element. A semiconductor device comprising an amplifier circuit.   The amplifier circuit controls the level of the bias potential so that the bias current decreases as the reference current decreases, and controls the level of the bias potential so that the bias current increases as the reference current increases. The semiconductor device according to claim 1.   The amplifier circuit includes a differential circuit that outputs the bias potential according to a potential difference between a monitor node potential and a reference potential, which is a connection point between the first power supply wiring and the second antifuse element. The semiconductor device according to claim 2.   4. The amplifier circuit according to claim 3, further comprising: a first transistor connected between the first power supply wiring and the monitor node, wherein the bias potential is supplied to a control electrode. 5. Semiconductor device.   5. The amplifier circuit according to claim 4, further comprising: a second transistor connected between the second power supply wiring and the monitor node, wherein the reference potential is supplied to a control electrode. 6. Semiconductor device.   The semiconductor device according to claim 3, wherein the determination circuit includes a first inverter circuit having an input node connected to the sense node.   The semiconductor device according to claim 6, further comprising a second inverter circuit in which an input node and an output node are short-circuited and the reference potential is output from the output node.   The semiconductor device according to claim 1, wherein the bias circuit includes a bias transistor in which the bias potential is supplied to a control electrode.   9. The semiconductor according to claim 8, wherein the bias circuit further includes a third transistor of a first conductivity type that is connected in series to the bias transistor and whose conduction state is controlled based on the determination signal. apparatus.   The fourth transistor according to claim 9, further comprising a fourth transistor of a second conductivity type connected between a third power supply wiring and the sense node and controlled in conduction state based on the determination signal. Semiconductor device.   The second potential supplied to the second power supply wiring is different from the potential supplied to the third power supply wiring when programming the first antifuse element, and the determination circuit 11. The semiconductor device according to claim 10, wherein the potential is the same as the potential supplied to the third power supply wiring during the sensing operation according to 11.   12. The semiconductor device according to claim 10, further comprising an enable transistor connected in series to the fourth transistor and brought into a conductive state during a sensing operation by the determination circuit.   The semiconductor device according to claim 1, further comprising a precharge circuit that precharges the sense node to the first potential.   The semiconductor device according to claim 1, wherein a plurality of the first antifuse elements are assigned to a sense circuit including the determination circuit and a bias circuit.   The semiconductor device according to claim 1, wherein the second antifuse element includes a plurality of antifuse elements connected in parallel. First and second power supply lines to which first and second potentials are respectively supplied;
A first inverter circuit having an input node connected to the sense node;
A bias circuit connected between the first power supply line and the sense node, and causing a bias current corresponding to a bias potential to flow to the sense node;
A first antifuse element connected between the second power supply wiring and the sense node;
A second inverter circuit in which an input node and an output node are short-circuited and a reference potential is output from the output node;
And a bias generation circuit that outputs the bias potential in accordance with the reference potential.   An operating voltage is supplied to the second inverter circuit when the control signal is at the first logic level, and the operating voltage is cut off when the control signal is at the second logic level. The semiconductor device according to claim 16.   The bias generation circuit outputs the bias potential in accordance with a second antifuse element connected between the second power supply wiring and the monitor node, and a potential difference between the potential of the monitor node and the reference potential. 18. The semiconductor device according to claim 16, further comprising a differential circuit.   The bias generation circuit further includes a first transistor connected between the first power supply wiring and the monitor node, and supplied with the bias potential to a control electrode. Semiconductor device.   The bias generation circuit further includes a second transistor connected between the second power supply line and the monitor node, and supplied with the reference potential to a control electrode. Semiconductor device.

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