JP2015185200A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a latency counter having small current consumption and a relatively simple circuit configuration.SOLUTION: First counter circuits and second counter circuit for making a terminal control signal ODTi delay in synchronous with an internal clock signal PCLK are coupled in series. The first counter circuits 111-114 switch a delay amount of the terminal control signal ODTi by a 8 clock cycle in synchronous with the internal clock signal PCLK, and the second counter circuit 120 switches the delay amount of the terminal control signal ODTi by a 1 clock cycle in synchronization with the internal clock signal PCLK. According to the invention, the semiconductor device having a latency counter having small current consumption and a relatively simple circuit configuration can be provided.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a latency counter that counts latency of a control signal.

  A semiconductor device such as a DRAM (Dynamic Random Access Memory) is generally a synchronous type that operates in synchronization with a clock signal, and the operation speed is improved by increasing the frequency of the clock signal to be used. However, the operation in the back-end circuit such as the sense operation is an analog operation to the last, and it is difficult to increase the speed in proportion to the frequency of the clock signal. For this reason, the number of clock cycles from when an external command is input until the actual output of read data or ODT (On Die Termination) operation tends to increase as the frequency of the clock signal increases. Such a number of clock cycles is generally called latency.

  As a latency counter for counting latency, circuits described in Patent Documents 1 and 2 are known. The latency counter described in Patent Document 1 uses a shift register having a variable number of stages. In addition, the latency counter described in Patent Document 2 uses a so-called point shift type FIFO circuit.

JP 2011-060372 A JP 2008-047267 A

  However, a latency counter using a shift register increases current consumption in proportion to the number of latencies. On the other hand, the latency counter using the point shift type FIFO circuit can reduce current consumption more than the latency counter using the shift register, but the circuit configuration becomes complicated if there are many types of selectable latency. There was a problem. Therefore, a semiconductor device including a latency counter that consumes less current and has a relatively simple circuit configuration is desired.

  In a semiconductor device according to an aspect of the present invention, first and second counter circuits that delay a control signal in synchronization with a first clock signal are connected in series, and the first counter circuit includes the first counter circuit. The delay amount of the control signal is switched at a first pitch in synchronization with the first clock signal, and the second counter circuit sets the delay amount of the control signal in synchronization with the first clock signal. It is characterized by switching at a second pitch smaller than the first pitch.

  According to another aspect of the present invention, a semiconductor device includes a first counter circuit including a plurality of FIFO circuits each including a plurality of first latch circuits that latch control signals, and the number of the FIFO circuits through which the control signals pass. And a selector for switching between the first counter circuit and the first counter circuit, the second counter circuit for switching the delay amount of the control signal in synchronization with the first clock signal, and the first clock signal. A plurality of frequency dividing circuits that generate a plurality of second clock signals having different phases by rotating, and the plurality of first latch circuits included in the same FIFO circuit includes the plurality of second clock signals. The control signal is captured in synchronization with different ones of the plurality of clock signals, the control signal is output in synchronization with different ones of the plurality of second clock signals, Each of the first latch circuit, wherein the synchronization with those same among the plurality of second clock signal for fetching and outputting of the control signal.

  According to the present invention, it is possible to provide a semiconductor device including a latency counter that consumes less current and has a relatively simple circuit configuration.

1 is a block diagram showing an overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention. It is a block diagram which extracts and shows the part relevant to the termination | terminus control signal ODT. It is a timing diagram for demonstrating termination | terminus operation | movement based on termination | terminus control signal ODT, and has shown the case where ODT latency is set to 5 clock cycles. It is a timing diagram for demonstrating termination | terminus operation | movement based on termination | terminus control signal ODT, and has shown the case where ODT latency is set to 10 clock cycles. It is a circuit diagram of the latency counter 100X by a prototype. FIG. 10 is a timing diagram for explaining the operation of the latency counter 100X, and shows a case where the shift amount is set to 3 clock cycles. FIG. 3 is a circuit diagram of a latency counter 100a according to the first embodiment. 3 is a block diagram showing a configuration of a shift amount decoder 140. FIG. 3 is a circuit diagram of a frequency dividing circuit 151. FIG. FIG. 6 is a timing chart for explaining the operation of the frequency dividing circuit 151. 3 is a circuit diagram of a FIFO circuit 111. FIG. It is a circuit diagram of the latch circuit LAT0. 5 is a timing chart for explaining the operation of the FIFO circuit 111. FIG. 2 is a circuit diagram of a FIFO circuit 120. FIG. It is a circuit diagram of the latch circuit LAT32. 3 is a circuit diagram of an output pointer generation circuit 160. FIG. It is a circuit diagram of clock selector CS0. 5 is a timing chart for explaining the operation of the output pointer generation circuit 160. FIG. 4 is a timing chart for explaining the operation of the FIFO circuit 120. FIG. It is a circuit diagram of the latency counter 100b by 2nd Embodiment. 3 is a circuit diagram of a frequency dividing circuit 152. FIG. FIG. 9 is a circuit diagram of a latency counter 100c according to a third embodiment. 2 is a circuit diagram of a shift circuit 121. FIG. It is a circuit diagram of the latency counter 100d by 4th Embodiment. 3 is a circuit diagram of a FIFO circuit 115 and a synthesis circuit 170. FIG. 3 is a circuit diagram of a shift circuit 122. FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DDR4 (Double Data Rate 4) type DRAM integrated on one semiconductor chip, and includes a memory cell array 11 divided into n + 1 banks as shown in FIG. ing. A bank is a unit capable of executing commands individually, and basically non-exclusive operations are possible between banks.

  The memory cell array 11 is provided with a plurality of word lines WL and a plurality of bit lines BL intersecting with each other, and memory cells MC are arranged at the intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. Each bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 14, and the bit line BL selected by the column decoder 13 is connected to the data controller 15 via the sense amplifier SA. The data controller 15 includes a main amplifier, a verification circuit, and the like, and is connected to the data input / output circuit 17 via the FIFO circuit 16. The data input / output circuit 17 is a circuit block that inputs and outputs data via the data input / output terminal 21.

  In addition to the data input / output terminal 21, the semiconductor device 10 includes strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminal 30, 31, a data mask terminal 32, an ODT terminal 33 and the like are provided.

  The strobe terminals 22 and 23 are terminals for inputting and outputting strobe signals DQST and DQSB, respectively. The strobe signals DQST and DQSB are complementary signals and define the input / output timing of data input / output via the data input / output terminal 21. Specifically, at the time of data input, that is, at the time of write operation, the strobe signals DQST and DQSB are supplied to the strobe circuit 18, and the strobe circuit 18 controls the operation timing of the data input / output circuit 17 based on them. As a result, the write data DQ input via the data input / output terminal 21 is taken into the data input / output circuit 17 in synchronization with the strobe signals DQST and DQSB. On the other hand, at the time of data output, that is, at the time of read operation, the operation of the strobe circuit 18 is controlled by the strobe controller 19. As a result, the data input / output circuit 17 outputs the read data DQ in synchronization with the strobe signals DQST and DQSB.

  The clock terminals 24 and 25 are terminals to which external clock signals CK and / CK are input, respectively. The input external clock signals CK and / CK are supplied to the clock generator 40. In this specification, a signal having “/” at the head of a signal name means a low active signal or an inverted signal of the corresponding signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generator 40 is activated based on the clock enable signal CKE input via the clock enable terminal 26, and generates the internal clock signal ICLK. The external clock signals CK and / CK supplied via the clock terminals 24 and 25 are also supplied to the DLL circuit 41.

  The DLL circuit 41 is a circuit that generates an output clock signal LCLK whose phase is controlled based on the external clock signals CK and / CK. The output clock signal LCLK is used as a timing signal that defines the output timing of read data by the data input / output circuit 17. Further, the termination control signal ODT is also supplied to the DLL circuit 41 via the ODT terminal 33.

  The address terminal 27 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the row control circuit 50, the column control circuit 60, the mode register 42, the command decoder 43, and the like. The row control circuit 50 is a circuit block including an address buffer 51 and a refresh counter 52, and controls the row decoder 12 based on the row address. The column control circuit 60 is a circuit block including an address buffer 61 and a burst counter 62, and controls the column decoder 13 based on the column address. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 42, whereby the contents of the mode register 42 are updated.

  The command terminal 28 is a terminal to which a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a parity signal PRTY, a reset signal RST, and the like are supplied. These command signals CMD are supplied to the command decoder 43, and the command decoder 43 generates an internal command ICMD based on these command signals CMD. The internal command signal ICMD is supplied to the control logic circuit 44. The control logic circuit 44 controls operations of the row control circuit 50, the column control circuit 60, the data controller 15 and the like based on the internal command signal ICMD.

  The command decoder 43 includes a verification circuit (not shown). The verification circuit verifies the address signal ADD and the command signal CMD based on the parity signal PRTY. As a result, if there is an error in the address signal ADD or the command signal CMD, the verification circuit passes through the control logic circuit 44 and the output circuit 45. To output an alert signal ALRT. The alert signal ALRT is output to the outside via the alert terminal 29.

  The power supply terminals 30 and 31 are terminals to which power supply potentials VDD and VSS are supplied, respectively. The power supply potentials VDD and VSS supplied via the power supply terminals 30 and 31 are supplied to the power supply circuit 46. The power supply circuit 46 is a circuit block that generates various internal potentials based on the power supply potentials VDD and VSS. The internal potential generated by the power supply circuit 46 includes a boosted potential VPP, a power supply potential VPERI, an array potential VARY, a reference potential VREF, and the like. The boosted potential VPP is generated by boosting the power supply potential VDD, and the power supply potential VPERI, the array potential VARY, and the reference potential VREF are generated by stepping down the external potential VDD.

  The boosted voltage VPP is a potential mainly used in the row decoder 12. The row decoder 12 drives the word line WL selected based on the address signal ADD to the VPP level, thereby turning on the cell transistor included in the memory cell MC. The internal potential VARY is a potential mainly used in the sense circuit 14. When the sense circuit 14 is activated, the read data read out is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The power supply voltage VPERI is used as an operating potential for most peripheral circuits such as the row control circuit 50 and the column control circuit 60. By using the power supply potential VPERI having a voltage lower than the power supply potential VDD as the operating potential of these peripheral circuits, the power consumption of the semiconductor device 10 is reduced. The reference potential VREF is a potential used in the data input / output circuit 17.

  The data mask terminal 32 and the ODT terminal 33 are terminals to which a data mask signal DM and a termination control signal ODT are supplied, respectively. The data mask signal DM and the termination control signal ODT are supplied to the data input / output circuit 17. The data mask signal DM is activated when masking part of the write data and read data, and the termination control signal ODT is used when the output buffer included in the data input / output circuit 17 is used as a termination resistor. It is a signal that is activated.

  The above is the overall structure of the semiconductor device 10 according to the present embodiment. Hereinafter, the semiconductor device 10 according to the present embodiment will be described in more detail with attention paid to the latency counter that delays the termination control signal ODT.

  FIG. 2 is a block diagram showing a portion related to the termination control signal ODT.

  As shown in FIG. 2, the DLL circuit 41 includes two delay lines 71 and 72 and a DLL control circuit 73 for controlling them. The delay line 71 generates an internal clock signal LCLK for output by delaying the internal clock signal PCLK output via the clock receiver 81. On the other hand, the delay line 72 generates the termination control signal ODTi by delaying the termination control signal ODT output via the ODT receiver 82 and the latch circuit 83.

Both the internal clock signal LCLK and the termination control signal ODTi are supplied to the data input / output circuit 17. The data input / output circuit 17 includes a latency counter 100 that counts the latency of the termination control signal ODTi. The latency counter 100 delays the termination control signal ODTi by a preset latency and outputs it as a termination control signal ODTf. The setting of the latency is determined by the additive latency AL and write latency CWL supplied from the mode register 42 and the lock value NT supplied from the DLL control circuit 73. Specifically, when the clock signal count, which is the delay amount of the latency counter 100, is S,
S = AL + CWL-NT-2
Defined by

  The termination control signal ODTf output from the latency counter 100 is supplied to the ODT driver 84. The ODT driver 84 is a driver for causing the data input / output terminal 21 and the strobe terminals 22 and 23 to function as termination resistors, and operates in synchronization with the internal clock signal LCLK for output. The ODT driver 84 may be shared with the driver used to output the read data DQ and the strobe signals DQST and DQSB, or may be provided separately from these drivers.

  3 and 4 are timing diagrams for explaining the termination operation based on the termination control signal ODT. FIG. 3 shows a case where the ODT latency is set to 5 clock cycles, and FIG. This shows the case where the clock cycle is set.

  As shown in FIGS. 3 and 4, when the termination control signal ODT changes to a high level, the ODT latency is counted with reference to the next rising edge of the external clock signal CK. In the examples shown in FIG. 3 and FIG. 4, since the termination control signal ODT changes to the high level immediately before the edge # 2 of the external clock signal CK, the ODT latency is set to 5 clock cycles. Terminates in synchronization with the edge # 7 of the external clock signal CK. When the ODT latency is set to 10 clock cycles, the termination operation begins in synchronization with the edge # 12 of the external clock signal CK. .

  Here, of the ODT latency, the last two clock cycles are a synchronization period by the ODT driver 84 shown in FIG. 2, and the remaining delay amount (shift period) is defined by the latency counter 100. Therefore, in the example shown in FIG. 3, the shift period is 3 clock cycles, and in the example shown in FIG. 4, the shift period is 8 clock cycles.

  Here, before describing the latency counter according to the embodiment of the present invention, the prototype latency counter studied by the inventors in the course of completing the invention will be described.

  FIG. 5 is a circuit diagram of a prototype latency counter 100X.

  The prototype latency counter 100X shown in FIG. 5 includes a shift register SL including 40 flip-flop circuits FF0 to FF39 connected in cascade, and a selector SEL that supplies a termination control signal ODTi to the shift register SL. The selector SEL supplies the termination control signal ODTi to any one of the input nodes S0 to S39 of the flip-flop circuits FF0 to FF39 based on the additive latency AL, the write latency CWL, and the lock value NT. As a result, the number of stages of the shift register SL through which the termination control signal ODTi passes is variable, so that any latency can be counted. Here, the reason why the 40 flip-flop circuits FF0 to FF39 are used for the shift register SL is to correspond to the maximum ODT latency that can be set according to the standard.

  FIG. 6 is a timing chart for explaining the operation of the latency counter 100X, and shows a case where the shift amount is set to 3 clock cycles.

  As shown in FIG. 6, when the shift amount by the latency counter 100X is set to 3 clock cycles, the selector SEL supplies the termination control signal ODTi to the flip-flop circuit FF37. As a result, the termination control signal ODTi passes through the three flip-flop circuits FF37 to FF39 and is output as the termination control signal ODTf. That is, the termination control signal ODTi synchronized with the edge # 4 of the external clock signal CK is output as the termination control signal ODTf synchronized with the edge # 7 of the external clock signal CK, and the termination control synchronized with the edge # 12 of the external clock signal CK. The signal ODTi is output as a termination control signal ODTf synchronized with the edge # 15 of the external clock signal CK.

  When the latency counter 100X having such a configuration is used, there is no big problem when the value of the ODT latency is small, but the number of flip-flop circuits to be used increases as the value of the ODT latency increases. The current consumption increases in proportion.

  In the latency counter according to the embodiment of the present invention described below, such a problem is solved, and a low current consumption is realized by a relatively simple circuit configuration.

  FIG. 7 is a circuit diagram of the latency counter 100a according to the first embodiment.

  As shown in FIG. 7, the latency counter 100a according to the first embodiment includes four FIFO circuits 111 to 114 that constitute a first counter circuit, and a FIFO circuit 120 that constitutes a second counter circuit. These have the structure connected in series. Any of the FIFO circuits 111 to 114 and 120 is a so-called point shift type FIFO circuit, but the relationship between the input pointer and the output pointer is fixed with respect to the FIFO circuits 111 to 114, and the input pointer and the output with respect to the FIFO circuit 120. The pointer relationship is variable.

  The FIFO circuits 111 to 114, 120 are connected in series via the selectors 131 to 134. The selector 131 supplies either the termination control signal ODTi or the output signal of the FIFO circuit 111 to the FIFO circuit 112 based on the selection signal SELU32. The selector 132 supplies either the termination control signal ODTi or the output signal of the FIFO circuit 112 to the FIFO circuit 113 based on the selection signal SELU24. Further, the selector 133 supplies either the termination control signal ODTi or the output signal of the FIFO circuit 113 to the FIFO circuit 114 based on the selection signal SELU16. Then, the selector 134 supplies either the termination control signal ODTi or the output signal of the FIFO circuit 114 to the FIFO circuit 120 based on the selection signal SELU8.

  Specifically, the input node a is selected when the selection signal input to the selectors 131 to 134 is at a high level, and the input node b is selected when the selection signal is at a low level.

  With this configuration, when the selection signal SELU8 is at a low level, the FIFO circuits 111 to 114 are all bypassed, and the termination control signal ODTi is directly input to the FIFO circuit 120. When the selection signal SELU8 is at a high level and the selection signal SELU16 is at a low level, the FIFO circuits 111 to 113 are bypassed, and the termination control signal ODTi is input to the FIFO circuit 120 after passing through the FIFO 114. When the selection signals SELU8 and 16 are at a high level and the selection signal SELU24 is at a low level, the FIFO circuits 111 and 112 are bypassed, and the termination control signal ODTi is input to the FIFO circuit 120 after passing through the FIFOs 113 and 114. . When the selection signals SELU8, 16, and 24 are at a high level and the selection signal SELU32 is at a low level, the FIFO circuit 111 is bypassed, and the termination control signal ODTi is input to the FIFO circuit 120 after passing through the FIFOs 112 to 114. . When all the selection signals SELU8, 16, 24, and 32 are at a high level, the termination control signal ODTi is input to the FIFO circuit 120 after passing through all the FIFOs 111 to 114.

  The selection signals SELU8, 16, 24, and 32 are generated by the shift amount decoder 140.

  FIG. 8 is a block diagram showing a configuration of the shift amount decoder 140.

  As shown in FIG. 8, the shift amount decoder 140 includes an adder 141, a subtractor 142, and a decoder 143. The adder 141 is a circuit that adds the additive latency AL and the write latency CWL, and the output value is supplied to the subtractor 142. The subtractor 142 is a circuit that subtracts the lock value NT from the output value of the adder 141, and the output value is supplied to the decoder 143. The decoder 143 converts the output value of the subtractor 142 from binary to octal, generates selection signals SELU32, 34, 16, and 8 according to the upper digits, and selects signals SEL0 to SEL7 according to the lower digits. Is generated.

  Specifically, if the upper digit value of the output value of the subtractor 142 is “0”, the selection signals SELU 32, 24, 16, and 8 are all set to the low level, and if the output value is “1”, the selection signals SELU 32, 24, 16 is low level, the selection signal SELU8 is high level, if "2", the selection signals SELU32, 34 are low level, the selection signals SELU16, 8 are high level, and if "3", the selection signal SELU32 is low level. The selection signals SELU 24, 16, and 8 are set to the high level, and if “4”, the selection signals SELU 32, 24, 16, and 8 are all set to the low level. As a result, the number of FIFO circuits 111 to 114 through which the termination control signal ODTi passes is selected according to the upper digit of the subtractor 142.

  The decoder 143 sets any one of the selection signals SEL0 to SEL7 to a high level according to the value of the lower digit of the subtractor 142. For example, if the value of the lower digit of the subtractor 142 is “1”, the selection signal SEL1 is set to high level, and if the value of the lower digit of the subtractor 142 is “7”, the selection signal SEL7 is set to high level. The selection signals SEL0 to SEL7 are supplied to the output pointer generation circuit 160 shown in FIG. As will be described later, the output pointer generation circuit 160 is a circuit that generates the output pointer OP based on the selection signals SEL0 to SEL7 and the input pointer IP.

  As shown in FIG. 7, each of the FIFO circuits 111 to 114, 120 has eight latch circuits. As described above, the FIFO circuits 111 to 114 and 120 are point shift type FIFO circuits, which latch the termination control signal ODTi in response to the activation of the input pointer, and also use the latched termination control signal ODTi to activate the output pointer. Output in response to conversion. The input pointer IP is generated by a frequency dividing circuit 151 that divides the internal clock signal PCLK that is the first clock signal.

  FIG. 9 is a circuit diagram of the frequency dividing circuit 151.

  As shown in FIG. 9, the frequency dividing circuit 151 is composed of eight flip-flop circuits FF10 to FF17 connected in a circulating manner. The output signals of the flip-flop circuits FF10 to FF17 are used as pointer signals IP0 to IP7 constituting the input pointer IP. The pointer signals IP0 to IP7 are a plurality of second clock signals.

  These flip-flop circuits FF10 to FF17 perform a latch operation in synchronization with the internal clock signal PCLK. A power-on signal PON that is temporarily at a high level when the power is turned on is supplied to the set node of the predetermined flip-flop circuit FF10. Set nodes of other flip-flop circuits FF11 to FF17 are fixed to the ground level.

  Therefore, when the power is turned on, high level data is latched in the flip-flop circuit FF10, and then the high level data circulates in the flip-flop circuits FF10 to FF17 in synchronization with the clocking of the internal clock signal PCLK. Thereby, as shown in FIG. 10, the pointer signals IP0 to IP7 constituting the input pointer IP are sequentially activated in synchronization with the internal clock signal PCLK. The activation cycle of each of the pointer signals IP0 to IP7 is 8 clock cycles of the internal clock signal PCLK.

  FIG. 11 is a circuit diagram of the FIFO circuit 111.

  As shown in FIG. 11, the FIFO circuit 111 includes eight latch circuits LAT0 to LAT7 connected in parallel. The input nodes of these eight latch circuits LAT0 to LAT7 are commonly connected to receive the termination control signal ODTi (in), and the output nodes of the eight latch circuits LAT0 to LAT7 are commonly connected to be terminated control signal ODTi (out ) Is output. A level keeper LK1 that holds the level of the output signal is connected to the output nodes of the latch circuits LAT0 to LAT7.

  The latch signals LAT0 to LAT7 are supplied with pointer signals IP0 to IP7 constituting the input pointer IP, respectively. In the FIFO circuit 111, the input pointer IP also serves as an output pointer.

  FIG. 12 is a circuit diagram of the latch circuit LAT0.

  As shown in FIG. 12, the latch circuit LAT0 includes an input latch unit Li composed of inverter circuits IV1 and IV2 connected in a circulating manner and an output latch unit Lo composed of inverter circuits IV3 and IV4 connected in a circulating manner. An inverter circuit IV5 is inserted between the input node Ni and the input latch unit Li, an inverter circuit IV6 is inserted between the input latch unit Li and the output latch unit Lo, and the output latch unit Lo and the output node An inverter circuit IV7 is inserted between No.

  Here, the inverter circuits IV2, IV5 to IV7 are tristate type, and the inverter circuits IV5 and IV7 are activated when the pointer signal IP0 is at a high level, and the inverter circuits IV5 and IV7 are activated when the pointer signal IP0 is at a low level. Circuits IV2 and IV6 are activated. Accordingly, the latch circuit LAT0 latches the termination control signal ODTi supplied to the input node Ni in the input latch unit Li when the pointer signal IP0 is at the high level, and when the pointer signal IP0 changes to the low level, the input latch unit The termination control signal ODTi latched in Li is transferred to the output latch unit Lo. When the pointer signal IP0 changes to the high level again, the termination control signal ODTi latched in the output latch unit Lo is output from the output node No. Thus, since the pointer signal IP0 is an input pointer and is used as an output pointer, the pointer signal IP0 can be delayed by one cycle of the termination control signal ODTi.

  The other latch circuits LAT1 to LAT7 included in the FIFO circuit 111 have the same circuit configuration as the latch circuit LAT0 shown in FIG. 12, except that the pointer signals IP1 to IP7 are used instead of the pointer signal IP0. Yes.

  FIG. 13 is a timing chart for explaining the operation of the FIFO circuit 111.

  In the example shown in FIG. 13, the termination control signal ODTi (in) is input to the FIFO circuit 111 in synchronization with the pointer signals IP2 and IP4. In this case, the termination control signal ODTi synchronized with the pointer signal IP2 is latched by the latch circuit LAT2, and the termination control signal ODTi synchronized with the pointer signal IP4 is latched by the latch circuit LAT4.

  The termination control signal ODTi latched in the latch circuits LAT2 and LAT4 is output in synchronization with the next activated pointer signals IP2 and IP4. As a result, the FIFO circuit 111 is always given a delay of 8 clock cycles of the internal clock signal PCLK, regardless of the timing at which the termination control signal ODTi (in) is input. It is output as ODTi (out).

  The circuit configurations and operations of the other FIFO circuits 112 to 114 are the same as those of the FIFO circuit 111 described above. Therefore, if one FIFO circuit 114 is passed, the termination control signal ODTi can be delayed by 8 clock cycles, and if two FIFO circuits 113 and 114 are passed, the termination control signal ODTi is 16 clocks. A delay corresponding to the cycle can be given, and if the three FIFO circuits 112 to 114 are passed, the termination control signal ODTi can be given a delay corresponding to 24 clock cycles, and the four FIFO circuits 111 to 114 are allowed to pass. Thus, a delay of 32 clock cycles can be given to the termination control signal ODTi.

  As described above, the FIFO circuits 111 to 114 constituting the first counter circuit can switch the delay amount of the termination control signal ODTi at an 8-clock cycle pitch, and the delay of 32 clock cycles at the maximum can be changed to the termination control signal ODTi. Can be given. And since the FIFO circuits 111 to 114 are not a general counter using a shift register but a point shift type FIFO circuit, current consumption can be reduced. In addition, in the FIFO circuits 111 to 114, since the input pointer and the output pointer are shared, there is no need to generate an output pointer according to the required ODT latency, and the circuit configuration is not complicated.

  FIG. 14 is a circuit diagram of the FIFO circuit 120.

  As shown in FIG. 14, the FIFO circuit 120 includes eight latch circuits LAT32 to LAT39 connected in parallel. The input nodes of these eight latch circuits LAT32 to LAT39 are commonly connected to receive the termination control signal ODTi, and the output nodes of the eight latch circuits LAT32 to LAT39 are commonly connected to output the termination control signal ODTf. A level keeper LK2 that holds the level of the output signal is connected to the output nodes of the latch circuits LAT32 to LAT39.

  The latch circuits LAT32 to LAT39 are supplied with pointer signals IP0 to IP7 constituting the input pointer IP and pointer signals OP0 to OP7 constituting the output pointer OP, respectively.

  FIG. 15 is a circuit diagram of the latch circuit LAT32.

  As shown in FIG. 15, the latch circuit LAT32 includes a latch portion L composed of inverter circuits IV8 and IV9 connected in a circulating manner. An inverter circuit IV10 is inserted between the input node Ni and the latch unit L, and an inverter circuit IV11 is inserted between the latch unit L and the output node No.

  Here, the inverter circuits IV9 to IV11 are of a tristate type. The inverter circuit IV9 is activated when the pointer signal IP0 is at a low level, and is deactivated when the pointer signal IP0 is at a high level. The inverter circuit IV10 is activated when the pointer signal IP0 is at a high level, and is deactivated when the pointer signal IP0 is at a low level. The inverter circuit IV11 is activated when the pointer signal OP0 is at a high level, and is deactivated when the pointer signal OP0 is at a low level.

  With this configuration, the latch circuit LAT32 latches the termination control signal ODTi supplied to the input node Ni when the pointer signal IP0 is at a high level, and the pointer signal OP0 is at a high level with respect to the latched termination control signal ODTi. Output from the output node No. Therefore, the termination control signal ODTi can be delayed by the phase difference between the pointer signal IP0 and the pointer signal OP0 and output as the termination control signal ODTf.

  The other latch circuits LAT33 to LAT39 included in the FIFO circuit 120 also use the pointer signals IP1 to IP7 as the input pointer IP instead of the pointer signal IP0, respectively, and the pointer signal OP1 as the output pointer OP instead of the pointer signal OP0. Except for the use of -OP7, it has the same circuit configuration as the latch circuit LAT32 shown in FIG.

  The pointer signals OP0 to OP7 constituting the output pointer OP are generated by the output pointer generation circuit 160.

  FIG. 16 is a circuit diagram of the output pointer generation circuit 160.

  As shown in FIG. 16, the output pointer generation circuit 160 includes eight clock selectors CS0 to CS7. Each of the clock selectors CS0 to CS7 receives pointer signals IP0 to IP7 and selection signals SEL0 to SEL7 constituting the input pointer IP, and outputs pointer signals OP0 to OP7 based on them.

  Here, the pointer signals IP0 to IP7 and the selection signals SEL0 to SEL7 shown in FIG. 16 are displayed in a corresponding order. That is, in the clock selector CS0, the pointer signals IP0 to IP7 correspond to the selection signals SEL0 to SEL7, respectively, while in the clock selector CS1, the pointer signals IP0 to IP7 correspond to the selection signals SEL1 to SEL7 and SEL0, respectively. Thus, although the same signal group is input to each of the clock selectors CS0 to CS7, the correspondence relationship between the pointer signal and the selection signal is different.

  FIG. 17 is a circuit diagram of the clock selector CS0.

  As shown in FIG. 17, the clock selector CS0 includes eight NAND gate circuits G0 to G7 that receive the pointer signal IPi (i = 0 to 7) and the selection signal SELi. The output signals of these NAND gate circuits G0 to G7 are supplied to the OR gate circuit G10 via NAND gate circuits G8 and G9. With this configuration, when both of the two inputs in any of the NAND gate circuits G0 to G7 are at a high level, the pointer signal OP0 is at a high level. For example, when the selection signal SEL3 is at a high level, the NAND gate circuit G3 is selected, so that the pointer signal OP0 is at a high level in conjunction with the pointer signal IP3.

  The other clock selectors CS1 to CS7 have the same circuit configuration as the clock selector CS0 shown in FIG. 17 except that the order of the selection signals SEL0 to SEL7 input to the NAND gate circuits G0 to G7 is different. In general, in the clock selector CSi, the pointer signal IPi and the selection signal SELi + 1 are input to the same NAND gate circuit.

  With this configuration, the output pointer generation circuit 160 determines the pointer signals IP0 to IP7 constituting the input pointer IP and the pointer signals OP0 to OP7 constituting the output pointer OP depending on which of the selection signals SEL0 to SEL7 is at a high level. The correspondence relationship can be switched.

  FIG. 18 is a timing chart for explaining the operation of the output pointer generation circuit 160.

  In the example shown in FIG. 18, the selection signal SEL3 is activated to a high level. Therefore, when the pointer IP3 constituting the input pointer IP is activated, the pointer OP0 constituting the output pointer OP is activated. As a result, the difference between the input pointer IP and the output pointer OP is 3 clock cycles.

  FIG. 19 is a timing chart for explaining the operation of the FIFO circuit 120.

  Also in the example shown in FIG. 19, the selection signal SEL3 is activated to a high level, and the difference between the input pointer IP and the output pointer OP is 3 clock cycles. Further, the termination control signal ODTi input to the FIFO circuit 120 is at a low level in a period synchronized with the edges # 0 to # 3 of the internal clock signal PCLK, and in a period synchronized with the edges # 4 to # 7 of the internal clock signal PCLK. This level is high, and this pattern is repeated every 8 clock cycles.

  In this case, the termination control signal ODTi synchronized with the edges # 4 to # 7 of the internal clock signal PCLK is latched by the latch circuits LAT36 to LAT39 in synchronization with the pointer signals IP4 to IP7, respectively. The termination control signal ODTi latched in the latch circuits LAT36 to LAT39 is output as the termination control signal ODTf after three clock cycles have elapsed. As a result, a delay of 3 clock cycles, which is the difference between the input pointer IP and the output pointer OP, is given to the termination control signal ODTi, and thereby the termination control signal ODTf can be generated.

  The amount of delay by the FIFO circuit 120 can be switched at 1 clock cycle pitch in the range of 0 to 7 clock cycles according to the selection signals SEL0 to SEL7. As described above, the FIFO circuit 120 constituting the second counter circuit is not a general counter using a shift register but a point shift type FIFO circuit, so that current consumption can be reduced. it can. As for the termination control signal ODT, the same pattern may be repeatedly input in 8 clock cycles as in the example shown in FIG. 19, and in this case, the latch data of the eight latch circuits LAT32 to LAT39 is input. Does not change. For this reason, even when the termination control signal ODT having a predetermined pattern is repeatedly input, the charge / discharge current accompanying the change of the latch data does not occur, and the current consumption can be reduced.

  The above is the circuit configuration and operation of the latency counter 100a according to the first embodiment. As described above, in the latency counter 100a according to the present embodiment, the first counter circuit (FIFO circuits 111 to 114) in which the delay amount switching pitch is 8 clock cycles and the delay amount switching pitch in the first clock cycle is 1 clock cycle. Since the two counter circuits (FIFO circuit 120) are connected in series, a wide setting range of the latency can be secured in units of one clock cycle. Specifically, the latency can be arbitrarily set in units of one clock cycle in the range of 0 to 40.

  The first counter circuit is configured by four FIFO circuits 111 to 114 having a delay of 8 clock cycles, and the FIFO circuits 111 to 114 that are not used are bypassed, so that current consumption can be suppressed. It becomes. In addition, since the FIFO circuits 111 to 114 and 120 are point shift type FIFO circuits, it is possible to reduce current consumption compared to the case where a shift register is used.

  Next, a second embodiment of the present invention will be described.

  FIG. 20 is a circuit diagram of the latency counter 100b according to the second embodiment.

  As shown in FIG. 20, the latency counter 100b according to the second embodiment is different from the first embodiment shown in FIG. 7 in that a frequency dividing circuit 152 is added instead of the output pointer generating circuit 160 being deleted. This is different from the latency counter 100a according to the form. Since the other points are the same as those of the latency counter 100a according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 21 is a circuit diagram of the frequency dividing circuit 152.

  As shown in FIG. 21, the frequency dividing circuit 152 is constituted by eight flip-flop circuits FF20 to FF27, and the output signals thereof are used as pointer signals OP0 to OP7 constituting the output pointer OP.

  These flip-flop circuits FF20 to FF27 perform a latch operation in synchronization with the internal clock signal PCLK. Output signals of the clock selectors CS0 to CS7 are supplied to input nodes of the flip-flop circuits FF20 to FF27, respectively. The circuit configurations and functions of the clock selectors CS0 to CS7 are as described with reference to FIGS.

  If the frequency dividing circuit 152 having such a configuration is used, the timing at which the pointer signals OP0 to OP7 change is synchronized with the internal clock signal PCLK. Therefore, the pointer signals IP0 to IP7 constituting the input pointer IP and the output pointer OP are set. It is possible to reduce the skew with the pointer signals OP0 to OP7 to be configured.

  As a result, even when a higher-speed clock signal is used than in the first embodiment, the latency can be correctly counted.

  Next, a third embodiment of the present invention will be described.

  FIG. 22 is a circuit diagram of a latency counter 100c according to the third embodiment.

  As shown in FIG. 22, the latency counter 100 b according to the third embodiment is different from the latency counter 100 a according to the first embodiment shown in FIG. 7 in that a shift circuit 121 is used instead of the FIFO circuit 120. ing. Accordingly, the output pointer generation circuit 160 has been deleted. Further, in the present embodiment, the selection signal SELU8 is input to the frequency divider 151, and when it is at a low level, the operation of the frequency divider 151 is stopped. Since the other points are the same as those of the latency counter 100a according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 23 is a circuit diagram of the shift circuit 121.

  As shown in FIG. 23, the shift circuit 121 includes a shift register SL including eight flip-flop circuits FF32 to FF39 connected in cascade, and a selector SEL that supplies a termination control signal ODTi to the shift register SL. . The selector SEL supplies the termination control signal ODTi to any one of the input nodes S32 to S39 of the flip-flop circuits FF32 to FF39 based on the selection signals SEL0 to SEL7. As a result, the number of stages of the shift register SL through which the termination control signal ODTi passes is variable, so that any latency can be counted.

  With such a configuration, the delay amount by the shift circuit 121 can be switched at a clock cycle pitch in the range of 0 to 7 clock cycles. However, since the shift circuit 121 uses a shift register, current consumption increases as the number of flip-flop circuits used (shift amount) increases.

  However, in this embodiment, when the selection signal SELU8 is at a low level, that is, when the latency count by the latency counter 100c is 7 or less, the operation of the frequency divider circuit 151 is stopped. The current consumption due to 151 can be reduced.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 24 is a circuit diagram of a latency counter 100d according to the fourth embodiment.

  As shown in FIG. 24, in the latency counter 100b according to the fourth embodiment, the shift circuit 122 is used instead of the FIFO circuit 120, and the FIFO circuit 115 and the synthesis circuit 170 that controls the first counter circuit are provided. In addition, it is different from the latency counter 100a according to the first embodiment shown in FIG. 7 in that a selector 135 and a NOR gate circuit G11 for controlling the selector 135 are added. Since the other points are the same as those of the latency counter 100a according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The FIFO circuit 115 gives a delay of 4 clock cycles to the termination control signal ODTi output from the selector 134. The termination control signal ODTi output from the FIFO circuit 115 is supplied to the shift circuit 122 via the selector 135.

  FIG. 25 is a circuit diagram of the FIFO circuit 115 and the synthesis circuit 170.

  As shown in FIG. 25, the FIFO circuit 115 includes four latch circuits LAT32 to LAT35 connected in parallel. The input nodes of the four latch circuits LAT32 to LAT35 are connected in common and the termination control signal ODTi (in) is input, and the output nodes of the four latch circuits LAT32 to LAT35 are connected in common and the termination control signal ODTi (out) ) Is output. A level keeper LK3 that holds the level of the output signal is connected to the output nodes of the latch circuits LAT32 to LAT35.

  The latch circuits LAT32 to LAT35 are respectively supplied with pointer signals IP04, IP15, IP26, and IP37 generated based on the input pointer IP. Also in the FIFO circuit 115, the input pointer and the output pointer are shared. The pointer signals IP04, IP15, IP26, and IP37 are generated by the synthesis circuit 170 shown in FIG. The combining circuit 170 is composed of an OR gate circuit that combines pointer signals IP0 and IP4, IP1 and IP5, IP2 and IP6, and IP3 and IP7. As a result, the pointer signals IP04, IP15, IP26, and IP37 have different phases and are activated every four clock cycles.

  With this configuration, the FIFO circuit 115 can give a delay of 4 clock cycles to the termination control signal ODTi output from the selector 134.

  FIG. 26 is a circuit diagram of the shift circuit 122.

  As shown in FIG. 26, the shift circuit 122 includes a shift register SL including four cascade-connected flip-flop circuits FF36 to FF39, and a selector SEL that supplies a termination control signal ODTi to the shift register SL. . The selector SEL supplies the termination control signal ODTi to any one of the input nodes S36 to S39 of the flip-flop circuits FF36 to FF39 based on the selection signals SEL0 to SEL7. As a result, the number of stages of the shift register SL through which the termination control signal ODTi passes is variable, so that any latency can be counted.

  With this configuration, the delay amount by the shift circuit 122 can be switched at a clock cycle pitch in the range of 0 to 3 clock cycles. Since the shift circuit 122 uses the shift register SL, the current consumption increases as the number of stages (shift amount) of the flip-flop circuit used increases, but the shift circuit 122 used in the present embodiment is the flip-flop circuit used. Since the maximum number of stages is four, the current consumption does not increase so much.

  As shown in FIG. 24, in this embodiment, the selection signals SEL0 to SEL3 are input to the NOR gate circuit G11, and the selector 135 is controlled by the output signal. The selector 135 selects the input node a when the output signal of the NOR gate circuit G11 is high level, and selects the input node b when the output signal is low level.

  As a result, when the value of the lower digit of the subtracter 142 shown in FIG. 8 is any one of “0” to “3”, the selector 135 selects the input node b, so that the FIFO circuit 115 is bypassed. The On the other hand, when the value of the lower digit of the subtracter 142 is any one of “4” to “7”, the selector 135 selects the input node a, so that the termination control signal ODTi passes through the FIFO circuit 115.

  For example, if the latency count by the latency counter 100d is “15”, the termination control signal ODTi is shifted after passing through the FIFO circuits 114 and 115 and delayed by 12 clock cycles (= 8 + 4). Circuit 122 adds a delay of 3 clock cycles. Thus, in the present embodiment, by using the FIFO circuit 115, the number of stages of the shift register constituting the shift circuit 122 is reduced, so that it is possible to suppress current consumption generated by the shift register. .

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above-described embodiment, the latency counter that delays the termination control signal ODTi has been described as an example. The application target of the present invention is not limited to this, and can be widely applied to semiconductor devices that delay an arbitrary control signal in synchronization with a clock signal.

  Further, the connection order of the first counter circuit and the second counter circuit is not limited to the above embodiment, and may be reversed.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Sense circuit 15 Data controller 16 FIFO circuit 17 Data input / output circuit 18 Strobe circuit 19 Strobe controller 21 Data input / output terminals 22 and 23 Strobe terminals 24 and 25 Clock terminal 26 Clock enable Terminal 27 Address terminal 28 Command terminal 29 Alert terminal 30, 31 Power supply terminal 32 Data mask terminal 33 ODT terminal 40 Clock generator 41 DLL circuit 42 Mode register 43 Command decoder 44 Control logic circuit 45 Output circuit 46 Power supply circuit 50 Row control circuit 51 Address Buffer 52 Refresh counter 60 Column control circuit 61 Address buffer 62 Burst counter 71, 2 delay line 73 DLL control circuit 81 clock receiver 82 ODT receiver 83 latch circuit 84 ODT driver 100, 100a to 100d, 100X latency counter 111 to 115, 120 FIFO circuit 121, 122 shift circuit 131 to 135 selector 140 shift amount decoder 141 addition 142 Subtractor 143 Decoder 151, 152 Frequency divider 160 Output pointer generator 170 Synthesizing circuit BL Bit lines CS0 to CS7 Clock selectors FF0 to FF39 Flip-flop circuits G0 to G11 Gate circuits IV1 to IV11 Inverter circuit L Latch units LAT0 to LAT7 , LAT32 to LAT39 Latch circuit Li Input latch part LK1 to LK3 Level keeper Lo Output latch part MC Memory cell Ni Input node No Out Node S0~S39 input nodes SA the sense amplifier SEL selector SL shift register WL the word line

Claims (20)

First and second counter circuits that delay the control signal in synchronization with the first clock signal are connected in series,
The first counter circuit switches a delay amount of the control signal at a first pitch in synchronization with the first clock signal;
The semiconductor device, wherein the second counter circuit switches a delay amount of the control signal at a second pitch smaller than the first pitch in synchronization with the first clock signal.   2. The semiconductor device according to claim 1, wherein the first pitch is larger than a maximum delay amount of the control signal by the second counter circuit.   The first pitch is N cycles of the first clock signal, and the second pitch is M cycles of the period of the first clock signal (where M <N). Item 3. The semiconductor device according to Item 1 or 2.   The semiconductor device according to claim 3, wherein the second pitch is one clock cycle of the first clock signal.   5. The semiconductor device according to claim 3, wherein the first counter circuit includes a plurality of FIFO circuits having a delay amount of N cycles of the first clock signal.   The semiconductor device according to claim 5, wherein the first counter circuit further includes a selector that switches the number of the plurality of FIFO circuits through which the control signal passes.   The FIFO circuit delays the control signal by N cycles of the first clock signal in synchronization with a plurality of second clock signals having a period N times that of the first clock signal and having different phases. The semiconductor device according to claim 5, wherein:   The FIFO circuit captures the control signal in synchronization with a corresponding one of the plurality of second clock signals, and outputs the control signal captured in synchronization with a corresponding one of the plurality of second clock signals The semiconductor device according to claim 7, further comprising a plurality of first latch circuits. The plurality of first latch circuits included in the same FIFO circuit capture the control signal in synchronization with different ones of the plurality of second clock signals, and different ones of the plurality of second clock signals. The control signal is output in synchronization with
Among the plurality of second clock signals supplied to the same FIFO circuit, the plurality of second clock signals used for capturing the control signal and the plurality of second clock signals used for outputting the control signal The semiconductor device according to claim 8, wherein the relationship between and is fixed.   The plurality of first latch circuits included in the same FIFO circuit each capture and output the control signal in synchronization with the same one of the plurality of second clock signals. 9. The semiconductor device according to 9. The second counter circuit captures the control signal in synchronization with a corresponding one of the plurality of second clock signals, and captures the control signal in synchronization with a corresponding one of the plurality of second clock signals. A plurality of second latch circuits for outputting signals;
The plurality of second latch circuits capture the control signal in synchronization with different ones of the plurality of second clock signals, and perform the control in synchronization with different ones of the plurality of second clock signals. Output signal,
Among the plurality of second clock signals supplied to the second counter circuit, the plurality of second clock signals used for capturing the control signal and the plurality of second clock signals used for outputting the control signal. 11. The semiconductor device according to claim 7, wherein the relationship with the clock signal is variable. A first and second frequency dividing circuit for generating the plurality of second clock signals by dividing the first clock signal;
Among the plurality of second clock signals supplied to the second counter circuit, the plurality of second clock signals used for capturing the control signal are generated by the first frequency dividing circuit,
Among the plurality of second clock signals supplied to the second counter circuit, the plurality of second clock signals used for outputting the control signal are generated by the second frequency dividing circuit. The semiconductor device according to claim 11, wherein the semiconductor device is characterized in that:   6. The second counter circuit includes a shift register having a variable number of stages that performs a shift operation in synchronization with the first clock signal. Semiconductor device.   The first counter circuit includes a plurality of first FIFO circuits having a delay amount of N cycles of the first clock signal, and P cycles of the first clock signal (where M <P <N). The semiconductor device according to claim 13, further comprising a second FIFO circuit having a delay amount. The first counter circuit further includes a selector that switches the number of the first and second FIFO circuits through which the control signal passes,
The selector switches so that the control signal bypasses the second FIFO circuit when the number of stages of the shift register constituted by the second counter circuit is a first value, and the number of stages of the shift register 15. The semiconductor device according to claim 14, wherein the control signal is switched so as to pass through the second FIFO circuit when is a second value larger than the first value. A frequency dividing circuit for generating the plurality of second clock signals by dividing the first clock signal;
14. The semiconductor device according to claim 5, wherein when the control signal bypasses all of the first and second FIFO circuits, the frequency divider circuit is deactivated.   The semiconductor device according to claim 1, wherein the control signal is a termination control signal. A first counter circuit comprising a plurality of FIFO circuits each including a plurality of first latch circuits for latching control signals;
A selector for switching the number of the FIFO circuits through which the control signal passes;
A second counter circuit that is provided separately from the first counter circuit and switches a delay amount of the control signal in synchronization with a first clock signal;
A frequency dividing circuit that generates a plurality of second clock signals having different phases by dividing the first clock signal;
The plurality of first latch circuits included in the same FIFO circuit capture the control signal in synchronization with different ones of the plurality of second clock signals, and different ones of the plurality of second clock signals. The control signal is output in synchronization with
Each of the plurality of first latch circuits captures and outputs the control signal in synchronization with the same one of the plurality of second clock signals. The second counter circuit includes a plurality of second latch circuits that latch the control signal,
The plurality of second latch circuits capture the control signal in synchronization with different ones of the plurality of second clock signals, and perform the control in synchronization with different ones of the plurality of second clock signals. Output signal,
Among the plurality of second clock signals supplied to the plurality of second latch circuits, the plurality of second clock signals used for capturing the control signal and the plurality of plurality used for outputting the control signal. 19. The semiconductor device according to claim 18, wherein the relationship with the second clock signal is variable.   The semiconductor device according to claim 18, wherein the second counter circuit includes a shift register having a variable number of stages that performs a shift operation in synchronization with the first clock signal.

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