JP2015165530A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device capable of suppressing current collapse and a method for manufacturing the same. The present invention relates to a channel layer 3 formed on a semiconductor substrate 1, a barrier layer 4 made of a nitride semiconductor containing In and formed on the channel layer 3, and partially on the barrier layer 4. , A cap layer 5 made of a nitride semiconductor and partially formed on the barrier layer 4, and a drain electrode 7 partially formed on the cap layer 5. The end of the gate electrode 8 on the side close to the drain electrode 7 and the cap layer 5 are formed apart from each other. [Selection] Figure 1

Description

  The present invention relates to a semiconductor device which is a heterojunction field effect transistor including a nitride semiconductor, and a manufacturing method thereof.

Heterojunction field effect transistor using a nitride semiconductor containing In, in particular, In _x Al _y Ga _1-xy N (0 <x ≦ 1, 0 <y ≦ 1, 0 <x + y ≦ 1) as a barrier layer Is expected to contribute to higher output of the transistor since it has a high carrier concentration.

  However, when InAlGaN is used as a barrier layer, a high Al composition is required for the barrier layer in order to reduce lattice mismatch between the barrier layer and the channel layer. Therefore, the contact resistance between the barrier layer and the ohmic electrode tends to increase. Moreover, the barrier layer surface is easily oxidized.

  As a result, high output of the transistor cannot be realized, transistor characteristics change over time, pulse driving called current collapse occurs, or current reduction phenomenon occurs during high-frequency operation. There was a problem.

  On the other hand, a technique is disclosed in which a cap layer made of GaN is formed on an InAlN barrier layer, and a gate electrode is formed on the cap layer (for example, Patent Document 1). This technique has been applied to a transistor using AlGaN that does not contain In as a barrier layer (for example, Patent Document 2).

JP 2012-33653 A JP-A-2005-286135

  However, it is difficult to meet the practically required level particularly in terms of current collapse in the characteristics obtained by the structure in which the cap layer made of GaN is formed on the InAlN barrier layer and the gate electrode is formed on the cap layer. There is a need for further improvement in characteristics.

  The present invention has been made to solve the above-described problems, and is a heterojunction field effect transistor using a nitride semiconductor containing In as a barrier layer, and a semiconductor capable of suppressing current collapse. It is an object of the present invention to provide an apparatus and a manufacturing method thereof.

  A semiconductor device according to one embodiment of the present invention is a heterojunction field effect transistor including a nitride semiconductor, the channel layer formed over a semiconductor substrate, and the nitride containing In formed over the channel layer A barrier layer made of a semiconductor, a gate electrode partially formed on the barrier layer, a cap layer made of the nitride semiconductor partially formed on the barrier layer, and a portion on the cap layer And at least an end portion of the gate electrode closer to the drain electrode and the cap layer are formed apart from each other.

  A method for manufacturing a semiconductor device according to one embodiment of the present invention is a method for manufacturing a heterojunction field effect transistor including a nitride semiconductor, and the nitride including a channel layer and In is formed on a semiconductor substrate using an epitaxial growth method. A layer structure forming step of sequentially forming a barrier layer made of a semiconductor and a cap layer made of the nitride semiconductor, an electrode forming step of forming a source electrode and a drain electrode apart from each other on the cap layer, and the source electrode A removing step of removing a part of the cap layer located between the drain electrode and an insulating film forming step of forming an insulating film covering at least the region including the barrier layer exposed in the removing step; A part of the insulating film located between the source electrode and the drain electrode is removed to expose the barrier layer. An exposure step, and a gate electrode formation step for forming a gate electrode on the barrier layer exposed in the exposure step, the exposure step without exposing the cap layer on the side close to the drain electrode, A step of exposing the barrier layer;

  A method for manufacturing a semiconductor device according to another aspect of the present invention is a method for manufacturing a heterojunction field effect transistor including a nitride semiconductor, and the nitride including the channel layer and In on a semiconductor substrate using an epitaxial growth method. A layer structure forming step of sequentially forming a barrier layer made of a physical semiconductor; a mask layer forming step of partially forming a mask layer on the barrier layer; and the nitridation using an epitaxial growth method on the barrier layer. A cap layer forming step of forming a cap layer made of a physical semiconductor, a removing step of removing the mask layer, an electrode forming step of forming a source electrode and a drain electrode separately from each other on the cap layer, Insulating film type for forming an insulating film covering the region including the barrier layer exposed in the removing step A step of removing a part of the insulating film located between the source electrode and the drain electrode to expose the barrier layer; and a gate electrode on the barrier layer exposed in the exposing step. A gate electrode forming step to be formed, and the exposing step is a step of exposing the barrier layer without exposing the cap layer on the side close to the drain electrode.

  According to the above aspect of the present invention, the end portion of the gate electrode close to the drain electrode and the cap layer are formed apart from each other. Therefore, the cap layer at the end close to the drain electrode, where the strong electric field is applied, is removed, and the trapping of electrons at the location is suppressed, so that current collapse (current drop during pulse driving) ) Can be suppressed.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is a top view which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of a heterojunction field effect transistor in case a cap layer exists in the gate electrode and its vicinity. It is the figure which showed the drain current-drain voltage characteristic at the time of direct current drive and pulse drive of the structure shown in FIG. 1 and the structure shown in FIG. It is a figure which shows the relationship between the heat processing temperature and the electron mobility of the semiconductor device regarding embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is sectional drawing which shows the structure of the semiconductor device regarding embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment. It is a figure which illustrates the manufacturing process of the semiconductor device regarding an embodiment.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

<First Embodiment>
<Configuration>
FIG. 1 is a cross-sectional view illustrating the structure of a heterojunction field effect transistor made of a nitride semiconductor according to this embodiment. FIG. 2 is a top view thereof.

  As shown in FIG. 1, a heterojunction field effect transistor as a semiconductor device according to this embodiment includes a semiconductor substrate 1, a buffer layer 2 formed on the (0001) plane of the semiconductor substrate 1, and a channel layer 3. A barrier layer 4, a cap layer 5, a source electrode 6, a drain electrode 7, a gate electrode 8, a protective film 9, and an element isolation region 10.

The channel layer 3 is formed on the buffer layer 2. The channel layer 3 is represented by Al _z Ga _1-z N (0 ≦ z ≦ 1, GaN when z = 0).

The barrier layer 4 is formed on the channel layer 3. The barrier layer 4 is represented by In _x Al _y Ga _1-xy N (0 <x ≦ 1, 0 <y ≦ 1, 0 <x + y ≦ 1).

  When the channel layer 3 and the barrier layer 4 are formed on the (0001) plane of the semiconductor substrate 1 via the buffer layer 2, a high concentration called a two-dimensional electron gas (2-Dimensional Electron Gas, 2DEG) is formed at the heterointerface. A career occurs. Since an undoped semiconductor is used for the channel layer 3, 2DEG has high mobility. Therefore, a transistor using this structure can achieve high frequency and high current.

  The cap layer 5 is formed on a part of the barrier layer 4. The cap layer 5 is made of a nitride semiconductor.

  The gate electrode 8 is formed in a part on the barrier layer 4. Further, the cap layer 5 is not formed in the periphery of the region where the gate electrode 8 is formed (including not only the side close to the drain electrode 7 but also the side close to the source electrode 6).

  The source electrode 6 is formed on a part of the cap layer 5.

  The drain electrode 7 is formed on a part of the cap layer 5. Further, the source electrode 6 and the drain electrode 7 are disposed on different sides as viewed from the gate electrode 8.

  When a voltage is appropriately applied to the gate electrode 8, the source electrode 6 and the drain electrode 7, the heterojunction field effect transistor operates.

  The element isolation region 10 is formed in a region on the channel layer 3 where the barrier layer 4 is not formed.

  The protective film 9 is formed so as to cover the barrier layer 4, the cap layer 5, and the element isolation region 10. The protective film 9 is formed in a region excluding the region where the gate electrode 8, the source electrode 6 and the drain electrode 7 are formed.

  According to such a configuration, the source electrode 6 and the drain electrode 7 are formed on the cap layer 5 made of GaN having a band gap smaller than that of the barrier layer 4. Can be realized.

  Further, as described above, the cap layer 5 does not exist in the vicinity of the gate electrode 8 and the drain side end of the gate electrode 8. That is, the end of the gate electrode 8 on the side close to the drain electrode 7 and the cap layer 5 are formed to be separated from each other.

  FIG. 3 is a cross-sectional view showing the structure of the heterojunction field effect transistor in the case where the cap layer 5a exists in the vicinity of the gate electrode 8a.

  FIG. 4 is a diagram showing drain current-drain voltage characteristics at the time of DC driving and pulse driving of the structure shown in FIG. 1 and the structure shown in FIG. In FIG. 4, the vertical axis represents the drain current [a. u. ], The horizontal axis represents the drain voltage [V], respectively. Since the drain current-drain voltage characteristics at the time of DC driving are almost the same regardless of the presence or absence of the cap layer, in FIG. 4, the structure without the cap layer (the structure shown in FIG. 1) is the same at the time of DC driving. Only the drain current-drain voltage characteristics are shown. The pulse driving condition is a rectangular wave having a pulse width of 1 [μsec] and a duty ratio of 0.1 [%].

  As shown in FIG. 4, the drain current value during pulse driving is lower than the drain current value during DC driving. This is a phenomenon called current collapse, which is well known for nitride semiconductor transistors.

  Further, when the amount of decrease is compared, the structure shown in FIG. 1 (corresponding to a pulse without GaN cap) has a current drop due to current collapse compared to the structure shown in FIG. 3 (corresponding to a pulse with GaN cap). It can be seen that the effect of is significantly suppressed.

  This current collapse is a phenomenon that does not occur in, for example, a conventional transistor having an AlGaN barrier / GaN channel structure, and is a phenomenon peculiar to a transistor using a nitride semiconductor containing In as a barrier layer. The inventors have found that the cause is that when a large number of crystal defects are formed on the surface of the cap layer 5 or in the crystal, electrons are trapped in the defect. The inventors have found that the current is reduced because electrons are trapped in the defect during pulse driving.

  When a nitride semiconductor containing In is used as the barrier layer 4, the crystal growth temperature is desirably 900 ° C. or lower in order to prevent deterioration of crystal quality due to In aggregation or desorption.

  On the other hand, in order to form a GaN layer with good crystal quality, a crystal growth temperature of 1000 ° C. or higher is generally required. However, when the cap layer 5 made of GaN is formed at a high temperature of 1000 ° C. or more, In aggregation, desorption, or nitrogen desorption occurs in the barrier layer 4 made of a nitride semiconductor containing In. Therefore, the inventors have found that the crystal quality is deteriorated and the carrier concentration or mobility is lowered.

FIG. 5 is a diagram showing the relationship between the heat treatment temperature and the electron mobility. In FIG. 5, the vertical axis represents electron mobility [cm ² / Vs], and the horizontal axis represents temperature [° C.]. Considering the relationship shown in FIG. 5, it is desirable that the crystal growth temperature of the cap layer 5 made of GaN is 900 ° C. or less at which the deterioration of the crystal quality does not occur.

  However, since the cap layer 5 made of GaN formed at 900 ° C. or less contains many crystal defects, a current drop due to current collapse occurs as shown in FIG. In order to solve this problem, the cap layer 5 does not exist under the gate electrode where the electric field is concentrated and at the gate electrode end, particularly at the drain-side gate electrode end.

  The electric field strength is maximized at the gate electrode end on the drain side and rapidly decreases as the distance from the gate electrode end increases. Therefore, if there is even a region where the cap layer 5 does not exist, a current collapse suppressing effect can be obtained. Moreover, if the said area | region becomes large, the current collapse suppression effect will increase. However, since it is preferable to have the cap layer 5 in order to suppress the long-term surface state change of the barrier layer 4, the cap layer 5 may be formed according to the desired element lifetime, electrical characteristics, or processing process accuracy. What is necessary is just to design the width | variety of the area | region which does not exist.

  Further, a protective film 9 is formed on the barrier layer 4 on the drain electrode 7 side from the end of the gate electrode 8 to further reduce current collapse by reducing the defect level formed on the surface of the barrier layer 4. be able to.

  As a result, when a nitride semiconductor containing In is used as a barrier layer, a large current can be realized and a high output transistor can be obtained.

<Manufacturing method>
Next, an example of a manufacturing method of the heterojunction field effect transistor made of the nitride semiconductor shown in FIG. 1 will be described.

First, a buffer layer for reducing crystal lattice distortion by applying an epitaxial growth method such as a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method on a semiconductor substrate 1 made of SiC. 2, channel layer 3 made of Al _z Ga _1-z N (0 ≦ z ≦ 1), In _x Al _y Ga _1-xy N (0 <x ≦ 1, 0 <y ≦ 1, 0 <x + y ≦ The barrier layer 4 made of 1) and the cap layer 5 made of GaN are epitaxially grown (FIG. 6).

  The semiconductor substrate 1 is not limited to one made of SiC, but may be one made of sapphire, Si, GaN, AlN, or the like. When a semiconductor substrate having a lattice constant close to that of the channel layer is used, the buffer layer 2 may not be provided.

  Next, the source electrode 6 and the drain electrode 7 are formed on the cap layer 5 so as to be separated from each other. For the formation, a method of depositing a layer structure using an evaporation method or a sputtering method, and further forming by a lift-off method or the like can be employed (FIG. 7). As the source electrode 6 and the drain electrode 7, for example, Ti / Al / Ti / Au laminated with a thickness of 20/40/20/50 [nm] can be employed.

  In order to reduce the contact resistance of these electrodes, heat treatment is performed at 850 ° C. for 1 minute using a rapid thermal annealing (RTA) method. The source electrode 6 and the drain electrode 7 may be made of materials such as Pt, Nb, Au, Hf, Zr, Sr, Ni, Ta, Mo, or W in addition to Ti, Al, or Au. In order to reduce the resistance, a technique such as electron beam irradiation or laser irradiation may be used.

Next, the element isolation region 10 is formed in the channel layer 3 and the barrier layer 4 outside the region for manufacturing the transistor by using, for example, ion implantation or etching (FIG. 8). In the case of using an ion implantation method, for example, Ar may be implanted with an acceleration energy of 300 [keV] and a dose of 5 × 10 ¹⁴ [cm ⁻² ]. FIG. 8 shows a method by an ion implantation method.

  Next, using a pattern formed on the cap layer 5 with a resist or the like, by a reactive ion etching (RIE) method or the like, a region where the gate electrode 8 is to be formed later and a region corresponding to the region (source electrode 6 and drain) are formed. The cap layer 5 in a region located between the electrodes 7) is selectively removed to expose the barrier layer 4 (FIG. 9).

Subsequently, the protective film 9 made of aluminum oxide Al ₂ O ₃ , silicon nitride SiN, silicon oxide SiO ₂ or the like is formed using a sputtering method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like. For example, 50 [nm] is formed (FIG. 10).

  Here, in FIG. 10, the entire semiconductor surface is covered with the protective film 9, but the entire surface is not necessarily covered. However, in order to obtain the effect of the present invention, at least the region on the drain electrode 7 side from the end portion of the gate electrode 8 in the barrier layer 4 exposed by removing the cap layer 5 is covered. There is a need. This is because, when the transistor is operated, current collapse is caused by a region where the end of the gate electrode 8 to which a strong electric field is applied is in contact with the semiconductor surface.

  Next, using a pattern formed on the protective film 9 with a resist or the like, a region in which a gate electrode is formed using a reactive ion etching (RIE) method or a wet etching method (between the source electrode 6 and the drain electrode 7). The protective film 9 in the region located at (5) is selectively removed to expose the barrier layer 4 (FIG. 11). Here, in this step, the cap layer 5 on the side close to the drain electrode 7 is not exposed.

  Subsequently, a gate electrode 8 in which Ni / Au is laminated at a thickness of 30/100 [nm] is deposited using an evaporation method or a sputtering method, and is formed in the above region by a lift-off method or the like (FIG. 12). ). The gate electrode 8 only needs to obtain Schottky characteristics, and may be formed of a single layer or a laminated film containing a material having a high work function such as Pt, Ir, Pd, Ni, or Au.

  With the above method, the heterojunction field effect transistor having the structure shown in FIGS. 1 and 12 is manufactured. Although only the minimum necessary elements that operate as a transistor are described above, they are finally used as a device through processes such as wiring electrode formation, via hole formation, and electrode protection film formation. Therefore, the electrode and the protective film may have a multilayer structure. Alternatively, a multi-finger structure in which a plurality of transistors are connected may be employed.

  Moreover, the order of the formation process of the source electrode 6, the drain electrode 7, the gate electrode 8, the protective film 9, and the element isolation region 10 may be changed. For example, the element isolation region 10 may be formed before the source electrode 6 and the drain electrode 7 are formed.

  Further, in the manufacturing method and the drawings described above, a region where the gate electrode 8 and the protective film 9 are opened is described in the approximate center of the region where the cap layer 5 on the barrier layer 4 is removed. Since the effect of the present invention can be obtained even if the position is deviated from the center, the formation position is not limited to the center.

  13 and 14, the cap layer 5 and the gate electrode may be in contact with each other between the gate electrode and the source electrode 6 (the gate electrode 8b in FIG. 13). , And the gate electrode 8c in FIG. As described above, the main cause of current collapse is the trapping of electrons at the gate electrode end on the drain electrode side where the electric field is concentrated, and removing the cap layer 5 at the gate electrode end on the source electrode side Although effective in reducing current collapse, it does not contribute much. Therefore, when the distance between the source electrode 6 and the gate electrode is shortened and the access resistance is reduced to further increase the output, the cap layer 5 and the gate electrode may be in contact with each other.

  The gate electrode has a T-shaped shape (a gate electrode 8d in FIG. 15) in which a part of the gate electrode projects on the protective film, or a Γ-shaped shape (a gate electrode 8e in FIG. 16) that projects only on the drain side. ). That is, the side surface of the gate electrode closer to the drain electrode 7 may be stepped (stepped). With such a structure, the electric field concentrates also in the vicinity of the end portion of the overhanging portion, so that the electric field strength at the gate electrode end is reduced and current collapse can be suppressed. Note that in the T-type gate electrode structure shown in FIG. 15, the overhanging length may be determined according to the electric field strength, and the overhanging lengths on the source electrode side and the drain electrode side may be different.

  Further, the protruding portion of the gate electrode has a stepped shape of at least one step above the region where the cap layer 5 on the drain electrode side is removed (the gate electrode 8f in FIG. 17 and the gate in FIG. 18). By using the electrode 8g), the electric field strength in the region where the drain electrode side end of the gate electrode is in contact with the barrier layer 4 can be significantly reduced, and current collapse can be greatly suppressed.

An example of a manufacturing method of the structure will be described. In forming the protective film 9 in FIG. 10, the protective film 9 composed of two or more insulating films in which SiO ₂ is formed on SiN, for example, is formed. Next, by performing dry etching with high anisotropy, the two-layer protective film 9 is opened, and the structure shown in FIG. 11 is formed. Subsequently, when wet etching using dilute hydrofluoric acid or the like is performed, the etching rate differs for each insulating film, so that the side surface of the protective film 9 removed by dry etching becomes a stepped shape (stepped shape). If a gate electrode is formed at this position, a gate electrode having a stepped shape (stepped shape) on the side surface can be formed.

  As the insulating film, the above-mentioned different materials may be used, and as the upper insulating film, an insulating film of the same material having a low film density and a higher etching rate than that of the lower layer may be used.

<Effect>
Below, the effect by this embodiment is illustrated.

  According to the present embodiment, the semiconductor device is a heterojunction field effect transistor including a nitride semiconductor and includes a channel layer 3 formed on the semiconductor substrate 1 and In formed on the channel layer 3. A barrier layer 4 made of a nitride semiconductor; a gate electrode 8 partially formed on the barrier layer 4; a cap layer 5 made of a nitride semiconductor partially formed on the barrier layer 4; 5 and a drain electrode 7 partially formed on the substrate 5.

  At least the end of the gate electrode 8 on the side close to the drain electrode 7 and the cap layer 5 are formed to be separated from each other.

  According to such a configuration, the end of the gate electrode 8 on the side close to the drain electrode 7 and the cap layer 5 are formed to be separated from each other. For this reason, the cap layer 5 at the end close to the drain electrode 7 where the strong electric field is applied is removed, and the trapping of electrons at the location is suppressed, so that the current collapse (at the time of pulse driving) Current drop) can be suppressed.

  Moreover, according to such a configuration, the contact resistance of the ohmic electrode can be reduced. Further, according to such a configuration, it is possible to realize a high-output high-frequency transistor that performs a stable high-output operation.

  Note that the distance between the source electrode 6 and the gate electrode 8 can be set short by adopting a structure in which the gate electrode 8 and the cap layer 5 are in contact with each other on the side close to the source electrode 6. With this configuration, it is possible to reduce the access resistance and increase the output.

  Further, according to the present embodiment, the side surface of the gate electrode 8d (gate electrode 8e, gate electrode 8f, or gate electrode 8g) near the drain electrode 7 has a step shape.

  According to such a configuration, electric field concentration at the end of the gate electrode can be suppressed, and current collapse can be reduced.

  Further, according to the present embodiment, the semiconductor device includes the source electrode 6 partially formed on the cap layer 5.

  The end of the gate electrode 8 (gate electrode 8d, gate electrode 8e, or gate electrode 8f) near the source electrode 6 and the cap layer 5 are formed to be separated from each other.

  According to such a configuration, the cap layer 5 at the end close to the source electrode 6 is also removed, and current collapse (current reduction during pulse driving) can be suppressed.

  In addition, according to the present embodiment, the semiconductor device includes the protective film 9 as an insulating film formed so as to cover the barrier layer 4 and the cap layer 5.

  According to such a configuration, since the defect level formed on the surface of the barrier layer 4 can be reduced, current collapse can be suppressed.

  Further, according to the present embodiment, the cap layer 5 is GaN, and the crystal growth temperature thereof is 900 ° C. or lower.

  According to such a configuration, the crystal quality of the barrier layer 4 containing In can be prevented from being lowered by growing the cap layer 5 at a low temperature.

Further, according to this embodiment, the barrier layer _{4, In x Al y Ga 1-} x-y N (0 <x ≦ 1,0 <y ≦ 1,0 <x + y ≦ 1) consists, the channel layer 3 Is made of Al _z Ga _1-z N (0 ≦ z ≦ 1).

  According to such a configuration, a high concentration two-dimensional electron gas can be generated at the heterointerface.

  According to the present embodiment, the method for manufacturing a semiconductor device is a method for manufacturing a heterojunction field effect transistor including a nitride semiconductor, and includes a layer structure forming step, an electrode forming step, a removing step, and an insulating film. A formation step, an exposure step, and a gate electrode formation step.

  The layer structure forming step is a step of sequentially forming the channel layer 3, the barrier layer 4 made of a nitride semiconductor containing In, and the cap layer 5 made of a nitride semiconductor on the semiconductor substrate 1 by using an epitaxial growth method. The electrode forming step is a step of forming the source electrode 6 and the drain electrode 7 on the cap layer 5 so as to be separated from each other. The removing step is a step of removing a part of the cap layer 5 located between the source electrode 6 and the drain electrode 7. The insulating film forming step is a step of forming a protective film 9 as an insulating film covering at least the region including the barrier layer 4 exposed in the removing step. The exposure process is a process of removing a part of the protective film 9 located between the source electrode 6 and the drain electrode 7 to expose the barrier layer 4. The gate electrode formation step is a step of forming the gate electrode 8 on the barrier layer 4 exposed in the exposure step.

  The exposure step is a step of exposing the barrier layer 4 without exposing the cap layer 5 on the side close to the drain electrode 7.

  According to such a configuration, the end of the gate electrode 8 on the side close to the drain electrode 7 and the cap layer 5 are formed to be separated from each other. For this reason, the cap layer 5 at the end close to the drain electrode 7 where the strong electric field is applied is removed, and the trapping of electrons at the location is suppressed, so that the current collapse (at the time of pulse driving) Current drop) can be suppressed.

  Further, according to the present embodiment, the insulating film forming step is a step of forming two or more protective films 9 having different etching rates in the region removed in the exposing step, and the protective film removed in the exposing step The side surface 9 has a step shape, and the gate electrode formation step is a step of forming a gate electrode 8d (gate electrode 8e, gate electrode 8f or gate electrode 8g) having a side surface having a step shape.

  According to such a configuration, electric field concentration at the end of the gate electrode can be suppressed, and current collapse can be reduced.

Second Embodiment
<Manufacturing method>
The heterojunction field effect transistor made of a nitride semiconductor according to this embodiment is different from the first embodiment in that the cap layer 5 made of GaN is formed using selective regrowth. In addition, the same code | symbol is attached | subjected and shown about the structure similar to the structure demonstrated in the said embodiment, and the detailed description is abbreviate | omitted suitably. Moreover, about the manufacture similar to the manufacturing method demonstrated by the said embodiment, the detailed description is abbreviate | omitted suitably.

  First, the buffer layer 2, the channel layer 3, and the barrier layer 4 are epitaxially grown on the semiconductor substrate 1 (FIG. 19).

Next, silicon oxide SiO ₂ or the like is formed on the barrier layer 4 to a thickness of about 30 [nm], and the mask layer 11 is formed by selective etching using a patterned resist or the like (FIG. 20).

  Subsequently, a GaN layer is formed again by the epitaxial growth method, and a cap layer 5 made of a nitride semiconductor is selectively formed in a portion other than the mask layer 11. At this time, the growth temperature is desirably 900 ° C. or lower in order to suppress damage to the barrier layer 4 made of a nitride semiconductor containing In. Subsequently, the structure shown in FIG. 21 is obtained by removing the mask layer 11 by wet etching using hydrofluoric acid or the like.

  Subsequently, the source electrode 6 and the drain electrode 7 are formed using an evaporation method or a sputtering method, and the element isolation region 10 is formed using an ion implantation method or the like (FIG. 22). The structure shown in FIG. 22 has the same shape as the structure shown in FIG. 9 in the first embodiment.

  By using this manufacturing method, the transistor structure shown in FIG. 1 can be obtained without using a dry etching process of the cap layer 5 using plasma or the like in the vicinity of a region where a gate electrode is formed later. As a result, etching damage to the surface of the barrier layer 4 does not occur, and the formation of trap levels that cause current collapse can be suppressed. Therefore, it is possible to obtain a transistor that achieves high output even during pulse driving or high frequency driving.

The subsequent steps are the same as those shown in the first embodiment. That is, a protective film 9 made of Al ₂ O ₃ or SiN or the like is formed, and a reactive ion etching (RIE) method or a wet etching method is used using a pattern formed on the protective film 9 using a resist or the like. A part of the protective film 9 is selectively removed by using.

  Subsequently, a gate electrode 8 made of Ni / Au is deposited by vapor deposition or sputtering, and formed by a lift-off method or the like, whereby the structure shown in FIG. 1 is obtained.

<Effect>
Below, the effect by this embodiment is illustrated.

  According to the present embodiment, the method for manufacturing a semiconductor device is a method for manufacturing a heterojunction field effect transistor including a nitride semiconductor, a layer structure forming step, a mask layer forming step, a cap layer forming step, and a removal A process, an electrode formation process, an insulating film formation process, an exposure process, and a gate electrode formation process.

  The layer structure forming step is a step of sequentially forming the channel layer 3 and the barrier layer 4 made of a nitride semiconductor containing In on the semiconductor substrate 1 by using an epitaxial growth method. The mask layer forming step is a step of partially forming the mask layer 11 on the barrier layer 4. The cap layer forming step is a step of forming the cap layer 5 made of a nitride semiconductor on the barrier layer 4 using an epitaxial growth method. The removal process is a process of removing the mask layer 11. The electrode forming step is a step of forming the source electrode 6 and the drain electrode 7 on the cap layer 5 so as to be separated from each other. The insulating film forming step is a step of forming a protective film 9 as an insulating film covering at least the region including the barrier layer 4 exposed in the removing step. The exposure process is a process of removing a part of the protective film 9 located between the source electrode 6 and the drain electrode 7 to expose the barrier layer 4. The gate electrode formation step is a step of forming the gate electrode 8 on the barrier layer 4 exposed in the exposure step.

  The exposure step is a step of exposing the barrier layer 4 without exposing the cap layer 5 on the side close to the drain electrode 7.

  According to such a configuration, the mask layer 11 is partially formed on the barrier layer 4, and then the cap layer 5 is formed on the barrier layer 4. Therefore, by further removing the mask layer 11 after that, it is possible to form a region where the cap layer 5 is removed without using dry etching. Since dry etching is not required, crystal damage that occurs when the cap layer 5 is dry etched can be suppressed.

  In the said embodiment, although the material of each component, material, or the conditions of implementation etc. are described, these are illustrations in all the aspects, Comprising: It is not restricted to what this invention described. Accordingly, countless variations that are not illustrated (including modifications or omissions of arbitrary components and free combinations between different embodiments) can be envisaged within the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Buffer layer, 3 Channel layer, 4 Barrier layer, 5, 5a Cap layer, 6 Source electrode, 7 Drain electrode, 8, 8a, 8b, 8c, 8d, 8f, 8g Gate electrode, 9 Protective film, 10 element isolation region, 11 mask layer.

Claims (9)

A heterojunction field effect transistor comprising a nitride semiconductor,
A channel layer formed on a semiconductor substrate;
A barrier layer made of the nitride semiconductor containing In, formed on the channel layer;
A gate electrode partially formed on the barrier layer;
A cap layer made of the nitride semiconductor and partially formed on the barrier layer;
A drain electrode partially formed on the cap layer,
At least the end of the gate electrode on the side close to the drain electrode and the cap layer are formed apart from each other.
Semiconductor device. The side surface of the gate electrode close to the drain electrode has a step shape.
The semiconductor device according to claim 1. A source electrode partially formed on the cap layer;
The end of the gate electrode on the side close to the source electrode and the cap layer are formed apart from each other.
The semiconductor device according to claim 1. An insulating film formed to cover the barrier layer and the cap layer;
The semiconductor device according to claim 1. The cap layer is GaN, and the crystal growth temperature is 900 ° C. or lower.
The semiconductor device according to claim 1. The barrier layer _is made of _{In x Al y Ga 1-x} -y N (0 <x ≦ 1,0 <y ≦ 1,0 <x + y ≦ 1),
The channel layer is made of Al _z Ga _1-z N (0 ≦ z ≦ 1).
The semiconductor device according to claim 1. A method of manufacturing a heterojunction field effect transistor comprising a nitride semiconductor,
A layer structure forming step of sequentially forming a channel layer, a barrier layer made of the nitride semiconductor containing In, and a cap layer made of the nitride semiconductor on the semiconductor substrate using an epitaxial growth method;
An electrode forming step of forming a source electrode and a drain electrode apart from each other on the cap layer;
A removing step of removing a part of the cap layer located between the source electrode and the drain electrode;
An insulating film forming step of forming an insulating film covering at least the region including the barrier layer exposed in the removing step;
An exposing step of removing a part of the insulating film located between the source electrode and the drain electrode to expose the barrier layer;
A gate electrode forming step of forming a gate electrode on the barrier layer exposed in the exposing step,
The exposing step is a step of exposing the barrier layer without exposing the cap layer on the side close to the drain electrode.
A method for manufacturing a semiconductor device. A method of manufacturing a heterojunction field effect transistor comprising a nitride semiconductor,
A layer structure forming step of sequentially forming a channel layer and a barrier layer made of the nitride semiconductor including In on a semiconductor substrate by using an epitaxial growth method;
A mask layer forming step of partially forming a mask layer on the barrier layer;
A cap layer forming step of forming a cap layer made of the nitride semiconductor on the barrier layer using an epitaxial growth method;
A removing step of removing the mask layer;
An electrode forming step of forming a source electrode and a drain electrode apart from each other on the cap layer;
An insulating film forming step of forming an insulating film covering at least the region including the barrier layer exposed in the removing step;
An exposing step of removing a part of the insulating film located between the source electrode and the drain electrode to expose the barrier layer;
A gate electrode forming step of forming a gate electrode on the barrier layer exposed in the exposing step,
The exposing step is a step of exposing the barrier layer without exposing the cap layer on the side close to the drain electrode.
A method for manufacturing a semiconductor device. The insulating film forming step is a step of forming the insulating film of two or more layers having different etching rates in the region removed in the exposing step,
The side surface of the insulating film removed in the exposing step has a step shape,
The gate electrode forming step is a step of forming the gate electrode having a stepped side surface.
A method for manufacturing a semiconductor device according to claim 7 or 8.

Images