JP2015162579A - semiconductor device - Google Patents

Abstract

[Problem] In a semiconductor device including a semiconductor switching element and a free wheel diode, a simple configuration is used to achieve both low loss and high breakdown voltage. [Solution] A semiconductor device 10 includes a voltage-controlled first transistor ET1 (MOSFET) having a first main electrode (drain), a second main electrode (source) and a first control electrode (gate), and a voltage-controlled second transistor ET2 (JFET) having a third main electrode (drain), a fourth main electrode (source) and a second control electrode (gate). The first main electrode (drain) and the third main electrode (drain) are electrically connected, and the second main electrode (source) and the fourth main electrode (source) and the second control electrode (gate) are electrically connected. [Selected Figure] FIG.

Description

  The present invention relates to a semiconductor device including a semiconductor switching element and a free-wheeling diode.

  In recent years, adoption of wide band gap semiconductors as materials constituting semiconductor devices is being promoted. For example, wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are attracting attention as materials for power semiconductor elements.

  For example, in Japanese Patent No. 5108996 (Patent Document 1), a metal insulating film semiconductor type electric field using a wide band gap semiconductor as a power semiconductor element that forms a switching means for each phase arm of an inverter that drives a three-phase AC motor. The structure which employ | adopted the effect transistor (MISFET; Metal Insulator Semiconductor Field Effect Transistor) is disclosed.

  The inverter is provided with a free-wheeling diode so as to be anti-parallel to each switch means in order to secure a path for returning current when both the high-side switch means and the low-side switch means are turned off. Conventionally, a technique has been adopted in which a parasitic diode (hereinafter also referred to as a body diode) that the MISFET itself has is structurally used as a free-wheeling diode.

  In the above-mentioned Patent Document 1, each switching means is configured by a semiconductor element having a MISFET region in which a MISFET is formed and a diode region in which a Schottky barrier diode (hereinafter also referred to as SBD) is formed. Instead of the body diode, SBD is used as a free-wheeling diode.

Further, in Patent Document 1 described above, an n-type channel layer is formed between the n ⁻ drift layer of the MISFET and the gate insulating film so as to be in contact with the p body region, and a channel diode composed of this channel layer is used, A path is provided for returning current when the MISFET is off.

Japanese Patent No. 5108996

  When the body diode of the MISFET is used as the freewheeling diode, a recovery current flows due to the minority carrier accumulation effect, so that a short-circuit current may flow between the high-side switch means and the low-side switch means. Further, when a wide band gap semiconductor is used as the material of the MISFET, the rising voltage of the body diode is as high as about 2.5 V, so that there is a problem that the forward voltage drop is increased and the conduction loss is increased. Further, as a problem inherent to silicon carbide, there is a problem in that the crystal deterioration of silicon carbide progresses due to the forward current flowing through the pn junction, and the conduction loss increases accordingly.

  On the other hand, since the SBD is a unipolar diode, unlike a bipolar diode such as a body diode, a recovery current hardly flows. Further, since the rising voltage of SBD is lower than that of the body diode, the voltage drop in the forward direction is also reduced. In Patent Document 1 described above, by preventing current from flowing through the body diode, MISFET crystal deterioration is prevented from progressing, and conduction loss is prevented from increasing due to the high rising voltage of the diode.

  However, since the rising voltage of SBD is determined by the barrier height of the Schottky barrier, if the barrier height is lowered, the rising voltage can be lowered, while the leakage current when a reverse voltage is applied increases. For this reason, the SBD has a problem that it is difficult to achieve both reduction in conduction loss and improvement in reverse breakdown voltage.

In addition, as described above, in the configuration in which the channel diode is formed in the MISFET region, a step of forming the channel layer on the n ⁻ drift layer by epitaxial growth is required, which increases the number of steps in the manufacturing process and complicates the problem. is there.

  An object of the present invention is to realize both low loss and high breakdown voltage with a simple configuration in a semiconductor device including a semiconductor switching element and a free wheel diode.

  A semiconductor device according to one aspect of the present invention includes a voltage-controlled first transistor having a first main electrode, a second main electrode, and a first control electrode, a third main electrode, and a fourth main electrode. And a voltage-controlled second transistor having an electrode and a second control electrode. The first main electrode and the third main electrode are electrically connected, and the second main electrode, the fourth main electrode, and the second control electrode are electrically connected.

  According to the present invention, in a semiconductor device including a semiconductor switching element and a free-wheeling diode, both low loss and high breakdown voltage can be realized with a simple configuration.

1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. It is a circuit diagram showing an example of an inverter circuit constituted by a semiconductor device according to an embodiment of the present invention. It is an equivalent circuit diagram of a semiconductor device having a general free wheel diode. It is a figure which shows each current-voltage characteristic of JFET shown in FIG. 1, and BD and SBD shown in FIG. 1 is a partial cross sectional view schematically showing a configuration example of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a partial cross-sectional view schematically showing a current path in the semiconductor device of FIG. 5. FIG. 6 is a partial cross-sectional view schematically showing a current path in the semiconductor device of FIG. 5. It is a fragmentary sectional view showing roughly the 1st process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 3rd process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 5th process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a fragmentary sectional view which shows roughly the structural example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a fragmentary sectional view which shows roughly the structural example of the semiconductor device which concerns on Embodiment 3 of this invention.

[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described. “Electrically connected” is not limited to the case where electrical connection between the two elements is caused by the direct connection of the two elements. Including the case that occurs through another element arranged between two elements.

  (1) A semiconductor device according to an embodiment of the present invention includes a first main electrode (drain electrode or collector electrode), a second main electrode (source electrode or emitter electrode), and a first control electrode (gate electrode). A voltage-controlled first transistor (ET1) having a third main electrode (drain electrode), a fourth main electrode (source electrode), and a second control electrode (gate electrode) Type second transistor (ET2). The first main electrode (drain electrode or collector electrode) and the third main electrode (drain electrode) are electrically connected, and the second main electrode (source electrode or emitter electrode) and the fourth main electrode The (source electrode) and the second control electrode (gate electrode) are electrically connected.

  According to this configuration, the voltage-controlled second transistor in which one main electrode and the control electrode are connected is connected in parallel to the voltage-controlled first transistor. This second transistor can function as a free-wheeling diode for refluxing current when the first transistor is turned off. In particular, when a wide band gap semiconductor is used as the material of the semiconductor device, the rising voltage is maintained while maintaining a high reverse breakdown voltage as compared with the configuration using the body diode or SBD of the first transistor as the freewheeling diode. Can be lowered easily. Therefore, high breakdown voltage and low loss can be obtained with a simple configuration.

  (2) Preferably, the first transistor (ET1) and the second transistor (ET2) are normally-off transistors.

  According to this configuration, the second transistor can be turned off when the first transistor is on with the first main electrode at a higher potential than the second main electrode. In addition, when the first main electrode is at a low potential with respect to the second main electrode while the first transistor is in the off state, the second transistor is turned on, so that the second transistor has a return current. Can flow.

  (3) Preferably, the first transistor (ET1) is a metal oxide semiconductor field effect transistor (MOSFET). The second transistor (ET2) is a junction field effect transistor (JFET).

  According to this configuration, a MOSFET is used as a power semiconductor element such as a switching element used in an inverter circuit, and a JFET is used as a freewheeling diode, so that the body diode or SBD of the MOSFET is used as a freewheeling diode. Thus, a free-wheeling diode having a high breakdown voltage and a low on-resistance can be realized. As a result, high breakdown voltage and low loss can be obtained.

  (4) Preferably, the semiconductor device includes a first main surface (P1) and a second main surface (P2) located on the opposite side of the first main surface (P1). (90). The semiconductor layer (90) has a first conductivity type, is provided on the drift layer (81) including the first main surface (P1), and the drift layer (81), and is different from the first conductivity type. Provided in the first region (82) so as to be separated from the drift layer (81) and the first region (82) having the conductivity type of 2 and forming the body region of the first transistor (ET1). And the second region (83) having the first conductivity type and forming the source region of the first transistor (ET1), and being apart from the first region (82) in the drift layer (81) And a third region (85) having the second conductivity type and forming the gate region of the second transistor (ET2). The third region (85) is provided with an opening for exposing the drift layer (81) to the second main surface (P2). The semiconductor device includes a gate insulating film (91) provided on the first region (82) so as to connect the drift layer (81) and the second region (83), and the gate insulating film (91). A gate electrode (92) forming a first control electrode (gate electrode), electrically connected to the first main surface (P1), a first main electrode (drain electrode or collector electrode), and A first electrode (98) forming a third main electrode (drain electrode) and a second electrode provided on the second region (83) and forming a second main electrode (source electrode or emitter electrode) (94) and an ohmic junction to the third region (85) and an ohmic junction to the drift layer (81) through the opening, and a fourth main electrode (source electrode) and a second control electrode (gate) The third electrode (95) forming the electrode) To prepare for.

  According to this configuration, the first transistor (MOSFET) and the second transistor (JFET) that can function as a free-wheeling diode can be integrated in one semiconductor chip. According to this, since the inverter circuit can be realized with a smaller and simpler configuration, it is possible to construct a system that is superior in cost.

  (5) Preferably, the 1st recessed part (TR) is formed in the 2nd main surface (P2). The side wall surface (SW) of the first recess (TR) extends from the second main surface (P2) to the drift layer (81) through the second region (83) and the first region (82). Yes. The bottom surface (BT) of the first recess (TR) is located in the drift layer (81). The gate insulating film (91) is disposed so as to cover the side wall surface (SW) and the bottom surface (BT) of the first recess (TR).

  According to this configuration, since the first transistor (MOSFET) can be miniaturized, the cell integration degree of the first transistor can be further increased. In addition, since the channel density of the first transistor can be improved, on-resistance can be reduced.

  (6) Preferably, the semiconductor layer (90) is composed of a wide band gap semiconductor.

  According to this configuration, the semiconductor device according to the embodiment of the present invention is configured using a wide band gap semiconductor as a material, so that the semiconductor device having high breakdown voltage, low on-resistance, and high-speed operation can be reduced in size and simple. Can be realized.

  (7) Preferably, the semiconductor layer (90) is made of silicon carbide. The plane orientation of the side wall surface (SW) of the first recess (TR) is inclined from 50 degrees to 70 degrees from the (000-1) plane.

  According to this configuration, since the channel resistance can be reduced in the first transistor (MOSFET), the on-resistance can be further reduced.

  (8) Preferably, the semiconductor layer (90) is embedded in the drift layer (81) so as to face the first region (82) in the thickness direction of the semiconductor layer (90), and has the second conductivity type. A first impurity region (71T) having

  According to this configuration, the first impurity region can suppress the dielectric breakdown of the gate insulating film in the first transistor (MOSFET). Thereby, a high voltage can be applied to the semiconductor device. That is, the breakdown voltage can be increased.

  (9) Preferably, the semiconductor layer (90) is embedded in the drift layer (81) so as to face the third region (85) in the thickness direction of the semiconductor layer (90), and has the second conductivity type. A second impurity region (71D) having

  According to this configuration, the second impurity region can be used as the gate region of the second transistor (JFET). Thereby, a normally-off JFET can be easily realized.

  (10) Preferably, a second recess (HX, HY) is formed on the second main surface (P2). The side wall surface (SX, SY) of the second recess (HX, HY) penetrates the third region (85) from the second main surface (P2) to the drift layer (81). The bottom surface (SX, SY) of the second recess (HX, HY) is located in the drift layer (81). The third electrode (95) is disposed so as to cover the side wall surface (SX, SY) and the bottom surface (BX, BY) of the second recess (HX, HY).

  According to this configuration, the area of the third electrode that is in ohmic contact with the semiconductor layer can be increased. As a result, more carriers can be injected and withdrawn through the third electrode.

  (11) Preferably, the semiconductor layer (90) is made of silicon carbide. The plane orientation of the side wall surface (SX, SY) of the second recess (HX, HY) is inclined by 50 degrees or more and 70 degrees or less from the (000-1) plane.

  According to this configuration, the first recess provided in the first transistor (MOSFET) and the second recess provided in the second transistor (JFET) can be formed in a common process. Therefore, the ease of manufacturing the semiconductor device can be improved.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  FIG. 1 is an equivalent circuit diagram of a semiconductor device 10 according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor device 10 includes a first transistor ET1 and a second transistor ET2. Both the first transistor ET1 and the second transistor ET2 are voltage control type transistors in which a current flows between a pair of main electrodes by applying a voltage to the control electrode (gate).

  The first transistor ET1 is realized as a MOSFET, for example. The MOSFET which is the first transistor ET1 has a drain electrode (first main electrode), a source electrode (second main electrode), and a gate electrode (first control electrode). Note that the first transistor ET1 may be a MISFET other than a MOSFET. The first transistor ET1 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or a JFET. When the first transistor ET1 is an IGBT, the first main electrode is a collector electrode, the second main electrode is an emitter electrode, and the first control electrode is a gate electrode.

  The second transistor ET2 is realized as a JFET, for example. The JFET, which is the second transistor ET2, has a drain electrode (third main electrode), a source electrode (fourth main electrode), and a gate electrode (second control electrode).

  As shown in FIG. 1, the drain electrode (first main electrode) of the MOSFET and the drain electrode (third main electrode) of the JFET are electrically connected. The source electrode (second main electrode) of the MOSFET and the source electrode (fourth main electrode) of the JFET are electrically connected. The source electrode of the JFET is further electrically connected to the gate electrode (second control electrode) of the JFET. That is, the JFET is connected in parallel with the MOSFET with the gate electrode and the source electrode connected.

  In this embodiment, both the first transistor ET1 and the second transistor ET2 are normally off type (also called enhancement type), that is, off when the threshold voltage is higher than zero and the gate potential and the source potential are the same potential. It is a transistor that enters a state.

  FIG. 2 is a circuit diagram showing an example of an inverter circuit configured by semiconductor device 10 according to the embodiment of the present invention. Referring to FIG. 2, inverter circuit 101 is, for example, a single-phase inverter. The inverter circuit 101 is connected to the positive electrode and the negative electrode of the DC power supply 8 via the positive electrode terminal 5 and the negative electrode terminal 6, respectively. The inverter circuit 101 converts DC power supplied from the DC power supply 8 into single-phase AC. Single phase load 9A is an inductive load, for example, a single phase motor. However, the type of the single-phase load 9A is not particularly limited.

  Inverter circuit 101 includes semiconductor devices 10-1 to 10-4. Each configuration of the semiconductor devices 10-1 to 10-4 is the same as the configuration shown in FIG. Therefore, each of semiconductor devices 10-1 to 10-4 can be realized by semiconductor device 10 according to the present embodiment.

  Semiconductor devices 10-1 and 10-2 are connected in series between positive electrode terminal 5 and negative electrode terminal 6. Similarly, the semiconductor devices 10-3 and 10-4 are connected in series between the positive terminal 5 and the negative terminal 6.

  Inverter circuit 101 may be a three-phase inverter. In this case, two semiconductor devices connected in series between the positive electrode terminal 5 and the negative electrode terminal 6 may be added to the configuration shown in FIG.

  When switching a load including an inductance component, that is, an inductive load, a large current such as a surge current can be generated. This surge current may damage the MOSFET (first transistor ET1). In order to avoid damage to the MOSFET, a freewheeling diode is connected in antiparallel to the MOSFET.

In this embodiment, the normally-off JFET (second transistor ET2) has a function as a free-wheeling diode. Hereinafter, in each of the MOSFET and JFET, the potential of the drain electrode relative to the potential of the source electrode and V _DS, a potential of the gate electrode relative to the potential of the source electrode is defined as V _GS, it will be described.

In the state of V _DS ≧ 0 (forward bias state), when V _GS > 0 of the MOSFET, the MOSFET is turned on and current flows from the drain electrode toward the source electrode. On the other hand, the JFET is turned off because V _GS = 0, and the drain electrode and the source electrode are not conducted.

On the other hand, in the state of V _DS <0 (reverse bias state), when V _GS ≦ 0 of the MOSFET, the MOSFET is turned off and the drain electrode and the source electrode are not conducted. On the other hand, in the JFET, when the potential of the gate electrode becomes higher than the potential of the drain electrode, a forward voltage is applied to the pn junction formed by the gate and the drain. When the potential of the gate electrode with respect to the potential of the drain electrode becomes equal to or higher than the threshold voltage of the JFET, the JFET is turned on and current flows from the source electrode toward the drain electrode. In this way, a reflux current flows through the current path formed in the JFET.

  FIG. 3 is an equivalent circuit diagram of a semiconductor device having a general free-wheeling diode as a comparative example. The semiconductor device shown in FIG. 3A uses a body diode (BD) included in a MOSFET as a free wheel diode. In the semiconductor device shown in FIG. 3B, a Schottky barrier diode (SBD) is used as the freewheeling diode. In both the BD and the SBD, when a negative potential is applied to the drain electrode with respect to the source electrode of the MOSFET (reverse bias state), the BD and the SBD become conductive in a forward voltage state.

  FIG. 4 is a diagram showing current-voltage characteristics of the JFET shown in FIG. 1 and the BD and SBD shown in FIG. The horizontal axis in FIG. 4 indicates the forward voltage applied to the pn junction in each element, and the vertical axis in FIG. 4 indicates the current (forward current) flowing through each element. In the figure, k1 indicates the characteristics of the BD, k2 indicates the characteristics of the SBD, and k3 indicates the characteristics of the JFET.

  Referring to FIG. 4, BD exhibits a characteristic that when it exceeds a predetermined threshold voltage (rising voltage), it becomes conductive and the current increases rapidly. The rising voltage of BD depends on the size of the band gap of the semiconductor material. In the case of a MOSFET made of silicon, the rising voltage of BD is about 0.7V. On the other hand, in a MOSFET made of a wide band gap semiconductor such as silicon carbide, since the band gap is wider than that of silicon, the rising voltage of BD is as high as about 2.5V. As a result, the voltage drop in the forward direction is increased and the conduction loss is increased.

  Further, in the case of a MOSFET made of silicon carbide, when BD is used as a free-wheeling diode, the crystal deterioration of the MOSFET proceeds due to the bipolar operation by BD, leading to an increase in conduction loss.

  On the other hand, since the SBD is a unipolar diode, the rising voltage is as low as about 1 V and the forward voltage drop is also low as compared with the BD. However, since the rising voltage of the SBD is determined by the barrier height of the Schottky barrier, lowering the barrier height can lower the rising voltage, while increasing the leakage current when a reverse voltage is applied. For this reason, in SBD, there is a problem that it is difficult to achieve both reduction of conduction loss and improvement of reverse breakdown voltage.

  In this embodiment, as shown in FIG. 4, the rising voltage of the freewheeling diode can be further reduced by designing the threshold voltage of the normally-off JFET to be lower than the rising voltage of the SBD. Thereby, it is possible to realize a semiconductor device capable of reducing conduction loss while maintaining a high reverse breakdown voltage.

  In the semiconductor device 10 according to this embodiment, the first transistor ET1 and the second transistor ET2 can be realized by separate chips or discrete elements. Alternatively, the first transistor ET1 and the second transistor ET2 can be integrated on a single semiconductor chip. According to this, since the inverter circuit can be realized with a smaller and simpler configuration, it is possible to construct a system that is superior in cost.

  Hereinafter, a configuration example of a semiconductor device in which the first transistor ET1 and the second transistor ET2 are integrated on one semiconductor chip will be described.

(Embodiment 1)
FIG. 5 is a partial cross-sectional view schematically showing a configuration example of the semiconductor device 10 according to the first embodiment of the present invention.

  Referring to FIG. 5, semiconductor device 10 according to the first embodiment of the present invention is formed of a wide band gap semiconductor. In this embodiment, silicon carbide is employed as the wide band gap semiconductor. The wide band gap semiconductor is not limited to silicon carbide. Examples of other wide band gap semiconductors include gallium nitride and diamond.

  The semiconductor device 10 includes a single crystal substrate 80, an epitaxial layer (semiconductor layer) 90, a gate insulating film 91, a gate electrode 92, an interlayer insulating film 93, a source electrode 94 (second electrode), and a wiring layer. 97, a drain electrode 98 (first electrode), and an ohmic electrode 95 (third electrode).

  Epitaxial layer 90 includes element region IR. The epitaxial layer 90 may further include a termination region OR (see FIG. 13) surrounding the element region IR. In this case, the termination region OR may have a guard ring region 73 and a field stop region 69 (see FIG. 13).

  In this embodiment, the semiconductor device 10 includes a MOSFET that is the first transistor ET1 and a JFET that is the second transistor ET2. Each of the MOSFET and the JFET is preferably configured to be able to apply a voltage of 600 V or higher between the source electrode and the drain electrode, in other words, has a breakdown voltage of 600 V or higher. The JFET can function as a free-wheeling diode connected in antiparallel to the MOSFET, as will be described later.

  Single crystal substrate 80 is made of n-type (first conductivity type) silicon carbide. Single crystal substrate 80 preferably has a hexagonal crystal structure, and more preferably has polytype 4H.

Epitaxial layer 90 is a silicon carbide layer epitaxially grown on single crystal substrate 80. Epitaxial layer 90 has a lower surface P1 (first main surface) and an upper surface P2 (second main surface) located on the opposite side to lower surface P1. The epitaxial layer 90 includes an n ⁻ drift layer 81 (drift layer), a p body region 82 (first region), an n source region 83 (second region), a p ⁺ contact region 84, an embedded p ⁺ Region 71 and p ⁺ gate region 85 (third region).

The n ⁻ drift layer 81 has a lower layer 81A and an upper layer 81B. The lower layer 81A includes the lower surface P1 of the epitaxial layer 90. The upper layer 81B is provided on the lower layer 81A. A buried p ⁺ region 71 is partially provided on the surface of the lower layer 81A opposite to the lower surface P1. Upper layer 81B covers buried p ⁺ region 71.

N ⁻ drift layer 81 includes an impurity (donor) such as nitrogen, for example, and has n type (first conductivity type). The impurity concentration (donor concentration) of the n ⁻ drift layer 81 is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, for example, 8 × 10 ¹⁵ cm ⁻³ . The donor concentration of the lower layer 81A may be the same as the donor concentration of the upper layer 81B, or may be lower than the donor concentration of the upper layer 81B.

P body region 82 is a p-type (second conductivity type) region containing an impurity (acceptor) such as aluminum or boron. P body region 82 is provided on upper layer 81 < ^/ b> B of n ⁻ drift layer 81. The impurity concentration (acceptor concentration) of p body region 82 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁸ cm ⁻³ . The acceptor concentration of p body region 82 is higher than the donor concentration of n ⁻ drift layer 81.

N source region 83 is provided in p body region 82 so as to be separated from n ⁻ drift layer 81 by p body region 82. N source region 83 is an n type region including an impurity (donor) such as phosphorus. The donor concentration in n source region 83 is higher than the acceptor concentration in p body region 82.

The p ⁺ contact region 84 is provided surrounded by the n source region 83 and is connected to the p body region 82. The acceptor concentration of p ⁺ contact region 84 is higher than the acceptor concentration of p body region 82. The acceptor concentration of p ⁺ contact region 84 is, for example, about 1 × 10 ²⁰ cm ⁻³ . The p ⁺ contact region 84 forms the upper surface P2 of the epitaxial layer 90 together with the n source region 83. The p ⁺ contact region 84, the n source region 83, the p body region 82, and the drift layer 81 form a MOSFET cell as the first transistor ET1.

  The MOSFET cells are arranged periodically. “Periodic” means that the arrangement of a plurality of cells follows a certain rule. The periodic arrangement includes, for example, that a plurality of cells are arranged at a constant pitch. In this embodiment, the plurality of cells have a hexagonal shape and are regularly arranged in a two-dimensional shape.

A trench TR (first recess) is provided on the upper surface P2 of the epitaxial layer 90. Trench TR has side wall surface SW and bottom surface BT. Sidewall surface SW penetrates n source region 83 and p body region 82 and reaches upper layer 81B of n ⁻ drift layer 81. Sidewall surface SW includes a channel surface of the MOSFET on p body region 82. Sidewall surface SW is covered with gate insulating film 91.

  Side wall surface SW is preferably inclined with respect to upper surface P2 of epitaxial layer 90. In this case, trench TR is tapered toward bottom surface BT. The plane orientation of the side wall surface SW is preferably inclined by 50 ° or more and 70 ° or less with respect to the {0001} plane, and inclined by 50 ° or more and 70 ° or less with respect to the (000-1) plane. More preferred. Preferably, side wall surface SW has a predetermined crystal plane (also referred to as a special plane), particularly in a portion on p body region 82. A “special surface” is a surface including a first surface having a surface orientation {0-33-8}. More preferably, the special surface includes the first surface microscopically and further includes the second surface having the surface orientation {0-11-1} microscopically. More preferably, the first surface and the second surface include a composite surface having a plane orientation {0-11-2}. The special surface is a surface having an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} surface. The direction of the side wall surface SW is not particularly limited. For example, the side wall surface SW may be perpendicular to the upper surface P2 of the epitaxial layer 90.

Bottom surface BT is located on upper layer 81 < ^/ b> B of n ⁻ drift layer 81. The bottom surface BT may have a flat shape substantially parallel to the top surface P2 of the epitaxial layer 90 as shown in the drawing, or may have a U-shape or a V-shape. In this embodiment, trench TR extends to form a mesh having a honeycomb structure in a plan view. The upper surface P2 of the epitaxial layer 90 has a hexagonal shape surrounded by the mesh.

The p ⁺ gate region 85 is a p-type region containing an impurity (acceptor) such as aluminum or boron. The p ⁺ gate region 85 is provided on the upper layer 81 < ^/ b> B of the n ⁻ drift layer 81. The acceptor concentration of p ⁺ gate region 85 is preferably not less than 1 × 10 ¹⁷ cm ^{−3 and not} more than 5 × 10 ¹⁸ cm ⁻³ , for example, 1 × 10 ¹⁸ cm ⁻³ . The acceptor concentration of p ⁺ gate region 85 is higher than the donor concentration of n ⁻ drift layer 81.

A trench HY (second recess) is further provided on the upper surface P2 of the epitaxial layer 90. Trench HY has side wall surface SX and bottom surface BY. Sidewall surface SX passes through p ⁺ gate region 85 and reaches upper layer 81B of n ⁻ drift layer 81. Sidewall surface SX includes a channel region of JFET on n ⁻ drift layer 81.

Sidewall surface SX is preferably inclined with respect to upper surface P2 of epitaxial layer 90. In this case, trench HY is tapered toward bottom surface BY. The plane orientation of the side wall surface SX is preferably inclined by 50 ° or more and 70 ° or less with respect to the {0001} plane, and inclined by 50 ° or more and 70 ° or less with respect to the (000-1) plane. More preferred. Preferably, side wall surface SX has a special surface, particularly in a portion on upper layer 81B of n ⁻ drift layer 81. The direction of the side wall surface SX is not particularly limited. For example, the side wall surface SX may be perpendicular to the upper surface P2 of the epitaxial layer 90.

Bottom surface BY is located on upper layer 81 < ^/ b> B of n ⁻ drift layer 81. The bottom surface BY may have a flat shape substantially parallel to the upper surface P2 of the epitaxial layer 90 as shown in the drawing, or may have a U shape or a V shape.

  As described above, trench TR extends so as to form a mesh having a honeycomb structure in a plan view. A part of this trench TR is replaced with a trench HY. The trench TR and the trench HY can be formed in the same process, as will be described in a method for manufacturing the semiconductor device 10 described later.

Buried p ⁺ region 71 is a p-type region containing an impurity (acceptor) such as aluminum or boron. The buried p ⁺ region 71 is provided so as to be buried in the n ⁻ drift layer 81. In the buried p ⁺ region 71, an electric field relaxation region 71T (first impurity region) in which the first transistor ET1 (MOSFET) is disposed above and a second transistor ET2 (JFET) in the upper portion are disposed. P ⁺ gate region 71D (second impurity region). The impurity concentration of each of electric field relaxation region 71T and p ⁺ gate region 71D is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Electric field relaxation region 71T is separated from p body region 82 by upper layer 81B. Electric field relaxation region 71T is separated from each of side wall surface SW and bottom surface BT of trench TR. Preferably, buried p ⁺ region 71T is located on the lower surface P1 side of n ⁻ drift layer 81 with respect to bottom surface BT of trench TR.

In this embodiment, the electric field relaxation region 71T suppresses the dielectric breakdown of the gate insulating film 91 that is particularly likely to occur in the trench gate type MOSFET. Specifically, a depletion layer extending from electric field relaxation region 71T to lower surface P1 of n ⁻ drift layer 81 is formed when the voltage between drain electrode 98 and source electrode 94 is increased by turning off the MOSFET. . Therefore, the proportion of the voltage between the drain electrode 98 and the source electrode 94 that is borne by the portion between the electric field relaxation region 71T and the lower surface P1 is increased. In other words, the voltage applied to the portion shallower than the electric field relaxation region 71T (the upper portion in FIG. 5) is reduced. Thereby, the electric field strength in a portion shallower than the electric field relaxation region 71T can be reduced. In other words, it is possible to reduce the electric field strength in a portion where breakdown is likely to occur due to electric field concentration. As a result, a higher voltage can be applied between the drain electrode 98 and the source electrode 94 without destruction. That is, the breakdown voltage of the MOSFET is further increased.

  The MOSFET is preferably configured so that a voltage of 600 V or more can be applied between the source electrode 94 and the drain electrode 98. Thereby, the withstand voltage can be set to 600 V or more while the on-resistance is lowered.

The p ⁺ gate region 71D is separated from the p ⁺ gate region 85 by the upper layer 81B. The p ⁺ gate region 71D is separated from each of the side wall surface SX and the bottom surface BY of the trench HY. Preferably, p ⁺ gate region 71D is located on the lower surface P1 side of n ⁻ drift layer 81 with respect to bottom surface BY of trench HY.

The p ⁺ gate region 71D constitutes the gate of the JFET together with the p ⁺ gate region 85. The p ⁺ gate region 71D is preferably electrically connected to the ohmic electrode 95. Thereby, the potential of the p ⁺ gate region 71D can be set to the same potential as the potential of the p ⁺ gate region 85. When the gate potential of less than the threshold value to the p ⁺ gate region 71D and ^{the p +} gate region 85 is applied, ^{p +} gate region 71D and ^{the p +} gate region 85 sandwiched between been n ^- depletion layer spreads in the drift layer 81, The main current (drain current) flowing between the pair of main electrodes (between the drain and source) is cut off. On the other hand, when the ^{p +} gate region 71D and the gate potential of the threshold value or more to the ^{p +} gate region 85 is applied, a depletion layer disappears, sandwiched between the ^{p +} gate region 71D and ^{the p +} gate region 85 n ^- drift The main current flows through the layer 81. Thus, the n ⁻ drift layer 81 sandwiched between the p ⁺ gate region 71D and the p ⁺ gate region 85 constitutes a JFET channel.

In this embodiment, the JFET is normally off type (enhancement type), that is, formed so as to be turned off when the threshold voltage is higher than zero and the gate potential V _G and the source potential V _S are the same potential. Specifically, when gate potential V _G and source potential V _S are the same potential, n ⁻ drift layer 81 is completely depleted by the depletion layer extending from each of p ⁺ gate region 71D and p ⁺ gate region 85. Thus, the channel width is determined. The channel width corresponds to the distance (preferably the shortest distance) between the p ⁺ gate region 85 and the p ⁺ gate region 71D in the thickness direction (vertical direction in FIG. 5). The channel width can be determined based on the impurity concentration of p ⁺ gate region 71D, p ⁺ gate region 85 and n ⁻ drift layer 81, the diffusion potential of the pn junction, and the like.

Gate insulating film 91 covers sidewall surface SW and bottom surface BT of trench TR. Gate insulating film 91 is provided on p body region 82 so as to connect n ⁻ drift layer 81 and n source region 83. In other words, the gate insulating film 91 is disposed so as to cover a portion of the p body region 82 located between the n source region 83 and the n ⁻ drift layer 81. The gate electrode 92 is provided on the gate insulating film 91. More specifically, the gate electrode 92 is in contact with the gate insulating film 91 and is provided inside the trench TR. The interlayer insulating film 93 is provided in contact with the gate electrode 92 and the gate insulating film 91 and electrically insulates the gate electrode 92 and the source electrode 94 from each other. Interlayer insulating film 93 is made of, for example, silicon dioxide (SiO ₂ ).

The source electrode 94 is provided on the n source region 83 and ^{p +} contact region 84 is in contact with each of n source regions 83 and ^{p +} contact region 84. Source electrode 94 is made of a material capable of ohmic contact with each of n source region 83 and p ⁺ contact region 84. The source electrode 94 is nickel, for example. Source electrode 94 may include, for example, titanium and aluminum. Source electrode 94 may include, for example, nickel and silicon.

The ohmic electrode 95 covers the side wall surface SX and the bottom surface BY of the trench HY. The ohmic electrode 95 may be formed so as to fill the region inside the trench HY. The ohmic electrode 95 is in electrical contact with each of the p ⁺ gate region 85 and the n ⁻ drift layer 81 by being in contact therewith. The ohmic electrode 95 is made of a material capable of ohmic contact with each of the p ⁺ gate region 85 and the n ⁻ drift layer 81. The ohmic electrode 95 is, for example, nickel. The ohmic electrode 95 may contain titanium and aluminum, for example. The ohmic electrode 95 may contain, for example, nickel and silicon. The ohmic electrode 95 may be formed simultaneously with the source electrode 94 described above.

According to this embodiment, the area of the ohmic electrode 95 that is in ohmic contact with each of the p ⁺ gate region 85 and the n ⁻ drift layer 81 can be increased. Therefore, many carriers can be injected and extracted through the ohmic electrode 95.

Specifically, when a forward bias (V _DS ≧ 0) is applied to the MOSFET (see FIG. 6), many holes can be extracted from the p ⁺ gate region 85 by the ohmic electrode 95. Thereby, the depletion layer DL2 (FIG. 6) can be quickly expanded.

On the other hand, when a reverse bias (V _DS <0) is applied to the MOSFET (see FIG. 7), many carriers (electrons) can be injected from the ohmic electrode 95 into the n ⁻ drift layer 81. Thereby, the depletion layer DL2 (FIG. 6) can be quickly released.

  The wiring layer 97 is disposed in contact with the source electrode 94 and the ohmic electrode 95. Wiring layer 97 is a conductive layer made of aluminum, for example, and is electrically connected to each of source electrode 94 and ohmic electrode 95. Thereby, the ohmic electrode 95 is electrically connected to the source electrode 94. The wiring layer 97 is insulated from the gate electrode 92 by the interlayer insulating film 93.

  In the configuration of the semiconductor device 10 shown in FIG. 1, the drain electrode (first main electrode) of the MOSFET which is the first transistor ET1 is realized by the drain electrode 98 shown in FIG. The source electrode (second main electrode) of the MOSFET is realized by the source electrode 94. The gate electrode (first control electrode) of the MOSFET is realized by the gate electrode 92.

On the other hand, the drain electrode (third main electrode) of the JFET, which is the second transistor ET2, is realized by the drain electrode 98 shown in FIG. The source electrode (fourth main electrode) of the JFET is realized by the ohmic electrode 95. The gate electrode of the JFET is realized by an ohmic electrode 95 that is electrically connected to the p ⁺ gate region 85. In other words, by realizing the source electrode and the gate electrode of the JFET with the common ohmic electrode 95, the source electrode and the gate electrode are electrically connected.

  Further, the source electrode and the gate electrode (ohmic electrode 95) of the JFET are electrically connected to the source electrode (source electrode 94) of the MOSFET through the wiring layer 97. The drain electrode of the JFET is electrically connected to the drain electrode of the MOSFET through the drain electrode 98.

  In this way, the semiconductor device 10 is realized in which the MOSFET as the first transistor ET1 and the JFET as the second transistor ET2 are integrated on one semiconductor chip. Hereinafter, the operation of the semiconductor device 10 according to the embodiment of the present invention will be described.

  6 and 7 are partial cross-sectional views schematically showing current paths in the semiconductor device 10. FIG. 6 shows a current path when the first transistor ET1 is in an on state, and FIG. 7 shows a current path when the first transistor ET1 is in an off state.

Referring to FIG. 6, source potential V _S is applied to n source region 83 and p ⁺ contact region 84 through wiring layer 97 and source electrode 94. Further, source potential V _S is applied to p ⁺ gate region 85 and n ⁻ drift layer 81 through wiring layer 97 and ohmic electrode 95. The source potential V _S is, for example, a ground potential.

The electric field relaxation region 71T, is supplied with the potential _{V P.} Potential V _P may be the same potential as the source potential V _S (ground potential). Alternatively, potential V _P may be settable independently of the floating potential (floating) or the source potential V _S. Potential V _P is for example higher than the source potential V _S, may be less than or equal to the drain potential V _D.

In order to turn on the first transistor ET1 (MOSFET), a drain potential V _D is applied to the drain electrode 98, and a gate potential V _G is applied to the gate electrode 92. Drain potential _{V D} and the gate potential _{V G} is higher than both the source potential _{V S.} In the example of FIG. 6, it is assumed that V _D > V _G > V _S.

As indicated by arrows in FIG. 6, current flows from the drain electrode 98 to the source electrode 94 through the single crystal substrate 80, the n ⁻ drift layer 81, the channel CH and the n source region 83 formed in the p body region 82. And flow.

Incidentally, the electric field relaxation region 71T and n ^- for reverse voltage is applied between the drift layer 81, the electric field alleviation region 71T and the n ^- from the junction surface of the drift layer 81, the electric field slow area 71T side and n ^- drift The depletion layer DL1 spreads on the layer 81 side. To the electric field relaxation region 71T, by applying a high potential _{V D} following potential _{V P} than the potential _{V S,} the potential difference between the potential _{V D} and potential _{V P} a _(V D -V _P), the potential V _It can be made smaller than the potential difference (V _D −V _S ) between _D and the potential V _S. Thus, as compared with a case where the potential V _P at the same potential as the potential V _S, a depletion layer DL1 is reduced. As a result, the depletion layer DL1 is prevented from narrowing the path through which electrons flow, so that the on-resistance of the MOSFET can be reduced.

In the second transistor ET2 (JFET), the drain potential V _D is applied to the drain electrode 98. Source potential V _S (ground potential) is applied to each of n ⁻ drift layer 81 and p ⁺ gate region 85 through interconnection layer 97 and ohmic electrode 95. Since the p ⁺ gate region 71D is electrically connected to the wiring layer 97, the source potential V _S (ground potential) is also applied to the p ⁺ gate region 71D. That _is, a _{V D> V S = V G} .

As described above, the JFET is a normally-off transistor. Therefore, when the gate voltage _{V G} and the source potential _{V S} is the same potential (ground potential), as shown in FIG. 6, from each of the ^{p +} gate region 71D and ^{the p +} gate region 85 n ^- toward the drift layer 81 The channel is completely depleted by the formed depletion layer DL2. As a result, the current flow path is interrupted, and the JFET is turned off.

In contrast, with reference to FIG. 7, when a negative gate potential V _G to the source potential V _S to the gate electrode 92 is applied, current is extinguished channels CH formed in the p body region 82 By becoming zero, the MOSFET is turned off. When the drain potential V _D becomes lower than the source potential V _S (V _DS <0), a forward voltage is applied to the pn junction between the p ⁺ gate regions 85 and 71D and the n ⁻ drift layer 81 in the JFET. Therefore, the depletion layer DL2 (FIG. 6) disappears. Therefore, as indicated by arrows in FIG. 7, the current flows from the ohmic electrode 95 through the channel formed in the n ⁻ drift layer 81 and the single crystal substrate 80 to the drain electrode 98.

  As shown in FIG. 4, the threshold voltage of the JFET is higher than zero and lower than the rising voltage of the body diode BD of the MOSFET. For this reason, the JFET is turned on before the body diode BD becomes conductive, and a reflux current flows through the JFET. As described above, the JFET functions as a free-wheeling diode, so that conduction loss can be reduced. In particular, in a semiconductor device made of a wide band gap semiconductor such as silicon carbide, the effect of reducing the conduction loss is significant.

  Next, a method for manufacturing the semiconductor device 10 (FIG. 5) according to the first embodiment of the present invention will be described below.

Referring to FIG. 8, lower layer 81 < ^/ b> A that forms part of n ⁻ drift layer 81 (FIG. 5) and forms lower surface P <b> 1 of epitaxial layer 90 is formed on single crystal substrate 80. Specifically, lower layer 81 </ b> A is formed by epitaxial growth on single crystal substrate 80. This epitaxial growth is performed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. be able to. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.

As shown in FIG. 8, by implantation of acceptor ions (impurity ions for imparting the second conductivity type) using an implantation mask (not shown) on the lower layer 81A, a buried p ⁺ region 71 (electric field) Relaxation region 71T and p ⁺ gate region 71D) are formed. The order of forming the impurity regions is arbitrary.

Referring to FIG. 9, after buried p ⁺ region 71 is formed, upper layer 81B is formed on lower layer 81A. By the formation of the upper layer 81B and the formation of the lower layer 81A described above, the n ⁻ drift layer 81 is formed. Buried p ⁺ region 71 is buried in n ⁻ drift layer 81 apart from each of lower surface P1 and upper surface P2. The upper layer 81B can be formed by a method similar to the method for forming the lower layer 81A.

As shown in FIG. 9, p body region 82, n source region 83, and p ⁺ gate region 85 are formed on n ⁻ drift layer 81. A p ⁺ contact region 84 is formed on p body region 82. These formations can be performed, for example, by ion implantation onto the n ⁻ drift layer 81. In ion implantation for forming p body region 82, p ⁺ contact region 84 and p ⁺ gate region 85, for example, an impurity for imparting p-type, such as aluminum (Al), is ion-implanted. In ion implantation for forming n source region 83, an impurity for imparting n-type, such as phosphorus (P), is implanted. Instead of ion implantation, epitaxial growth accompanied by addition of impurities may be used.

  Next, a heat treatment for activating the impurities is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

  Referring to FIG. 10, mask layer 61 having an opening is formed on upper surface P <b> 2 of epitaxial layer 90. As mask layer 61, for example, a silicon oxide film or the like can be used. The opening is formed corresponding to the position of the trenches TR and HY.

In the opening of mask layer 61, n source region 83, p body region 82, p ⁺ gate region 85, and part of n ⁻ drift layer 81 are removed by etching. As an etching method, for example, reactive etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and oxygen (O ₂ ) as a reaction gas can be used. By such etching, a recess (not shown) having a side wall substantially along the thickness direction is formed in a region where the trenches TR and HY are to be formed.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCl ₃ , SF ₆ , or CH ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.

Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon (Ar) gas, helium (He) gas, or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of silicon carbide is about 70 μm / hour, for example. Further, in this case, the mask layer 61 made of silicon oxide has a very high selection ratio with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.

As shown in FIG. 10, trenches TR and HY are formed in the upper surface P2 of the epitaxial layer 90 by the above thermal etching. Trench TR (the first recess) is, n through the n source region 83 and p body region 82 ^- and a bottom BT positioned in the drift layer 81 ^- and the side wall surface SW reaching the drift layer 81, n. Each of side wall surface SW and bottom surface BT is separated from electric field relaxation region 71T. Trench HY (second recess) is, n through the ^{p +} gate region 85 ^- and a bottom BY located in the drift layer 81 ^- and the side wall surface SX reaching the drift layer 81, n. Side wall surface SX and bottom surface BY are each separated from p ⁺ gate region 71D. Preferably, when trench TR is formed, a special surface is self-formed on side wall surface SW, particularly on p body region 82. Further, when the trench HY is formed, a special surface is self-formed on the side wall surface SX, particularly on the n ⁻ drift layer 81. Next, the mask layer 61 is removed by an arbitrary method such as etching.

  As shown in FIG. 11, gate insulating film 91 is formed to cover each of sidewall SW and bottom surface BT of trench TR and sidewall SX and bottom surface BY of trench HY. The gate insulating film 91 can be formed by thermal oxidation, for example. This may be followed by NO annealing using carbon monoxide (CO) gas as the atmospheric gas. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate insulating film 91 and p body region 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate insulating film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate insulating film 91 and p body region 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Next, a gate electrode 92 is formed on the gate insulating film 91. Specifically, gate electrode 92 is formed on gate insulating film 91 so as to fill the region inside trench TR with gate insulating film 91 interposed therebetween. The gate electrode 92 can be formed by, for example, film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).

Referring to FIG. 12, interlayer insulating film 93 is formed on gate electrode 92 and gate insulating film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate insulating film 91. Specifically, the gate insulating film 91 and the interlayer insulating film 93 in the region where the source electrode 94 and the ohmic electrode 95 are formed are removed by etching. Through this opening, the n source region 83, the p ⁺ contact region 84, the p ⁺ gate region 85, and a part of the n ⁻ drift layer 81 are exposed.

Next, source electrode 94 in contact with each of n source region 83 and p ⁺ contact region 84 is formed. An ohmic electrode 95 in contact with each of p ⁺ gate region 85 and part of n ⁻ drift layer 81 is formed. The source electrode 94 and the ohmic electrode 95 may be formed at the same time or may be formed in separate steps. For example, an alloy containing titanium, aluminum, and silicon is formed in the region exposed by the opening. Specifically, a titanium layer, an aluminum layer, and a silicon layer are formed in this order on the above region, and then these layers are heated to produce an alloy containing titanium, aluminum, and silicon. Alternatively, after a mixed layer containing titanium, aluminum, and silicon is formed over the above region, the mixed layer can be heated to produce an alloy containing titanium, aluminum, and silicon. On the other hand, drain electrode 98 is formed on lower surface P <b> 1 of epitaxial layer 90 through single crystal substrate 80.

  Referring to FIG. 5 again, a wiring layer 97 is formed. Thereby, the semiconductor device 10 is obtained.

(Embodiment 2)
FIG. 13 is a partial cross sectional view schematically showing a configuration example of the semiconductor device 11 according to the second embodiment of the present invention.

  Referring to FIG. 13, in semiconductor device 11 according to the second embodiment of the present invention, epitaxial layer 90 includes a termination region OR in addition to element region IR. The termination region OR is disposed so as to surround the element region IR. Specifically, the termination region OR has a guard ring region 73 and a field stop region 69.

  The guard ring region 73 is provided so as to surround the element region IR in plan view. The field stop region 69 is provided so as to surround the guard ring region 73.

Guard ring region 73 has the same conductivity type as buried p ⁺ region 71, that is, p-type. The impurity concentration of guard ring region 73 may be lower than the impurity concentration of buried p ⁺ region 71. The guard ring region 73 has a guard ring 73J located on the innermost periphery. Guard ring 73J is preferably in contact with buried p ⁺ region 71, and in FIG. 13, is in contact with p ⁺ gate region 71D. The guard ring region 73 may further include a guard ring 73I provided so as to surround the guard ring 73J in plan view.

Field stop region 69 is an n-type region. The impurity concentration of field stop region 69 is higher than the impurity concentration of n ⁻ drift layer 81.

  The termination region OR is arranged further outside the MOSFET cell arranged on the outermost side. In the semiconductor device 11 according to the second embodiment of the present invention, the second transistor ET2 is arranged in the termination region OR. The second transistor ET2 is composed of a planar gate type JFET. That is, the trench HY (FIG. 5) is not provided on the upper surface P2 of the epitaxial layer 90, and the ohmic electrode 95 is provided on the flat upper surface P2.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the second embodiment of the present invention, the guard ring region 73 for increasing the breakdown voltage and the second transistor ET2 (JFET) that can function as a free wheel diode are arranged in the termination region OR. Thereby, the termination region OR is effectively used. As a result, the semiconductor device 11 can be reduced in size while increasing the breakdown voltage of the semiconductor device 11.

In the second embodiment of the present invention, in the planar gate type JFET, the channel formed in the n ⁻ drift layer 81 between the adjacent p ⁺ gate regions 85 when the gate potential and the source potential are the same potential is used. By determining the distance between the p ⁺ gate regions 85 so as to be completely depleted, a normally-off transistor can be realized. In this case, the potential of the p ⁺ gate region 71D may be a floating potential (floating). For example, by providing the ^{p +} gate region 71D in the vicinity of the ^{p +} gate region 85, since the carrier from the ^{p +} gate regions 85 in the ^{p +} gate region 71D (holes) can be efficiently supplied, ^{p +} gate Depletion of the region 71D can be eliminated in a short time. Therefore, the response speed of the JFET can be improved.

(Embodiment 3)
FIG. 14 is a partial sectional view schematically showing a configuration example of the semiconductor device 12 according to the third embodiment of the present invention.

  Referring to FIG. 14, in semiconductor device 12 according to the third embodiment of the present invention, terrace portion HX (second recess) is provided on upper surface P2 of epitaxial layer 90 in termination region OR. The JFET that is the second transistor ET2 is provided in the terrace portion HX.

The terrace portion HY has a side wall surface SX and a bottom surface BX. Side wall surface SX includes p ⁺ gate region 85 and n ⁻ drift layer 81. The bottom surface BX is located on the upper layer 81B of the n ⁻ drift layer 81. Side wall surface SX and bottom surface BX of terrace portion HY are covered with ohmic electrode 95. The ohmic electrode 95 is in electrical contact with each of the p ⁺ gate region 95 and the n ⁻ drift layer 81 by being in contact therewith.

Side wall surface SX is preferably inclined with respect to upper surface P <b> 2 of epitaxial layer 90. The plane orientation of the side wall surface SX is preferably inclined by 50 ° or more and 70 ° or less with respect to the {0001} plane, and inclined by 50 ° or more and 70 ° or less with respect to the (000-1) plane. More preferred. Preferably, side wall surface SX has a special surface, particularly in a portion on upper layer 81B of n ⁻ drift layer 81. The direction of the side wall surface SX is not particularly limited. For example, the side wall surface SX may be perpendicular to the upper surface P2 of the epitaxial layer 90.

  Since the configuration other than the above is substantially the same as the configuration of the first and second embodiments described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the third embodiment of the present invention, guard ring region 73 for increasing the breakdown voltage and second transistor ET2 (JFET) that can function as a freewheeling diode are arranged in termination region OR. Thereby, the termination region OR is effectively used. As a result, the semiconductor device 12 can be reduced in size while increasing the breakdown voltage of the semiconductor device 12.

Furthermore, according to Embodiment 3 of the present invention, ohmic electrode 95 is ohmically joined to p ⁺ gate region 85 and n ⁻ drift layer 81 in terrace portion HX (second recess) formed in termination region OR. Thereby, since the area of the ohmic electrode 95 can be increased, the switching speed of the JFET can be increased.

  In the first to third embodiments, epitaxial layer 90 (semiconductor layer) is an n-type silicon carbide layer as a whole. That is, in the above embodiment, the first conductivity type that is the conductivity type of the epitaxial layer 90 is n-type, and the second conductivity type that is the conductivity type of the body region 82 and the gate region 85 is p-type. By forming the p-type region in the n-type epitaxial layer, the ease of manufacturing the semiconductor device can be improved. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 5 Positive electrode terminal 6 Negative electrode terminal 8 DC power supply 9A Single phase load 10, 10-1 to 10-4, 11, 12 Semiconductor device 61 Mask layer 71 Embedded p ⁺ area | region 71T Electric field relaxation area | region 80 Single crystal substrate 81 n ^- drift layer 82 p body region 83 n source region 84 p ⁺ contact region 71D, 85 p ⁺ gate region 90 epitaxial layer 91 gate insulating film 92 gate electrode 93 interlayer insulating film 94 source electrode 94
95 Ohmic electrode 97 Wiring layer 98 Drain electrode 101 Inverter circuit ET1 First transistor ET2 Second transistor IR Element region OR Termination region TR, HX, HY Trench

Claims (11)

A voltage-controlled first transistor having a first main electrode, a second main electrode, and a first control electrode;
A voltage-controlled second transistor having a third main electrode, a fourth main electrode, and a second control electrode;
The first main electrode and the third main electrode are electrically connected, and the second main electrode, the fourth main electrode, and the second control electrode are electrically connected. A semiconductor device.   The semiconductor device according to claim 1, wherein the first transistor and the second transistor are normally-off transistors. The first transistor is a metal oxide semiconductor field effect transistor,
The semiconductor device according to claim 1, wherein the second transistor is a junction field effect transistor. A semiconductor layer having a first main surface and a second main surface located on the opposite side to the first main surface;
The semiconductor layer is
A drift layer having a first conductivity type and including the first main surface;
A first region provided in the drift layer, having a second conductivity type different from the first conductivity type, and forming a body region of the first transistor;
A second region provided in the first region so as to be separated from the drift layer, having the first conductivity type, and forming a source region of the first transistor;
A third region disposed in the drift layer away from the first region, having the second conductivity type, and forming a gate region of the second transistor;
The third region is provided with an opening for exposing the drift layer to the second main surface,
A gate insulating film provided on the first region so as to connect the drift layer and the second region;
A gate electrode provided on the gate insulating film and forming the first control electrode;
A first electrode electrically connected to the first main surface and forming the first main electrode and the third main electrode;
A second electrode provided on the second region and forming the second main electrode;
And a third electrode that is ohmic-bonded to the third region and that is ohmic-bonded to the drift layer through the opening, and that forms the fourth main electrode and the second control electrode. The semiconductor device according to any one of claims 1 to 3. A first recess is formed on the second main surface,
The sidewall surface of the first recess extends from the second main surface to the drift layer through the second region and the first region,
A bottom surface of the first recess is located in the drift layer;
The semiconductor device according to claim 4, wherein the gate insulating film is arranged to cover a side wall surface and a bottom surface of the first recess.   The semiconductor device according to claim 4, wherein the semiconductor layer is made of a wide band gap semiconductor. The semiconductor layer is made of silicon carbide,
The semiconductor device according to claim 5, wherein the surface orientation of the side wall surface of the first recess is inclined from 50 degrees to 70 degrees with respect to the (000-1) plane. The semiconductor layer is
8. The semiconductor device according to claim 7, further comprising a first impurity region embedded in the drift layer so as to face the first region in a thickness direction of the semiconductor layer and having the second conductivity type. The semiconductor device according to any one of the above. The semiconductor layer is
The semiconductor device further includes a second impurity region embedded in the drift layer so as to face the third region in a thickness direction of the semiconductor layer and having the second conductivity type. The semiconductor device according to any one of the above. A second recess is formed in the second main surface,
The sidewall surface of the second recess extends from the second main surface through the third region to the drift layer,
A bottom surface of the second recess is located in the drift layer;
The semiconductor device according to claim 4, wherein the third electrode is disposed so as to cover a side wall surface and a bottom surface of the second recess. The semiconductor layer is made of silicon carbide,
11. The semiconductor device according to claim 10, wherein the surface orientation of the side wall surface of the second recess is inclined from 50 degrees to 70 degrees with respect to the (000-1) plane.

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