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JP2015154410A - Method for manufacturing piezoelectric device - Google Patents

Method for manufacturing piezoelectric device Download PDF

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JP2015154410A
JP2015154410A JP2014028709A JP2014028709A JP2015154410A JP 2015154410 A JP2015154410 A JP 2015154410A JP 2014028709 A JP2014028709 A JP 2014028709A JP 2014028709 A JP2014028709 A JP 2014028709A JP 2015154410 A JP2015154410 A JP 2015154410A
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substrate
hole
main surface
piezoelectric device
conductive
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JP6339378B2 (en
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義紀 那須
Yoshinori Nasu
義紀 那須
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Kyocera Crystal Device Corp
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders or supports
    • H03H9/10Mounting in enclosures
    • H03H9/1007Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H03H9/1021Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device the BAW device being of the cantilever type

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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a piezoelectric device capable of being thinned.SOLUTION: On the sides of two short sides of a through-hole 21 of a substrate 2, two conductive layers 32A and 32B are separated from each other and formed so as to cover hole inner walls. A thermistor element 3 is temporarily fixed by a thermally peelable adhesive sheet 34 which blocks one opening side of the through-hole 21 and placed in the through-hole. Between the respective terminals 31A and 31B of the thermistor element 3 and conductive layers corresponding thereto, conductive adhesives DS are supplied and cured by heat, respectively, and the adhesive sheet 34 is thermally peeled off.

Description

本発明は、電子機器等に用いられる圧電デバイスの製造方法に関するものである。   The present invention relates to a method for manufacturing a piezoelectric device used in an electronic apparatus or the like.

圧電デバイスは、パッケージ内に設けられた圧電振動素子、例えば水晶振動素子の温度情報を得るために、同一パッケージ内にサーミスタ素子を搭載したものが知られている(例えば、特許文献1を参照)。   A piezoelectric device is known in which a thermistor element is mounted in the same package in order to obtain temperature information of a piezoelectric vibration element provided in the package, for example, a crystal vibration element (see, for example, Patent Document 1). .

特許文献1に記載の素子構造は、基板部と、基板部の一方の主面に設けられる第1の枠部と、基板部の他方の主面に設けられる第2の枠部とからなる素子搭載部材を有する。
圧電振動素子は、素子搭載部材において、基板部と第1の枠部とで形成される第1の凹部空間内に露出した基板部の一方の主面に搭載される。一方、サーミスタ素子は、素子搭載部材において、基板部と第2の枠部とで形成される第2の凹部空間内に露出した基板部の他方の主面に搭載される。
第2の枠部の基板部から遠い側の面は、素子搭載部材全体の底面であり、当該底面に、圧電振動素子の1対の外部端子と、サーミスタ素子の1対の外部端子が設けられている。
The element structure described in Patent Document 1 includes an element including a substrate portion, a first frame portion provided on one main surface of the substrate portion, and a second frame portion provided on the other main surface of the substrate portion. It has a mounting member.
The piezoelectric vibration element is mounted on one main surface of the substrate portion exposed in the first concave space formed by the substrate portion and the first frame portion in the element mounting member. On the other hand, the thermistor element is mounted on the other main surface of the substrate portion exposed in the second recessed space formed by the substrate portion and the second frame portion in the element mounting member.
The surface of the second frame portion far from the substrate portion is the bottom surface of the entire element mounting member, and a pair of external terminals of the piezoelectric vibration element and a pair of external terminals of the thermistor element are provided on the bottom surface. ing.

特開2011−211340号公報JP 2011-2111340 A

圧電デバイスは、携帯情報端末などの薄型の電子機器に搭載され、小型化および薄型化が進んでいる。   Piezoelectric devices are mounted on thin electronic devices such as portable information terminals, and are becoming smaller and thinner.

上記特許文献1に記載の素子搭載部材(パッケージ主部材)は、サーミスタ素子を基板部の裏面(他方の主面)に搭載するために、当該サーミスタ素子を保護し、かつ外部端子の形成箇所を確保する必要から、第2の枠部が必須の構成となっている。したがって、特に第2の枠部の存在により、パッケージ自体の厚さを薄型にすることに限界があり、このことが圧電デバイスの薄型化を阻害している。   The element mounting member (package main member) described in Patent Document 1 protects the thermistor element and mounts external terminals in order to mount the thermistor element on the back surface (the other main surface) of the substrate portion. Since it is necessary to ensure, the second frame portion is an essential configuration. Accordingly, the presence of the second frame portion has a limit in reducing the thickness of the package itself, which hinders the piezoelectric device from being thinned.

本発明の目的は、薄型化可能な圧電デバイスの製造方法を提供することにある。   The objective of this invention is providing the manufacturing method of the piezoelectric device which can be reduced in thickness.

本発明の一態様に係る圧電デバイスの製造方法は、圧電素子が実装される基板を厚さ方向に貫通する貫通孔内に2端子の感温素子を配置する工程を含む、圧電デバイスの製造方法であって、前記基板の貫通孔の一方向に相対する2つの内壁の側に、2つの導電層を分離して形成する導電層形成工程と、前記貫通孔の一方の開口側を塞ぐ熱剥離可能な粘着シートにより前記感温素子を前記基板の一方の主面に仮固定して、当該感温素子を前記貫通孔内に配置する素子仮固定工程と、前記仮固定された感温素子の各端子と、対応する導電層との間に、それぞれ導電接着剤を供給する導電接着工程と、加熱により前記導電接着剤を硬化させて、前記感温素子の各端子を前記対応する導電層に固定するとともに、前記粘着シートを熱剥離する素子固定工程と、を有する。   A method for manufacturing a piezoelectric device according to one aspect of the present invention includes a step of disposing a two-terminal temperature-sensitive element in a through-hole penetrating a substrate on which a piezoelectric element is mounted in a thickness direction. A conductive layer forming step of separating and forming two conductive layers on the two inner wall sides facing in one direction of the through hole of the substrate, and thermal separation for closing one opening side of the through hole Temporarily fixing the temperature sensitive element to one main surface of the substrate with a possible adhesive sheet, and an element temporary fixing step of disposing the temperature sensitive element in the through-hole, and the temporarily fixed temperature sensitive element A conductive bonding step of supplying a conductive adhesive between each terminal and the corresponding conductive layer, and curing the conductive adhesive by heating, so that each terminal of the temperature-sensitive element becomes the corresponding conductive layer. Fix the element to fix and heat-release the adhesive sheet Has a degree, the.

好適には、前記素子固定工程後に、前記貫通孔の少なくとも一方の開口側を封止材で封止する孔封止工程と、前記基板のいずれかの主面に、前記圧電素子を実装する圧電素子実装工程と、を有する。   Preferably, after the element fixing step, a hole sealing step for sealing at least one opening side of the through-hole with a sealing material, and a piezoelectric element for mounting the piezoelectric element on any one of the main surfaces of the substrate And an element mounting process.

好適に、前記導電層形成工程で用いる前記基板は、第1主面に前記圧電素子を接続する2つの接続パッドが予め形成され、第2主面に前記圧電素子の2つの外部端子と前記感温素子の2つの外部端子とが予め形成されたものである。   Preferably, in the substrate used in the conductive layer forming step, two connection pads for connecting the piezoelectric element are formed in advance on a first main surface, and the two external terminals of the piezoelectric element and the sensitivity are formed on the second main surface. Two external terminals of the temperature element are formed in advance.

好適に、前記導電層形成工程において、前記感温素子の各端子に対応する2つの導電層を形成することにより、各導電層が、前記感温素子の2つの外部端子のうち、対応する1つの外部端子に電気的に接続される。
さらに好適に、前記素子仮固定工程において、前記貫通孔に対し前記粘着シートを前記基板の第1主面または第2主面の側から貼り付けた後、前記貫通孔が粘着シートで塞がれていない側から前記感温素子を貫通孔内に供給し、当該感温素子を粘着シートの粘着面に仮固定する。
Preferably, in the conductive layer forming step, by forming two conductive layers corresponding to the terminals of the temperature sensitive element, each conductive layer corresponds to one of the two external terminals of the temperature sensitive element. Electrically connected to two external terminals.
More preferably, in the element temporary fixing step, after the adhesive sheet is attached to the through hole from the first main surface or the second main surface side of the substrate, the through hole is closed with the adhesive sheet. The temperature sensitive element is supplied into the through-hole from the side that is not, and the temperature sensitive element is temporarily fixed to the adhesive surface of the adhesive sheet.

好適に、前記導電接着工程で供給される前記導電接着剤により、前記感温素子の各端子に対応する2つの導電層の各々が、前記感温素子の2つの外部端子のうち、対応する1つの外部端子に電気的に接続される。
さらに好適に、前記素子仮固定工程において、前記貫通孔に対し前記粘着シートを前記基板の第1主面の側から貼り付けた後、前記基板の第2主面の側から前記感温素子を貫通孔内に供給し、当該感温素子を粘着シートの粘着面に仮固定する。
Preferably, each of the two conductive layers corresponding to each terminal of the temperature sensitive element corresponds to one of the two external terminals of the temperature sensitive element by the conductive adhesive supplied in the conductive adhesion step. Electrically connected to two external terminals.
More preferably, in the element temporary fixing step, after the adhesive sheet is attached to the through-hole from the first main surface side of the substrate, the temperature sensitive element is mounted from the second main surface side of the substrate. It supplies in a through-hole and the said temperature sensitive element is temporarily fixed to the adhesive surface of an adhesive sheet.

好適に、前記基板は主面が矩形であり、前記導電層を形成する2つの内壁が相対する前記一方向が、前記基板の矩形の長辺方向と一致する。
あるいは好適に、前記基板は主面が矩形であり、前記導電層を形成する2つの内壁が相対する前記一方向が、前記基板の矩形の短辺方向と一致する。
Preferably, the substrate has a rectangular main surface, and the one direction in which the two inner walls forming the conductive layer face each other coincides with the long side direction of the rectangle of the substrate.
Alternatively, preferably, the substrate has a rectangular main surface, and the one direction in which two inner walls forming the conductive layer face each other coincides with the short side direction of the rectangle of the substrate.

上記の構成によれば、薄型になっても基板の内部に感温素子を確実に固定可能な圧電デバイスの製造方法が提供される。   According to said structure, the manufacturing method of the piezoelectric device which can fix a thermosensitive element inside a board | substrate reliably even if it becomes thin is provided.

第1の実施形態に係る圧電デバイスの組立時の斜視図である。It is a perspective view at the time of the assembly of the piezoelectric device which concerns on 1st Embodiment. 基板の裏面図(A)と上面図(B)、および基板封止キャップの上面図である。It is the back view (A) and top view (B) of a board | substrate, and the top view of a board | substrate sealing cap. 貫通孔を形成後の基板の裏面図および断面図である。It is the reverse view and sectional drawing of a board | substrate after forming a through-hole. 導電層を形成後の基板の裏面図および断面図である。It is the back view and sectional drawing of a board | substrate after forming a conductive layer. サーミスタ素子を仮固定後の基板の裏面図および断面図である。It is the reverse view and sectional drawing of a board | substrate after temporarily fixing a thermistor element. 導電接着剤を供給後の基板の裏面図および断面図である。It is the back view and sectional drawing of the board | substrate after supplying a conductive adhesive. 封止材を形成後の基板の上面図および断面図である。It is the top view and sectional drawing of a board | substrate after forming the sealing material. 水晶素子を接合後の基板の上面図と、基板封止キャップを被せた後の基板の概略断面図である。It is the upper side figure of the board | substrate after joining a crystal element, and the schematic sectional drawing of the board | substrate after covering the board | substrate sealing cap. 第2の実施形態に係る圧電デバイスの製造途中の断面図である。It is sectional drawing in the middle of manufacture of the piezoelectric device which concerns on 2nd Embodiment. 第3の実施形態にかかる圧電デバイスの製造途中の断面図である。It is sectional drawing in the middle of manufacture of the piezoelectric device concerning 3rd Embodiment. 第4の実施形態にかかる圧電デバイスの製造途中の裏面図である。It is a reverse view in the middle of manufacture of the piezoelectric device concerning 4th Embodiment. 変形例1,2に係る圧電デバイスの概略断面図である。6 is a schematic cross-sectional view of a piezoelectric device according to Modifications 1 and 2. FIG.

本発明の実施形態を、感温素子がサーミスタ素子の場合を例として、図面を参照して各種実施形態および変形例を説明する。なお、感温素子は、サーミスタ素子以外でも、環境温度により抵抗値等の物理量が変化可能なトランジスタやダイオード等の2端子素子であればよい。
また、第2の実施形態以降において、既に説明した構成と同一又は類似する構成については、互いに同一の符号を付して説明することがある。
Various embodiments and modifications of the present invention will be described with reference to the drawings, taking as an example the case where the temperature sensitive element is a thermistor element. The temperature sensitive element may be a two-terminal element such as a transistor or a diode that can change a physical quantity such as a resistance value depending on the environmental temperature, other than the thermistor element.
In the second and subsequent embodiments, the same or similar configurations as those already described may be described with the same reference numerals.

以下、次の順で説明を行う。
1.第1の実施形態:サーミスタ素子を第1主面に仮固定し、導電接着剤による電気的接続と本固定の後に、貫通穴を第1主面側から封止材で塞ぐ形態である。
2.第2の実施形態:電極(外部端子)の端部にまで導電接着剤の塗布範囲を拡大させる形態である。
3.第3の実施形態:サーミスタ素子を第2主面に仮固定する形態である。
4.第4の実施形態:貫通穴と基板を直交配置する形態である。
5.変形例1,2:貫通穴を第1,第2主面の両側から封止材で塞ぐ変形例(変形例1)、および、貫通穴を第2主面側から塞ぐ封止材で変形例(変形例2)である。
Hereinafter, description will be given in the following order.
1. 1st Embodiment: It is the form which temporarily fixes a thermistor element to a 1st main surface, and plugs a through-hole with a sealing material from the 1st main surface side after the electrical connection by a conductive adhesive and this fixing.
2. 2nd Embodiment: It is a form which expands the application | coating range of a conductive adhesive to the edge part of an electrode (external terminal).
3. Third embodiment: A thermistor element is temporarily fixed to the second main surface.
4). Fourth Embodiment: A mode in which the through holes and the substrate are arranged orthogonally.
5. Modifications 1 and 2: Modifications (Modification 1) in which the through hole is closed with the sealing material from both sides of the first and second main surfaces, and Modifications with the sealing material that closes the through hole from the second main surface side (Modification 2).

<1.第1の実施形態>
図1は、本発明の第1の実施形態に係る圧電デバイスについて、サーミスタ素子が既に固定された基板に水晶素子を実装する際の組立図である。また、図2(A)と図2(B)は、圧電デバイスの基板の裏面図と上面図、図2(C)は圧電デバイスの基板封止キャップの上面図である。
最初に、図1および図2(A)〜図2(C)を用いて、主に圧電デバイスの構造を説明する。
<1. First Embodiment>
FIG. 1 is an assembly diagram when a crystal element is mounted on a substrate on which a thermistor element is already fixed in the piezoelectric device according to the first embodiment of the present invention. 2A and 2B are a back view and a top view of the substrate of the piezoelectric device, and FIG. 2C is a top view of the substrate sealing cap of the piezoelectric device.
First, the structure of the piezoelectric device will be mainly described with reference to FIGS. 1 and 2A to 2C.

図1に示す圧電デバイス1は、主な構成として、基板2と、基板2の貫通孔21の内部に実装された感温素子の一例としてのサーミスタ素子3と、基板2の一方の主面に実装された圧電素子の一例としての水晶素子4と、水晶素子4が実装された側から基板2を覆う基板封止キャップ(不図示、図2(C)参照)とを有する。   A piezoelectric device 1 shown in FIG. 1 has, as main components, a substrate 2, a thermistor element 3 as an example of a temperature sensitive element mounted in a through hole 21 of the substrate 2, and one main surface of the substrate 2. It has a crystal element 4 as an example of a mounted piezoelectric element, and a substrate sealing cap (not shown, see FIG. 2C) that covers the substrate 2 from the side where the crystal element 4 is mounted.

水晶素子4は、矩形板状の水晶素板41と、当該水晶素板41の両面に形成された1対の電極を有する。各電極は、図1に示すように、水晶素板41の主面に広く配置された矩形状の励振電極42と、水晶素板41の一方の角部を覆って水晶素板41の両面に配置された接続電極43Aと、接続電極43Aを励振電極42に接続する引出電極44と、を有する。これらの電極(42,43A,44)は、一体の導電層(例えば金属膜)から形成したものである。図1では、水晶素板41の短辺のもう片側の角部に他の電極の接続電極43Bが図示してある。この他の電極は、接続電極43Bと、不図示の水晶素板41の他の面に配置された励振電極および引出電極とを一体の導電層から形成したものである。水晶素子4は、外部からの交番電圧が接続電極43から引出電極44及び励振電極42を介して水晶素板41に印加されると、水晶素板41が所定の振動モード及び周波数で励振を起こすようになっている。   The crystal element 4 includes a rectangular plate-shaped crystal element plate 41 and a pair of electrodes formed on both surfaces of the crystal element plate 41. As shown in FIG. 1, each electrode has a rectangular excitation electrode 42 widely disposed on the main surface of the crystal base plate 41, and covers both corners of the crystal base plate 41 on both sides of the crystal base plate 41. The connection electrode 43A is disposed, and the extraction electrode 44 that connects the connection electrode 43A to the excitation electrode 42 is provided. These electrodes (42, 43A, 44) are formed from an integral conductive layer (for example, a metal film). In FIG. 1, a connection electrode 43 </ b> B of another electrode is illustrated at the other corner of the short side of the crystal base plate 41. In this other electrode, the connection electrode 43B and the excitation electrode and the extraction electrode arranged on the other surface of the crystal base plate 41 (not shown) are formed from an integral conductive layer. In the crystal element 4, when an alternating voltage from the outside is applied from the connection electrode 43 to the crystal base plate 41 through the extraction electrode 44 and the excitation electrode 42, the crystal base plate 41 is excited in a predetermined vibration mode and frequency. It is like that.

基板2は、例えばアルミナセラミックス、ガラス−セラミックス等のセラミック材料からなる絶縁層を1層または複数層積層し、焼成して形成することができる。   The substrate 2 can be formed by laminating one layer or a plurality of insulating layers made of a ceramic material such as alumina ceramics or glass-ceramics and firing the laminated layers.

基板2は、第1主面S1と第2主面S2を厚さ方向に貫く貫通孔21を有する。ここで第1主面S1は、水晶素子4が実装される側の主面であり、第2主面S2は、水晶素子4およびサーミスタ素子3の4つの外部端子(25B等)が配置され、圧電デバイス全体の底面を構成する他の主面である。   The board | substrate 2 has the through-hole 21 which penetrates 1st main surface S1 and 2nd main surface S2 in thickness direction. Here, the first main surface S1 is a main surface on the side where the crystal element 4 is mounted, and the second main surface S2 is arranged with four external terminals (25B and the like) of the crystal element 4 and the thermistor element 3, It is the other main surface which comprises the bottom face of the whole piezoelectric device.

基板2は、おおよそ矩形板状の外形を有し、貫通孔21も、基板2と長辺方向が揃う矩形に形成されている。貫通孔21を矩形とすることは必須でない。ただし、サーミスタ素子等の2端子電子部品が一般に矩形箱状の外形を有することから、貫通孔21も、素子外形に適合した形状として、ここでは矩形に形成されている。また、貫通孔21は、第1主面S1の接続パッドや配線、第2主面S2の外部端子と干渉しない位置、例えば基板2の中央付近に形成されている。貫通孔21の位置は、電極や外部端子の配置態様に合わせて、適宜変更可能である。   The substrate 2 has an approximately rectangular plate-like outer shape, and the through hole 21 is also formed in a rectangle whose long side direction is aligned with the substrate 2. It is not essential that the through hole 21 is rectangular. However, since a two-terminal electronic component such as a thermistor element generally has a rectangular box-shaped outer shape, the through-hole 21 is also formed in a rectangular shape as a shape suitable for the element outer shape. Further, the through hole 21 is formed at a position where it does not interfere with the connection pads and wirings of the first main surface S1 and the external terminals of the second main surface S2, for example, near the center of the substrate 2. The position of the through hole 21 can be appropriately changed according to the arrangement mode of the electrodes and the external terminals.

基板部2の第1主面S1に、接続パッド22A,22Bが配置されている。接続パッド22Aは水晶素子4の接続電極43Aと接続され、接続パッド22Bは水晶素子4の接続電極43Bと接続される。また、接続パッド22Bは、近くの角付近のビアランド23Bに接続され、接続パッド22Aは、ビアランド23Bから対角側に離れたビアランド23Aと、配線24を介して接続されている。これら接続パッドとビアランド(および配線)は、一体の導電層(例えば金属膜)から形成したものである。   Connection pads 22 </ b> A and 22 </ b> B are arranged on the first main surface S <b> 1 of the substrate unit 2. The connection pad 22A is connected to the connection electrode 43A of the crystal element 4, and the connection pad 22B is connected to the connection electrode 43B of the crystal element 4. Further, the connection pad 22B is connected to a via land 23B near a nearby corner, and the connection pad 22A is connected to a via land 23A that is away from the via land 23B on the diagonal side via a wiring 24. These connection pads and via lands (and wirings) are formed from an integral conductive layer (for example, a metal film).

図2(A)に示すように、基板2の第2主面S2の4隅側に、金属膜等の導電層からなる4つの電極(外部端子)が配置されている。
具体的には、中央付近の貫通孔21を避けるように、対角状に配置された第1電極25A,25Bと、貫通孔21に対し他の対角側から接する2つの第2電極26A,26Bが配置されている。第1電極25A,25Bは水晶素子用であり、第2電極26A,26Bはサーミスタ素子用である。
第1電極25Aは、基板2を厚さ方向に貫いて埋め込まれたビア(不図示)を介してビアランド23Aと接続されている。同様に、第1電極25Bは、他のビア(不図示)を介してビアランド23Bと接続されている。
As shown in FIG. 2A, four electrodes (external terminals) made of a conductive layer such as a metal film are arranged on the four corner sides of the second main surface S2 of the substrate 2.
Specifically, the first electrodes 25A and 25B arranged diagonally so as to avoid the through hole 21 near the center, and the two second electrodes 26A that are in contact with the through hole 21 from the other diagonal side. 26B is arranged. The first electrodes 25A and 25B are for crystal elements, and the second electrodes 26A and 26B are for thermistor elements.
The first electrode 25A is connected to the via land 23A through a via (not shown) embedded through the substrate 2 in the thickness direction. Similarly, the first electrode 25B is connected to the via land 23B through another via (not shown).

第2電極26A,26Bとサーミスタ素子3との接続の詳細は後述する。   Details of the connection between the second electrodes 26A and 26B and the thermistor element 3 will be described later.

図1に示すように、サーミスタ素子3は、貫通孔21と長辺同士を合わせて、貫通孔21のほぼ中央に配置されている。サーミスタ素子3は、両短辺のそれぞれの側で端面、両側面の一部、上下面の一部を覆う、素子端子31A,31Bを予め有する。サーミスタ素子3は、望ましくは、基板2より若干薄い程度の厚さを有する。あるいは、用いるサーミスタ素子3の厚さに応じて、基板2の厚さが決められている。   As shown in FIG. 1, the thermistor element 3 is disposed substantially at the center of the through hole 21, with the long sides and the through holes 21 being aligned. The thermistor element 3 has element terminals 31A and 31B in advance covering the end face, part of both side faces, and part of the upper and lower faces on each side of both short sides. The thermistor element 3 desirably has a thickness that is slightly thinner than the substrate 2. Alternatively, the thickness of the substrate 2 is determined according to the thickness of the thermistor element 3 to be used.

例えば、基板2の長辺の長さが1.2〜2.0mm、短辺の長さが1.0〜1.6mmの場合に、貫通孔21は、長辺の長さを0.5〜0.8mm、短辺の長さを0.3〜0.5mm程度にすることができる。この場合、サーミスタ素子3は、長辺の長さが0.4〜0.6mmで、短辺の長さが0.2〜0.3mmのものを好適に用いることができる。また、基板2の厚さ(貫通孔21の深さ)を0.15〜0.5mmとすると、サーミスタ素子3は、厚さが0.1〜0.3mm程度のものを好適に用いることができる。
なお、基板2とサーミスタ素子3の厚さを同程度とすることも可能であるが、基板2からの伝熱の影響を抑制する意味で、両者間に少なくとも0.05mm程度の厚さの違いがあり、これにより空隙が形成されることが望ましい。
For example, when the long side length of the substrate 2 is 1.2 to 2.0 mm and the short side length is 1.0 to 1.6 mm, the through-hole 21 has a long side length of 0.5. The length of the short side can be about 0.3 to 0.5 mm. In this case, the thermistor element 3 having a long side length of 0.4 to 0.6 mm and a short side length of 0.2 to 0.3 mm can be suitably used. Further, when the thickness of the substrate 2 (depth of the through hole 21) is 0.15 to 0.5 mm, the thermistor element 3 having a thickness of about 0.1 to 0.3 mm is preferably used. it can.
Although the thickness of the substrate 2 and the thermistor element 3 can be approximately the same, in order to suppress the influence of heat transfer from the substrate 2, a difference in thickness of at least about 0.05 mm between the two. Therefore, it is desirable that voids are formed.

貫通孔21の各短辺側において、孔の内壁から、基板2の底面(第2主面S2)の孔短辺付近部にかけて2つの導電層32A,32Bが互いに分離して形成されている。導電層32Aと素子端子31A、導電層32Bと素子端子31Bは、それぞれ、導電接着剤DSの介在により導通がとられている。導電接着剤DSは熱硬化されているため、機械的な固着部材としての役目も果たしている。   On each short side of the through hole 21, two conductive layers 32 </ b> A and 32 </ b> B are formed separately from each other from the inner wall of the hole to the vicinity of the short side of the bottom surface (second main surface S <b> 2) of the substrate 2. The conductive layer 32A and the element terminal 31A, and the conductive layer 32B and the element terminal 31B are electrically connected to each other through the conductive adhesive DS. Since the conductive adhesive DS is thermally cured, it also serves as a mechanical fixing member.

なお、水晶素子4と基板2の接合に関し、接続電極43Aと接続パッド22A、接続電極43Bと接続パッド22Bとの接合時にも導電接着剤DSが用いることが可能である。但し、本実施形態では、ハンダを用いる。
導電接着剤DSとして、例えば、シリコーン樹脂等のバインダーの中に導電フィラーとして導電性粉末が含有されているものであり、導電性粉末としては、アルミニウム(Al)、モリブデン(Mo)、タングステン(W)、白金(Pt)、パラジウム(Pd)、銀(Ag)、チタン(Ti)、ニッケル(Ni)、ニッケル鉄(NiFe)、のうちのいずれかまたはこれらの組み合わせを含むものを、好適に用いることができる。
Regarding the bonding of the crystal element 4 and the substrate 2, the conductive adhesive DS can be used also when the connection electrode 43A and the connection pad 22A and the connection electrode 43B and the connection pad 22B are bonded. However, in this embodiment, solder is used.
As the conductive adhesive DS, for example, a conductive powder is contained as a conductive filler in a binder such as a silicone resin. As the conductive powder, aluminum (Al), molybdenum (Mo), tungsten (W ), Platinum (Pt), palladium (Pd), silver (Ag), titanium (Ti), nickel (Ni), nickel iron (NiFe), or any combination thereof is suitably used. be able to.

図1では図示を省略しているが、基板2の貫通孔21を、例えば第1主面S1側から覆う封止材が設けられることが望ましい。これにより、サーミスタ素子の実装部からの不純物等が近距離の水晶素子4に付着して、水晶素子4の厚みすべり振動が阻害されることにより、その発振周波数が変動することを未然に防止することが可能である。なお、封止材は、サーミスタ素子の実装部からの不純物等を阻止する必要性に乏しい場合でも、サーミスタ素子を外部から覆うために設けることができる。そのため、封止材が第2主面S2側から貫通孔21を覆う構成でもよいし、封止材を第1主面S1と第2主面S2の両方の側に設けてもよい(変形例1,2参照)。
封止材として、例えば、印刷等で形成される薄いガラス材を好適に用いることができる。
Although not shown in FIG. 1, it is desirable to provide a sealing material that covers the through hole 21 of the substrate 2 from, for example, the first main surface S1 side. As a result, impurities and the like from the mounting portion of the thermistor element adhere to the crystal element 4 at a short distance, and the thickness-shear vibration of the crystal element 4 is inhibited, thereby preventing the oscillation frequency from changing. It is possible. Note that the sealing material can be provided to cover the thermistor element from the outside even when it is not necessary to block impurities from the mounting portion of the thermistor element. Therefore, the structure which the sealing material covers the through-hole 21 from the 2nd main surface S2 side may be sufficient, and a sealing material may be provided in both the 1st main surface S1 and the 2nd main surface S2 (modification example). 1 and 2).
As the sealing material, for example, a thin glass material formed by printing or the like can be suitably used.

図2(C)に示す基板封止キャップ5は、例えばセラミック製または金属製の封止部材であり、水晶素子4の収容空間を形成するため片側開放の箱板形状を有している。基板封止キャップ5は、その開放端の全周縁部が外側に折れ曲がった形状の封止接合縁部51を有する。
図1において、水晶素子4を基板2に接合した後、封止接合縁部51を基板2の第1主面S1の周縁部に気密接合することで基板封止キャップ5が取り付けられる。
The substrate sealing cap 5 shown in FIG. 2C is, for example, a ceramic or metal sealing member, and has a box plate shape that is open on one side to form a housing space for the crystal element 4. The substrate sealing cap 5 has a sealing joint edge 51 having a shape in which the entire peripheral edge portion of the open end is bent outward.
In FIG. 1, after bonding the crystal element 4 to the substrate 2, the substrate sealing cap 5 is attached by airtightly bonding the sealing bonding edge portion 51 to the peripheral edge portion of the first main surface S <b> 1 of the substrate 2.

つぎに、上記構成の圧電デバイス1について、本実施形態の製造方法を、図1,2に加え適宜、図3以降を参照しつつ説明する。   Next, for the piezoelectric device 1 having the above-described configuration, the manufacturing method of the present embodiment will be described with reference to FIG.

図1および図2に示す、セラミック材料からなる基板2と、水晶素子4と、基板封止キャップ5をそれぞれ形成する。但し、この段階で基板2の貫通孔21は未穿孔である。
水晶素子4の形成では、まず、人工水晶体から所定のカットアングルで切断し外形加工を施すことによって水晶素板41を得る。その後、例えば、水晶素板41の両主面にスパッタリング等によって金属膜を被着させて加工する、あるいは印刷等により、それぞれ、励振電極42、接続電極43A(または43B)、引出電極44を有する1対の電極を形成する。
セラミック材料からなる基板2については、焼成前にドリル等でビア開口を予め開けておき、その後、ビア開口に金属材料を埋め込むことで2つのビアを形成する。また、上記と同様な電極形成技術を用いて、第1主面S1に接続パッド22A,22B、ビアランド23A,23Bおよび配線24を、第2主面S2に第1電極25A,25Bおよび第2電極26A,26Bを形成する。
A substrate 2 made of a ceramic material, a crystal element 4 and a substrate sealing cap 5 shown in FIGS. 1 and 2 are formed. However, the through hole 21 of the substrate 2 is not perforated at this stage.
In the formation of the crystal element 4, first, a quartz base plate 41 is obtained by cutting from an artificial crystalline lens at a predetermined cut angle and performing external processing. Thereafter, for example, both main surfaces of the quartz base plate 41 are processed by depositing a metal film by sputtering or the like, or by printing or the like, the excitation electrode 42, the connection electrode 43A (or 43B), and the extraction electrode 44 are provided. A pair of electrodes is formed.
For the substrate 2 made of a ceramic material, via openings are previously opened with a drill or the like before firing, and then two vias are formed by embedding a metal material in the via openings. Further, using the same electrode forming technique as described above, the connection pads 22A and 22B, the via lands 23A and 23B and the wiring 24 are formed on the first main surface S1, and the first electrodes 25A and 25B and the second electrode are formed on the second main surface S2. 26A and 26B are formed.

図3(A)および図3(B)は、基板2に貫通孔21を開口した工程後の裏面図および断面図である。図3(B)は、図3(A)に示すA−A線に沿った断面図である。なお、この裏面図と断面図の関係は、図4以降も同様である。
貫通孔21の形成は、セラミック焼成前は金型で抜く方法が好適である。また、セラミック焼成後では、レーザー加工で孔形成が好適であり、その他、サンドブラストでの孔形成法も採用可能である。
3A and 3B are a back view and a cross-sectional view after the step of opening the through hole 21 in the substrate 2. FIG. 3B is a cross-sectional view along the line AA shown in FIG. The relationship between the rear view and the cross-sectional view is the same in FIG.
The formation of the through-hole 21 is preferably a method of extracting with a mold before firing the ceramic. In addition, after ceramic firing, hole formation by laser processing is suitable, and in addition, a hole formation method by sandblasting can also be adopted.

導電層形成工程は、図4(A)および図4(B)に示すように、形成された貫通孔21の2つの短辺側に、その孔内壁を覆い、一部が裏面(第2主面S2)に延在する導電層32A,32Bを形成する。導電層32A,32Bは、例えば、銀パラジウム(AgPd)、金(Au)などからなる導電性ペーストを印刷し、焼成して形成することができる。本実施形態では、導電層32Aと第2電極26Aが一部重ねられ互いの導通がとられている。同様に、導電層32Bと第2電極26Bが一部重ねられ互いの導通がとられている。また、基板2の上面に、導体層32A,32Bが延在しないようにすることにより、水晶素子の励振電極42と導体層32A,32Bとが接触し、短絡してしまうことを抑えることができる。   As shown in FIGS. 4A and 4B, the conductive layer forming step covers the inner wall of the two short sides of the formed through-hole 21 and a part of the back surface (second main side). Conductive layers 32A and 32B extending on the surface S2) are formed. The conductive layers 32A and 32B can be formed by printing and baking a conductive paste made of, for example, silver palladium (AgPd), gold (Au), or the like. In the present embodiment, the conductive layer 32 </ b> A and the second electrode 26 </ b> A are partially overlapped to establish mutual conduction. Similarly, the conductive layer 32 </ b> B and the second electrode 26 </ b> B are partially overlapped to establish electrical continuity. Further, by preventing the conductor layers 32A and 32B from extending on the upper surface of the substrate 2, it is possible to prevent the excitation electrode 42 of the crystal element and the conductor layers 32A and 32B from coming into contact with each other and causing a short circuit. .

素子仮固定工程は、図5(A)および図5(B)に示すように、例えば、基板2の上面(第1主面S1)側から貫通孔21の開口を塞ぐように、熱剥離可能な粘着シート34を基板2に貼り付ける。熱剥離可能な粘着シート34としては、例えば、日東電工製の「リバアルファ」(商標名)を用いることができる。
また、基板2の裏面(第2主面S2)側から、サーミスタ素子3を供給し、貫通孔21に位置合わせして、その中央に配置する。これにより、サーミスタ素子3は、粘着シート34を介して基板2の第1主面S1に仮固定される。このようにすることにより、後述する素子固定工程の際に、サーミスタ素子3が外れることなく、確実に導電層32A,32Bと接続することが可能となる。なお、サーミスタ素子3を予め粘着シート34に貼り付けた状態で、粘着シート34を基板2に貼り付ける方法も採用可能である。
In the element temporary fixing step, as shown in FIGS. 5A and 5B, for example, heat peeling is possible so as to close the opening of the through hole 21 from the upper surface (first main surface S1) side of the substrate 2. A sticky adhesive sheet 34 is attached to the substrate 2. As the heat-peelable pressure-sensitive adhesive sheet 34, for example, “Riva Alpha” (trade name) manufactured by Nitto Denko can be used.
Further, the thermistor element 3 is supplied from the back surface (second main surface S2) side of the substrate 2, aligned with the through hole 21, and disposed at the center thereof. Thereby, the thermistor element 3 is temporarily fixed to the first main surface S <b> 1 of the substrate 2 through the adhesive sheet 34. By doing so, the thermistor element 3 can be reliably connected to the conductive layers 32A and 32B without detaching in the element fixing step described later. It is also possible to employ a method in which the adhesive sheet 34 is attached to the substrate 2 with the thermistor element 3 attached in advance to the adhesive sheet 34.

導電接着工程は、図6(A)および図6(B)に示すように、基板2の裏面(第2主面S2)側から、例えばAgPdペースト、Auペーストなどの導電接着剤DSを印刷または、ディスペンスで素子端子側2箇所に供給する。これにより、サーミスタ素子3の素子端子31Aと導電層32Aが接続され、素子端子31Bと導電層32Bが接続される。
素子固定工程は、その後、150〜300℃の加熱により導電接着剤DSを硬化させることで、サーミスタ素子3の素子端子31Aと導電層32Aとが固定され、素子端子31Bと導電層32Bとが固定される。このとき、粘着シート34が熱で基板2の第1主面S1より剥離し脱落する。
In the conductive bonding step, as shown in FIGS. 6A and 6B, a conductive adhesive DS such as AgPd paste or Au paste is printed or printed from the back surface (second main surface S2) side of the substrate 2. Then, supply to the element terminal side two places by dispensing. Thereby, the element terminal 31A and the conductive layer 32A of the thermistor element 3 are connected, and the element terminal 31B and the conductive layer 32B are connected.
In the element fixing step, the element terminal 31A and the conductive layer 32A of the thermistor element 3 are fixed and the element terminal 31B and the conductive layer 32B are fixed by curing the conductive adhesive DS by heating at 150 to 300 ° C. Is done. At this time, the adhesive sheet 34 is peeled off from the first main surface S1 of the substrate 2 by heat.

孔封止工程は、図7(A)および図7(B)に示すように、粘着シート34が剥がれた後の貫通孔21を第1主面S1側から塞ぐように封止材35、例えばガラス材を印刷によりコーティングする。この封止材35は、400℃以上、より望ましくは500〜800℃の融点を有し、以後の工程において加熱で形状が変化しない材料のものを用いる。具体的には、水晶素子4を導電接着剤DSで基板2に接合する際の加熱温度を考慮すると、500〜800℃の融点を有する結晶化ガラスを封止材35と用いることが望ましい。なお、水晶素子4を導電接着剤DS以外のより低温接合が可能な方法を用いる場合、封止材35は、より融点の低いものも使用可能である。また、封止材35の上下方向の厚みは、0.01〜0.03mmとなっている。   In the hole sealing step, as shown in FIGS. 7A and 7B, the sealing material 35, for example, so as to close the through-hole 21 from the first main surface S1 side after the pressure-sensitive adhesive sheet 34 has been peeled off. Glass material is coated by printing. The sealing material 35 is made of a material having a melting point of 400 ° C. or higher, more preferably 500 to 800 ° C., and whose shape does not change by heating in the subsequent steps. Specifically, considering the heating temperature when the crystal element 4 is bonded to the substrate 2 with the conductive adhesive DS, it is desirable to use crystallized glass having a melting point of 500 to 800 ° C. as the sealing material 35. In addition, when using the method in which the crystal element 4 can be joined at a lower temperature other than the conductive adhesive DS, the sealing material 35 having a lower melting point can be used. Moreover, the thickness of the sealing material 35 in the vertical direction is 0.01 to 0.03 mm.

また、図7に示す例では、封止材35を第1主面S1のみに形成しているため、その封止箇所で水晶素子4の気密性を確保する必要がある。水晶素子4は、その特性がパッケージの気密性と関係するため、気密性を10−9m・Pa/S以下とする必要がある。封止材35による貫通孔の片側封止の場合、上記値以下の気密性が得られるように、封止法と封止材質が選定される。 Moreover, in the example shown in FIG. 7, since the sealing material 35 is formed only on the first main surface S1, it is necessary to ensure the airtightness of the crystal element 4 at the sealing portion. Since the characteristics of the crystal element 4 are related to the hermeticity of the package, the hermeticity needs to be 10 −9 m · Pa / S or less. In the case of one-side sealing of the through hole with the sealing material 35, the sealing method and the sealing material are selected so that airtightness equal to or lower than the above value is obtained.

圧電素子実装工程は、図8(A)に示すように、水晶素子4を基板2に対し、片持構造となるように導電接着剤DSで接合する。また、図8(B)に示すように、基板封止キャップ5を、その封止接合縁部51と基板との間にキャップ封止材52を介在させた状態で被せ、加熱等で密封する。キャップ封止材52は、300℃〜400℃で溶融するガラスである例えばバナジウムを含有した低融点ガラス又は酸化鉛系ガラスから構成されている。ガラスは、バインダーと溶剤とが加えられペースト状であり、溶融された後固化されることで他の部材と接着する。
なお、図8(B)では裏面側の電極等の構成は図示を省略している。
In the piezoelectric element mounting step, as shown in FIG. 8A, the crystal element 4 is bonded to the substrate 2 with a conductive adhesive DS so as to have a cantilever structure. Further, as shown in FIG. 8B, the substrate sealing cap 5 is covered with a cap sealing material 52 interposed between the sealing bonding edge portion 51 and the substrate, and sealed by heating or the like. . The cap sealing material 52 is made of, for example, low melting glass or lead oxide glass containing vanadium that is a glass that melts at 300 ° C to 400 ° C. Glass is pasty with a binder and a solvent added, and is melted and then solidified to adhere to other members.
In FIG. 8B, the illustration of the configuration of the back side electrode and the like is omitted.

以上の実施形態では、粘着シート34によりサーミスタ素子3を貫通穴21内で仮固定してから、導電接着剤DSを供給し熱硬化させるため、素子の位置決めが容易である。粘着シート34は導電接着剤DSの熱硬化時に剥離されるため、粘着シート34を貼っていた側から孔封止が可能である。
圧電デバイス1は、サーミスタ素子3が基板2に埋め込まれており、パッケージの薄型化を可能としている。また、貫通孔21を塞ぐ封止材35により気密性も確保されるため、水晶素子4の特性も維持される。
In the above embodiment, since the thermistor element 3 is temporarily fixed in the through hole 21 by the adhesive sheet 34, the conductive adhesive DS is supplied and thermally cured, so that the element can be easily positioned. Since the pressure-sensitive adhesive sheet 34 is peeled off when the conductive adhesive DS is thermally cured, holes can be sealed from the side on which the pressure-sensitive adhesive sheet 34 is pasted.
In the piezoelectric device 1, the thermistor element 3 is embedded in the substrate 2, and the package can be made thin. In addition, since the airtightness is ensured by the sealing material 35 that closes the through hole 21, the characteristics of the crystal element 4 are also maintained.

<2.第2の実施形態>
図9に、第2の実施形態に係る圧電デバイスの製造途中の断面図を示す。この断面図は、導電接着剤DSの供給後であり、第1の実施形態に係る図6(B)に対応する。
<2. Second Embodiment>
FIG. 9 shows a cross-sectional view of the piezoelectric device according to the second embodiment in the middle of manufacture. This cross-sectional view is after supply of the conductive adhesive DS and corresponds to FIG. 6B according to the first embodiment.

図3に示す第1の実施形態では、第2電極26A,26Bと貫通孔21が対角方向で接続され、その後の工程で貫通孔21に対して形成される導電層を、電極と接触させる。   In the first embodiment shown in FIG. 3, the second electrodes 26 </ b> A and 26 </ b> B and the through hole 21 are connected in a diagonal direction, and the conductive layer formed for the through hole 21 in the subsequent process is brought into contact with the electrode. .

これに対し、第2の実施形態は、導電層に代えて、あるいは導電層とともに、導電接着剤DSを電極との接続に寄与させる形態である。
具体的に、図9に示すように、第2電極26A,26Bが貫通孔21から離して形成される場合に、導電接着剤DSを印刷で塗布する範囲を第2電極26A,26Bの端部にまで拡大する。これにより、導電接着剤DSを電極接続の手段としても機能させている。このようにすることにより、導電接着剤DSにて導電層32A、32Bと第2電極26A,26Bとを電気的に接続するので、断線の虞がなく確実に導通させることが可能となる。なお、図9では導電層32A,32Bは、第2電極26A,26Bと重なっていないが、第1の実施形態と同様に、両者を重ねたうえで、さらに導電接着剤DSを第2電極26A,26Bに接続させてもよい。
On the other hand, the second embodiment is a form in which the conductive adhesive DS contributes to the connection with the electrode instead of or together with the conductive layer.
Specifically, as shown in FIG. 9, when the second electrodes 26 </ b> A and 26 </ b> B are formed away from the through hole 21, the range in which the conductive adhesive DS is applied by printing is set to the end portions of the second electrodes 26 </ b> A and 26 </ b> B. Expand to. As a result, the conductive adhesive DS also functions as a means for electrode connection. By doing so, since the conductive layers 32A and 32B and the second electrodes 26A and 26B are electrically connected by the conductive adhesive DS, it is possible to reliably conduct without fear of disconnection. In FIG. 9, the conductive layers 32A and 32B do not overlap the second electrodes 26A and 26B. However, like the first embodiment, the conductive layers 32A and 32B are overlapped with each other, and the conductive adhesive DS is further added to the second electrode 26A. , 26B.

図9に示し説明した以外は、第1の実施形態と共通するため、ここでの説明を省略する。   Except for the description with reference to FIG. 9, the description is omitted here because it is common to the first embodiment.

<3.第3の実施形態>
図10に、第3の実施形態に係る圧電デバイスの製造途中の断面図を示す。この断面図は、導電接着剤DSの供給後であり、第1の実施形態に係る図6(B)に対応する。
<3. Third Embodiment>
FIG. 10 shows a cross-sectional view of the piezoelectric device according to the third embodiment in the course of manufacturing. This cross-sectional view is after supply of the conductive adhesive DS and corresponds to FIG. 6B according to the first embodiment.

粘着シート34を第2電極26A,26Bが形成された基板2の第2主面S2側から、貫通孔21を塞ぐように貼る。そして、サーミスタ素子3や導電接着剤DSの供給は、第1主面S1側から行う。このようにしても、第1の実施形態と同様の効果を有する。その他の工程は、第1の実施形態と共通するため、ここでの説明を省略する。なお、第2の実施形態のように導電接着剤の塗布範囲を第2電極まで拡大することは、本実施形態では困難である。   The adhesive sheet 34 is pasted from the side of the second main surface S2 of the substrate 2 on which the second electrodes 26A and 26B are formed so as to close the through hole 21. Then, the thermistor element 3 and the conductive adhesive DS are supplied from the first main surface S1 side. Even if it does in this way, it has an effect similar to 1st Embodiment. Other steps are the same as those in the first embodiment, and a description thereof is omitted here. Note that it is difficult in this embodiment to expand the application range of the conductive adhesive to the second electrode as in the second embodiment.

<4.第4の実施形態>
図11に、第4の実施形態に係る圧電デバイスの製造途中の裏面図を示す。この裏面図は、粘着シートを熱剥離した後のものである。
<4. Fourth Embodiment>
FIG. 11 shows a back view of the piezoelectric device according to the fourth embodiment in the course of manufacturing. This back view is the one after the adhesive sheet has been thermally peeled off.

上記第1〜第3の実施形態では、導電層32A,32Bを形成する2つの内壁が相対する一方向が、基板2の矩形の長辺方向と一致するように設けられているが、本実施形態では、導電層32A,32Bを形成する2つの内壁が相対する一方向が、基板2の矩形の短辺方向と一致するように設けられている。つまり、第1〜第3の実施形態では、貫通孔21およびサーミスタ素子3の長辺方向と、基板2の長辺方向は一致させていたが、本実施形態では、図示のように両者を直交配置させている。
基板主面や貫通孔の大きさや縦横比によっては、このように基板2と貫通孔21の長辺方向を90度異なるようにすると、配置効率がよい場合があり、本発明は、このような構成にも適用できる。
In the first to third embodiments, the direction in which the two inner walls forming the conductive layers 32A and 32B are opposed to each other is provided so as to coincide with the long side direction of the rectangle of the substrate 2. In the embodiment, one direction in which the two inner walls forming the conductive layers 32 </ b> A and 32 </ b> B are opposed to each other coincides with the rectangular short side direction of the substrate 2. That is, in the first to third embodiments, the long side direction of the through hole 21 and the thermistor element 3 and the long side direction of the substrate 2 are matched, but in the present embodiment, they are orthogonal to each other as illustrated. It is arranged.
Depending on the size and aspect ratio of the main surface of the substrate and the through-holes, if the long side directions of the substrate 2 and the through-holes 21 are different by 90 degrees in this way, the arrangement efficiency may be good. Applicable to configuration.

図11では、導電層32A,32Bの片側を第2電極26A,26B側に延在させて、各電極との直接接続を実現している。
但し、接続パターンは図示のものに限定されず、また、第2の実施形態のように導電接着剤を接続手段に用いることも可能である。さらに、第1,第3の実施形態のように、どの主面側から粘着シートを貼るかも任意である。
上記直交配置以外の構成は、第1の実施形態等と共通するため、ここでの説明を省略する。
In FIG. 11, one side of the conductive layers 32A, 32B is extended to the second electrodes 26A, 26B side to realize direct connection with each electrode.
However, the connection pattern is not limited to that shown in the figure, and a conductive adhesive can be used as the connection means as in the second embodiment. Further, as in the first and third embodiments, it is also arbitrary from which main surface side the adhesive sheet is pasted.
Since the configuration other than the orthogonal arrangement is the same as that of the first embodiment, the description thereof is omitted here.

<5.変形例1,2>
図12(A)に変形例1に係る圧電デバイスの概略断面図を示し、図12(B)に変形例2に係る圧電デバイスの概略断面図を示す。
図12(A)では、封止材35を第1主面S1と第2主面S2の両側から貼り付けている。また、図12(B)では、封止材35を第2主面S2から貼り付けている。このように基板2の貫通孔21の両面を封止材35により塞ぐことにより、基板2の気密封止性をさらに向上させることができる。
これらの変形例は、上記第1〜第4のいずれの実施形態に対しても適用可能である。
<5. Modifications 1 and 2>
FIG. 12A shows a schematic cross-sectional view of the piezoelectric device according to the first modification, and FIG. 12B shows a schematic cross-sectional view of the piezoelectric device according to the second modification.
In FIG. 12A, the sealing material 35 is pasted from both sides of the first main surface S1 and the second main surface S2. In FIG. 12B, the sealing material 35 is pasted from the second main surface S2. Thus, by sealing both surfaces of the through hole 21 of the substrate 2 with the sealing material 35, the hermetic sealing performance of the substrate 2 can be further improved.
These modified examples are applicable to any of the first to fourth embodiments.

本発明は、以上の実施形態および変形例に限定されず、種々の態様で実施されてよい。   The present invention is not limited to the above embodiments and modifications, and may be implemented in various ways.

1…圧電デバイス、2…基板、3…サーミスタ素子、4…水晶素子、5…基板封止キャップ、21…貫通孔、22A,22B…接続パッド、23A,23B…ビアランド、24…配線、25A,25B…第1電極、26A,26B…第2電極、31A,31B…素子端子、32A,32B…導電層、34…粘着シート、51…封止接合縁部、S1…第1主面、S2…第2主面、DS…導電接着剤   DESCRIPTION OF SYMBOLS 1 ... Piezoelectric device, 2 ... Board | substrate, 3 ... Thermistor element, 4 ... Crystal element, 5 ... Board | substrate sealing cap, 21 ... Through-hole, 22A, 22B ... Connection pad, 23A, 23B ... Via land, 24 ... Wiring, 25A, 25B ... 1st electrode, 26A, 26B ... 2nd electrode, 31A, 31B ... Element terminal, 32A, 32B ... Conductive layer, 34 ... Adhesive sheet, 51 ... Sealing joint edge, S1 ... 1st main surface, S2 ... Second main surface, DS: conductive adhesive

Claims (9)

圧電素子が実装される基板を厚さ方向に貫通する貫通孔内に2端子の感温素子を配置する工程を含む、圧電デバイスの製造方法であって、
前記基板の貫通孔の一方向に相対する2つの内壁の側に、2つの導電層を分離して形成する導電層形成工程と、
前記貫通孔の一方の開口側を塞ぐ熱剥離可能な粘着シートにより前記感温素子を前記基板の一方の主面に仮固定して、当該感温素子を前記貫通孔内に配置する素子仮固定工程と、
前記仮固定された感温素子の各端子と、対応する導電層との間に、それぞれ導電接着剤を供給する導電接着工程と、
加熱により前記導電接着剤を硬化させて、前記感温素子の各端子を前記対応する導電層に固定するとともに、前記粘着シートを熱剥離する素子固定工程と、
を有する圧電デバイスの製造方法。
A method for manufacturing a piezoelectric device, comprising a step of disposing a two-terminal temperature sensitive element in a through hole penetrating a substrate on which a piezoelectric element is mounted in a thickness direction,
A conductive layer forming step of separately forming two conductive layers on the two inner wall sides opposite to one direction of the through hole of the substrate;
Temporarily fixing the temperature-sensitive element to one main surface of the substrate with a heat-peelable adhesive sheet that closes one opening side of the through-hole, and temporarily fixing the element in the through-hole Process,
A conductive bonding step of supplying a conductive adhesive between each terminal of the temporarily fixed temperature-sensitive element and a corresponding conductive layer;
An element fixing step of curing the conductive adhesive by heating, fixing each terminal of the temperature sensitive element to the corresponding conductive layer, and thermally peeling the adhesive sheet;
A method of manufacturing a piezoelectric device having
前記素子固定工程後に、
前記貫通孔の少なくとも一方の開口側を封止材で封止する孔封止工程と、
前記基板のいずれかの主面に、前記圧電素子を実装する圧電素子実装工程と、
を有する請求項1記載の圧電デバイスの製造方法。
After the element fixing step,
A hole sealing step of sealing at least one opening side of the through hole with a sealing material;
A piezoelectric element mounting step for mounting the piezoelectric element on any main surface of the substrate;
The method for manufacturing a piezoelectric device according to claim 1, comprising:
前記導電層形成工程で用いる前記基板は、第1主面に前記圧電素子を接続する2つの接続パッドが予め形成され、第2主面に前記圧電素子の2つの外部端子と前記感温素子の2つの外部端子とが予め形成されたものである、
請求項1または2記載の圧電デバイスの製造方法。
In the substrate used in the conductive layer forming step, two connection pads for connecting the piezoelectric element are formed in advance on a first main surface, and two external terminals of the piezoelectric element and the temperature sensitive element on the second main surface. Two external terminals are formed in advance.
A method for manufacturing a piezoelectric device according to claim 1 or 2.
前記導電層形成工程において、前記感温素子の各端子に対応する2つの導電層を形成することにより、各導電層が、前記感温素子の2つの外部端子のうち、対応する1つの外部端子に電気的に接続される、
請求項3記載の圧電デバイスの製造方法。
In the conductive layer forming step, by forming two conductive layers corresponding to the terminals of the temperature sensitive element, each conductive layer corresponds to one external terminal corresponding to the two external terminals of the temperature sensitive element. Electrically connected to the
The method for manufacturing a piezoelectric device according to claim 3.
前記素子仮固定工程において、前記貫通孔に対し前記粘着シートを前記基板の第1主面または第2主面の側から貼り付けた後、前記貫通孔が粘着シートで塞がれていない側から前記感温素子を貫通孔内に供給し、当該感温素子を粘着シートの粘着面に仮固定する、
請求項4記載の圧電デバイスの製造方法。
In the element temporary fixing step, after the adhesive sheet is attached to the through hole from the first main surface or the second main surface side of the substrate, the through hole is not covered with the adhesive sheet. Supplying the temperature sensitive element into the through-hole, and temporarily fixing the temperature sensitive element to the adhesive surface of the adhesive sheet;
The method for manufacturing a piezoelectric device according to claim 4.
前記導電接着工程で供給される前記導電接着剤により、前記感温素子の各端子に対応する2つの導電層の各々が、前記感温素子の2つの外部端子のうち、対応する1つの外部端子に電気的に接続される、
請求項3記載の圧電デバイスの製造方法。
Due to the conductive adhesive supplied in the conductive bonding step, each of the two conductive layers corresponding to the terminals of the temperature sensitive element is one corresponding external terminal of the two external terminals of the temperature sensitive element. Electrically connected to the
The method for manufacturing a piezoelectric device according to claim 3.
前記素子仮固定工程において、前記貫通孔に対し前記粘着シートを前記基板の第1主面の側から貼り付けた後、前記基板の第2主面の側から前記感温素子を貫通孔内に供給し、当該感温素子を粘着シートの粘着面に仮固定する、
請求項6記載の圧電デバイスの製造方法。
In the element temporary fixing step, after the adhesive sheet is attached to the through hole from the first main surface side of the substrate, the temperature sensitive element is inserted into the through hole from the second main surface side of the substrate. Supply and temporarily fix the temperature sensitive element to the adhesive surface of the adhesive sheet,
The method for manufacturing a piezoelectric device according to claim 6.
前記基板は主面が矩形であり、
前記導電層を形成する2つの内壁が相対する前記一方向が、前記基板の矩形の長辺方向と一致する、
請求項1から7の何れか一項記載の圧電デバイスの製造方法。
The substrate has a rectangular main surface,
The one direction in which the two inner walls forming the conductive layer face each other coincides with the long side direction of the rectangle of the substrate.
The manufacturing method of the piezoelectric device as described in any one of Claim 1 to 7.
前記基板は主面が矩形であり、
前記導電層を形成する2つの内壁が相対する前記一方向が、前記基板の矩形の短辺方向と一致する、
請求項1から7の何れか一項記載の圧電デバイスの製造方法。
The substrate has a rectangular main surface,
The one direction in which the two inner walls forming the conductive layer face each other coincides with the short side direction of the rectangle of the substrate.
The manufacturing method of the piezoelectric device as described in any one of Claim 1 to 7.
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