JP2015023654A - Device for detecting current through semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current detection device that precisely detects a current flowing through a semiconductor element.SOLUTION: An IGBT 2 as the semiconductor element includes a sense emitter terminal S, and a short circuit overcurrent detection circuit 4 detects an overcurrent to perform a protective action on the basis of a terminal voltage Vp of a current detection resistor 3. The IGBT 2 is fed with a gate driving current Idrv from a MOSFET 8. A bypass circuit 13 shunts a current component Is flowing through the sense emitter terminal S in accordance with the gate driving current Idrv flowing between a gate and an emitter when the IGBT 2 is driven. This enables precise detection of a collector current Ic even while the IGBT 2 is driven.

Description

  The present invention relates to a current detection device for a semiconductor element.

  Some semiconductor elements used in inverter devices and the like have a current detection terminal. On the other hand, in the switching operation of the semiconductor element, when a drive signal is supplied to the control terminal, a current flowing from the control terminal to the current detection terminal is generated, and this current may be superimposed on a load current to be detected.

  For this reason, the detected current value may become large during driving, and there is a technique for masking so as not to perform the current detection operation in order to avoid this. However, the current flowing through the load cannot be detected during the mask period, and the current detection operation cannot be performed accurately.

JP 2004-312924 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a current detection device for a semiconductor element that can perform a current detection operation even during a period in which a drive current flows through a control terminal of the semiconductor element. It is in.

  The current detection apparatus for a semiconductor element according to claim 1 is a current detection apparatus for a semiconductor element for detecting a current of a semiconductor element having a current detection terminal in addition to an output terminal and a control terminal, A current detection circuit that detects a current flowing through the current detection terminal, and a current component that flows from the control terminal to the current detection terminal out of the current that flows through the semiconductor element by a drive signal applied to the control terminal from the current detection terminal. And a bypass circuit for bypassing.

  According to the above configuration, when driving the semiconductor element, when detecting the current flowing through the current detection terminal of the semiconductor element, there may occur a period in which the current flowing from the control terminal to the output terminal side is included at the start of driving. . During this period, the current flowing through the current detection terminal flows in a state where the drive current is added to the current flowing between the output terminals. For this reason, if the current flowing through the current detection terminal is directly detected by the current detection circuit, it is detected in a state where the drive current is added. On the other hand, since the current component flowing from the control terminal of the semiconductor element to the current detection terminal is bypassed from the current detection terminal by the bypass circuit, the current flowing from the current detection terminal to the current detection circuit is excluded from the drive current. Can be detected. Thereby, the current flowing through the output terminal when the semiconductor element is driven can be detected with high accuracy.

Electrical configuration diagram showing the first embodiment Electrical configuration diagram showing the second embodiment Electrical configuration diagram showing the third embodiment Electrical configuration diagram showing the fourth embodiment Time chart showing signal status of each part Electrical configuration diagram showing the fifth embodiment Electrical configuration diagram showing the sixth embodiment Time chart showing signal status of each part Electrical configuration diagram showing the seventh embodiment Time chart showing signal status of each part

(First embodiment)
Hereinafter, an example in which the first embodiment of the present invention is applied to a current detection device for a semiconductor element incorporated in an inverter device will be described with reference to FIG.
For example, as semiconductor elements constituting the main circuit of the inverter device, there are IGBTs 1 and 2 constituting arms of a bridge-connected circuit. The IGBTs 1 and 2 are connected in series between the DC power supply terminal Vc and the ground terminal GND. A coil L such as a motor as a load is connected to a common connection point of the high-side IGBT 1 and the low-side IGBT 2. Here, although one arm is shown, for example, it constitutes a part of a three-phase inverter device.

  The free-wheeling diodes 1a and 2a are connected in parallel to the IGBTs 1 and 2, respectively. These free-wheeling diodes 1a and 2a may be externally attached or may be incorporated. The IGBTs 1 and 2 each include a collector C that is an output terminal, an emitter E, and a gate G that is a control terminal, and a sense emitter S that is a current detection terminal. The IGBT 2 has a configuration in which the current flowing from the collector C to the emitter E side is divided and sent to the emitter E and the sense emitter S at a predetermined ratio, for example, n: 1. The value of n indicating the ratio is set to a predetermined value such as 2000 or 5000, for example.

  In the following description, a circuit configuration of a current detection device connected to the low-side IGBT 2 will be described. The same circuit configuration of the current detection device is also connected to the high-side IGBT 1. The sense emitter S of the IGBT 2 is connected to the ground terminal GND through the current detection resistor 3. The short-circuit overcurrent protection circuit 4 as a current detection circuit is configured to perform a protective operation when a terminal voltage Vp of the current detection resistor 3 is input and a short-circuit current or an overcurrent flows through the IGBT 2.

  The short circuit overcurrent protection circuit 4 includes a comparator 5 and a voltage dividing circuit 7. The terminal voltage Vp of the current detection resistor 3 is input to the non-inverting input terminal of the comparator 5. The reference voltage Vr is input from the voltage dividing circuit 7 to the inverting input terminal of the comparator 5. The voltage dividing circuit 7 is formed by connecting a series circuit of voltage dividing resistors 7a and 7b between a power supply terminal Vd and a ground terminal GND. The voltage generated at the common connection point of the voltage dividing resistors 7a and 7b becomes the reference voltage Vr.

  The IGBT 2 is given a gate voltage Vg by a gate drive circuit having a p-channel type MOSFET 8, an n-channel type MOSFET 9 and a resistor 10. The source / drain terminal of the MOSFET 8 is connected between the power supply terminal Vd and the gate G of the IGBT 2. An ON drive signal is input to the gate of the MOSFET 8 through the OR circuit 11. The drain terminal of the MOSFET 9 is connected to the gate G of the IGBT 2 via the resistor 10, and the source terminal is connected to the ground terminal GND. An off drive signal is applied to the gate of the MOSFET 9. In the OR circuit 11, the output terminal of the comparator 5 is connected to the other input terminal.

  The noise reduction circuit 12 includes a bypass circuit 13 and a drive circuit 14. The bypass circuit 13 bypasses and flows a part of the current flowing through the sense emitter S of the IGBT 2. The drive circuit 14 gives a drive signal to the bypass circuit 13 so as to bypass the current component flowing through the sense emitter S in the current Idrv flowing from the gate G to the emitter E of the IGBT 2. The drive circuit 14 has a bypass current corresponding to a current detection type in which a bypass current is set based on a value obtained by detecting the gate drive current Idrv and a configuration in which the gate drive current Idrv is supplied to the IGBT 2 with a constant current. It is shown as a comprehensive configuration including both a constant current type and a constant current type.

  Next, the operation of the above configuration will be described. In the IGBT 2, when the drive signal Si changing from the high level to the low level is input to the OR circuit 11, the MOSFET 8 is turned on to apply a voltage from the power supply terminal Vd to the gate terminal G. In this case, the comparator 5 of the short circuit overcurrent protection circuit 4 outputs a low level signal because no current has yet flowed through the current detection resistor 3. Thereby, the other input terminal of the OR circuit 11 is in a state where a low level signal is inputted. Therefore, when the drive signal Si is inverted to the low level, the OR circuit 11 outputs a low level signal.

  In the IGBT 2, when a voltage is applied to the gate terminal G, a gate current Idrv for charging the gate flows. The gate voltage Vg increases due to the charging of the gate capacitance by the gate current Idrv. When the gate voltage Vg reaches the threshold voltage, the IGBT 2 is turned on. As a result, the collector current Ic starts to flow from the collector C to the emitter E in the IGBT 2. The collector current Ic flows through the emitter E and the sense emitter S at an n: 1 ratio.

On the other hand, when the gate current Idrv when charging the gate capacitance flows into the gate terminal G of the IGBT 2, the current Idrv flows through the emitter E and the sense emitter S. Since the current component Is flowing through the sense emitter S of the current Idrv is 1 / (n + 1) of the gate current Idrv,
Is = Idrv / (n + 1)
It is. The drive circuit 14 outputs a command to the bypass circuit 13 so as to bypass the current component Is flowing in the sense emitter S of the IGBT 2 with respect to Idrv flowing from the MOSFET 8 to the gate G of the IGBT 2.

  Thereby, the current flowing through the current detection resistor 3 is cut by bypassing the current component Is caused by the gate current Idrv. In this case, a current component (= Idrv−Is) caused by the gate current Idrv is added as a current flowing through the emitter E. However, since the current component Is is cut as the terminal voltage of the current detection resistor 3, the voltage due to the current component flowing in the sense emitter terminal S out of the current component Ic flowing from the collector C can be detected.

  When the IGBT 2 shifts to the ON state, the gate current Idrv for charging initially flows to the emitter side and shifts to the ON state when the gate voltage Vg reaches the threshold voltage. Thereafter, the gate drive current Idrv shifts to a mirror period that flows to the collector side. When the mirror period ends, the gate drive current Idrv flows again to the emitter side, and when the gate voltage Vg reaches a predetermined potential, the gate drive current Idrv flows. Disappear.

  Therefore, the current Is can be bypassed from the sense emitter terminal S by the bypass circuit 13 during the two periods in which the gate drive current Idrv flows to the emitter side of the IGBT 2. As a result, the collector current flowing through the IGBT 2 can be accurately detected even when shifting to the ON operation.

  Further, since the collector current Ic can be accurately detected even during the on-transition period, the detection operation can be accurately performed even when an overcurrent or a short circuit occurs, and the IGBT 2 can be protected. The short circuit overcurrent protection circuit 4 can detect the current flowing through the sense emitter S of the IGBT 2 based on the terminal voltage Vp of the current detection resistor 3 as described above.

  The short-circuit overcurrent protection circuit 4 gives a high level signal from the comparator 5 to the OR circuit 11 when the terminal voltage Vp exceeds the reference voltage Vr indicating the overcurrent level. As a result, the OR circuit 11 provides a high level signal to the gate of the MOSFET 8, so that the MOSFET 8 is turned off. At this time, a signal for shifting to the ON state is applied to the gate of the MOSFET 9. As a result, the potential of the gate G is lowered and the IGBT 2 shifts to the off state. The IGBT 2 that is in a state where an overcurrent is flowing is given a signal for causing the gate G to shift to an OFF state, whereby the overcurrent can be prevented from continuing to be protected and the element can be protected.

  According to the first embodiment, since the noise reduction circuit 12 is provided to bypass the current Is flowing through the sense emitter terminal S corresponding to the gate drive current Idrv, the current detection resistor is connected from the sense emitter terminal S. 3 can be detected as a current that does not include the gate drive current Idrv. As a result, it is possible to prevent detection of a current when the gate drive current Idrv flows to the emitter side when the IGBT 22 shifts to the ON state, and even when the IGBT 2 shifts to the ON state, the short-circuit overcurrent protection circuit The operation 4 can be performed with high accuracy.

(Second Embodiment)
FIG. 2 shows the second embodiment. The difference from the first embodiment is that a drive IC 21 is provided and a noise reduction circuit 22 having functions of a drive circuit and a current detection type bypass circuit is configured. is there. Further, the noise reduction circuit 22 is configured to detect a gate-emitter current Idrv flowing through the IGBT 2 by the drive circuit and to bypass a component in which a corresponding current flows through the sense emitter terminal S.

  That is, the noise reduction circuit 22 constitutes a current mirror circuit by providing MOSFETs 23 to 25 for the driving MOSFETs 8 and 9 and the resistor 10 constituting the driving circuit. The MOSFET 23 is set such that a current of a ratio of 1 / (n + 1) flows with respect to the current flowing through the driving MOSFET 8. The MOSFETs 24 and 25 are set so that the same current as the MOSFET 23 flows. The MOSFET 25 has a drain connected to the sense emitter terminal S of the IGBT 2 and bypasses a part of the current flowing through the sense emitter terminal S.

  In the above configuration, when the drive signal Si changing from the high level to the low level is input to the OR circuit 11, the MOSFET 8 is turned on to apply a voltage from the power supply terminal Vd to the gate terminal G of the IGBT2. In the IGBT 2, when a voltage is applied to the gate terminal G, a gate current Idrv for charging the gate flows. The gate voltage Vg increases due to the charging of the gate capacitance by the gate current Idrv. When the gate voltage Vg reaches the threshold voltage, the IGBT 2 is turned on. As a result, the collector current Ic starts to flow from the collector C to the emitter E in the IGBT 2. The collector current Ic flows through the emitter E and the sense emitter S at a ratio of n: 1.

  On the other hand, the MOSFET 23 constituting the current mirror circuit is supplied with the same gate potential as that of the MOSFET 8 at the gate terminal, so that a current at a ratio of 1 / (n + 1) of the current Idrv flowing through the gate G of the IGBT 2, that is, the sense emitter S of the IGBT 2. A current corresponding to the current component Is flowing through is supplied. The current Is flowing through the MOSFET 24 is also driven to flow through the MOSFET 25, and bypasses the current component Is of the current flowing through the sense emitter S.

  As a result, the current flowing through the current detection resistor 3 is cut by bypassing the component due to the gate current Idrv. As a result, a component caused by the gate current Idrv is added to the current flowing through the emitter E. However, the terminal voltage of the current detection resistor 3 is the current flowing through the sense emitter S due to the component of the current component Ic flowing from the collector C. Can be detected.

  When the IGBT 2 shifts to the on state, the gate current Idrv for charging flows initially, and then after the mirror period, the gate current Idrv flows again after being turned on. Accordingly, the current Is flowing through the sense emitter S corresponding to the gate current Idrv during both periods is bypassed by the bypass circuit 13 so that the component due to the gate current Idrv does not flow through the current detection resistor 3. Can do. As a result, the collector current flowing through the IGBT 2 can be accurately detected even when shifting to the ON operation.

  Further, since the collector current Ic can be accurately detected even during the on-transition period, the IGBT 2 can be protected in an appropriate manner even when an overcurrent or a short circuit occurs. The short circuit overcurrent protection circuit 4 can detect the current flowing through the sense emitter S of the IGBT 2 based on the terminal voltage Vp of the current detection resistor 3 as described above.

  Since the protection operation by the short circuit overcurrent protection circuit 4 is performed in the same manner as in the first embodiment, the detection operation is performed without being affected by the current component Is caused by the gate drive current Idrv, and the short circuit or overcurrent is detected. Problems due to current can be prevented.

  According to such a second embodiment, the current Is flowing through the sense emitter terminal S corresponding to the gate drive current Idrv is bypassed by the MOSFET 25 in the current mirror circuit, so that the gate drive current Idrv is the gate terminal of the IGBT 2. Of the current flowing to the emitter side via G, the current flowing to the sense emitter terminal S can be bypassed. As a result, the current detection operation by the current detection resistor 3 can be detected in a state where the noise component due to the current flowing from the gate terminal G to the emitter side is removed.

(Third embodiment)
FIG. 3 shows the third embodiment. The difference from the second embodiment is that the noise reduction circuit 22a is not a ground terminal GND but a negative power supply terminal having a negative power supply voltage Vm (V) (<0 V). It has just been configured to connect.

  The noise reduction circuit 22a can operate by connecting the MOSFETs 24 and 25 to the negative power supply voltage Vm even when the current flowing through the sense emitter terminal S is small, that is, when the terminal voltage of the current detection resistor 3 is low. . As a result, the operation of the noise reduction circuit 22a can be performed not only in the case of a short circuit or in a state where an overcurrent flows, but also in the case of a small current, and a highly accurate current detection operation is performed. Can do.

(Fourth embodiment)
FIG. 4 and FIG. 5 show the fourth embodiment, and the differences from the second embodiment will be described below. In the fourth embodiment, a noise reduction circuit 22b is provided as the drive IC 21b, and a period during which the gate drive current Idrv contributes to increasing the gate potential relative to the current flowing through the sense emitter terminal S of the IGBT 2 is detected. Thus, the current Is is bypassed.

  The noise reduction circuit 22b has a configuration in which a MOSFET 26 as a switching circuit is added to the configuration of the noise reduction circuit 22a in the second embodiment. The MOSFET 26 has a function of turning on and off the operation of the current mirror circuit, and a drain-source terminal is connected between the gates of the MOSFETs 24 and 25 and the ground terminal GND.

  The mirror period determination circuit 27 as a voltage fluctuation detection circuit detects a mirror period in which the gate voltage Vg does not change during the period in which the gate drive current Idrv flows, and controls the operation of the noise reduction circuit 22b. The mirror period determination circuit 27 includes a differentiation circuit 28 and a comparator 29. The differentiating circuit 28 includes a capacitor 28 a and a resistor 28 b, and inputs a signal obtained by differentiating the voltage change at the gate terminal G of the IGBT 2 to the inverting input terminal of the comparator 29. The comparison reference voltage Vc is input from the voltage dividing circuit 30 to the non-inverting input terminal of the comparator 29. The voltage dividing circuit 30 is formed by connecting a series circuit of voltage dividing resistors 30a and 30b between a power supply terminal Vd and a ground terminal GND. The voltage generated at the common connection point of the voltage dividing resistors 30a and 30b is the reference voltage Vc. The output terminal of the comparator 5 is connected to the gate terminal of the MOSFET 26.

Next, the operation of the above configuration will be described with reference to FIG. FIG. 5 is a time chart showing changes in signals of the respective parts.
First, a change in the gate voltage Vg that is the potential of the gate terminal G of the IGBT 2 when the gate drive current Idrv flows will be described. In the above configuration, when the drive signal Si changing from the high level to the low level is input to the OR circuit 11 at time T0 (see FIG. 5A), the MOSFET 8 is turned on and the power supply terminal Vd to the gate terminal G of the IGBT 2 Apply voltage. In the IGBT 2, when a voltage is applied to the gate terminal G, a gate current Idrv for charging the gate flows between the gate and the emitter (see FIG. 5C).

  The gate voltage Vg is increased by charging the gate capacitance by the gate current Idrv (see FIG. 5B), and when the gate voltage Vg reaches the threshold voltage (time T1), the IGBT 2 is turned on. As a result, the collector current Ic starts to flow from the collector C to the emitter E in the IGBT 2 (see FIG. 5D). The collector current Ic flows through the emitter E and the sense emitter S at a ratio of n: 1.

  Thereafter, when the IGBT 2 is turned on, the collector current Ic flows, and at the same time, the mirror period is started and the gate drive current Idrv flows to the collector side. During this mirror period, the gate potential Vg is kept constant (see FIG. 5B), and the gate-emitter current to the sense emitter terminal S does not flow (see FIG. 5C). When the mirror period ends, the gate drive current Idrv again flows to the emitter side and contributes as a current flowing to the sense emitter terminal S (see FIG. 5C).

  Since the gate drive current Idrv has such a property, the gate potential Vg rises during the period in which the gate drive current Idrv flows to the emitter side. Therefore, a constant voltage is output from the differentiating circuit 28 of the mirror period determination circuit 27 during a period in which the gate potential Vg is rising at a constant rate of increase. At this time, the output voltage of the differentiation circuit 28 becomes higher than the comparison voltage Vc, and the comparator 29 outputs a low level signal. As a result, the MOSFET 26 of the noise reduction circuit 22b is shifted to the OFF state, and the current mirror circuit is shifted to the operating state.

  On the other hand, in the period in which the gate potential Vg of the IGBT 2 does not increase, the potential does not change, so that the output is zero in the differentiation circuit 28 of the mirror period determination circuit 27 and the comparator 29 outputs a high level signal. Become. In this state, since the gate drive current Idrv does not flow to the emitter side, current bypassing by the noise reduction circuit 22b is an unnecessary period. In this state, since the MOSFET 26 of the noise reduction circuit 22b is turned on, the MOSFET 25 is held in the off state, and the current mirror circuit is brought into a stopped state.

  Since the mirror period determination circuit 27 operates as described above, when the drive signal Si changing from the high level to the low level is input to the OR circuit 11 and the gate voltage Vg of the IGBT 2 starts to rise, the change in the gate voltage Vg is changed. It is detected by the mirror period determination circuit 27. As a result, during the period when the gate voltage Vg rises, the noise reduction circuit 22b operates. A current Is flowing through the sense emitter terminal S corresponding to the gate drive current Idrv is bypassed by the noise reduction circuit 22b, and a current corresponding to the collector current Ic flows through the current detection resistor 3 (see FIG. 5G). As a result, the potential Vp of the sense emitter terminal S can be detected as a potential corresponding to the collector current Ic. At this time, a current component of the sum of the collector current Ic and the gate drive current Idrv flows through the emitter terminal E.

  Thereafter, during the mirror period, the current due to the gate drive current Idrv does not flow to the sense emitter terminal S of the IGBT 2. During this period, since the gate voltage Vg is a constant voltage, the operation of the noise reduction circuit 22b is stopped by the mirror period determination circuit 27, and the operation of bypassing the current from the sense emitter terminal S is not performed. During this mirror period, the gate drive current Idrv does not flow through the sense emitter terminal S of the IGBT 2, so that a current corresponding to the collector current Ic of the IGBT 2 flows through the current detection resistor 3.

  When the mirror period ends and the gate voltage Vg of the IGBT 2 starts to rise again due to the gate drive current Idrv, the noise reduction circuit 22b is shifted to the operating state, and the current Is flowing through the sense emitter terminal S corresponding to the gate drive current Idrv. Is bypassed, and a current corresponding to the collector current Ic flows through the current detection resistor 3.

  Thereafter, when the gate voltage Vg of the IGBT 2 becomes constant, the gate voltage Vg does not change, so that the comparator 29 of the mirror period determination circuit 27 outputs a high level signal and turns on the MOSFET 26 of the noise reduction circuit 22b. As a result, the noise reduction circuit 22b is disabled, and the operation of bypassing the current from the sense emitter terminal S is stopped.

  Since the noise reduction circuit 22b operates as described above, the terminal voltage Vp of the current detection resistor 3 appearing at the sense emitter terminal S is the collector current Ic (the collector / current of the collector current Ic (FIG. 5D)) as shown in FIG. It can be obtained as a voltage signal indicating a change corresponding to the emitter current reference. In this case, since the noise reduction circuit 22b operates as described above, it can be detected as the sense voltage Vp as shown in FIG. 5G, but when the noise reduction circuit 22b does not operate, the gate drive current Idrv is included. It is detected as a voltage signal (see FIG. 5E). As a result, the sense voltage Vp can be detected in a state in which the voltage signal corresponding to the gate drive current Idrv is superimposed on the voltage signal Vp appearing at the sense emitter terminal S as noise.

  Since the protection operation by the short circuit overcurrent protection circuit 4 is performed in the same manner as in the first embodiment, the detection operation is performed without being affected by the current component Is caused by the gate drive current Idrv, and the short circuit or overcurrent is detected. Problems due to current can be prevented.

(Fifth embodiment)
FIG. 6 shows the fifth embodiment, and the following description will focus on the differences from the second embodiment. That is, in this embodiment, the drive IC 21c is configured to include a current mirror (C / M) type current detection circuit 31 instead of the current detection resistor 3 connected to the sense emitter terminal S of the IGBT 2. This is configured such that the current flowing through the sense emitter terminal S of the IGBT 2 is extracted by a current mirror circuit and converted into a voltage signal, which is output to the short-circuit overcurrent detection circuit 4.

  Therefore, according to the fifth embodiment, the C / M-type current detection circuit 31 performs the current detection operation for detecting the current corresponding to the collector current Ic flowing through the sense emitter terminal S of the IGBT 2, thereby enabling the second embodiment. The same effect can be obtained.

(Sixth embodiment)
FIG. 7 and FIG. 8 show the sixth embodiment, and the following description will focus on the differences from the second embodiment. In this embodiment, in the drive IC 21d, an operation control MOSFET 26 is added as the noise reduction circuit 22c, and a drive current detection resistor 32 (hereinafter referred to as a power supply path) from the power supply terminal Vd to the current mirror circuit of the noise reduction circuit 22c. It is simply configured as a resistor 32). Further, the current mirror control circuit 33 is newly added.

  The current mirror control circuit 33 is configured around the comparator 34. The non-inverting input terminal of the comparator 34 is connected to a connection point between the resistor 32 of the noise reduction circuit 22c and the current mirror circuit of the noise reduction circuit 22c. When a current flows through the current mirror circuit, the potential of the connection point decreases due to a voltage drop due to the resistor 32. When the current stops flowing, the voltage drop of the resistor 32 decreases and the potential increases. In this configuration, the potential at this time is input to the comparator 34. The comparison reference voltage Vk is applied from the voltage dividing circuit 35 to the inverting input terminal of the comparator 34. The voltage dividing circuit 35 is set so that a series circuit of resistors 35a and 35b is connected between the power supply terminal Vd and the ground terminal GND, and the voltage at the common connection point thereof becomes the comparison reference voltage Vk.

  Next, the operation of the above configuration will be described with reference to FIG. FIG. 8 is a time chart showing changes in signals of the respective parts. A change in the gate voltage Vg of the gate terminal G of the IGBT 2 when the gate drive current Idrv flows will be briefly described. When the drive signal Si that changes to the low level is input to the OR circuit 11 at time T0 as described above (see FIG. 8A), the MOSFET 8 is turned on to apply a voltage from the power supply terminal Vd to the gate terminal G of the IGBT2. To do. In the IGBT 2, when a voltage is applied to the gate terminal G, a gate current Idrv for charging the gate flows between the gate and the emitter (see FIG. 8C).

  The gate voltage Vg increases due to the charging of the gate capacitance by the gate current Idrv (see FIG. 8B), and when the gate voltage Vg reaches the threshold voltage (time T1), the IGBT 2 shifts to the ON state. As a result, the collector current Ic starts to flow from the collector C to the emitter E in the IGBT 2 (see FIG. 8D). The collector current Ic flows through the emitter E and the sense emitter S at a ratio of n: 1.

  Thereafter, when the IGBT 2 is turned on, the collector current Ic flows, and at the same time, the mirror period is started and the gate drive current Idrv flows to the collector side. During this mirror period, the gate potential Vg is kept constant (see FIG. 8B), and the gate-emitter current to the sense emitter terminal S does not flow (see FIG. 8C). When the mirror period ends, the gate drive current Idrv again flows to the emitter side and contributes as a current flowing to the sense emitter terminal S (see FIG. 8C).

  When the gate voltage Vg rises to a predetermined voltage as described above, the IGBT 2 is turned on, and the gate drive current Idrv from the MOSFET 8 of the noise reduction circuit 22c to the gate terminal G does not flow. The voltage Vq in the portion from the power supply terminal Vd of the noise reduction circuit 22c through the resistor 32 is a low voltage due to a voltage drop when the gate drive current Idrv is flowing, and the gate drive current Idrv does not flow. In the state, the voltage rises to a voltage close to the power supply voltage Vd.

  In contrast, the current mirror control circuit 33 outputs a low-level signal when the voltage Vq input to the non-inverting input terminal of the comparator 34 is low and lower than the reference voltage Vk, and when the voltage Vq exceeds the reference voltage Vk. A high level signal is output. Therefore, the current mirror control circuit 33 is in a state where the gate drive current Idrv does not flow through the MOSFET 8 of the noise reduction circuit 22c before the drive signal Si is input to the OR circuit 11 at time T0. A level signal is output. Thereby, the noise reduction circuit 22c is in a state where the operation of the current mirror circuit is stopped, and the operation of bypassing the current from the sense emitter terminal S of the IGBT 2 is not performed.

  Thereafter, when the drive signal Si is input and the gate drive current Idrv starts to flow, the current mirror control circuit 33 outputs a low level signal. In the noise reduction circuit 22c, the MOSFET 26 provided in the current mirror circuit is turned off by a low level signal from the comparator 34. During this period, the noise reduction circuit 22c is in a state in which the operation of the current mirror circuit is performed, and a current at a ratio of 1 / (n + 1) to the gate drive current Idrv, that is, a current component that flows through the sense emitter S of the IGBT 2 A current corresponding to Is is caused to flow by being bypassed by the MOSFET 25.

  As a result, during the period in which the gate drive current Idrv flows from the noise reduction circuit 22c to the gate terminal G, the current flowing to the sense emitter terminal S by the current mirror circuit both during the period when the gate voltage Vg rises and during the mirror period. Is bypassed (see FIG. 8G).

  In this case, the current flowing through the sense emitter terminal S is the current during two periods (between T0 and T1, between T2 and T3) of the gate drive current Idrv that contributes as the gate-emitter current (see FIG. 8C). And the collector current Ic flowing from the collector to the emitter (see FIG. 8D) is a current corresponding to the added current. Accordingly, when the current Is is not bypassed by the noise reduction circuit 22c, a voltage as shown in FIG. 5E appears as a terminal voltage (sense voltage) of the current detection resistor 3.

  Then, since the current mirror circuit of the noise reduction circuit 22c is operated by the output signal of the current mirror control circuit 33, the current Is is bypassed from the sense emitter terminal S, and the voltage Vp as shown in FIG. 8 (g) is detected. . Here, since the bypass current Is by the noise reduction circuit 22c is bypassed by the operation of the current mirror circuit even during the period when the gate drive current Idrv does not flow to the emitter side, the detected voltage Vp is as shown in FIG. The voltage waveform is shifted lower by a certain voltage. However, the negative voltage portion is actually held as zero.

  As a result, the voltage signal Vp appearing at the sense emitter terminal S is obtained as a voltage signal slightly different from the collector current Ic during the period in which the IGBT 2 is turned on, but the component corresponding to the gate drive current Idrv is removed. It can be detected as a voltage signal corresponding to the collector current Ic.

Since the protection operation by the short circuit overcurrent protection circuit 4 is performed in the same manner as in the second embodiment, the detection operation is performed without being affected by the current component Is caused by the gate drive current Idrv, and the short circuit or overcurrent is detected. Problems due to current can be prevented.
According to the sixth embodiment, by providing the current mirror control circuit 33, it is possible to obtain substantially the same operational effects as those of the second embodiment.

(Seventh embodiment)
FIG. 9 and FIG. 10 show the seventh embodiment, and the following description will focus on parts that are different from the first embodiment. In this embodiment, the gate drive current Idrv is a constant current type, and a constant current type bypass circuit is provided. In this embodiment, instead of the gate drive circuit and bypass circuit 12, a drive IC 21e having these functions is provided.

  In FIG. 9, the drive IC 21 e includes a short-circuit overcurrent protection circuit 4 and a noise reduction circuit 36. The noise reduction circuit 36 is provided with a constant current circuit 37 in place of the MOSFET 8 constituting the gate drive circuit. The constant current circuit 37 supplies a gate drive current Idrv necessary for the gate drive of the IGBT 2 as a constant current according to the gate drive signal Si given through the OR circuit 11. The IGBT 2 is configured to be gate-driven with a constant current by the constant current circuit 37.

  Since the gate drive current Idrv becomes a constant current, the bypass circuit 38 for extracting the current and the timing for supplying the bypass current are set as a configuration for bypassing the component corresponding to the gate drive current Idrv from the current flowing through the emitter sense S. A timer circuit 39 is provided.

  In the bypass circuit 38, a circuit in which a MOSFET 39 and a resistor 40 are connected in series is connected between the sense emitter terminal S of the IGBT 2 and the ground terminal GND, and the output terminal of the comparator 41 is connected to the gate of the MOSFET 39. The inverting input terminal of the comparator 41 is connected to a common connection point between the MOSFET 39 and the resistor 40. A non-inverting output terminal of the comparator 41 is connected to the reference voltage setting unit 42. When a drive signal is given from the timer circuit 39, the reference voltage setting unit 42 supplies a comparison reference voltage so as to flow a current that bypasses the current component flowing through the emitter sense S in response to the gate drive current Idrv from the constant current circuit 37. Va is supplied to the comparator 41.

  The comparator 41 gives a signal to the gate of the MOSFET 39 so that the bypass current flowing through the MOSFET 39 has a current value corresponding to the reference voltage Va. When the gate drive signal Si is input, the timer circuit 39 operates the reference voltage setting unit 42 during a period in which the gate-emitter current Idrv flows through the IGBT 2.

  Next, the operation of the above configuration will be described with reference to FIG. When the drive signal Si changing from the high level to the low level is input to the OR circuit 11 (see FIG. 10A), the constant current circuit 37 is activated and the gate drive current Idrv is supplied to the gate terminal G of the IGBT 2 at a constant current. Come to supply. In the IGBT 2, when a current is supplied to the gate terminal G, the gate voltage Vg rises due to charging of the gate capacitance (see FIG. 10B), and the gate drive current Idrv flows to the emitter side. During this period, a high level signal is output from the timer circuit 39 (see FIG. 10G), and the reference voltage Va is set to the reference voltage setting unit 42. Thereby, the bypass circuit 38 bypasses the current flowing through the sense emitter terminal S of the IGBT 2.

When the gate drive current Idrv flows to the emitter side as described above, the component Is flowing to the sense emitter terminal S is
Is = Idrv / (1 + n)
Thus, the current Is is set to flow while being bypassed. Therefore, as the reference voltage Va input to the non-inverting input terminal of the comparator 41,
Va = Is × R
= Idrv × R / (1 + n)
Is set by the reference voltage setting unit 42. Here, R indicates the resistance value of the resistor 40. Since the base drive current Idrv is a constant current, all values for setting the reference voltage Va are known, and thus the reference voltage Va can be set in advance.

  As a result, when the bypass circuit 38 operates, the current Is set by the reference voltage Va is bypassed from the sense emitter terminal S during the period in which the gate drive current Idrv flows through the gate G of the IGBT 2.

  Thereafter, when the gate voltage Vg rises to the threshold voltage, the IGBT 2 is turned on. As a result, the collector current Ic begins to flow between the collector and the emitter of the IGBT 2. In this state, the gate drive current Idrv does not flow from the gate terminal G to the emitter side, but a mirror period in which it flows to the collector side. Further, the gate voltage Vg does not increase during this mirror period (see FIG. 10B). During this period, the timer circuit 39 outputs a low level signal to the reference voltage setting unit 42 to stop the operation. Therefore, current bypass by the bypass circuit 38 is not performed during the mirror period.

  After this, when the mirror period ends, the gate drive current Idrv again flows to the emitter side of the IGBT 2, and during this period, the timer circuit 39 also outputs a high-level signal by the reference voltage setting unit 42 to bypass the bypass circuit 38. Make it work. Thereby, the current Is flowing in the sense emitter terminal S of the IGBT 2 in the gate drive current Idrv can be bypassed by the bypass circuit 38.

  When the gate voltage Vg rises to a predetermined voltage, the gate drive current Idrv is stopped, and the timer circuit 39 also outputs a low level signal. In this state, the operation of the bypass circuit 38 is stopped.

  In the above operation, as shown in FIG. 10C, the gate drive current Idrv is constant for a certain period immediately after the activation signal Si is input (period T0 to T1) and constant after the mirror period ends. It flows to the emitter side of the IGBT 2 during a period (period of time T2 to T3). As shown in FIG. 10D, the collector current Ic of the IGBT 2 starts to flow gradually from the time (time T1) when the gate voltage Vg reaches the threshold voltage.

  As a result, the voltage detected at the sense emitter terminal S is a current obtained by combining the gate drive current Idrv and the collector current Ic as shown in FIG. This voltage is generated when it flows. When the noise reduction circuit 36 operates without the timer circuit 39, the current Is is bypassed from the sense emitter terminal S as a whole during the period in which the gate drive current Idrv flows as shown in FIG. Is done. As a result, the sense voltage shown in FIG. 10E becomes the sense voltage in a state in which the amount corresponding to the gate drive current Idrv is lowered over the period of time T0 to T3.

  However, in this case, since the amount corresponding to the gate drive current Idrv is lowered even during the mirror period, the sense voltage during the mirror period (time T1 to T2) is slightly lowered. Therefore, since the timer circuit 39 detects the mirror period and stops the operation of the bypass circuit 36, the current Is can be prevented from being bypassed during the mirror period. As a result, the terminal (sense) voltage Vp as shown in FIG. 10H can be detected. In this case, a component caused by the gate current Idrv is added as the current flowing through the emitter E, but the terminal voltage Vp of the current detection resistor 3 flows through the sense emitter S due to the component of the current component Ic flowing from the collector C. The current can be detected.

  Since the protection operation by the short circuit overcurrent protection circuit 4 is performed in the same manner as in the first embodiment, the detection operation is performed without being affected by the current component Is caused by the gate drive current Idrv, and the short circuit or overcurrent is detected. Problems due to current can be prevented.

  According to the seventh embodiment, the bypass circuit 38 and the timer circuit 39 are provided in the configuration in which the gate drive current Idrv of the IGBT 2 is driven at a constant current. As a result, the current Is is bypassed during the period when the gate voltage Vp rises, that is, during the period when the gate drive current Idrv flows into the sense emitter terminal S, so that the detection operation corresponding to the collector current Ic as the terminal voltage Vp of the current detection resistor 3 It can be performed.

(Other embodiments)
In addition, this invention is not limited only to one embodiment mentioned above, It can apply to various embodiment in the range which does not deviate from the summary, For example, it can deform | transform or expand as follows. .
The current detection circuit can be configured as a circuit that detects the value of the current flowing through the current detection terminal of the semiconductor element, in addition to a circuit that detects a short circuit current or an overcurrent, such as the short circuit overcurrent detection circuit 4.

In addition to the IGBTs 1 and 2, the semiconductor element can also be applied to a MOSFET that is a voltage-controlled semiconductor element having a gate control terminal or a bipolar transistor that is a current-controlled semiconductor element.
Although the MOSFET 8 is used as the configuration for supplying the gate drive current Idrv to the gate terminal G of the IGBT 2, a bipolar transistor can also be used.

  In the drawings, 1 and 2 are IGBTs (semiconductor elements), 3 is a current detection resistor, 4 is a short-circuit overcurrent detection circuit (current detection circuit), 8 is a p-channel MOSFET, 11 is an OR circuit, and 12 is a noise reduction circuit. , 13 and 38 are bypass circuits, 21 is a drive IC, 22, 22a, 11b, 22c and 36 are noise reduction circuits (bypass circuits), 25 is an n-channel MOSFET, and 26 is an n-channel MOSFET (switching circuit). , 27 is a mirror period determination circuit (voltage fluctuation detection circuit), 28 is a differentiation circuit, 31 is a current mirror type current detection circuit, 32 is a drive current detection resistor, 33 is a current mirror control circuit, 37 is a constant current circuit, and 39 is It is a timer circuit.

Claims (9)

A semiconductor element current detection device for detecting a current of a semiconductor element (1, 2) provided with a current detection terminal (S) in addition to an output terminal (C, E) and a control terminal (G),
A current detection circuit (4) for detecting a current flowing through the current detection terminal of the semiconductor element;
By-pass circuits (13, 22, 22a, 22b, for bypassing a current component flowing from the control terminal to the current detection terminal out of the current flowing through the semiconductor element by a drive signal applied to the control terminal from the current detection terminal. 22c, 38). A semiconductor element current detection device. The current detection apparatus for a semiconductor element according to claim 1,
The bypass circuit (13, 22, 22a, 22b, 22c) detects a current flowing through the control terminal based on the drive signal applied to the control terminal, and obtains a current component flowing through the current detection terminal from the detected current. A current detecting device for a semiconductor element, wherein the current detecting terminal is bypassed. The current detection apparatus for a semiconductor element according to claim 2,
The bypass circuit (22, 22a, 22b, 22c) operates when the same signal as the drive signal applied to the control terminal is provided, and the current detection terminal among the currents flowing to the control terminal by the drive signal. A current detection device for a semiconductor element, comprising a current mirror circuit that generates current at a ratio of current components flowing through the current detection circuit and bypasses the current detection terminal. The current detection apparatus for a semiconductor element according to claim 3,
The current mirror circuit (22a) is configured to generate a current for bypassing with an operating voltage larger than a detection voltage generated at the current detection terminal. The current detection apparatus for a semiconductor element according to claim 1,
The semiconductor element is configured such that a constant current signal is provided as a drive signal to the control terminal,
The bypass circuit (13, 38) obtains a current component flowing through the current detection terminal based on a constant current value of a drive signal applied to the control terminal and bypasses the current detection terminal. Semiconductor device current detection device. In the electric current detection apparatus of the semiconductor element according to any one of claims 1 to 5,
A current detecting device for a semiconductor element, wherein the operation of the current bypass by the bypass circuit (22b) is performed during a voltage fluctuation period of a control terminal of the semiconductor element. The current detection apparatus for a semiconductor element according to claim 6,
A potential fluctuation detection circuit (27) for detecting a voltage fluctuation period of a control terminal of the semiconductor element;
A current detecting device for a semiconductor element, comprising a switching circuit (26) for switching the operation of the bypass circuit (22b) in accordance with a detection signal of a voltage fluctuation period of the control terminal by the potential fluctuation detecting circuit. The current detection apparatus for a semiconductor element according to claim 6 or 7,
The electric potential fluctuation detection circuit (27) is configured to detect a voltage fluctuation of a control terminal of the semiconductor element by a differentiating circuit (28). The current detection apparatus for a semiconductor element according to claim 3,
A drive current detection resistor (32) provided in the current mirror circuit (22c) and causing a voltage drop due to a current flowing through the control terminal by the drive signal;
A current mirror control circuit (33) for detecting a period during which a current flows to the control terminal by the drive current detection resistor;
A current detection device for a semiconductor element, comprising a switching circuit (26) for driving the current mirror circuit during a period in which a current flows to the control terminal by the current mirror control circuit.

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