JP2015018849A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for reduction in an area of a semiconductor storage device.SOLUTION: A method for manufacturing a semiconductor storage device comprises the steps of: forming a first silicon oxide film on a first region of a semiconductor substrate and a second silicon oxide film on a second region of the semiconductor substrate; forming a first silicon nitride film on the first silicon oxide film and a second silicon nitride film on the second silicon oxide film; forming a third silicon oxide film on the second silicon nitride film and a fourth silicon oxide film on the first silicon nitride film; removing the fourth silicon oxide film; and forming a first gate electrode on the first silicon nitride film from which the fourth silicon oxide film was removed and a second gate electrode on the third silicon oxide film.

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof.

  As a memory cell of a nonvolatile semiconductor memory device which can be electrically written and erased, one having a trapping insulating film under a gate electrode of a MIS (Metal Insulator Semiconductor) transistor is known. As a memory cell having a trapping insulating film, there is a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell. In this memory cell, electric charges are stored as stored information in a nitride film positioned between the bottom oxide film and the top oxide film, and can be read out as a threshold voltage of the MIS transistor.

  In order to perform writing, erasing and reading of information with respect to such a memory cell, there is one in which one selection transistor is combined with one memory cell. This selection transistor has a MOS (Metal Oxide Semiconductor) structure, and the insulating film under the gate electrode is an oxide film, so that charges are not accumulated.

  As a method of manufacturing a semiconductor memory device in which the memory cell and the selection transistor are arranged as described above, a bottom oxide film, a nitride film, and a top oxide film are formed on a region where the memory cell and the selection transistor are formed, and then the selection transistor The bottom oxide film, nitride film, and top oxide film on the region where the selective transistor is formed are removed, and a gate oxide film is formed on the region where the selection transistor is formed (see, for example, Patent Document 1). ).

JP 2002-324860 A

  However, in the manufacturing method described in Patent Document 1, it is necessary to remove not only the bottom oxide film and the top oxide film on the region where the selection transistor is to be formed, but also the nitride film positioned between them, thereby improving processing accuracy. It was sometimes difficult.

  The present invention has been made in view of the above technical problems. Some aspects of the present invention relate to reducing the space margin of the MONOS memory cell and the select transistor, and enabling the area of the semiconductor memory device to be reduced.

In some embodiments of the present invention, a method of manufacturing a semiconductor memory device includes forming a first silicon oxide film on a first region of a semiconductor substrate and forming a second silicon oxide film on a second region of the semiconductor substrate. Forming a first silicon nitride film on the first silicon oxide film, forming a second silicon nitride film on the second silicon oxide film, and forming a third silicon nitride film on the second silicon nitride film. Forming a silicon oxide film and forming a fourth silicon oxide film on the first silicon nitride film; removing the fourth silicon oxide film; and first silicon from which the fourth silicon oxide film has been removed Forming a first gate electrode on the nitride film and forming a second gate electrode on the third silicon oxide film.
According to this aspect, the fourth silicon oxide film is removed, the first gate electrode is formed on the first silicon nitride film from which the fourth silicon oxide film has been removed, and the second silicon oxide film is formed on the third silicon oxide film. Since the gate electrode is formed, it is not necessary to remove the first silicon nitride film, and the area of the semiconductor memory device can be reduced.

In the above aspect, the step of forming the fifth silicon oxide film on the third region of the semiconductor substrate and forming the sixth silicon oxide film on the fourth region of the semiconductor substrate, and removing the sixth silicon oxide film A step of forming a seventh silicon oxide film on the fourth region from which the sixth silicon oxide film has been removed, a third gate electrode formed on the fifth silicon oxide film, and a seventh silicon oxide film Forming a fourth gate electrode on the film, and preferably removing the fourth silicon oxide film and removing the sixth silicon oxide film simultaneously.
According to this, since the step of removing the fourth silicon oxide film and the step of removing the sixth silicon oxide film are performed simultaneously, an increase in the number of steps can be suppressed.

In the above aspect, the film thickness of the fifth silicon oxide film is larger than the sum of the film thickness of the first silicon oxide film and the film thickness of the first silicon nitride film, and the film thickness of the first silicon oxide film The total thickness of one silicon nitride film may be larger than the thickness of the seventh silicon oxide film.
According to this, the transistor having the fifth silicon oxide film as the gate insulating film can be a high breakdown voltage transistor, and the transistor having the seventh silicon oxide film as the gate insulating film can be a transistor capable of operating at high speed with low breakdown voltage. .

In another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate including a first region and a second region of a first conductivity type, a first silicon oxide film located on the first region, and a first silicon oxide film A first silicon nitride film located above, a first gate electrode located on the first silicon nitride film, a second silicon oxide film located on the second region, and a first silicon oxide film located on the second silicon oxide film A second silicon nitride film; a third silicon oxide film located on the second silicon nitride film; and a second gate electrode located on the third silicon oxide film.
According to this aspect, the first silicon oxide film and the first silicon nitride film are positioned in this order on the first region, and the second silicon oxide film on the second region and the second silicon oxide film Since the silicon nitride film has the same configuration as that of the silicon nitride film, it is not necessary to provide a large space margin between the first region and the second region, and the area of the semiconductor memory device can be reduced.

  In the above aspect, the difference in film thickness between the first silicon oxide film and the second silicon oxide film and the difference in film thickness between the first silicon nitride film and the second silicon nitride film are the same as those in the second silicon oxide film. It may be smaller than the difference in film thickness with the third silicon oxide film.

In the above-described aspect, it is desirable that the thickness of the first silicon nitride film is 100 angstroms or less.
According to this, even if charges are stored in the first silicon nitride film, the charges can escape toward the first gate electrode.

1 is a cross-sectional view of a semiconductor memory device according to an embodiment. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor memory device of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor memory device of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor memory device of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor memory device of FIG. 1.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. Further, not all of the configurations described in the present embodiment are essential as a solution means of the present invention. The same constituent elements are denoted by the same reference numerals, and description thereof is omitted.

<1. Configuration and Operation>
FIG. 1 is a cross-sectional view conceptually showing a semiconductor memory device according to one embodiment of the present invention. The semiconductor memory device according to the present embodiment includes a cell array region 100 including memory cells MC and selection transistors ST, and electrons for supplying voltages for writing, erasing, and reading to the memory cells MC and selection transistors ST. And a peripheral circuit region 300 including a circuit. The cell array region 100 and the peripheral circuit region 300 are located on one semiconductor substrate 10 made of, for example, single crystal silicon.

<1-1. Configuration of Cell Array Region 100>
FIG. 1 representatively shows one memory cell MC and one select transistor ST arranged in the cell array region 100. In the cell array region 100, a large number of combinations of such memory cells MC and selection transistors ST are arranged.

  The selection transistor ST is located in the first region 11 located on the first surface of the semiconductor substrate 10. The memory cell MC is located in the second region 12 located on the first surface of the semiconductor substrate 10. The first region 11 and the second region 12 have a first conductivity type (for example, N type). Even if the first region 11 and the second region 12 are located in a part of the semiconductor substrate 10, a well (not shown) having a conductivity type opposite to that of the semiconductor substrate 10 is formed. Good.

  On the first surface of the semiconductor substrate 10, a first diffusion layer 51 of a second conductivity type (for example, P type) is located in contact with the first region 11 where the selection transistor ST is formed. Further, a second diffusion layer 52 of the second conductivity type is located in contact with the second region 12 where the memory cell MC is formed. Between the first region 11 and the second region 12, the third diffusion layer 53 of the second conductivity type is located. Element isolation insulating films 61 and 62 are located around the region where the first and second regions 11 and 12 and the first to third diffusion layers 51 to 53 are located.

A first silicon oxide film 21 is located on the first region 11 where the selection transistor ST is formed, and a first silicon nitride film 31 is located on the first silicon oxide film 21. On the top, the first gate electrode 41 made of, for example, polycrystalline silicon is located.
A second silicon oxide film 22 is located on the second region 12 where the memory cell MC is formed, a second silicon nitride film 32 is located on the second silicon oxide film 22, and a second silicon nitride film 32 is located. A third silicon oxide film 23 is located above, and a second gate electrode 42 made of, for example, polycrystalline silicon is located on the third silicon oxide film 23.
In the present embodiment, “up” refers to a direction toward the first surface when viewed from the surface opposite to the first surface of the semiconductor substrate 10.

  With such a structure, in the memory cell MC, it becomes possible to store electric charge in the second silicon nitride film 32 located between the second silicon oxide film 22 and the third silicon oxide film 23, and the memory cell MC Can store information. On the other hand, in the select transistor ST, since the first silicon nitride film 31 is in contact with the first gate electrode 41, even if charges are stored in the first silicon nitride film 31, the charges are directed toward the first gate electrode 41. And get out. In order to make it easier for the charge to escape from the first silicon nitride film 31, the thickness of the first silicon nitride film 31 is preferably 100 angstroms or less. The second silicon nitride film 32 may have the same thickness.

The first gate electrode 41 included in the selection transistor ST is connected to, for example, a first word selection line (not shown). The second gate electrode 42 included in the memory cell MC is connected to, for example, a second word selection line (not shown).
The first diffusion layer 51 is connected to, for example, a bit selection line (not shown). The second diffusion layer 52 is connected to a source line (not shown) having a constant potential, for example.

<1-2. Operation of Cell Array Region 100>
When the potential V1 is applied to the first gate electrode 41 by the first word selection line and the potential V2 is applied to the second gate electrode 42 by the second word selection line, these potentials are respectively When the threshold voltage is higher than the threshold voltage of the selection transistor ST and the memory cell MC, channels are formed in the first region 11 and the second region 12, respectively. At this time, when a potential different from the potential of the source line is applied to the bit selection line, a current flows between the first diffusion layer 51 and the second diffusion layer 52.

  In the semiconductor memory device according to the present embodiment, the threshold voltage of the memory cell MC changes between when the charge is stored in the second silicon nitride film 32 of the memory cell MC and when the charge is erased. Therefore, for example, when the threshold voltage of the memory cell MC changes between Vta and Vtb (where Vta <Vtb), the potential V2 applied to the second gate electrode 42 by the second word selection line is set to Vta < A range of V2 <Vtb is set.

  As a result, the current flowing between the first diffusion layer 51 and the second diffusion layer 52 is turned ON or OFF depending on whether charges are stored in the second silicon nitride film 32 and when the charges are erased. Therefore, the information stored in the memory cell MC can be read. In such a read operation, the potential applied through the first word selection line, the second word selection line, and the bit selection line need not be very high.

  On the other hand, in the operation of storing charges in the second silicon nitride film 32 of the memory cell MC and the operation of erasing these charges, for example, a high potential may be applied to the second gate electrode 42. For example, when the potential V1 is applied to the first gate electrode 41 to form a channel in the first region 11 and the potential V3 is applied to the second gate electrode 42, the absolute value of the potential V3 is the potential V1. There is a method in which the charge passing through the channel formed in the second region 12 is used as a hot carrier and the charge is drawn into the second silicon nitride film 32 by setting the potential sufficiently higher than the absolute value of. Alternatively, when the potential applied to the first gate electrode 41 is changed so that no channel is formed in the first region 11 and the potential V4 is applied to the second gate electrode 42, the potential V4 and the potential of the source line There is a method of drawing a charge from the second region 12 or the second gate electrode 42 to the second silicon nitride film 32 or drawing a charge of the second silicon nitride film 32 by making the difference of the potential sufficiently high. In either method, a high potential may be applied to the second gate electrode 42 in some cases.

<1-3. Peripheral circuit region 300>
In order to enable the operation of the cell array region 100 as described above, a high breakdown voltage transistor HV and a low breakdown voltage transistor LV are arranged in the peripheral circuit region 300 as transistors for applying a potential to the memory cell MC and the selection transistor ST. Has been. FIG. 1 representatively shows only one high voltage transistor HV and one low voltage transistor LV.

  The high breakdown voltage transistor HV is located in the third region 13 located on the first surface of the semiconductor substrate 10. The low breakdown voltage transistor LV is located in the fourth region 14 located on the first surface of the semiconductor substrate 10. The third region 13 and the fourth region 14 may be the same conductivity type as the first conductivity type, or may be the opposite conductivity type. Even if the third region 13 or the fourth region 14 is located in a part of the semiconductor substrate 10, a well (not shown) having a conductivity type opposite to that of the semiconductor substrate 10 is formed. Good.

Conductivity opposite to the conductivity type of the third region 13 on the first surface of the semiconductor substrate 10 is in contact with the third region 13 where the high voltage transistor HV is formed and on both sides of the third region 13 in plan view. A fourth diffusion layer 54 and a fifth diffusion layer 55 of the mold are located. Element isolation insulating films 63 and 64 are located around the region where the third region 13 and the fourth and fifth diffusion layers 54 and 55 are located. In the present embodiment, “plan view” refers to a state viewed from above the first surface in a direction perpendicular to the first surface.
Further, in contact with the fourth region 14 where the low breakdown voltage transistor LV is formed and on both sides of the fourth region 14 in plan view, a sixth diffusion layer 56 of a conductivity type opposite to the conductivity type of the fourth region 14 and The seventh diffusion layer 57 is located. Element isolation insulating films 65 and 66 are located around the region where the fourth region 14 and the sixth and seventh diffusion layers 56 and 57 are located.

A fifth silicon oxide film 25 is located on the third region 13 where the high voltage transistor HV is formed, and a third gate electrode 43 is located on the fifth silicon oxide film 25.
A seventh silicon oxide film 27 is located on the fourth region 14 where the low breakdown voltage transistor LV is formed, and a fourth gate electrode 44 is located on the seventh silicon oxide film 27.

  The fifth silicon oxide film 25 is thicker than the seventh silicon oxide film 27. Thereby, the high breakdown voltage transistor HV can supply a relatively high potential to the cell array region 100. On the other hand, the low breakdown voltage transistor LV can operate at high speed because the film thickness of the seventh silicon oxide film 27 is small. For example, information stored in the cell array region 100 can be read out at high speed.

<2. Manufacturing method>
2 to 4 are cross-sectional views showing manufacturing steps of the semiconductor memory device shown in FIG. As shown in FIG. 2A, first, regions where the first and second regions 11 and 12 and the first to third diffusion layers 51 to 53 are formed on the first surface of the semiconductor substrate 10. Element isolation insulating films 61 and 62 located around the element region, element isolation insulating films 63 and 64 located around the third region 13 and the region where the fourth and fifth diffusion layers 54 and 55 are formed, The fourth region 14 and element isolation insulating films 65 and 66 located around the regions where the sixth and seventh diffusion layers 56 and 57 are formed are formed, respectively, and a sacrificial oxide film of about 130 Å is formed. 80 is formed.

Next, as shown in FIG. 2B, a portion of the sacrificial oxide film 80 located on the cell array region 100 is removed.
Next, as shown in FIG. 2C, a silicon oxide film 20a is formed on the cell array region 100 from which the sacrificial oxide film 80 has been removed. The silicon oxide film 20 a includes a first silicon oxide film 21 on the first region 11 and a second silicon oxide film 22 on the second region 12.

  At this time, there may be no boundary between the first silicon oxide film 21 and the second silicon oxide film 22, and the first silicon oxide film 21 and the second silicon oxide film 22 may be connected. The film thicknesses of the first silicon oxide film 21 and the second silicon oxide film 22 are, for example, about 40 angstroms.

  Next, as illustrated in FIG. 3D, the silicon nitride film 30 and the silicon oxide film 20 b are formed on the entire first surface of the semiconductor substrate 10. The silicon nitride film 30 includes a first silicon nitride film 31 located on the first silicon oxide film 21 on the first region 11 and a second silicon oxide film 22 located on the second region 12. And a silicon nitride film 32. The silicon oxide film 20 b includes a third silicon oxide film 23 located on the second silicon nitride film 32 and a fourth silicon oxide film 24 located on the first silicon nitride film 31.

  At this time, there may be no boundary between the first silicon nitride film 31 and the second silicon nitride film 32, and the first silicon nitride film 31 and the second silicon nitride film 32 may be connected. Further, there may be no boundary between the third silicon oxide film 23 and the fourth silicon oxide film 24, and the third silicon oxide film 23 and the fourth silicon oxide film 24 may be connected. The film thicknesses of the first silicon nitride film 31 and the second silicon nitride film 32 are, for example, about 45 angstroms. The film thicknesses of the third silicon oxide film 23 and the fourth silicon oxide film 24 are, for example, about 85 angstroms.

  As described above, the first silicon oxide film 21 and the second silicon oxide film 22 are formed simultaneously, and the first silicon nitride film 31 and the second silicon nitride film 32 are formed simultaneously. The difference in film thickness with the second silicon oxide film 22 and the difference in film thickness between the first silicon nitride film 31 and the second silicon nitride film 32 are small and become substantially the same film thickness. For example, the difference in film thickness between the first silicon oxide film 21 and the second silicon oxide film 22 and the difference in film thickness between the first silicon nitride film 31 and the second silicon nitride film 32 are determined by the second silicon oxide film. It may be smaller than the difference in film thickness between 22 and the third silicon oxide film 23.

Next, as shown in FIG. 3E, portions of the silicon oxide film 20b and the silicon nitride film 30 formed in FIG. 3D that are located on the peripheral circuit region 300 are dry-etched. Remove.
Next, as shown in FIG. 3F, a portion of the sacrificial oxide film 80 formed in FIG. 2A located on the peripheral circuit region 300 is removed by wet etching.

  Next, as shown in FIG. 4G, a silicon oxide film 20c is formed on the peripheral circuit region 300 from which the sacrificial oxide film 80 has been removed. The silicon oxide film 20 c includes a fifth silicon oxide film 25 located on the third region 13 and a sixth silicon oxide film 26 located on the fourth region 14. The film thicknesses of the fifth silicon oxide film 25 and the sixth silicon oxide film 26 are, for example, about 105 angstroms at this stage. Note that the thickness of the third silicon oxide film 23 and the fourth silicon oxide film 24 may be reduced to about 55 angstroms, for example, during cleaning before the formation of the silicon oxide film 20c.

  Next, as shown in FIG. 4H, the sixth silicon oxide film 26 and the fourth silicon oxide film 24 are simultaneously removed by wet etching. In the etching of the fourth silicon oxide film 24, since the first silicon nitride film 31 serves as an etching stopper, the thickness of the gate insulating film of the select transistor ST can be obtained with high accuracy. Further, since it is not necessary to etch the first silicon nitride film 31, it is not necessary to increase the space margin of the memory cell MC and the select transistor ST in consideration of the processing accuracy of the silicon nitride film, and the area of the semiconductor memory device is reduced. can do.

  Next, as shown in FIG. 4I, a seventh silicon oxide film 27 is formed on the fourth region 14 from which the sixth silicon oxide film 26 has been removed. The film thickness of the seventh silicon oxide film 27 is, eg, about 35 angstroms. At this time, the thickness of the fifth silicon oxide film 25 may be increased to about 120 angstroms. Further, at the time of cleaning before the seventh silicon oxide film 27 is formed, the film thickness of the third silicon oxide film 23 may be reduced to, for example, about 45 angstroms.

Next, as shown in FIG. 5J, a polycrystalline silicon film 40 is formed over the entire first surface of the semiconductor substrate 10.
Next, as shown in FIG. 5K, the first to fourth gate electrodes are removed by leaving the portions of the polycrystalline silicon film 40 above the first to fourth regions 11-14. 41 to 44 are formed.

  Next, as shown in FIG. 5L, the first, second, third, fifth, and seventh silicon oxide films 21, 22, and 23 are used with the first to fourth gate electrodes 41 to 44 as masks. , 25 and 27 and the first and second silicon nitride films 31 and 32 are etched to form gate insulating films of the select transistor ST, the memory cell MC, the high breakdown voltage transistor HV, and the low breakdown voltage transistor LV.

  Thereafter, for example, as shown in FIG. 1, the first to seventh diffusion layers 51 to 57 are formed by implanting impurities of the second conductivity type into a part of the semiconductor substrate 10, and other processes not shown in the figure. I do. Thereby, the semiconductor memory device according to this embodiment is manufactured.

  HV ... High breakdown voltage transistor, LV ... Low breakdown voltage transistor, MC ... Memory cell, ST ... Select transistor, 10 ... Semiconductor substrate, 11 ... First region, 12 ... Second region, 13 ... Third region, 14 ... Fourth region , 21 ... 1st silicon oxide film, 22 ... 2nd silicon oxide film, 23 ... 3rd silicon oxide film, 24 ... 4th silicon oxide film, 25 ... 5th silicon oxide film, 26 ... 6th silicon oxide film, 27 ... 7th silicon oxide film, 31 ... 1st silicon nitride film, 32 ... 2nd silicon nitride film, 40 ... Polycrystalline silicon film, 41 ... 1st gate electrode, 42 ... 2nd gate electrode, 43 ... 3rd gate electrode 44 ... 4th gate electrode, 51 ... 1st diffused layer, 52 ... 2nd diffused layer, 53 ... 3rd diffused layer, 54 ... 4th diffused layer, 55 ... 5th diffused layer, 56 ... 6th diffused layer, 57: Seventh diffusion layer, 61-66 Isolation insulating film, 80 ... sacrificial oxide film, 100 ... cell array region, 300 ... peripheral circuit region.

Claims (6)

Forming a first silicon oxide film on the first region of the semiconductor substrate and forming a second silicon oxide film on the second region of the semiconductor substrate;
Forming a first silicon nitride film on the first silicon oxide film, and forming a second silicon nitride film on the second silicon oxide film;
Forming a third silicon oxide film on the second silicon nitride film and forming a fourth silicon oxide film on the first silicon nitride film;
Removing the fourth silicon oxide film;
Forming a first gate electrode on the first silicon nitride film from which the fourth silicon oxide film has been removed, and forming a second gate electrode on the third silicon oxide film;
A method for manufacturing a semiconductor memory device comprising: In claim 1,
Forming a fifth silicon oxide film on the third region of the semiconductor substrate and forming a sixth silicon oxide film on the fourth region of the semiconductor substrate;
Removing the sixth silicon oxide film;
Forming a seventh silicon oxide film on the fourth region from which the sixth silicon oxide film has been removed;
Forming a third gate electrode on the fifth silicon oxide film and forming a fourth gate electrode on the seventh silicon oxide film;
Further comprising
A method of manufacturing a semiconductor memory device, wherein the step of removing the fourth silicon oxide film and the step of removing the sixth silicon oxide film are simultaneously performed. In claim 2,
The film thickness of the fifth silicon oxide film is greater than the sum of the film thickness of the first silicon oxide film and the film thickness of the first silicon nitride film; and
A method of manufacturing a semiconductor memory device, wherein the total thickness of the first silicon oxide film and the first silicon nitride film is larger than the thickness of the seventh silicon oxide film. A semiconductor substrate including a first region and a second region of the first conductivity type;
A first silicon oxide film located on the first region;
A first silicon nitride film located on the first silicon oxide film;
A first gate electrode located on the first silicon nitride film;
A second silicon oxide film located on the second region;
A second silicon nitride film located on the second silicon oxide film;
A third silicon oxide film located on the second silicon nitride film;
A second gate electrode located on the third silicon oxide film;
A semiconductor memory device. In claim 4,
The difference in film thickness between the first silicon oxide film and the second silicon oxide film and the difference in film thickness between the first silicon nitride film and the second silicon nitride film are different from those in the second silicon oxide film. A semiconductor memory device having a thickness smaller than that of the third silicon oxide film. In claim 4 or claim 5,
A semiconductor memory device, wherein the first silicon nitride film has a thickness of 100 angstroms or less.

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