JP2015099054A - Overlay measuring method and measuring apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable simple and robust overlay measurement in a region where an actual device circuit pattern is formed in the manufacturing of a semiconductor device.SOLUTION: A method of measuring an overlay among a plurality of exposure processes for a semiconductor device in which a circuit pattern is formed by the plurality of exposure processes, includes: picking up a measurement image at a designated measurement coordinate position of the semiconductor device; reading an image library in which a plurality of template images corresponding to the circuit pattern formed at the designated measurement coordinate position of the semiconductor device and an overlay linked to each of the plurality of template images are stored in advance; calculating a similarity between each of the plurality of template images included in the read image library and the measurement image; and measuring an overlay in the measurement image on the basis of the calculated similarity between each of the plurality of template images and the measurement image.

Description

  The present invention relates to a method and apparatus for measuring an overlay generated during manufacture of a semiconductor wafer, and more particularly to a method and apparatus for measuring an overlay using an image captured using a charged particle microscope. is there.

  In general, a semiconductor product requires a plurality of exposure steps in order to form a circuit pattern necessary for operation. For example, in the manufacture of a semiconductor product composed of a plurality of circuit patterns, an exposure process for forming holes connecting the layers is required in addition to an exposure process for forming circuit patterns of the layers. In recent years, double patterning has been performed to form fine circuit patterns with high density.

  In semiconductor manufacturing, it is important to adjust the position of a circuit pattern formed by a plurality of exposure processes within an allowable range. If it does not fall within the allowable range, appropriate electrical characteristics cannot be obtained and the yield decreases. Therefore, a circuit pattern misalignment amount (overlay) between exposures is measured and fed back to the exposure apparatus.

  As a method for performing overlay measurement, there is a method in which a circuit pattern for measurement is formed on a wafer, an image of the pattern for measurement is captured using an optical microscope, and overlay measurement is performed from a signal waveform obtained from the image. 1. Since the measurement pattern needs to have a size of about several tens of μm, it is generally formed on a scribe line around the semiconductor die. Therefore, it is not possible to directly measure an overlay at a place where a circuit pattern (actual pattern) of an actual device is formed, and it is necessary to estimate by an interpolation or the like. However, with the recent miniaturization of semiconductor processes, the allowable range of overlay has also been reduced, making it difficult to obtain the required measurement accuracy.

  Patent Document 2, Patent Document 3, Patent Document 4, and Non-Patent Document 1 describe a method of capturing an image of a real pattern using a scanning electron microscope and measuring an overlay. Patent Documents 2 and 3 describe a method of measuring an overlay by comparing contour information of a circuit pattern extracted from a captured image with design information (CAD data) of a measurement target sample. Patent Document 4 calculates a relative position between a circuit pattern formed by the first exposure and a circuit pattern formed by the second exposure, and compares the relative position with a reference value obtained from CAD data. A method for measuring the overlay is described. Non-Patent Document 1 describes a method of measuring an overlay by individually recognizing each circuit pattern region formed by a plurality of exposure steps and individually quantifying the amount of positional deviation from a non-defective image. Has been.

U.S. Pat. No. 7,181,57 JP 2006-351888 A JP 2012-112974 A JP 2011-142321 A

Jaehyoung Oh, et al., "In-die overlay metrology method using defect review SEM images", Proc. Of SPIE Vol.8681, 868111, 2013

  The present invention enables overlay measurement on an actual pattern.

  4A to 4C are schematic diagrams illustrating an example of an actual pattern that is an overlay measurement target. A layout image 401 in FIG. 4A represents actual pattern design information in one region of the sample, and shows the layout of the pattern 402 formed by the first exposure and the pattern 403 formed by the second exposure. Yes. 4B are schematic diagrams of SEM images obtained by capturing circuit patterns. A cross section 407 in FIG. 4C is a diagram showing a cross sectional shape of the image 406 in FIG. 4B along the line AB, and is formed by the layer 408, the pattern 409 formed by the first exposure, and the second exposure. The vertical relationship of the pattern 410 is shown. 4C is a diagram showing a cross-sectional shape along line CD of the image 411 in FIG. 4B, and has a cross-sectional shape similar to that of the cross-section 407, but a pattern 412 formed by the second exposure is shown in FIG. This represents a case where the pattern 413 formed by the first exposure is formed by being shifted by dx (414) in the x direction.

  As a simple overlay measurement method, there is a method of measuring an edge distance between circuit patterns formed in each exposure process and measuring an overlay based on the distance between edges.

  In the case shown in FIG. 4A, the overlay dx can be calculated by (Equation 1) if the left edge distance 404 (dL) and the right edge distance 405 (dR) can be measured (the x direction). The same applies to the y direction. However, in practice, in the captured image 406 of FIG. 4B, a part of the pattern 4021 formed by the first exposure is shielded by the pattern 4031 formed by the second exposure, and therefore the distance between the edges can be calculated. It becomes impossible.

他の方法としては、前述のとおり前記特許文献２、特許文献３、特許文献４および非特許文献１に実パターンを撮像した画像を用いてオーバーレイを計測する手法が記載されている。

As another method, as described above, Patent Document 2, Patent Document 3, Patent Document 4, and Non-Patent Document 1 describe a method of measuring an overlay using an image obtained by capturing an actual pattern.

  The overlay measurement methods described in Patent Document 2 and Patent Document 3 measure the overlay by extracting circuit pattern outline information from the captured image and measuring the amount of positional deviation from the design information (CAD data) of the sample. Yes. For this reason, when it is difficult to stably extract the contour information, such as when the boundary of the circuit pattern is unclear, the measurement stability is lowered.

  In addition, the overlay measurement described in Patent Document 4 calculates the relative position of the circuit pattern, and the measurement stability decreases when a part of the circuit pattern disappears due to a defective formation of the circuit pattern.

  In addition, the overlay measurement described in Non-Patent Document 1 recognizes a circuit pattern area based on grayscale information from a captured image. As described above, the circuit pattern boundary is unclear or the grayscale contrast is low. In some cases, measurement stability is reduced.

  As described above, there are cases where it is difficult to stably measure the overlay in the prior art. Accordingly, the present invention provides a method and apparatus for measuring overlay with stability and high accuracy.

In order to solve the above problems, in the present invention,
Imaging a measurement image at a designated measurement coordinate position of a semiconductor device in a method of measuring an overlay between the exposure processes for a semiconductor device having a circuit pattern formed by a plurality of exposure processes; and a semiconductor Reading a plurality of template images corresponding to a circuit pattern formed at a designated measurement coordinate position of the device, an image library stored in advance by linking each of the plurality of template images with an overlay, A step of calculating the similarity between each of the plurality of template images included in the read image library and the measurement image, and an overlay on the measurement image based on the similarity between each of the calculated template images and the measurement image With steps to measure It was to be measured.

  In order to solve the above problems, in the present invention, an apparatus for measuring an overlay between a plurality of exposure processes is specified for a semiconductor device on which a circuit pattern is formed by a plurality of exposure processes. Means for capturing a measurement image at the measured measurement coordinate position, a plurality of template images corresponding to a circuit pattern formed at a designated measurement coordinate position of the semiconductor device, and an overlay of each of the plurality of template images , And storing as an image library, a means for calculating the similarity between a plurality of template images included in the image library stored in the storing means and a measurement image obtained by imaging means, Based on the similarity to the plurality of template images calculated by the calculating means, Constructed by a means for measuring the ray.

  According to the present invention, it is possible to provide a method and apparatus for measuring an overlay on an actual pattern stably and with high accuracy even when the boundary of a circuit pattern is unclear in a captured image or when the contrast is low. .

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a block diagram of an overlay measurement apparatus. It is a block diagram of the control part of a overlay measuring device, a memory | storage part, and a calculating part. It is a graph showing a chip coordinate system. It is a graph showing a wafer coordinate system. It is a top view of the real pattern showing the design information of the real pattern. It is a schematic diagram of the SEM image of a circuit pattern. It is sectional drawing which shows the AB cross section and CD cross section of a SEM image. It is a SEM image and AB sectional drawing of an overlay measurement object. It is the SEM image of overlay measurement object, and CD sectional drawing. It is the SEM image and EF sectional drawing of an overlay measurement object. It is the SEM image of overlay measurement object, and GH sectional drawing. It is a flowchart of an overlay measurement process. It is a block diagram showing the structure of the calculating part concerning an overlay measurement process. It is a flowchart of the process which images the image of the designated measurement coordinate on a wafer. It is a graph which shows the result of having calculated the distribution of similarity with respect to each template image. It is a top view of the pattern which shows the example of a setting of a region of interest. It is a flowchart of the process which sets a region of interest. It is a top view of the pattern explaining the necessity to expand a region of interest. It is a flowchart which calculates the overlay of a measurement image from the overlay calculated about each region of interest. It is a flowchart of the creation process of the image library using design information. It is a flowchart of the creation process of the image library using design information. It is the figure which showed the data structure of the image library in tabular form. It is a front view of the screen showing an example of the interface which designates a measurement coordinate. It is a front view of the screen showing an example of the interface which designates measurement conditions. It is a front view of the screen showing an example of the interface which displays a measurement result. It is a front view of the screen showing an example of the interface which designates the creation conditions of an image library. It is a top view of the wafer showing the example of the overlay creation conditions at the time of creating the wafer concerning creation of an image library. It is a flowchart of the process which produces an image library based on the wafer which created the overlay intentionally. It is a flowchart of the process which sets the region of interest in a measurement image based on the region of interest designated on the reference image by the user. It is a front view of the screen showing an example of the interface for a user to set a region of interest on a reference image.

  The present invention relates to an overlay measurement method and a measurement apparatus, which captures a measurement coordinate position of a sample to obtain a measurement image, and calculates a similarity between each template image and the measurement image included in an image library stored by linking the overlay and the image. The overlay is measured in a stable and highly accurate manner by measuring the overlay in the measurement image based on the similarity to each template image.

  Hereinafter, embodiments of an overlay measuring apparatus according to the present invention will be described with reference to the drawings.

  In this embodiment, a case where overlay measurement is performed using an image captured by an imaging apparatus equipped with a scanning electron microscope (SEM) will be described. However, the imaging apparatus according to the present invention may be other than SEM, such as ions. An imaging device using a charged particle beam may be used.

  FIG. 1 illustrates a configuration diagram of an overlay measurement apparatus 100 according to the present embodiment. An SEM 101 that captures an image, a control unit 102 that performs overall control, and a storage unit that stores information in a magnetic disk, a semiconductor memory, or the like. 103, a calculation unit 104 that performs calculation according to a program, an external storage medium input / output unit 105 that inputs / outputs information to / from an external storage medium connected to the apparatus, and a user interface unit 106 that controls input / output of information to / from a user The network interface unit 107 communicates with other devices via the network. The user interface unit 106 is connected to an input / output terminal 113 including a keyboard, a mouse, a display, and the like.

  The SEM 101 detects a movable stage 109 on which the sample wafer 108 is mounted, an electron source 110 for irradiating the sample wafer 108 with an electron beam, and secondary electrons and reflected electrons generated from the sample wafer 108 irradiated with the electron beam. In addition to the detector 111, an electron lens (not shown) for converging the electron beam onto the sample, a deflector (not shown) for scanning the electron beam on the sample wafer, and a signal from the detector 111 are digitalized. An image generating unit 112 that converts and generates a digital image is provided. These are connected via the bus 114 and can exchange information with each other.

  FIG. 2 shows detailed configurations of the control unit 102, the storage unit 103, and the calculation unit 104. The control unit 102 controls the wafer transfer control unit 201 that controls the transfer of the sample wafer 108, the stage control unit 202 that controls the movable stage 109, and the irradiation position on the sample wafer 108 of the electron beam emitted from the electron source 110. A beam shift control unit 203 and a beam scan control unit 204 that controls scanning of the electron beam emitted from the electron source 110 on the sample wafer 108 are provided.

  The storage unit 103 stores secondary image data and reflected electrons generated from the sample wafer 108 irradiated with the electron beam by the detector 111 and stores image data digitally converted by the image generation unit 112. , A recipe storage unit 206 that stores imaging conditions (for example, acceleration voltage, probe current, number of added frames, imaging field size, etc.) and processing parameters, and a measurement coordinate storage unit that stores coordinates of a location to be measured on the sample wafer 108 207, an overlay image library storage unit 208 that stores the overlay image whose overlay has been calculated by the calculation unit 104 in a library format, and an image similarity storage unit 209 that stores the similarity of the image calculated by the calculation unit 104. .

  The calculation unit 104 includes a region-of-interest setting unit 210 that sets a region of interest (ROI) from the captured image obtained by digital conversion of the output from the detector 111 by the image generation unit 112, and image similarity calculation that calculates the similarity between images. A unit 211, an overlay calculation 212 for calculating an overlay, and a similarity distribution evaluation unit 213 for evaluating the distribution of the image similarity calculated by the image similarity calculation unit 211.

  The region-of-interest setting unit 210, the image similarity calculation unit 211, and the overlay calculation unit 212 may be configured as hardware designed to perform each calculation, or may be implemented as software and used as a general-purpose calculation device (for example, It may be configured to be executed using a CPU or GPU.

Next, a method for acquiring an image of designated coordinates will be described.
First, the sample wafer 108 to be measured is placed on the stage 109 by a robot arm (not shown) under the control of the wafer transfer control unit 201. Next, the stage controller 202 sets the stage so that a desired imaging region on the sample wafer 108 set based on the design data of the sample wafer 108 is included in the beam irradiation range of the sample wafer 108 irradiated with the beam. The position of 109 is controlled. At this time, in order to absorb the movement error of the stage 109, the position of the stage 109 is measured, and a deflector (not shown) is controlled by the beam shift control unit 203 so that the movement error is canceled out on the sample wafer 108. The beam irradiation position is adjusted.

  The electron beam emitted from the electron source 110 is scanned in the imaging field by a deflector (not shown) controlled by the beam scan control unit 204. Secondary electrons and reflected electrons generated from the sample wafer 108 by the beam irradiation are detected by the detector 111 and converted into a digital image by the image generation unit 112. This digital image data is stored in the image storage unit 205 together with incidental information such as imaging conditions, imaging date and time, imaging coordinates, and the like.

  Here, the measurement coordinates which are one of the inputs of overlay measurement according to the present embodiment will be described. 3A shows the chip coordinate system on the sample wafer 108, and FIG. 3B shows the chip 301 and the wafer 302 on the sample wafer 108 in the wafer coordinate system. The chip coordinate system in FIG. 3A is a coordinate system with one point on the chip 301 as the origin, and the wafer coordinate system in FIG. 3B is a coordinate system with one point in the plane including the wafer 302 as the origin.

Usually, as shown in FIG. 3B, a plurality of chips 301 are laid out on the surface of the wafer 302. In this wafer 302, the point indicated by + in the chip at the position (u, v), the wafer coordinate (x, y) in the wafer coordinate system shown in FIG. 3B, and the chip coordinate system shown in FIG. 3A, The relationship with the chip coordinates (cx, cy) is expressed by (Equation 2), and mutual conversion can be easily performed. However, in equation (2), W, H represents a first width and height of the _chip, o x, _{o y} offset.

  By using the relationship of (Expression 2), the user may specify the chip coordinates (cx, cy) of the overlay measurement target and the measurement target chip position (u, v). That is, the chip coordinates (cx, cy) can be obtained from the designated information using the relationship of (Equation 2). For example, if n chip coordinates are specified and m measurement target chips are specified, n × m measurement coordinates are obtained.

  The overlay measurement method according to the present embodiment treats images having the same chip coordinates as one group. In order to group the images, a position ID (PID) assigned for each chip coordinate is assigned as image auxiliary information at the time of image capture (in the above example, position ID: 1 to n).

つぎに、本実施例で計測するオーバーレイについて再度、図４Ａ乃至図４Ｃを用いて説明する。図４Ａの４０１は試料の一領域における実パターンの設計情報を表したものであり、第１の露光により形成されるパターン４０２と第２の露光により形成されるパターン４０３のレイアウトを示している。また、図４Ｂの画像４０６及び画像４１１は、それぞれ回路パターンを撮像したＳＥＭ画像の模式図である。図４Ｃの断面４０７は、図４Ｂの画像４０６のラインＡ−Ｂにおける断面形状を表した図であり、層４０８と、第１の露光により形成されるパターン４０９と、第２の露光により形成されるパターン４１０の上下関係を表している。

Next, the overlay measured in the present embodiment will be described again with reference to FIGS. 4A to 4C. Reference numeral 401 in FIG. 4A represents design information of an actual pattern in one region of the sample, and shows a layout of the pattern 402 formed by the first exposure and the pattern 403 formed by the second exposure. 4B are schematic diagrams of SEM images obtained by capturing circuit patterns. A cross section 407 in FIG. 4C is a diagram showing a cross sectional shape of the image 406 in FIG. 4B along the line AB. The cross section 407 is formed by the layer 408, the pattern 409 formed by the first exposure, and the second exposure. The vertical relationship of the pattern 410 is expressed.

  A cross section 414 in FIG. 4C is a diagram showing a cross sectional shape along line CD of the image 411 in FIG. 4B, and has a cross sectional shape similar to that of the cross section 407, but a pattern 412 formed by the second exposure is This represents a case where the pattern 413 formed by the first exposure is formed by being shifted by dx (414) in the x direction.

  In the method according to the present embodiment, a measurement image (for example, the SEM image 406 in FIG. 4B) and each template image (for example, the layout image 401 in FIG. 4A) included in the image library in which the overlay and the image are linked and stored are stored. The similarity is calculated, and the overlay in the image to be measured is measured based on the similarity with each template image.

  The overlay may measure the shift amount of the pattern formed by the second exposure based on the pattern formed by the first exposure, or may be measured based on the pattern formed by the second exposure. The amount of deviation of the pattern formed by this exposure may be measured. When reversed, the magnitude of the shift amount does not change, but the sign of the calculated value is inverted. The n-th exposure here is not limited to the n-th exposure but is simply an index representing a difference in the exposure process. The “pattern formed by exposure” is not limited to the circuit pattern formed only by the exposure process, and indicates a circuit pattern formed including an etching process after the exposure process.

  5A to 5D show other examples of overlay measurement targets. Images 501 to 504 in FIGS. 5A to 5D schematically represent SEM images and cross-sectional structures. FIG. 5A shows an image 501 and a cross-sectional view taken along line AB of the image 501 below the image 501. The configuration in this sectional view shows a state in which a film 511 and a circuit pattern 512 formed by the second exposure are stacked on the circuit pattern 510 formed on the lower layer film or the wafer 513 by the first exposure. Represents. Thus, even when the film is laminated on the circuit pattern formed by the first exposure, the shape of the circuit pattern 510 formed by the first exposure is observed by adjusting the acceleration voltage of the SEM. It is possible. However, the boundary portion of the circuit pattern 510 formed by the first exposure is often unclear due to electron scattering inside the film.

  FIG. 5B shows an image 502 and a cross-sectional view taken along line CD of the image 502 below the image 502. The structure in this cross-sectional view represents an image of the hole process, and is formed in the lower layer film 523 by the first exposure from the opening 521 of the circuit pattern 520 formed on the lower layer film 523 by the second exposure. The state in which the circuit pattern 522 is observed is shown. When the aspect ratio of the opening 521 is high, electrons generated from the hole bottom 5212 are shielded by the opening side wall 5211, and the contrast of the pattern 522 formed by the first exposure may be lowered.

  FIG. 5C shows an image 503 and a cross-sectional view taken along line EF of the image 503 below the image 503. The configuration in this cross-sectional view shows a state in which the wiring 531 and the hole 532 are formed in the insulating film 534 on the lower layer film 533 by the first and second exposures, respectively.

  FIG. 5D shows an image 504 and a cross-sectional view taken along line GH of the image 504 on the lower side. The configuration in this sectional view shows circuit patterns 541 and 542 formed by double patterning on the lower layer film or wafer 543. Double patterning is a technique for forming a circuit pattern with high density by forming a circuit pattern 541 by first exposure and forming a circuit pattern 542 by second exposure.

  As shown in the image 503 in FIG. 5C and its cross-sectional view, and the image 504 in FIG. 5D and its cross-sectional view, when the patterns formed by the first and second exposures are the same layer, separation by image shading is difficult. Thus, with the method described in Non-Patent Document 1, it becomes difficult to individually recognize the circuit pattern regions formed by the first and second exposures.

  In either case, overlay measurement of the circuit pattern formed by the first exposure and the circuit pattern formed by the second exposure is important. The circuit pattern structure that enables overlay measurement according to the present embodiment is not limited to these. For example, in an image in which a pattern formed by a total of three exposures is observed, overlay between each exposure can be measured.

  FIG. 6 is a flowchart of overlay measurement according to the present embodiment, and FIG. 7 is a configuration diagram of the calculation unit 104 related to overlay measurement. In the overlay measurement flow shown in FIG. 6, first, the measurement location is read from the measurement coordinate storage unit 207, and the SEM 101 is controlled by the control unit 102 according to the recipe stored in the recipe storage unit 206. An image of the measurement location (measurement image) is acquired (S601). The acquired image is sequentially stored in the image storage unit 205 together with the accompanying information.

  After the measurement image of the sample wafer 108 is acquired by the SEM 101, an image having the same position ID is extracted in order to perform processing for each position ID (S602). Note that the processing order for each position ID may be set arbitrarily, or only the image of the position ID specified by the user may be processed. Since the extracted images have the same chip coordinates, circuit patterns that have essentially the same shape are captured.

  Next, an overlay image library corresponding to the position ID is read from the overlay image library storage unit 208 (S603). The overlay image library is a library in which a plurality (N) of template images with known overlays are stored, and is prepared by a method described later prior to measurement. Next, the region of interest (ROI) used for overlay calculation is extracted from the measurement image by the region of interest extraction unit 210 (S604).

  After ROI extraction, the i-th ROI image cutout unit 2101 cuts out the i-th ROI image (S6051), the j-th template image reading unit 2102 reads in the j-th template image (S6052), and the image similarity calculation unit 211 Then, the similarity between the i-th ROI and the j-th template image is calculated (S605) and stored in the image similarity storage unit 209.

  After completion of similarity calculation for a plurality of templates included in the overlay image library for the i-th ROI, the similarity distribution evaluation unit 213 evaluates the distribution of similarity calculated for the i-th ROI, and overlays in the ROI Is calculated (S606).

  As described above, the similarity calculation S605 and the similarity distribution evaluation S606 are repeatedly processed for a plurality of ROIs extracted in S604. Based on the overlay calculated in each ROI, the overlay calculation unit 212 calculates the overlay in the measurement image (S607).

  The processing of S604 to S607 described above is a processing flow for one measurement image of the sample wafer 108 acquired by the SEM 101. The above processing is repeatedly performed for all measurement images of the sample wafer 108 acquired by the SEM 101 (S608), and overlays are calculated for all position IDs (, S609).

  Thereafter, the process of acquiring the measurement image (S601), the process of evaluating the similarity distribution (S606), the process of extracting the ROI from the measurement image (S604), and the process of calculating the similarity between the ROI and the template image (S605). Details will be described in the order of the process of calculating the overlay of the measurement image (S607).

  A detailed flow of the process (S601) for acquiring the measurement image will be described with reference to FIG. First, the sample wafer 108 to be measured is loaded on the stage 109 of the SEM 101 (S801), and the control unit 102 reads a recipe corresponding to the sample wafer 108 from the recipe storage unit 206 (S802). Next, the control unit 102 reads imaging coordinates from the measurement coordinate storage unit 207 (S803).

  After reading the imaging coordinates (or in parallel), wafer alignment is performed (S804). Wafer alignment is a process in which a circuit pattern with a known wafer coordinate is imaged by the SEM 101, the position of this circuit pattern is detected, and a deviation between the stage coordinate of the overlay measuring apparatus 100 and the wafer coordinate is corrected.

  After the wafer alignment, the SEM 101 is controlled by the above-described method, and an image of the sample wafer 108 at the read image pickup coordinate position is taken (S805). At this time, imaging conditions, imaging date / time, imaging coordinates, position ID, and the like are attached to the captured image as supplementary information and stored in the image storage unit 205. It repeats until imaging is completed for all imaging coordinates on the sample wafer 108 (S806), and finally the wafer is unloaded (S807).

  Next, details of the process (S606) for evaluating the similarity distribution executed by the similarity distribution evaluation unit 213 will be described. In this process, an overlay that maximizes the similarity is calculated based on the similarity distribution obtained as a result of calculating the similarity between the ROI and the plurality of template images by the image similarity calculation unit 211 in the previous step S605. FIG. 9 shows an example of the similarity distribution. The horizontal axis represents the index of the template image, and the vertical axis represents the similarity with the ROI. Since an overlay is associated with each template image, the horizontal axis can be converted into an overlay value, and the overlay calculation unit 212 calculates the value of the horizontal axis that maximizes the degree of similarity. The overlay at can be calculated.

  At this time, if a large number of template images in which the overlay value is slightly changed are prepared, the calculation accuracy can be improved. However, there is a trade-off that the processing time for calculating the similarity distribution in the image similarity calculation unit 211 increases. Therefore, an overlay is calculated with high accuracy from a small number of template images by interpolating the similarity distribution calculated by the image similarity calculation unit 211 by the distribution interpolation unit 2131. As a method of interpolating the similarity distribution, a parametric model (for example, a polynomial such as a quadratic function or a Gaussian distribution) may be applied using a least square method or may be calculated by applying a spline curve or the like. . In addition, a general curve fitting method may be used.

  In the overlay calculation unit 212, the overlay in the ROI is calculated from the value on the horizontal axis that maximizes the similarity in the distribution of similarity after interpolation by the distribution interpolation unit 2131. In this process, the reliability of the distribution is calculated. When an extraction failure occurs in the previous ROI extraction process described later, or when the overlay in the target ROI exceeds the overlay range stored in the overlay image library storage unit 207, the correct overlay is calculated. I can't. Therefore, in this process, the reliability calculation unit 2132 calculates the reliability of the overlay calculated based on the shape of the similarity distribution.

  As a simple method of calculating the reliability in the reliability calculation unit 2132, the maximum value of the similarity may be used, or the difference between the maximum value and the minimum value of the similarity may be evaluated. Otherwise, it may be calculated based on the error when the model is applied, or the unimodality of the distribution may be evaluated. A plurality of reliability evaluation values may be calculated and integrated. The calculated reliability is used in the process of calculating the overlay of the measurement image based on the overlay calculated from one or more ROIs (S607).

  Next, the process of extracting the ROI from the measurement image (S602) in the region of interest extraction unit 210 will be described in detail. First, an outline of this process will be described with reference to FIG. An image 1001 is an example of a schematic diagram of a template image 1001 included in the overlay image library, and an image 1002 is an example of a schematic diagram of a measurement image 1002 obtained by imaging the sample wafer 108 with the SEM 101.

  This process is a process of extracting an area having the same structure as the pattern included in the template image 1001 from the field of view of the measurement image 1002 as an ROI. By imaging the measurement image 1002 over a wide field of view so as to include a plurality of ROIs, measurement at a plurality of locations can be performed at once. If the measurement results at each ROI are averaged, an average overlay in the field of view can be calculated. It becomes possible.

  In order to extract the ROI from the measurement image 1002, this process searches the measurement image for an area similar to the template image 1001 included in the overlay image library stored in the overlay image library storage unit 208.

  To calculate the similarity Sj (u, v) between the partial image having a width W × height H starting from the position (u, v) of the measurement image 1002 and the j-th template image, for example, (Equation 3) to ( A normalized cross-correlation value calculated by the equation 5) may be used. However, I represents a measurement image, Tj represents the jth template image, and W and H represent the width and height of the template image, respectively.

具体的な処理のフローを図１１に示す。まず、テンプレート画像１００１と計測画像１００２の画素サイズが同一となるようにテンプレート画像１００１または計測画像１００２もしくは両方に拡大縮小処理を適用する（Ｓ１１０１）。次に、計測画像１００２の各画素（ｕ、ｖ）を起点とした部分画像とｊ番目のテンプレート画像との類似度Ｓｊ（ｕ、ｖ）を前述の方法により算出する。ここで、計測画像１００２にはどの程度のオーバーレイが生じているかが不明であるため、オーバーレイ画像ライブラリ記憶部２０８に記憶されているオーバーレイ画像ライブラリに含まれる１つ以上テンプレート画像１００１を用いて類似度Ｓｊ（ｕ、ｖ）を算出する（ループｊ）。

A specific processing flow is shown in FIG. First, enlargement / reduction processing is applied to the template image 1001 and / or the measurement image 1002 so that the template image 1001 and the measurement image 1002 have the same pixel size (S1101). Next, the similarity Sj (u, v) between the partial image starting from each pixel (u, v) of the measurement image 1002 and the j-th template image is calculated by the method described above. Here, since it is unclear how much overlay has occurred in the measurement image 1002, the similarity is determined using one or more template images 1001 included in the overlay image library stored in the overlay image library storage unit 208. Sj (u, v) is calculated (loop j).

  Next, the similarity Sj (u, v) calculated using one or more template images 1001 is averaged to calculate an average similarity S (u, v) (S1103). Finally, (u, v) that is equal to or greater than a predetermined threshold in the average similarity S (u, v) is selected as the ROI starting point coordinate (S1104). Note that, before calculating the similarity, image processing such as a smoothing filter, an edge extraction filter, and contrast conversion may be applied as preprocessing to the measurement image and / or the template image.

  The similarity may be an evaluation value other than the normalized cross-correlation described above. For example, a local region having a characteristic shading variation may be extracted as a key point from the image, and the similarity between the key points may be evaluated. Alternatively, the image may be projected onto the feature amount space, and the distance in the feature amount space may be used as the evaluation value. The similarity may be calculated based on the degree of inconsistency such as a difference value of image density, or an area where the degree of inconsistency falls below a predetermined threshold may be extracted.

  Next, details of the processing (S605) for calculating the similarity between the ROI and the template image in the image similarity calculation unit 211 will be described. In this process, the similarity between each target ROI and each template image included in the overlay image stored in the overlay image library storage unit 208 is calculated. At this time, in order to eliminate the influence of the ROI calculation error, the size of the ROI is expanded, and the maximum value of the similarity is searched in the expanded ROI.

  FIG. 12 is a diagram showing the necessity of ROI expansion, and shows an example of setting results of the measurement image 1201 and ROI (1203). A position 1206 at which the degree of similarity with respect to the template image 1205 is higher than the starting point 1202 of the ROI (1203). This shift is caused by the overlay of the template image 1207 having a high similarity among the one or more template images used at the time of ROI calculation and the overlay of the jth template that is the comparison target in this processing. Therefore, it is necessary to expand the size of the ROI (1203) and search for the maximum value of the similarity in the expanded ROI (1204). The size to be expanded may be constant for all template images and may be set based on the overlay range included in the overlay image library.

  Note that any of the evaluation values described in the above description of the ROI calculation process may be used as the similarity calculated in this process. Further, the minimum mismatch degree may be searched using the mismatch degree such as the difference value of the image density. In this case, the distribution corresponding to the similarity distribution shown in FIG. 9 has a downwardly convex shape, and the position on the horizontal axis that minimizes the degree of mismatch may be calculated as an overlay.

  Finally, details of the process of calculating the overlay of the measurement image (S607) will be described. In this process, the overlay in the measurement image is calculated based on the overlay calculated from each ROI and its reliability. The processing flow is shown in FIG. In the drawing, “reliability [i]” represents the reliability of the overlay calculated from the i-th ROI, and “OVL [i]” represents the overlay value calculated from the i-th ROI. In this process, a weighted average with reliability as a weight is calculated for an overlay calculation result whose reliability is equal to or higher than a preset threshold value Th.

Specifically, the reliability (reliability [i]) calculated from the i-th ROI is compared with the threshold value Th (S1301), and when the threshold value is exceeded, the total weight W is updated (S1302). ), and updates the overlay sum sigma _OVL (S1303), repeats the processing for all of the ROI from S1301 to S1303, after completion, the sum of the overlay sigma _VOL the summing Wde division weight (S1304) that the weighted average Is calculated. Note that an average may be simply calculated (a weighted average with a weight of 1) for an overlay calculation result whose reliability is equal to or greater than a preset threshold Th. As described above, one overlay is calculated from one measurement image.

  The overlay measurement method using the overlay image library stored in the overlay image library storage unit 208 has been described above. Hereinafter, a method for creating an overlay image library will be described.

  The data structure of the overlay image library 1600 to be created is shown in FIG. The overlay image library 1600 includes an index 1601, a template image 1602, an overlay 1603, and a pattern size variation 1604. However, the pattern size variation 1604 is not necessarily included. A method of using the design information of the semiconductor sample in the creation processing flow of the overlay image library 1600 will be described with reference to FIG. First, design information around the measurement coordinate is cut out (S1401). The area to be cut out is not limited to the field of view of the measurement image, and an area necessary for considering charging and the like in the subsequent SEM simulation may be added. “Cut out design information” here means to extract only the information included in the target area from multiple line segment information, height information, material information, etc. included in the design information. To do.

  Next, information on the layer L1 related to the pattern formed by the first exposure in the measurement image and the layer L2 related to the pattern formed by the second exposure are extracted (S1402). The layer L1 and the layer L2 may be a combination of a plurality of layers among the layer information included in the design information.

  Next, information is generated by shifting the position of the layer L2 (coordinates in the line segment information) by (dx, dy) with respect to the layer L1 (S1403), and a simulated SEM image is generated by SEM simulation (S1404). In the SEM simulation, the electron beam trajectory from the electron gun to the sample surface and the beam profile on the sample surface are calculated based on the specified conditions, and the emission angles of secondary electrons and reflected electrons generated from the sample due to the interaction between the electron beam and the sample. And the energy are calculated by the Monte Carlo method, etc., the electron detection efficiency by which the secondary electrons and reflected electrons generated from the sample are detected by the detector is calculated, and the amplifier, A / D conversion, etc. for the detector output signal are simulated Thus, a simulated SEM image is generated.

  The simulated SEM image generated as described above is used as the template image 1602, the given shift amount (dx, dy) is used as the overlay 1603, and these are combined and stored in the overlay image library 1600 (S1405). The above process is repeated for the given overlay variation Vovl.

  The overlay image library 1600 may include pattern deformation factors other than overlay. For example, it is assumed that the pattern dimension varies during the manufacturing process. When the pattern dimension is changed in the measurement image, the similarity with the template image included in the overlay image library 1600 is lowered, and the overlay calculation accuracy is lowered. Therefore, a pseudo SEM image may be generated in consideration of variations in pattern dimensions in advance and stored in the overlay image library 1600 as pattern size variations 1604.

  FIG. 15 shows a procedure for creating an overlay image library 1600 that takes into account variations in pattern dimensions. In the processing procedure shown in FIG. 15, the process of enlarging or reducing the pattern of the layer L1 during the processing of S1402 and S1403 described with reference to FIG. 14 (the processing of S1502 and S1505 in FIG. 15) (S1503). And processing for enlarging or reducing the pattern of the layer L2 (S1504). When the layer L1 or the layer L2 includes a plurality of patterns, the pattern is enlarged or reduced around the center of gravity of each pattern so that the distance between the centers of the patterns does not change. In addition, if the overlay image library 1600 created by this processing is used, it is possible to measure the variation of the pattern dimension simultaneously with the overlay.

  Further, the layer L1 related to the pattern formed by the first exposure in the measurement image (for example, the pattern 409 in FIG. 4C) and the layer L2 related to the pattern formed by the second exposure (for example, the pattern 410 in FIG. 4C). ), The pseudo SEM images are generated independently by SEM simulation for each layer, and the weighted average of each pixel is calculated after adding a positional shift between the two pseudo SEM images. You may make it produce | generate the pseudo image which produced.

  The weight of each pixel at this time can be calculated at the time of the SEM simulation. For example, if the weight is changed in a region where a pattern is not formed based on layout information of a pattern formed by the second exposure. Good (Pattern that is not affected by the pattern formed by the second exposure is a pattern formed by the second exposure so that the shade of the pseudo SEM image relating to the pattern formed by the first exposure is observed. The weight of the pseudo SEM image is reduced).

  According to this overlay image library creation method, it is possible to reduce the time required for the SEM simulation.

  Alternatively, an image in which the user draws the appearance of the pattern formed by the first exposure and the pattern formed by the second exposure is read, and the weight of each pixel is added to the two read images after adding a positional deviation. By calculating the average, a pseudo image with an overlay may be generated. The weight of each pixel at this time may be the one specified by the user when drawing the appearance of the pattern. According to this overlay image library creation method, design information and SEM simulation are not required.

  The above is an example in which the circuit pattern formed by the first exposure and the circuit pattern formed by the second exposure are observed in the measurement image. However, the measurement image is formed by a total of three or more exposures. Even when a pattern is observed, an overlay image library can be created in the same manner.

Hereinafter, the user interface according to the present invention will be described.
An example of an interface for editing measurement coordinates is shown in FIG. In this interface 1700, an interface 1701 for displaying a list of registered chip coordinates, a button 1702 for calling an interface for registering new chip coordinates, a button 1703 for calling an interface for correcting registered chip coordinates, and registered chip coordinates A button 1704 for deleting the.

  Further, an interface 1705 for selecting a chip to be measured, an interface 1706 for displaying an image of registered measurement coordinates and related information, and an interface 1707 for displaying a list of measurement coordinates to be captured are provided. Further, a button 1709 for reading a list of previously registered measurement coordinates and a button 1710 for naming and saving the list of registered measurement coordinates are provided.

  FIG. 18 shows an example of an interface for setting overlay measurement conditions according to the present embodiment. The interface 1800 includes an interface 1801 for displaying a list of acquired images, an interface 1802 for displaying the position of a chip that has captured the image, a button 1803 for calling a library generation interface, a button 1804 for setting parameters relating to overlay measurement, and an acquired A button 1805 for applying overlay measurement processing to a series of measurement images is provided.

  An example of an interface for displaying the overlay measurement result according to the present embodiment is shown in FIG. The interface 1900 includes an interface 1901 for displaying the overlay measurement result on the wafer, an interface 1902 for displaying a histogram for the size of the overlay, and an interface 1903 for specifying the measurement result to be displayed on the wafer map or histogram. Further, an interface 1904 for selecting a measurement image to be displayed, an interface 1905 for displaying the selected measurement image and an arbitrary template image side by side, and an interface 1906 for displaying a similarity distribution for the selected measurement image are provided.

  An example of an interface for creating an overlay image library according to this embodiment is shown in FIG. This interface 2000 includes a button 2001 for designating and reading sample design information, an interface 2002 for displaying sample design information, an interface 2003 for designating SEM simulation conditions and confirming a simulated SEM image, first and second An interface 2004 for designating a layer related to a pattern formed by the second exposure, and an interface 2005 for designating variations related to pattern deformation such as overlay and pattern dimension variation are provided.

  In the interface 2002 for displaying the design information of the sample, a plurality of areas capable of displaying the layout of the circuit pattern are prepared, and layout information can be displayed at different magnifications in each area. The layout information centered on the coordinates designated by the operator may be displayed in another display area 2022 (for example, enlarged view 2). Further, in the interface 2002 for displaying design information or the interface 2003 for displaying a pseudo SEM image, an area (for example, 2006) stored in the template image library may be designated. In addition, a button 2007 for generating a pseudo SEM image for a variation related to the specified pattern deformation and registering it in the overlay image library is provided.

  As described above, according to the present embodiment, a measurement image is captured at a specified measurement coordinate, and the similarity between each template image and the measurement image included in the image library stored by linking the overlay and the image is calculated. By analyzing the distribution of similarity calculated from each template image, the overlay in the measurement image can be calculated. Therefore, unlike the method described in Patent Document 1, it is not necessary to form a dedicated pattern for overlay measurement on the wafer, and the overlay can be evaluated with an actual pattern.

  Further, according to the method described in the present embodiment, there is no need to extract the pattern contour shape from the measurement image unlike the methods described in Patent Document 2 and Patent Document 3, and the pattern contour is unclear. Can be calculated robustly and with high accuracy. Further, compared to a method of comparing relative vectors of coordinates as in the method described in Patent Document 4, the circuit pattern is robust against deformation of a circuit pattern due to defective formation. In addition, unlike the method described in Non-Patent Document 1, it is not necessary to recognize the circuit pattern area from the measurement image, so the overlay is calculated robustly even when the circuit pattern boundary is unclear or the contrast is low. It becomes possible.

  In the first embodiment, a measurement image is captured with respect to a designated measurement coordinate, the similarity between each template image and the measurement image included in the image library stored by linking the overlay and the image is calculated, and the similarity of each template image is calculated. The method of calculating the overlay in the measurement image by analyzing the change was described. In addition, as a method of creating an overlay image library, a method of generating a simulated SEM image by SEM simulation using design information has been described. In the second embodiment, as a method of creating an overlay image library, a method of capturing an image of a wafer, calculating an overlay of the captured image, and storing the captured image and the overlay in association will be described.

  The configuration of the overlay measurement apparatus according to the present embodiment is the same as the configuration illustrated in FIGS. 1 and 2 described in the first embodiment. The measurement flow is also the same as the flow described in FIG. The user interface is the same as that shown in FIGS. The difference is the method of creating an overlay image library to be stored in the overlay image library storage unit 208. Hereinafter, only the parts different from the first embodiment will be described.

  The method of the overlay image library according to the present embodiment captures an image of the sample wafer 108, calculates an overlay of the captured image, and stores the captured image and the overlay in association with each other. As a sample wafer 108 to be imaged, a wafer in which an overlay is intentionally formed can be used.

  Generally, an exposure apparatus has a function of correcting an overlay error according to wafer coordinates. Therefore, as shown in FIG. 21, correction data is created so that the overlay in the x direction and the overlay in the y direction change for each wafer coordinate, and a wafer having a desired overlay in the wafer plane is input to the exposure apparatus. It is possible to create. By using this correction data, the overlay of the captured image can be calculated from the wafer coordinates. When inputting correction data to the exposure apparatus, correction data for overlay error of the exposure apparatus may be taken into account.

  FIG. 22 shows a processing flow for creating an overlay image library using the wafer described above. First, according to the flow shown in FIG. 8, images are taken for a plurality of coordinate positions in the wafer surface (S2201). Next, the imaging coordinates are extracted from the supplementary information of the image, and the overlay is calculated by the method described in S607 of FIG. 6 of Embodiment 1 based on the imaging coordinates and the correction data created at the time of wafer creation (S2202). .

  Next, k or more images captured around the imaging coordinates are extracted (S2203), and an average image of the extracted k captured images is calculated (S2204). Generally, manufacturing tolerances such as line edge roughness and surface roughness exist in the circuit pattern, and shot images and noise due to dark current are included in the captured image. These manufacturing tolerances and noise can be a cause of a decrease in accuracy when calculating the image similarity when calculating the overlay. It is possible to reduce these manufacturing tolerances and noises by averaging k captured images around the imaging assuming that the overlay does not change locally.

  The average image created in this way is stored in the overlay image library storage unit 208 in association with the overlay calculated in S2202 (S2205). An overlay image library is created by repeatedly processing the acquired image (S2206).

  The above shows the method of using a wafer with an intentionally built overlay, but it does not have to be a wafer that has been intentionally created. The overlay is measured from the captured image by some method, and the measured image and the measured overlay are displayed. They may be linked and registered in the overlay image library.

  According to the method described above, an overlay image library can be created without using sample design information or SEM simulation.

  In the first embodiment, a measurement image is captured with respect to a designated measurement coordinate, the similarity between each template image and the measurement image included in the image library stored by linking the overlay and the image is calculated, and the similarity of each template image is calculated. The method of calculating the overlay in the measurement image by analyzing the change was described. Further, as a method for extracting the ROI from the measurement image, a method for searching the measurement image for a region similar to the template image included in the overlay image library has been described. In the third embodiment, a method for extracting an ROI in a measurement image using an ROI designated on an image serving as a reference by a user will be described.

  The configuration of the overlay measuring apparatus according to this embodiment is the same as that shown in FIGS. 1 and 2 shown in the first embodiment. Moreover, since the measurement flow is the same as that of FIG. 6, description thereof is omitted. The user interface is the same as that shown in FIGS. The difference is the processing procedure of the process of extracting the ROI from the measurement image (S604). Hereinafter, only the parts different from the first embodiment will be described.

  In the ROI extraction process from the measurement image according to the present embodiment, information stored in association with a reference image (hereinafter referred to as a reference image) and an ROI designated by the user on the reference image is used. The processing flow is shown in FIG.

  First, the reference image and ROI information designated by the user stored as incidental information are read from the image storage unit 205 (S2301, S2302).

  Next, the imaging position deviation between the measurement image and the reference image is calculated using a technique such as template matching (S2303), and the ROI designated by the user is moved based on the imaging position deviation amount (S2304). In order to move the ROI, for example, the imaging position deviation amount may be added to or subtracted from the coordinates of the ROI. Thereby, the ROI in the measurement image can be extracted.

  FIG. 24 shows an example of a user interface 2400 for the user according to the present embodiment to set the ROI for the reference image.

  In the user interface 2400, a button 2401 for selecting and reading a reference image from images stored in the image storage unit 205, an interface 2402 for overlay display of the reference image and the designated ROI, and a rectangle on the reference image are added. A tool button 2403 for switching the operation for deletion is displayed. In the interface 2402 for displaying the ROI in an overlay manner, the ROI area can be designated by dragging the mouse connected to the input / output terminal 113 or the like.

  According to the method described above, in the process of extracting the ROI from the measurement image, the process of searching for a similar region from the measurement image using one or more template images included in the overlay image library becomes unnecessary. Compared with this method, the amount of calculation can be reduced.

  DESCRIPTION OF SYMBOLS 101 ... Scanning electron microscope (SEM) 112 ... Image generation part 207 ... Measurement coordinate memory | storage part 208 ... Overlay image library memory | storage part 209 ... Image similarity memory | storage part 210 .... Region of interest ( ROI) Extraction unit 211 ... Image similarity calculation unit 212 ... Overlay calculation unit 213 ... Similarity distribution evaluation unit 415 ... Overlay 701 ... Region of interest extraction unit 702 ... Image similarity calculation Unit 703 ... Similarity distribution evaluation unit 704 ... Overlay calculation unit.

Claims (10)

A method for measuring an overlay between the plurality of exposure steps, targeting a semiconductor device in which a circuit pattern is formed by a plurality of exposure steps,
Capturing a measurement image at a specified measurement coordinate position of the semiconductor device;
A plurality of template images corresponding to the circuit pattern formed at the designated measurement coordinate position of the semiconductor device, and an image library stored in advance by associating each of the plurality of template images with the overlay Step to read
Calculating a similarity between each of the plurality of template images included in the read image library and the measurement image;
An overlay measurement method comprising: measuring an overlay in the measurement image based on the calculated similarity between each of the plurality of template images and the measurement image. The overlay measurement method according to claim 1,
The step of measuring the overlay in the measurement image includes
A first sub-step of calculating an overlay associated with each template image in the image library, and a similarity distribution combining the similarity between each template image and the measurement image;
An overlay measurement method comprising: a second sub-step of interpolating the calculated similarity distribution to calculate an overlay that maximizes the similarity. The overlay measurement method according to claim 1,
The step of measuring the overlay in the measurement image includes
Extracting a region of interest from the measurement image;
Calculating an overlay for each extracted region of interest;
An overlay measurement method, comprising: calculating an overlay in the measurement image from an overlay calculated for each region of interest. The overlay measurement method according to claim 3,
Extracting the region of interest from the measurement image is performed by searching the measurement image for a region similar to one or more template images from the template images included in the image library, and extracting the region of interest. An overlay measurement method characterized by being performed. The overlay measurement method according to claim 1,
The image library
Extracting layout information L1 related to the pattern formed by the first exposure process and layout information L2 related to the pattern formed by the second exposure process from the design information of the semiconductor device;
The layout information is integrated after shifting the relative positions of the layout information L1 and the layout information L2 by a predetermined amount,
A simulated image is generated by simulation based on the integrated layout information,
Storing the generated simulated image in association with a predetermined amount by shifting the relative position;
An overlay measurement method characterized by being created by a method. An apparatus for measuring an overlay between the plurality of exposure processes, targeting a semiconductor device in which a circuit pattern is formed by a plurality of exposure processes,
Means for capturing a measurement image at a specified measurement coordinate position of the semiconductor device;
Means for associating a plurality of template images corresponding to the circuit pattern formed at the designated measurement coordinate position of the semiconductor device and the overlay of each of the plurality of template images and storing them as an image library; ,
Means for calculating the similarity between the plurality of template images included in the image library stored in the storing means and the measurement image obtained by imaging with the imaging means;
An overlay measurement apparatus comprising: means for measuring an overlay in the measurement image based on the similarity with the plurality of template images calculated by the calculation means. The overlay measurement device according to claim 6,
The means for measuring the overlay includes:
An overlay reading unit for reading an overlay associated with each of the plurality of template images from the plurality of image libraries stored in the storing unit, the overlay read by the overlay reading unit, and the calculating unit A linking part for connecting the calculated similarity,
An overlay measurement apparatus comprising: an overlay calculation unit that interpolates a similarity degree connected by the connection part and calculates an overlay that maximizes the similarity degree. The overlay measurement device according to claim 6,
The means for measuring the overlay includes:
A region of interest extraction unit that extracts a region of interest from the measurement image;
A region of interest overlay calculation unit that calculates an overlay for each region of interest extracted by the region of interest extraction unit;
An overlay measurement apparatus comprising: a measurement image overlay calculation unit that calculates an overlay in the measurement image captured by the imaging unit from an overlay calculated for each region of interest by the region of interest overlay calculation unit. The overlay measurement apparatus according to claim 8,
The region of interest extraction unit extracts a region of interest by searching the measurement image for a region similar to one or more template images among the template images included in the image library stored in the storage unit. An overlay measuring apparatus characterized by that. 7. The overlay measurement apparatus according to claim 6, wherein layout information L1 relating to a pattern formed by first exposure based on design information of the semiconductor device and layout information L2 relating to a pattern formed by second exposure. Layout information extracting means for extracting
The layout information integrating means for integrating the layout information after shifting the relative positions of the layout information L1 and the layout information L2 extracted by the layout information extracting means by a predetermined amount and the layout information integrated by the layout information integrating means are also included. And a simulated image generating means for generating a simulated image by simulation,
An image library creating means for creating an image library by associating and storing the simulated image generated by the simulated image generating means and the predetermined amount shifted in the relative position by the layout information integrating means; An overlay measuring apparatus, wherein the image library created by the library creating means is stored in the storing means.

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