JP2015087571A - Microlens array substrate manufacturing method, microlens array substrate, electro-optical device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a microlens array substrate, by which generation of cracks can be suppressed regardless of film formation conditions for a lens layer, and a microlens array substrate, an electro-optic device, and electronic equipment.SOLUTION: The method for manufacturing a microlens array substrate 60 includes steps of: forming a conductive layer 15 in a second region G of a surface 14b of a substrate 14 having a light-transmitting property; forming a plurality of recesses 12 in a first region F of the surface 14b of the substrate 14; and forming a lens material layer 13a having a light-transmitting property and a refractive index different from that of the substrate 14 so as to cover the plurality of recesses 12 and the conductive layer 15 on the surface 14b of the substrate 14.

Description

  The present invention relates to a method for manufacturing a microlens array substrate, a microlens array substrate, an electro-optical device, and an electronic apparatus.

  There is known an electro-optical device including an electro-optical material (for example, liquid crystal) between an element substrate and a counter substrate. Examples of the electro-optical device include a liquid crystal device used as a liquid crystal light valve of a projector. Such a liquid crystal device is required to realize high light utilization efficiency.

  Therefore, for example, a microlens array substrate is provided on at least one of the element substrate and the counter substrate of the liquid crystal device, and the light that is blocked by the light blocking layer among the light incident on the liquid crystal device is condensed by the microlens to open the pixel opening. There has been known a configuration in which a substantial aperture ratio of a liquid crystal device is improved by making it enter the region. The microlens array substrate is formed, for example, by embedding a plurality of concave portions provided on the surface of a substrate made of an inorganic material such as quartz with a lens layer made of an inorganic material having a refractive index different from that of the substrate (for example, Patent Document 1).

JP 2008-209860 A

  However, in the process of forming the lens layer, the lens layer is formed thicker than the depth of the concave portion on the substrate, so that a bending moment acts on the lens layer and stress is applied to the peripheral portion of the lens layer to cause cracks. There is a case. If it is attempted to suppress the generation of cracks by adjusting the film formation conditions of the lens layer, various restrictions are imposed on the process of forming the lens layer. Therefore, there is a demand for a method of manufacturing a microlens array substrate that can suppress the occurrence of cracks regardless of the film formation conditions of the lens layer.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A method for manufacturing a microlens array substrate according to this application example includes a step of forming a first layer in a second region of a first surface of a substrate having light transparency, and the first of the substrate. A step of forming a plurality of recesses in a first region of a surface, and a refraction different from the substrate having light transmittance so as to cover the plurality of recesses and the first layer of the first surface of the substrate. And a step of forming a second layer having a rate.

  According to the manufacturing method of this application example, the plurality of microlenses are configured by filling the plurality of concave portions formed in the first region of the substrate with the second layer having a refractive index different from that of the substrate. Further, the second layer is formed so as to cover the first layer formed in the second region. That is, the first layer is interposed between the substrate and the second layer in the second region. Therefore, even if a bending moment acts on the second layer formed on the substrate, the stress generated by the bending moment is relieved by the first layer, so that compared to the case where the first layer is not provided. It is possible to suppress the occurrence of cracks in the second layer.

  Application Example 2 In the manufacturing method of the microlens array substrate according to the application example, it is preferable that the first layer is formed up to a side end portion of the substrate.

  According to the manufacturing method of this application example, since the first layer is formed up to the side edge of the substrate, the first layer is interposed between the substrate and the peripheral edge of the second layer. Therefore, since the stress can be relieved by the first layer at the peripheral portion of the second layer where stress due to the bending moment is likely to concentrate, it is possible to more reliably suppress the occurrence of cracks in the second layer. .

  [Application Example 3] A method of manufacturing a microlens array substrate according to the application example, wherein the step of forming the first layer is performed on the opposite side of the first surface and the first surface of the substrate. A step of forming a conductive layer so as to cover the second surface, and a step of removing a portion of the conductive layer covering the first region of the first surface, wherein the first layer includes: The conductive layer is preferably a part of the conductive layer.

  According to the manufacturing method of this application example, since the conductive layer is formed on the second surface of the substrate, the second surface side of the substrate is fixed by an electrostatic chuck (electrostatic adsorption), and the processing on the first surface side is performed. Can be done. In addition, since the first layer is a part of the conductive layer, the number of steps can be reduced as compared with the case where the first layer is separately formed, so that productivity can be improved.

  Application Example 4 In the method of manufacturing a microlens array substrate according to the application example described above, the Poisson ratio of the material of the first layer is greater than the Poisson ratio of the material of the substrate and the Poisson ratio of the material of the second layer. Is also preferably large.

  According to the manufacturing method of this application example, since the Poisson's ratio of the material of the first layer is larger than the Poisson's ratio of the substrate and the material of the second layer, the first layer includes the substrate and the second layer. Compared with a layer, when a strain is generated by applying stress in one direction, the strain generated in a direction perpendicular to that direction is large. That is, the first layer is likely to be deformed in cross section when stress is applied as compared with the substrate and the second layer. Therefore, when the first layer is interposed between the substrate and the second layer, the stress applied to the second layer can be relaxed.

  Application Example 5 In the method for manufacturing a microlens array substrate according to the application example, it is preferable that the first layer is made of silicon.

  According to the manufacturing method of this application example, since the first layer is made of silicon having conductivity and a Poisson's ratio larger than that of the substrate and the second layer, the first layer and the conductive layer are the same. It can be made of any material. Further, by using silicon, the first layer can be easily formed to the side edge of the substrate.

  Application Example 6 A microlens array substrate according to this application example is manufactured by the microlens array substrate manufacturing method according to the application example.

  According to the configuration of this application example, in the step of forming the second layer, the stress due to the bending moment acting on the second layer is relaxed by the first layer, and a crack is generated in the second layer. Since it can suppress, the yield in a manufacturing process improves. Thereby, the microlens array substrate excellent in cost competitiveness can be provided.

  Application Example 7 An electro-optical device according to this application example includes a first substrate, a second substrate disposed opposite to the first substrate, the first substrate, and the second substrate. An electro-optic layer disposed therebetween, and the microlens array substrate of the above application example is provided on at least one of the first substrate and the second substrate.

  According to the configuration of this application example, it is possible to provide an electro-optical device having excellent cost competitiveness.

  Application Example 8 An electronic apparatus according to this application example includes the electro-optical device according to the application example.

  According to the configuration of this application example, it is possible to provide an electronic device having excellent cost competitiveness.

1 is a schematic plan view showing a configuration of a liquid crystal device according to a first embodiment. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device according to the first embodiment. 1 is a schematic cross-sectional view illustrating a configuration of a liquid crystal device according to a first embodiment. The figure explaining the manufacturing method of the micro lens array board | substrate which concerns on 1st Embodiment. The figure explaining the manufacturing method of the micro lens array board | substrate which concerns on 1st Embodiment. The figure explaining the manufacturing method of the micro lens array board | substrate which concerns on 1st Embodiment. FIG. 5 is a schematic cross-sectional view illustrating a configuration of a liquid crystal device according to a second embodiment. The figure explaining the manufacturing method of the micro lens array board | substrate which concerns on 2nd Embodiment. Schematic which shows the structure of the projector as an electronic device which concerns on 3rd Embodiment. The fragmentary sectional view which shows the structure of the micro lens array board | substrate which concerns on a modification. The figure which shows an example of a structure of the conventional microlens array board | substrate.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. The drawings to be used are appropriately enlarged, reduced or exaggerated so that the part to be described can be recognized. In addition, illustrations of components other than those necessary for the description may be omitted.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

(First embodiment)
<Electro-optical device>
Here, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of the electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (projector) described later.

  First, a liquid crystal device as an electro-optical device according to the first embodiment will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a schematic plan view showing the configuration of the liquid crystal device according to the first embodiment. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the configuration of the liquid crystal device according to the first embodiment. Specifically, FIG. 3 is a schematic cross-sectional view taken along the line A-A ′ of FIG. 1.

  As shown in FIGS. 1 and 3, the liquid crystal device 1 according to the first embodiment includes an element substrate 20 as a first substrate and a counter substrate 30 as a second substrate disposed to face the element substrate 20. And a sealing material 42 and a liquid crystal layer 40 as an electro-optical layer. As shown in FIG. 1, the element substrate 20 and the counter substrate 30 are substantially rectangular in a plan view. The element substrate 20 is larger than the counter substrate 30, and both the substrates are joined together via a sealing material 42 arranged in a frame shape along the edge of the counter substrate 30.

  The liquid crystal layer 40 is composed of liquid crystal having positive or negative dielectric anisotropy enclosed in a space surrounded by the element substrate 20, the counter substrate 30, and the sealing material 42. The sealing material 42 is made of an adhesive such as a thermosetting or ultraviolet curable epoxy resin. Spacers (not shown) are mixed in the sealing material 42 to keep the distance between the element substrate 20 and the counter substrate 30 constant.

  Inside the sealing material 42 arranged in a frame shape, the light shielding layers 22 and 26 provided on the element substrate 20 and the light shielding layer 32 provided on the counter substrate 30 are arranged. The light shielding layers 22, 26, and 32 have a frame-like peripheral portion, and are formed of, for example, a light shielding metal or metal oxide. Inside the frame-shaped light shielding layers 22, 26, 32 is a display area E in which a plurality of pixels P are arranged. The pixels P have, for example, a substantially rectangular shape and are arranged in a matrix.

  The display area E is an area that substantially contributes to display in the liquid crystal device 1. The light shielding layers 22 and 26 provided on the element substrate 20 are provided, for example, in a lattice shape in the display region E so as to partition the plurality of pixels P in a plane. The liquid crystal device 1 may include a dummy area that is provided so as to surround the display area E and does not substantially contribute to display.

  A data line driving circuit 51 and a plurality of external connection terminals 54 are provided along the first side on the side opposite to the display region E of the sealing material 42 formed along the first side of the element substrate 20. An inspection circuit 53 is provided on the display region E side of the sealing material 42 along the other second side facing the first side. Further, a scanning line driving circuit 52 is provided inside the sealing material 42 along the other two sides that are orthogonal to these two sides and face each other.

  On the display area E side of the sealing material 42 on the second side where the inspection circuit 53 is provided, a plurality of wirings 55 that connect the two scanning line driving circuits 52 are provided. Wirings connected to the data line driving circuit 51 and the scanning line driving circuit 52 are connected to a plurality of external connection terminals 54. In addition, a vertical conduction portion 56 is provided at a corner portion of the counter substrate 30 to establish electrical continuity between the element substrate 20 and the counter substrate 30. The arrangement of the inspection circuit 53 is not limited to this, and the inspection circuit 53 may be provided at a position along the inner side of the seal material 42 between the data line driving circuit 51 and the display area E.

  In the following description, the direction along the first side where the data line driving circuit 51 is provided is the X direction, and the direction along the other two sides orthogonal to the first side and facing each other is the Y direction. The X direction is a direction along the line A-A ′ in FIG. 1. The pixels P are partitioned in a lattice shape by the light shielding layers 22, 26 and 32, and are arranged in a matrix shape along the X direction and the Y direction. The light shielding layers 22, 26, and 32 are provided in a lattice shape or an island shape along the X direction and the Y direction.

  Further, a direction perpendicular to the X direction and the Y direction and directed upward in FIG. In this specification, viewing from the normal direction (Z direction) of the surface of the liquid crystal device 1 on the counter substrate 30 side is referred to as “plan view”.

  As shown in FIG. 2, in the display area E, the scanning lines 2 and the data lines 3 are formed so as to intersect with each other, and pixels P are provided corresponding to the intersections of the scanning lines 2 and the data lines 3. Yes. Each pixel P is provided with a pixel electrode 28 and a TFT 24 as a switching element.

  A source electrode (not shown) of the TFT 24 is electrically connected to the data line 3 extending from the data line driving circuit 51. Image signals (data signals) S1, S2,..., Sn are supplied to the data lines 3 from the data line driving circuit 51 (see FIG. 1) in a line sequential manner. A gate electrode (not shown) of the TFT 24 is a part of the scanning line 2 extending from the scanning line driving circuit 52. The scanning lines 2 are supplied with scanning signals G1, G2,..., Gm from the scanning line driving circuit 52 in a line sequential manner. A drain electrode (not shown) of the TFT 24 is electrically connected to the pixel electrode 28.

  The image signals S1, S2,..., Sn are written to the pixel electrode 28 through the data line 3 at a predetermined timing by turning on the TFT 24 for a certain period. The image signal of a predetermined level written in the liquid crystal layer 40 through the pixel electrode 28 in this manner is constant by the liquid crystal capacitance formed between the common electrode 34 (see FIG. 3) provided on the counter substrate 30. Hold for a period.

  In order to prevent the held image signals S1, S2,..., Sn from leaking, a storage capacitor 5 is formed between the capacitor line 4 formed along the scanning line 2 and the pixel electrode 28. Arranged in parallel with the liquid crystal capacitor. Thus, when a voltage signal is applied to the liquid crystal of each pixel P, the alignment state of the liquid crystal changes depending on the applied voltage level. As a result, the light incident on the liquid crystal layer 40 (see FIG. 3) is modulated to enable gradation display.

  The liquid crystal constituting the liquid crystal layer 40 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. For example, in the normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel P. In the normally black mode, the transmittance for incident light increases in accordance with the voltage applied in units of each pixel P, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device 1 as a whole.

  As shown in FIG. 3, the counter substrate 30 includes a microlens array substrate 10, an optical path length adjustment layer 31, a light shielding layer 32, a protective layer 33, a common electrode 34, and an alignment film 35.

  The microlens array substrate 10 includes a substrate 11 and a lens layer 13. The substrate 11 is made of an inorganic material having optical transparency such as glass or quartz. A surface of the substrate 11 on the liquid crystal layer 40 side is a surface 11b as a first surface. A surface of the substrate 11 opposite to the liquid crystal layer 40 is a surface 11a as a second surface. The substrate 11 has a plurality of recesses 12 formed on the surface 11b side. Each recess 12 is provided corresponding to the pixel P.

The lens layer 13 is provided so as to cover the surface 11 b side of the substrate 11. The lens layer 13 is formed thicker than the depth of the recess 12 and is formed so as to embed the plurality of recesses 12. The lens layer 13 is made of a material having optical transparency and a refractive index different from that of the substrate 11. More specifically, the lens layer 13 is made of an inorganic material having a higher refractive index than that of the substrate 11. Examples of such inorganic materials include SiON and Al ₂ O ₃ .

  By embedding the concave portion 12 with a material forming the lens layer 13, a convex microlens ML is configured. Accordingly, each microlens ML is provided corresponding to the pixel P. In addition, a microlens array MLA is configured by the plurality of microlenses ML. The surface of the microlens array substrate 10, that is, the surface of the lens layer 13, is a substantially flat surface.

  The optical path length adjustment layer 31 is provided so as to cover the microlens array substrate 10 (lens layer 13). The optical path length adjusting layer 31 is light transmissive and is made of, for example, an inorganic material having substantially the same refractive index as that of the substrate 11. The optical path length adjustment layer 31 has a function of adjusting the distance from the microlens ML to the light shielding layer 32 to a desired value. Therefore, the layer thickness of the optical path length adjusting layer 31 is appropriately set based on optical conditions such as the focal length of the microlens ML corresponding to the wavelength of light.

  The light shielding layer 32 is provided on the optical path length adjustment layer 31. The light shielding layer 32 is formed in a lattice shape or an island shape so as to overlap the light shielding layer 22 and the light shielding layer 26 of the element substrate 20 in plan view. FIG. 3 shows a case where the light shielding layer 32 is formed in a lattice shape and has an opening 32a. In this case, the inside of the opening 32a of the light shielding layer 32 is a region through which light is transmitted.

  The protective layer 33 is provided so as to cover the optical path length adjusting layer 31 and the light shielding layer 32. The common electrode 34 is provided so as to cover the protective layer 33. The common electrode 34 is formed across a plurality of pixels P. The common electrode 34 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment film 35 is provided so as to cover the common electrode 34.

  The protective layer 33 is for planarizing the surface on the liquid crystal layer 40 side where the common electrode 34 is formed so as to cover the light shielding layer 32. For example, the common electrode 34 may be formed so as to directly cover the conductive light shielding layer 32, and in that case, the protective layer 33 may be omitted.

  The element substrate 20 includes a substrate 21, a light shielding layer 22, an insulating layer 23, a TFT 24, an insulating layer 25, a light shielding layer 26, an insulating layer 27, a pixel electrode 28, and an alignment film 29. . The substrate 21 is made of a light transmissive material such as glass or quartz.

  The light shielding layer 22 is provided on the substrate 21. The light shielding layer 22 is formed in a lattice shape so as to overlap the light shielding layer 32 in plan view together with the upper light shielding layer 26. The light shielding layer 22 and the light shielding layer 26 are disposed so as to sandwich the TFT 24 therebetween in the thickness direction (Z direction) of the element substrate 20. The light shielding layer 22 overlaps at least the channel region of the TFT 24 in plan view.

  By providing the light shielding layer 22 and the light shielding layer 26, the incidence of light on the TFT 24 is suppressed. The region surrounded by the light shielding layer 22 (inside the opening 22a) and the region surrounded by the light shielding layer 26 (inside the opening 26a) overlap each other in plan view and become a region through which light is transmitted.

The insulating layer 23 is provided so as to cover the substrate 21 and the light shielding layer 22. The insulating layer 23 is made of an inorganic material such as SiO ₂ .

  The TFT 24 is provided on the insulating layer 23. The TFT 24 is a switching element that drives the pixel electrode 28. The TFT 24 includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode (not shown). A source region, a channel region, and a drain region are formed in the semiconductor layer. An LDD (Lightly Doped Drain) region may be formed at the interface between the channel region and the source region or between the channel region and the drain region.

  The gate electrode is formed on the element substrate 20 in a region overlapping with the channel region of the semiconductor layer in plan view via a part (gate insulating film) of the insulating layer 25. Although not shown, the gate electrode is electrically connected to the scanning line disposed on the lower layer side through a contact hole, and the TFT 24 is controlled to be turned on / off by applying a scanning signal.

The insulating layer 25 is provided so as to cover the insulating layer 23 and the TFT 24. The insulating layer 25 is made of an inorganic material such as SiO ₂ , for example. The insulating layer 25 includes a gate insulating film that insulates between the semiconductor layer of the TFT 24 and the gate electrode. The insulating layer 25 relieves surface irregularities caused by the TFT 24. A light shielding layer 26 is provided on the insulating layer 25. An insulating layer 27 made of an inorganic material is provided so as to cover the insulating layer 25 and the light shielding layer 26.

  The pixel electrode 28 is provided on the insulating layer 27 corresponding to the pixel P. The pixel electrode 28 is disposed in a region overlapping the opening 22 a of the light shielding layer 22 and the opening 26 a of the light shielding layer 26 in plan view. The pixel electrode 28 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment film 29 is provided so as to cover the pixel electrode 28. The liquid crystal layer 40 is sandwiched between the alignment film 29 on the element substrate 20 side and the alignment film 35 on the counter substrate 30 side.

  Note that the TFT 24 and electrodes and wiring (not shown) for supplying an electrical signal to the TFT 24 are provided in a region overlapping the light shielding layer 22 and the light shielding layer 26 in plan view. A configuration in which these electrodes and wirings also serve as the light shielding layer 22 and the light shielding layer 26 may be employed.

  In the liquid crystal device 1 according to the first embodiment, for example, light emitted from a light source or the like enters from the side of the counter substrate 30 (substrate 11) including the microlens ML and is collected by the microlens ML. Of the light incident on the microlens ML along the normal direction of the surface 11a from the substrate 11 side, the incident light L1 incident along the optical axis passing through the planar center of the region of the pixel P is the microlens ML. , Straight through, passes through the liquid crystal layer 40 and is emitted to the element substrate 20 side.

  When the incident light L2 incident on the peripheral edge of the microlens ML from a region overlapping with the light shielding layer 32 (or the light shielding layer 26) in a plan view outside the incident light L1 travels straight as it is, the light shielding layer as shown by the broken line. Although the light is blocked by 32 (or the light shielding layer 26), the light is refracted toward the planar center side of the region of the pixel P due to the difference in the optical refractive index between the substrate 11 and the lens layer 13.

  In the liquid crystal device 1, the incident light L2 that is shielded by the light shielding layer 32 (or the light shielding layer 26) when traveling straight in this way also enters the opening 32a (or the opening 26a) by the action of the microlens ML. The liquid crystal layer 40 can be passed through. As a result, since the amount of light emitted from the element substrate 20 side can be increased, the light utilization efficiency can be increased.

<Manufacturing method of microlens array substrate>
Next, a method for manufacturing the microlens array substrate according to the first embodiment will be described. 4, 5, and 6 are views for explaining a method of manufacturing the microlens array substrate according to the first embodiment. Specifically, FIG. 4 (a) is a schematic plan view of a large microlens array substrate, and FIG. 4 (b) is a partial cross-sectional view taken along line BB ′ of part C of FIG. 4 (a). . Each of FIGS. 5 and 6 corresponds to a partial cross-sectional view along the line BB ′ in FIG.

  FIG. 4A is a plan view of a large microlens array substrate 60 from which a plurality of microlens array substrates 10 can be taken as viewed from the direction of the liquid crystal layer 40 in FIG. In the manufacturing process of the microlens array substrate 10, processing is performed in a state of a large microlens array substrate 60, and finally the microlens array substrate 60 is cut and separated into a plurality of microlens array substrates. 10 is obtained.

  As shown in FIG. 4A, the base material of the microlens array substrate 60 includes a substantially circular wafer-like substrate 14 in plan view. The substrate 11 (see FIG. 3) of the microlens array substrate 10 is obtained by dividing the substrate 14 into pieces for each microlens array substrate 10. The microlens array substrate 60 includes a first region F in which a plurality of microlens array substrates 10 are formed, and a second region G that is disposed outside the first region F so as to surround the first region F. ing. In the first region F, a microlens array MLA (see FIG. 3) is provided for each microlens array substrate 10.

  4A and 4B show a state in which a lens material layer 13a as a second layer to be described later is formed on the substrate 14 (see FIG. 6B). 4B is upside down (Z direction) with respect to FIG. As shown in FIG. 4B, the substrate 14 has a surface 14 b as a first surface corresponding to the surface 11 b of the substrate 11 and a surface 14 a as a second surface corresponding to the surface 11 a of the substrate 11.

  In the microlens array substrate 60, a portion between the outer peripheral end of the surface 14b of the substrate 14 and the outer peripheral end of the surface 14a is referred to as a side end H. In the side end portion H, the corners of the surface 14b and the side surface 14c of the substrate 14 and the corners of the surface 14a and the side surface 14c are chamfered along the outer periphery of the substrate 14, and between the surface 14b and the side surface 14c. And a slope 14d is provided between the surface 14a and the side surface 14c.

  A conductive layer 15 is provided in the second region G of the surface 14 b of the substrate 14. The conductive layer 15 may be provided so as to cover the entire second region G in the surface 14b. The conductive layer 15 is provided across the first region F and the second region G on the surface 14a. Furthermore, the conductive layer 15 is preferably provided also on the side end H (the slope 14d between the surface 14a and the side surface 14c, the side surface 14c, and the slope 14d between the side surface 14c and the surface 14b). In other words, the conductive layer 15 has an opening 15a having a size including at least the first region F on the surface 14b of the substrate 14, and is provided so as to cover a portion other than the opening 15a of the substrate 14. Is preferred.

  The conductive layer 15 has a function for fixing the surface 14a side of the substrate 14 by electrostatic chuck (electrostatic adsorption) in the manufacturing process of the microlens array substrate 60, and a function for relieving stress generated in the lens material layer 13a. Have both. In other words, a portion of the conductive layer 15 provided on the surface 14a side is an electrostatic adsorption layer, and a portion provided on the surface 14b side is a stress relaxation layer as the first layer of the present invention. As shown in FIG. 4B, when the conductive layer 15 is also provided at the side end portion H, this portion of the conductive layer 15 also serves as a stress relaxation layer.

  The conductive layer 15 is made of a material having conductivity and having a Poisson ratio larger than the Poisson ratio of the substrate 14 and the Poisson ratio of the lens material layer 13a. As a material of such a conductive layer 15, for example, silicon can be used. The material of the conductive layer 15 may be a metal such as aluminum. The film thickness of the conductive layer 15 is, for example, about 350 nm to 2000 nm. The width in the X direction of the conductive layer 15 (the distance from the side end H side to the opening 15a) is, for example, about 3 mm to 5 mm.

  The lens material layer 13 a is provided across the first region F and the second region G of the surface 14 b of the substrate 14. A conductive layer 15 is disposed between the peripheral portion of the lens material layer 13 a and the substrate 14. The lens material layer 13a may be provided so that the peripheral edge thereof reaches the side end H, that is, the range from the surface 14b of the substrate 14 to the inclined surface 14d and the side surface 14c. As will be described later, the lens layer 13 is formed by polishing and flattening the upper surface of the lens material layer 13a.

  Subsequently, a process of manufacturing the microlens array substrate 60 (microlens array substrate 10) will be described with reference to FIGS. In addition, the part of 1st area | region F shown to each figure of FIG. 5 and FIG. 6 is a part in which the micro lens ML of the one micro lens array board | substrate 10 is formed.

  First, as shown in FIG. 5A, the surface of the substrate 14 made of quartz or the like and having light transmissivity, that is, the first region F and the second region G on the surfaces 14a and 14b is covered. Layer 15 is formed. By forming the conductive layer 15 on the surface 14a side of the substrate 14, it is possible to perform processing on the surface 14b side by fixing the surface 14a side of the substrate 14 with an electrostatic chuck (electrostatic adsorption) in the subsequent steps. It becomes.

  As a material of the conductive layer 15, for example, silicon can be used. As a method of forming the conductive layer 15, for example, a CVD (Chemical Vapor Deposition) method can be used. By using the CVD method, the silicon film to be the conductive layer 15 can be easily formed on the side end H (the slope 14d between the surface 14a and the side surface 14c, the side surface 14c, and the slope 14d between the side surface 14c and the surface 14b). Also, a film can be formed.

  Next, as shown in FIG. 5B, at least a portion covering the first region F is removed from the conductive layer 15 on the surface 14b side of the substrate 14, and the other portions are left. As a result, an opening 15 a having a size including at least the first region F is formed in the conductive layer 15. The surface 14b of the substrate 14 is exposed in the opening 15a.

  As a method of partially removing the conductive layer 15, for example, dry etching such as reactive ion etching (RIE) can be used. RIE accelerates ions generated from plasma in an RIE apparatus and bombards an object to be etched. By applying a bias to the substrate 14 through a stage that supports the substrate 14, the RIE of the conductive layer 15 is performed. Of these, the portion overlapping the stage in plan view can be removed. As a method of partially removing the conductive layer 15, wet etching can be used.

  Although not shown, each microlens array substrate 10 is provided with an alignment mark. The alignment marks are arranged at the four corners of each microlens array substrate 10 and are used for alignment with, for example, a mask used for patterning of the light shielding layer 32 by photolithography. In this embodiment, the alignment mark is formed by removing, by dry etching, a portion other than the alignment mark in the silicon film formed on the surface 14b (surface 11b) side of the substrate 14 (substrate 11) as the conductive layer 15. Is done.

  Therefore, in the step shown in FIG. 5B, a portion other than the alignment mark is removed from the silicon film formed on the surface 14b side of the substrate 14 for each microlens array substrate 10 in the first region F. By forming an alignment mark and leaving a portion formed in the second region G, the conductive layer 15 serving as a stress relaxation layer as the first layer can be formed. That is, the electrostatic adsorption layer, the stress relaxation layer, and the alignment mark can be formed in the same process.

  Next, as shown in FIG. 5C, a mask layer 71 is formed so as to cover the surface 14 b side of the substrate 14. Then, the mask layer 71 is patterned to form a plurality of openings 71 a in portions of the mask layer 71 in the first region F. The opening 71a is, for each microlens array substrate 10, a planar center position of the microlens ML (concave portion 12) obtained in a later step, that is, a planar center position of the region of the pixel P (see FIG. 3). It is provided corresponding to. Thereby, the surface 14b of the board | substrate 14 is exposed in the opening part 71a.

  Next, as shown in FIG. 5 (d), the substrate 14 is subjected to an isotropic etching process through the opening 71 a of the mask layer 71, so that a plurality of recesses are formed in the first region F of the substrate 14. 12 is formed. As the isotropic etching treatment, for example, wet etching using an etchant such as a hydrofluoric acid solution can be used.

  By this isotropic etching process, isotropic etching is performed from the surface 14b side of the substrate 14 around each of the plurality of openings 71a, a substantially hemispherical region is removed in a cross-sectional view, and the plurality of recesses 12 are formed. It is formed. The cross-sectional shape of the recess 12 is not limited to a spherical shape, and may be a shape that includes a substantially flat portion at the bottom or a tapered portion at the periphery.

Note that an oxide film such as SiO ₂ having an isotropic etching rate different from that of the substrate 14 may be formed on the substrate 14 before the mask layer 71 is formed. By doing so, the etching rate in the width direction (W direction) with respect to the etching rate in the depth direction (Z direction) when forming the recess 12 is appropriately adjusted to obtain a desired cross-sectional shape of the recess 12. Can do. When the isotropic etching process is completed, the mask layer 71 is removed from the substrate 14 as shown in FIG.

  Next, as shown in FIG. 6B, the material of the lens layer 13 is arranged in the first region F and the second region G on the surface 14 b side of the substrate 14, and a plurality of recesses 12 are embedded in a plan view. The lens material layer 13 a is formed so as to overlap with the conductive layer 15. As the material of the lens layer 13, silicon oxynitride (SiON), which is an inorganic material having optical transparency and a refractive index higher than that of the substrate 14, is used. The lens material layer 13a can be formed using, for example, a plasma CVD method.

  The lens material layer 13 a is formed to be thicker than the depth of the recess 12. The upper surface of the lens material layer 13a formed in the first region F has a concavo-convex shape reflecting a step between the concave portion 12 and the boundary portion between the concave portions 12 and a portion where the concave portion 12 is not formed. The lens material layer 13 a is formed so as to cover the conductive layer 15 in the second region G. The lens material layer 13a may be formed up to the side end H.

  Next, a planarization process is performed on the lens material layer 13a shown in FIG. As a planarization method, for example, a CMP (Chemical Mechanical Polishing) process or the like is used, and the upper uneven portion of the lens material layer 13a (the portion above the two-dot chain line shown in FIG. 6B). ) Is removed by polishing to flatten the surface. An etch back method may be used as the planarization method.

  As a result, as shown in FIG. 6C, the upper surface of the lens material layer 13 a is flattened to obtain the lens layer 13, and the microlens ML is configured by the lens layer 13 filling the recess 12. As a result, a plurality of microlens array substrates 10 (see FIG. 4A) including the microlens array MLA are formed in the first region F of the microlens array substrate 60.

  Next, although not shown, after removing the conductive layer 15 covering the surface 14 a of the substrate 14, the portion of the first region F of the microlens array substrate 60 is cut for each microlens array substrate 10. As a result, a plurality of microlens array substrates 10 can be obtained. In addition, after the microlens array substrate 10 is separated into pieces, the portion of the second region G and the side end portion H of the microlens array substrate 60 become unnecessary.

  When the counter substrate 30 including the microlens array substrate 10 is manufactured, as shown in FIG. 3, the optical path length adjustment layer 31, the light shielding layer 32, and the protective layer 33 are shared on the microlens array substrate 10. The electrode 34 and the alignment film 35 are formed in order. The light shielding layer 32 is formed by patterning a light shielding film formed so as to cover the optical path length adjusting layer 31, and the mask is aligned on the basis of the alignment mark described above during patterning.

  When the counter substrate 30 is manufactured in this way, each layer constituting the counter substrate 30 is formed for each microlens array substrate 10 in the state of the microlens array substrate 60 before cutting, and finally the individual pieces are cut and separated. May be used. In this case, the conductive layer 15 covering the surface 14a side of the substrate 14 may be removed after these layers are formed.

  Here, the effect as the stress relaxation layer of the conductive layer 15 provided on the surface 14b side of the substrate 14 will be described in comparison with the case where the conventional conductive layer 15 is not provided. FIG. 11 is a diagram illustrating an example of a configuration of a conventional microlens array substrate. Specifically, FIG. 11 (a) is a schematic plan view of a conventional microlens array substrate, FIG. 11 (b) is a side view of portion C of FIG. 11 (a) viewed from the X direction, and FIG. FIG. 11C is a partial cross-sectional view taken along the line BB ′ of the portion C in FIG.

  As shown in FIG. 11A, the conventional microlens array substrate 65 has substantially the same configuration as the microlens array substrate 60 of the present embodiment except that the conductive layer 15 is not provided. It shall be.

  As shown in FIGS. 11A, 11B, and 11C, the conventional microlens array substrate 65 has a problem that a crack K tends to occur in the peripheral portion of the lens material layer 13a. For example, the crack K is generated in the lens material layer 13a from the side end H side toward the second region G in the step of forming the lens material layer 13a shown in FIG. In some cases, the crack K generated in the peripheral portion of the lens material layer 13a reaches the first region F.

  The crack K is caused by a bending moment acting in the radial direction (X direction in FIG. 11C) of the substrate 14 and the lens material layer 13a in the configuration in which the lens material layer 13a is laminated on the substrate 14. It is considered that the stress is applied to the peripheral portion of 13a. The crack K is more likely to occur as the diameter of the substrate 14 is larger, and more likely to occur as the lens material layer 13a is thicker.

  As shown in FIG. 4B, in the microlens array substrate 60 according to the present embodiment, the conductive layer 15 is disposed between the peripheral portion of the lens material layer 13 a and the substrate 14. The Poisson's ratio of the substrate 14 made of quartz is about 0.14 to 0.17, and the Poisson's ratio of the lens material layer 13a is also about the same. In contrast, the Poisson ratio of the conductive layer 15 made of silicon is about 0.26 to 0.28, which is larger than the Poisson ratio of the substrate 14 and the Poisson ratio of the lens material layer 13a.

  Therefore, when the conductive layer 15 is distorted by applying stress in one direction (for example, the X direction) as compared to the substrate 14 and the lens material layer 13a, the direction is perpendicular to the direction (for example, the Y direction). There is a large amount of distortion. That is, the conductive layer 15 is likely to be deformed in cross section when stress is applied as compared with the substrate 14 and the lens material layer 13a. Accordingly, since the conductive layer 15 is interposed between the substrate 14 and the lens material layer 13a, the stress applied to the lens material layer 13a is relieved, so that the generation of the crack K in the lens material layer 13a can be suppressed. .

  Further, since the conductive layer 15 is also provided on the side end H (the slope 14d between the surface 14a and the side surface 14c, the side surface 14c, and the slope 14d between the side surface 14c and the surface 14b), the lens material layer Even if 13 a is formed around the side end H, the conductive layer 15 is interposed between the peripheral edge of the lens material layer 13 a and the substrate 14. Accordingly, since the A stress can be relaxed by the conductive layer 15 at the peripheral portion of the lens material layer 13a where stress due to bending moment tends to concentrate, the generation of cracks K in the lens material layer 13a can be more reliably suppressed. Can do.

  The effect of the conductive layer 15 as a stress relaxation layer is larger as the thickness of the conductive layer 15 is larger, and is larger as the width (area) of the conductive layer 15 is larger. Note that aluminum can also be used as the material of the conductive layer 15. Although the Poisson's ratio of aluminum is about 0.345, which is higher than that of silicon, silicon is preferable in that it has better heat resistance than aluminum.

  As described above, according to the method for manufacturing the microlens array substrate according to the present embodiment, the conductive layer 15 functioning as the first layer (stress relaxation layer) is formed on the surface 14b side of the substrate 14 to thereby form the substrate. In the step of forming the lens material layer 13a on the lens 14, it is possible to suppress the occurrence of cracks in the lens material layer 13a. Thereby, the manufacturing yield of the microlens array substrate 60 (microlens array substrate 10) is improved.

  Further, the first layer (stress relaxation layer) is a part of the conductive layer 15 as an electrostatic adsorption layer, and the process of forming the conductive layer 15 can be shared with the process of forming the alignment mark. There is no need to add a manufacturing process for forming the layer. Therefore, the microlens array substrate 10 having excellent cost competitiveness can be provided.

(Second Embodiment)
<Electro-optical device>
Next, a liquid crystal device 1A as an electro-optical device according to a second embodiment will be described. The liquid crystal device 1A according to the second embodiment is different from the first embodiment in that a light-transmitting layer 17 is provided on the surface 14b (surface 11b) of the substrate 14 (substrate 11), and the lens. The structure is substantially the same except that the light shielding layer 32 is provided on the layer 13. FIG. 7 is a schematic cross-sectional view showing the configuration of the liquid crystal device according to the second embodiment. Constituent elements common to the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 7, the liquid crystal device 1 </ b> A according to the second embodiment includes an element substrate 20, a counter substrate 30 </ b> A, and a liquid crystal layer 40. The counter substrate 30A includes a microlens array substrate 10A, a light shielding layer 32, an optical path length adjustment layer 31, a common electrode 34, and an alignment film 35.

A microlens array substrate 10 </ b> A according to the second embodiment includes a substrate 11, a translucent layer 17, and a lens layer 13. The light transmissive layer 17 is provided on the surface 11 b of the substrate 11. The translucent layer 17 is made of a translucent oxide film such as SiO ₂ . As will be described later, the translucent layer 17 has a function as a protective film for protecting the conductive layer 15 when the mask layer 71 (see FIG. 8B) is removed in the process of manufacturing the microlens array substrate 10A. .

  The recess 12 is formed by etching the surface 11b side of the substrate 11 on which the light transmissive layer 17 is formed. Therefore, the translucent layer 17 is arrange | positioned between the adjacent recessed parts 12 and the part in which the recessed part 12 is not provided. The lens layer 13 is provided so as to embed the plurality of concave portions 12 and cover the light transmitting layer 17.

  The light shielding layer 32 is provided on the lens layer 13. The optical path length adjustment layer 31 is provided so as to cover the lens layer 13 and the light shielding layer 32. In the counter substrate 30A according to the second embodiment, the optical path length adjustment layer 31 covers the light shielding layer 32 and also serves to flatten the surface on the liquid crystal layer 40 side where the common electrode 34 is formed. The protective layer 33 (see FIG. 3) can be omitted.

<Manufacturing method of microlens array substrate>
Next, a method for manufacturing a microlens array substrate according to the second embodiment will be described. FIG. 8 is a diagram for explaining a method of manufacturing a microlens array substrate according to the second embodiment. The manufacturing method of the microlens array substrate according to the second embodiment has a step of forming the light-transmitting layer 17 on the conductive layer 15 before forming the mask layer 71 with respect to the first embodiment. Except for the point, it has almost the same process.

In the method for manufacturing the microlens array substrate according to the second embodiment, after the conductive layer 15 shown in FIG. 5B is partially removed to form the opening 15a, as shown in FIG. 8A. The transparent layer 17 is formed so as to cover the surface 14b (11b) of the substrate 14 (substrate 11) and the conductive layer 15. In this step, a light-transmitting oxide film to be the light-transmitting layer 17 is formed with a material such as SiO ₂ and then annealed at a predetermined temperature to the light-transmitting layer. 17 is formed.

  Next, as shown in FIG. 8B, a mask layer 71 is formed so as to cover the light transmitting layer 17, and the mask layer 71 is patterned to form a plurality of openings 71a. Thereby, the translucent layer 17 is exposed in the opening 71a.

  Next, as shown in FIG. 8C, a plurality of recesses 12 are formed by performing isotropic etching on the light transmitting layer 17 and the substrate 14 through the openings 71 a of the mask layer 71. In this step, since the light transmissive layer 17 is also etched together with the substrate 14 in the first region F, a portion of the light transmissive layer 17 formed in FIG.

  Next, as shown in FIG. 8D, the mask layer 71 is removed from the substrate 14. In this step, in the second region G, the translucent layer 17 covering the conductive layer 15 functions as a protective film for the conductive layer 15. For example, when the mask layer 71 is formed on the conductive layer 15 as in the first embodiment, the conductive layer 15 may be damaged when the mask layer 71 is removed, or the conductive layer 15 together with the mask layer 71 may be damaged. May also be removed. In the second embodiment, even in such a case, it is possible to protect the conductive layer 15 by covering it with the light transmitting layer 17.

  Subsequently, as in the first embodiment, the steps after FIG. 6B are performed, and a plurality of microlens array substrates are provided in the first region F of the microlens array substrate 60 (see FIG. 4A). 10A (see FIG. 7) is formed. Although illustration is omitted, when manufacturing the counter substrate 30A including the microlens array substrate 10A, the light shielding layer 32 is formed on the lens layer 13, and the optical path length adjusting layer 31 is formed on the light shielding layer 32 and the lens layer 13. Form.

(Third embodiment)
<Electronic equipment>
Next, an electronic apparatus according to a third embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram illustrating a configuration of a projector as an electronic apparatus according to the third embodiment.

  As shown in FIG. 9, a projector (projection display device) 100 as an electronic apparatus according to the third embodiment includes a polarization illumination device 110, two dichroic mirrors 104 and 105, and three reflection mirrors 106 and 107. , 108, five relay lenses 111, 112, 113, 114, 115, three liquid crystal light valves 121, 122, 123, a cross dichroic prism 116, and a projection lens 117.

  The polarization illumination device 110 includes a lamp unit 101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 102, and a polarization conversion element 103. The lamp unit 101, the integrator lens 102, and the polarization conversion element 103 are disposed along the system optical axis Lx.

  The dichroic mirror 104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 110. Another dichroic mirror 105 reflects the green light (G) transmitted through the dichroic mirror 104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 104 is reflected by the reflection mirror 106 and then enters the liquid crystal light valve 121 via the relay lens 115. The green light (G) reflected by the dichroic mirror 105 enters the liquid crystal light valve 122 via the relay lens 114. The blue light (B) transmitted through the dichroic mirror 105 is incident on the liquid crystal light valve 123 via a light guide system composed of three relay lenses 111, 112, 113 and two reflection mirrors 107, 108.

  The transmissive liquid crystal light valves 121, 122, and 123 as light modulation elements are disposed to face the incident surfaces of the cross dichroic prism 116 for each color light. The color light incident on the liquid crystal light valves 121, 122, 123 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 116.

  The cross dichroic prism 116 is configured by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. Yes. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 130 by the projection lens 117 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 121 is applied with the liquid crystal device 1 including the microlens array substrate 10 of the above-described embodiment or the liquid crystal device 1A including the microlens array substrate 10A. The liquid crystal light valve 121 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and emission side of colored light. The same applies to the other liquid crystal light valves 122 and 123.

  According to the configuration of the projector 100 according to the third embodiment, since the liquid crystal device 1 or the liquid crystal device 1A that can obtain a bright display even if the plurality of pixels P are arranged with high definition, the quality is provided. The projector 100 can be provided with a high brightness.

  The above-described embodiments merely show one aspect of the present invention, and can be arbitrarily modified and applied within the scope of the present invention. As modifications, for example, the following can be considered.

(Modification 1)
The microlens array substrate 60 according to the above embodiment has a configuration in which the slope 14d is provided between the side surface 14c and the surface 14b of the substrate 14 and between the side surface 14c and the surface 14a at the side end portion H. However, the present invention is not limited to such a form. 10A and 10B are partial cross-sectional views illustrating the configuration of the microlens array substrate according to the first modification. Constituent elements common to the above-described embodiment are denoted by the same reference numerals and description thereof is omitted.

  Like the microlens array substrate 61 shown in FIG. 10A, a curved surface 14e is provided between the side surface 14c and the surface 14b of the substrate 14 and between the side surface 14c and the surface 14a. Also good. Further, as in the microlens array substrate 62 shown in FIG. 10B, a slope 14d and a curved surface 14e are provided between the side surface 14c and the surface 14b of the substrate 14 and between the side surface 14c and the surface 14a. You may have the structure which is not. Regardless of the cross-sectional shape of the substrate 14, the provision of the conductive layer 15 can suppress the occurrence of cracks K in the lens material layer 13 a.

(Modification 2)
In the microlens array substrate 60 according to the above embodiment, the conductive layer 15 is provided on the surface 14b side and the surface 14a side of the substrate 14, and the portion of the conductive layer 15 provided on the surface 14a side is the electrostatic adsorption layer. However, the present invention is not limited to such a form. When the electrostatic adsorption layer is not required, the conductive layer 16 having the function as the first layer (stress relaxation layer) is provided on the surface of the substrate 14 as in the microlens array substrate 63 shown in FIG. It is good also as a structure provided only in 14b side. In this case, it is preferable to provide the conductive layer 16 also on the side end portion H (side surface 14c and slope 14d).

(Modification 3)
In the liquid crystal devices 1 and 1A described above, the microlens array substrates 10 and 10A are provided on the counter substrate 30, but the present invention is not limited to such a form. For example, the microlens array substrate 10 may be provided on the element substrate 20. Further, the microlens array substrate 10 may be provided on both the element substrate 20 and the counter substrate 30.

(Modification 4)
The electronic apparatus to which the liquid crystal devices 1 and 1A according to the above embodiments can be applied is not limited to the projector 100. The liquid crystal devices 1 and 1A are, for example, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type, or a monitor direct-view type. It can be suitably used as a display unit for information terminal devices such as video recorders, car navigation systems, electronic notebooks, and POS.

  DESCRIPTION OF SYMBOLS 1,1A ... Liquid crystal device (electro-optical device) 10, 10A, 60, 61, 62, 63, 65 ... Micro lens array substrate, 11, 14 ... Substrate, 11a, 14a ... Surface (second surface), 11b, 14b ... surface (first surface), 12 ... concave, 13 ... lens layer, 13a ... lens material layer (second layer), 15, 16 ... conductive layer (first layer), 20 ... element substrate (first) Substrate), 30, 30A ... counter substrate (second substrate), 40 ... liquid crystal layer (electro-optic layer), 100 ... projector (electronic device), F ... first region, G ... second region, H ... side End, ML ... micro lens.

Claims (8)

Forming a first layer in the second region of the first surface of the substrate having optical transparency;
Forming a plurality of recesses in a first region of the first surface of the substrate;
Forming a second layer having light transmittance and a refractive index different from that of the substrate so as to cover the plurality of recesses and the first layer of the first surface of the substrate. A method of manufacturing a microlens array substrate, comprising: A method of manufacturing a microlens array substrate according to claim 1,
The method of manufacturing a microlens array substrate, wherein the first layer is formed up to a side end portion of the substrate. A method of manufacturing a microlens array substrate according to claim 1 or 2,
The step of forming the first layer includes:
Forming a conductive layer so as to cover the first surface of the substrate and the second surface opposite to the first surface;
Removing a portion of the conductive layer that covers the first region of the first surface,
The method for manufacturing a microlens array substrate, wherein the first layer is a part of the conductive layer. A method of manufacturing a microlens array substrate according to any one of claims 1 to 3,
A method for manufacturing a microlens array substrate, wherein the Poisson ratio of the material of the first layer is larger than the Poisson ratio of the substrate and the Poisson ratio of the material of the second layer. A method of manufacturing a microlens array substrate according to claim 4,
The method of manufacturing a microlens array substrate, wherein the material of the first layer is silicon.   A microlens array substrate manufactured by the method for manufacturing a microlens array substrate according to any one of claims 1 to 5. A first substrate;
A second substrate disposed opposite to the first substrate;
An electro-optic layer disposed between the first substrate and the second substrate,
An electro-optical device comprising the microlens array substrate according to claim 6 on at least one of the first substrate and the second substrate.   An electronic apparatus comprising the electro-optical device according to claim 7.

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