JP2015082668A - Pll synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output a wideband signal having low noise and good spurious characteristics.SOLUTION: A PLL synthesizer includes: a phase comparator 12 for detecting a phase difference between a reference signal and an input signal; a voltage-controlled oscillator 15 for generating an oscillation signal having a frequency corresponding to the phase difference detected by the phase comparator 12; a mixing unit 16 which mixes the oscillation signal with a local signal to output a mixing signal; a band limiting unit 20 which is provided between the mixing unit 16 and the phase comparator 12 and whose pass frequency band is variable; and a control unit 30 for controlling the pass frequency band of the band limiting unit 20.

Description

  The present invention relates to a PLL synthesizer.

  As a method for improving the phase noise of an output signal in a PLL synthesizer, it is known to reduce a multiplication number that is a magnification of an output frequency with respect to a phase comparison frequency. In order to reduce the multiplication number, it is conceivable to increase the phase comparison frequency. However, if the phase comparison frequency is increased, the variable frequency step is also increased, which causes a problem that the channel interval of the radio using the PLL synthesizer does not match. In order to solve this problem, means for reducing the apparent multiplication number by converting the output frequency to a low frequency by mixing and returning it to the phase comparator is known (see, for example, Patent Document 1). .

JP 2006-33042 A

  By the way, the noise level suppressed by the PLL synthesizer is represented by a value obtained by adding 10 Log (fcomp) +20 LogN to noise mainly generated by the phase comparator. Here, fcomp is a phase comparison frequency, and N is a multiplication number. From the above formula, it can be seen that a noise suppression improvement effect of 6 dB can be obtained when the multiplication factor is halved.

  FIG. 8 is a diagram showing a configuration of a conventional PLL synthesizer 100 that reduces the number of multiplications by inputting a signal obtained by frequency-converting the frequency of the output signal to the phase comparator. In the PLL synthesizer 100, the oscillation signal output from the voltage controlled oscillator 116 is input to the mixing unit 117 and mixed with the local signal output from the local oscillator 118. A filter 119 is provided between the mixing unit 117 and the phase comparator 113, and the mixed signal blocks the spurious component generated by the mixing in the filter 119 and then passes through the N counter 112B to the phase comparator 113. Entered.

  However, if the filter 119 is a narrow band filter to sufficiently cut off the spurious component, the output frequency of the voltage controlled oscillator 116 is cut off while the PLL is locked. As a result, there is a problem that the signal level input to the phase comparator 113 is lowered and the PLL cannot be locked.

  On the other hand, if the PLL can be locked by making the bandwidth of the filter 119 wider than the output frequency range of the voltage controlled oscillator 116, the filter 119 needs to be widened as the output frequency becomes wider. As a result, the filter 119 has a problem that the spurious component is not sufficiently attenuated, and the spurious level of the output signal of the PLL synthesizer 100 increases.

  Therefore, the present invention has been made in view of these points, and an object thereof is to provide a PLL synthesizer that can output a broadband signal having low noise and good spurious characteristics.

  A PLL synthesizer according to the present invention includes a phase comparator that detects a phase difference between a reference signal and an input signal, a voltage-controlled oscillator that generates an oscillation signal having a frequency corresponding to the phase difference detected by the phase comparator, A mixing unit that mixes the oscillation signal and the local signal and outputs a mixing signal; a band limiting unit that is provided between the mixing unit and the phase comparator; A control unit that controls the pass frequency band of the limiting unit.

  The band limiting unit includes, for example, a filter having a variable pass frequency band, and a transmission line having a pass frequency band equal to or higher than a frequency bandwidth that can be oscillated by the voltage-controlled oscillator. A signal that passes through the signal is input to the phase comparator as the input signal.

  For example, in a state where the PLL synthesizer is not locked, the control unit sets the pass frequency band of the band limiting unit to a frequency band greater than or equal to a frequency bandwidth that can be oscillated by the voltage controlled oscillator. After the synthesizer is locked, the frequency band is set such that the oscillation signal passes and unnecessary waves do not pass.

  The band limiting unit further includes a selection unit that selects one of the filter and the transmission line, and the control unit is configured to connect the transmission line to the selection unit in a state where the PLL synthesizer is not locked. And the filter may be selected by the selection unit after the PLL synthesizer is locked.

  The filter includes, for example, a plurality of sub-filters having different pass frequency bands and connected in parallel to each other, and the transmission path is provided in parallel with the plurality of sub-filters. A signal in a frequency band including all the pass frequency bands of the sub-filter is passed.

  The control unit causes the selection unit to select the transmission path in a state where the PLL synthesizer is not locked, and in a state where the PLL synthesizer is locked, among the plurality of sub-filters included in the filter, You may make the selection part select the sub filter which an oscillation signal passes and does not let an unnecessary wave pass.

  The band limiting unit may include a passband variable filter having a variable capacitance element whose capacitance changes according to an input control voltage. In this case, the control unit controls a control voltage applied to the variable capacitance element based on whether or not the PLL synthesizer is locked.

  According to the present invention, it is possible to output a broadband signal having low noise and good spurious characteristics.

It is a figure which shows the structure of the PLL synthesizer which concerns on 1st Embodiment. It is a figure which shows the pass frequency band of the band-limiting part in the state where the PLL synthesizer is not locked. It is a figure which shows the pass frequency band of the band limitation part after a PLL synthesizer locks. It is an operation | movement flowchart of a PLL synthesizer. It is a figure which shows the structure of the PLL synthesizer which concerns on 2nd Embodiment. It is a figure which shows the internal structure of a tunable filter. It is a figure which shows a mode that the passable frequency band of a tunable filter changes. It is a figure which shows the structure of the PLL synthesizer which concerns on 3rd Embodiment. It is a figure which shows the structure of the conventional PLL synthesizer.

<First Embodiment>
FIG. 1 is a diagram illustrating a configuration of a PLL synthesizer 1 according to the first embodiment.
The PLL synthesizer 1 includes a reference oscillator 10, an R counter 11A, an N counter 11B, a phase comparator 12, a charge pump circuit 13, a loop filter 14, a voltage control oscillator 15, a mixing unit 16, a local oscillator 17, a band limiting unit 20, and a control. Unit 30, storage unit 40, and lock detection unit 50.

  The reference oscillator 10 includes a crystal resonator, for example, and outputs a reference oscillation signal having a predetermined oscillation frequency. The R counter 11 </ b> A divides the reference oscillation signal output from the reference oscillator 10 to generate an R divided signal, and inputs the R divided signal to the phase comparator 12. The N counter 11 </ b> B divides the signal output from the band limiting unit 20 to generate an N divided signal, and inputs the N divided signal to the phase comparator 12.

  The phase comparator 12 detects a phase difference between the reference signal and the input signal. Specifically, the phase of the R divided signal input from the R counter 11A is compared with the phase of the N divided signal input from the N counter 11B, and a voltage corresponding to the phase difference is supplied to the charge pump circuit 13. Output. The charge pump circuit 13 outputs a charge pump signal having a voltage corresponding to the phase comparison result from the phase comparator 12 to the loop filter 14.

  The loop filter 14 is a low-pass filter that passes a frequency component lower than a predetermined cutoff frequency, which is included in the charge pump signal input from the charge pump circuit 13. The loop filter 14 is, for example, a lag lead filter. The signal that has passed through the loop filter 14 is input to the voltage controlled oscillator 15.

  The voltage controlled oscillator 15 generates an oscillation signal having a frequency corresponding to the phase difference detected by the phase comparator 12. That is, the voltage controlled oscillator 15 generates an oscillation signal having a frequency corresponding to the voltage of the signal that has passed through the loop filter 14. The oscillation signal generated by the voltage controlled oscillator 15 is output to the outside of the PLL synthesizer 1 and also input to the mixing unit 16.

  The mixing unit 16 mixes the oscillation signal output from the voltage controlled oscillator 15 and the local signal output from the local oscillator 17 and outputs a mixing signal. The mixing signal output from the mixing unit 16 is input to the band limiting unit 20.

  The band limiting unit 20 is provided between the mixing unit 16 and the phase comparator 12. The band limiting unit 20 has a variable pass frequency band. The band limiting unit 20 receives the input of the mixing signal from the mixing unit 16 and outputs a signal obtained by limiting the frequency band of the signal input from the mixing unit 16 to a predetermined pass frequency band via the N counter 11B. To enter.

  Specifically, the band limiting unit 20 includes a filter 203 having a variable pass frequency band, a transmission line 204 having a pass frequency band greater than or equal to a frequency bandwidth that can be oscillated by the voltage controlled oscillator 15, and the filter 203 and the transmission line 204. It has the selection part 201 and the selection part 202 which select any one. The filter 203 has a plurality of sub-filters having different pass frequency bands and connected in parallel to each other. The transmission path 204 is provided in parallel with the plurality of sub-filters, and passes signals in a frequency band including all the pass frequency bands of the plurality of sub-filters. That is, the transmission line 204 can pass all oscillation signals that can be output by the voltage controlled oscillator 15.

  The selection unit 201 and the selection unit 202 switch internal connections based on the control of the control unit 30. Specifically, based on the control of the control unit 30, the selection unit 201 selects which of the plurality of sub-filters and the transmission path 204 included in the filter 203 is connected to the output side of the mixing unit 16. . Also. Based on the control of the control unit 30, the selection unit 202 selects which of the plurality of sub-filters and the transmission path 204 included in the filter 203 are connected to the phase comparator 12.

  The control unit 30 is configured by a CPU, for example. The control unit 30 performs control for switching the internal connection of the selection unit 201 and the selection unit 202 based on, for example, data input from the outside or a condition defined in a program stored in the storage unit 40. In addition, the control unit 30 sets counter values based on the frequency set from the outside in the R counter 11A and the N counter 11B.

  The control unit 30 performs control so as to switch between a connection state of the selection unit 201 and the selection unit 202 in a state where the PLL synthesizer 1 is not locked and a connection state of the selection unit 201 and the selection unit 202 after being locked. The frequency band of the signal input to the phase comparator 12 is switched before and after the lock. More specifically, the control unit 30 selects the transmission line 204 for the selection unit 201 and the selection unit 202 in a state where the control system including the phase comparator 12, the voltage control oscillator 15, and the band limiting unit 20 is not locked. In the state where the control system is locked, the selection unit 201 and the selection unit 202 are made to select the sub-filter that passes the signal of the oscillation signal frequency and does not pass the unnecessary wave among the plurality of sub-filters. Here, the unnecessary wave is a signal including harmonic components and spurious components other than the frequency of the mixing signal to be input to the phase comparator 12.

  As described above, the control unit 30 sets the pass frequency band of the band limiting unit 20 to a frequency band greater than or equal to the frequency bandwidth that the voltage control oscillator 15 can oscillate in a state where the control system is not locked. Is set to a frequency band in which an oscillation signal output from the voltage controlled oscillator 15 passes and an unnecessary wave does not pass. The band limiting unit 20 selectively passes the highest level mixing signal output from the mixing unit 16 after the control system is locked under the control of the control unit 30.

  FIG. 2A is a diagram illustrating a pass frequency band of the band limiting unit 20 in a state where the PLL synthesizer 1 is not locked. FIG. 2B is a diagram illustrating a pass frequency band of the band limiting unit 20 after the PLL synthesizer 1 is locked. 2A and 2B, the horizontal axis indicates the frequency, and the vertical axis indicates the signal passing level of the band limiting unit 20. A region surrounded by a dotted line in FIGS. 2A and 2B is a pass frequency band of the band limiting unit 20.

  In FIG. 2A, the frequencies of all oscillation signals that can be output by the voltage controlled oscillator 15 are included in the pass frequency band, whereas in FIG. 2B, one oscillation that can be output by the voltage controlled oscillator 15 is included. Only the frequency of the signal is included in the pass frequency band. When the control unit 30 controls the selection unit 201 and the selection unit 202, the pass frequency band indicated by the dotted line in FIG. 2B moves.

  The storage unit 40 is a writable / readable non-volatile memory such as an EEPROM and a RAM. The storage unit 40 stores a program that causes the control unit 30 to operate, and stores data that the control unit 30 uses to control the selection unit 201 and the selection unit 202.

  The lock detection unit 50 detects whether or not the control system including the phase comparator 12, the voltage controlled oscillator 15, and the band limiting unit 20 is locked. For example, the lock detection unit 50 detects that the phase difference detected by the phase comparator 12 is not locked when the phase difference is not within a predetermined range, and locks when the phase difference is within the predetermined range. Detects that The lock detection unit 50 inputs a lock detection signal having a logical value 0 to the control unit 30 when the control system is not locked, and outputs the lock detection signal having a logical value 1 to the control unit 30 when the control system is locked. To enter.

  FIG. 3 is an operation flowchart of the PLL synthesizer 1. When the control unit 30 obtains an instruction of the set frequency from the outside (S1), the control unit 30 controls the selection unit 201 and the selection unit 202 to select the transmission path 204 as a passing path for the mixing signal (S2). Subsequently, the control unit 30 sets counter values corresponding to the set frequency acquired in S1 in the R counter 11A and the N counter 11B (S3), and the logical value of the lock detection signal output from the lock detection unit 50 Is monitored (S4).

  When the logical value of the lock detection signal is 0 in S4, the control unit 30 determines that the control system is not locked and continues monitoring the logical value of the lock detection signal. When the logical value of the lock detection signal is 1 in S4, the control unit 30 determines that the control system is locked, and controls the selection unit 201 and the selection unit 202 to set as a passing path for the mixing signal. A subfilter capable of passing a mixing signal corresponding to the frequency is selected (S5). By the above procedure, the PLL synthesizer 1 can lock to the set frequency and output a wideband signal having good spurious characteristics.

[Effect in the first embodiment]
As described above, according to the PLL synthesizer 1 according to the first embodiment, the band limiting unit 20 has a filter with a variable pass frequency band and a pass frequency band that is equal to or higher than the frequency bandwidth that the voltage controlled oscillator 15 can oscillate. Having a transmission line. Therefore, in a state where the control system is not locked, the pass frequency band of the band limiting unit 20 is set to a band through which a broadband signal passes, and the oscillation signal output from the voltage controlled oscillator 15 after the control system is locked is set. By setting the frequency band in which the signal of the frequency passes and does not allow the unnecessary wave to pass, the PLL synthesizer 1 can output a broadband signal having low noise and good spurious characteristics. .

<Second Embodiment>
FIG. 4 is a diagram illustrating a configuration of the PLL synthesizer 1 according to the second embodiment. A PLL synthesizer 1 shown in FIG. 4 has a tunable filter (pass-band variable filter) 300 having a variable capacitance element whose capacitance changes according to a control voltage input to the band limiting unit 20 instead of the filter 203 in FIG. And a transmission path 204 provided in parallel with the tunable filter 300. A digital-analog converter 60 is provided between the control unit 30 and the band limiting unit 20. The digital-analog converter 60 converts the digital signal output from the control unit 30 into an analog signal, and inputs the converted analog signal to the variable capacitance element of the tunable filter 300.

  FIG. 5 is a diagram illustrating an internal configuration of the tunable filter 300. The tunable filter 300 includes an inductor 301, a capacitor 302, a resistor 303, a variable capacitor 304, a variable capacitor 305, a resistor 306, a capacitor 307, an inductor 308, an inductor 309, a capacitor 310, a capacitor 311, a variable capacitor 312 and a resistor. 313. The inductor 301 is connected to an input terminal connected to the selection unit 201. The inductor 308 is connected to an output terminal connected to the selection unit 202.

  The variable capacitance element 304, the variable capacitance element 305, and the variable capacitance element 312 are, for example, varicap diodes. The cathodes of the variable capacitor 304 and the variable capacitor 305 are connected to the control voltage terminal Vc1 via a resistor 303 and a resistor 306, respectively. The cathode of the variable capacitance element 312 is connected to the control voltage terminal Vc2 via the resistor 313. The control voltage terminal Vc1 and the control voltage terminal Vc2 are connected to the digital / analog converter 60, and receive a control voltage output from the digital / analog converter 60 under the control of the control unit 30.

  The capacitance values of the variable capacitance element 304 and the variable capacitance element 305 change according to the control voltage applied to the control voltage terminal Vc1. The capacitance value of the variable capacitance element 312 changes according to the control voltage applied to the control voltage terminal Vc2. When the capacitance values of the variable capacitance element 304, the variable capacitance element 305, and the variable capacitance element 312 change, the frequency characteristics of the tunable filter 300 change, and the passable frequency band of the tunable filter 300 changes.

  FIG. 6 is a diagram illustrating how the passable frequency band of the tunable filter 300 changes due to changes in the control voltage applied to the control voltage terminal Vc1 and the control voltage terminal Vc2. The horizontal axis in FIG. 6 indicates the frequency (MHz), and the vertical axis indicates the pass level (dB). FIG. 6 shows the pass characteristics when four different control voltages are applied to the tunable filter 300, and it can be seen that the pass characteristics change by changing the control voltage.

  In a state where the control system is not locked, the control unit 30 controls the selection unit 201 and the selection unit 202 to select the transmission path 204 as a passing path for the mixing signal. After the control system is locked, the control unit 30 controls the selection unit 201 and the selection unit 202 to select the tunable filter 300 as a mixing signal passage path. In addition, the control unit 30 sets the variable capacitance element 305, the variable capacitance element 312 and the variable capacitance so that a signal having a frequency of the oscillation signal output from the voltage controlled oscillator 15 passes and does not allow unnecessary waves to pass. A control voltage applied to the element 312 is controlled.

[Effects of Second Embodiment]
According to the PLL synthesizer 1 according to the second embodiment, by using the tunable filter 300, it is possible to perform fine frequency adjustment in a narrow band with a smaller number of parts than in a configuration in which a plurality of sub-filters are provided. The effect of becoming.

<Third Embodiment>
FIG. 7 is a diagram illustrating a configuration of the PLL synthesizer 1 according to the third embodiment. The band limiting unit 20 in the PLL synthesizer 1 illustrated in FIG. 7 includes the tunable filter 320 and does not include the selection unit 201, the selection unit 202, and the transmission path 204, and is illustrated in FIG. 4 according to the second embodiment. Different from the PLL synthesizer 1. The tunable filter 320 is controlled by the control unit 30 without going through the digital-analog converter 60.

  The tunable filter 320 according to the present embodiment incorporates a transistor that switches a signal passing path and a variable capacitance element for changing a passing frequency band, and can change the passing frequency bandwidth and the passing frequency band. it can. Specifically, the tunable filter 320 is based on the setting information input from the control unit 30 and is one of a plurality of pass frequency bands through which the signal of the oscillation signal passes and does not pass unnecessary waves, or The pass frequency band can be switched to a frequency band in which the voltage controlled oscillator 15 can oscillate.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 Synthesizer, 10 Reference Oscillator, 11A R Counter, 11B N Counter, 12 Phase Comparator, 13 Charge Pump Circuit, 14 Loop Filter, 15 Voltage Control Oscillator, 16 Mixing Unit, 17 Local Oscillator, 20 Band Limiting Unit, 30 Control Unit , 40 storage unit, 50 lock detection unit, 60 digital analog converter, 100 synthesizer, 112A R counter, 112B N counter, 113 phase comparator, 116 voltage controlled oscillator, 117 mixing unit, 118 local oscillator, 119 filter, 201 selection Part, 202 selection part, 203 filter, 204 transmission line, 300 tunable filter, 301 inductor, 302 capacitor, 303 resistance, 304 variable capacity element, 305 variable capacity element, 306 resistance, 307 capacity Sita, 308 inductor, 309 inductor, 310 capacitor, 311 capacitor, 312 variable capacitance element, 313 resistance

Claims (8)

A phase comparator that detects the phase difference between the reference signal and the input signal;
A voltage controlled oscillator that generates an oscillation signal having a frequency corresponding to the phase difference detected by the phase comparator;
A mixing unit that mixes the oscillation signal and the local signal and outputs a mixing signal;
A band limiting unit provided between the mixing unit and the phase comparator, and having a variable pass frequency band;
A control unit for controlling the pass frequency band of the band limiting unit;
A PLL synthesizer comprising: The band limiting unit includes a filter having a variable pass frequency band, and a transmission line having a pass frequency band equal to or higher than a frequency bandwidth that can be oscillated by the voltage-controlled oscillator. The passed signal is input to the phase comparator as the input signal.
The PLL synthesizer according to claim 1. The control unit sets the pass frequency band of the band limiting unit to a frequency band greater than or equal to a frequency bandwidth that can be oscillated by the voltage controlled oscillator in a state where the PLL synthesizer is not locked, and the PLL synthesizer After locking, set to a frequency band through which the oscillation signal passes and does not pass unwanted waves,
The PLL synthesizer according to claim 2. The band limiting unit further includes a selection unit that selects one of the filter and the transmission path,
The control unit causes the selection unit to select the transmission path in a state where the PLL synthesizer is not locked, and causes the selection unit to select the filter after the PLL synthesizer is locked.
The PLL synthesizer according to claim 2 or 3. The filter has a plurality of sub-filters each having a different pass frequency band and connected in parallel to each other, and the transmission path is provided in parallel with the plurality of sub-filters. Pass the signal in the frequency band including all the pass frequency bands of the filter,
The PLL synthesizer according to claim 4. The control unit causes the selection unit to select the transmission path in a state where the PLL synthesizer is not locked, and in a state where the PLL synthesizer is locked, among the plurality of sub-filters included in the filter, Causing the selection unit to select a sub-filter through which an oscillation signal passes and does not pass an unnecessary wave;
The PLL synthesizer according to claim 5. The band limiting unit includes a passband variable filter having a variable capacitance element whose capacitance changes according to an input control voltage.
The PLL synthesizer according to any one of claims 1 to 4. The control unit controls a control voltage applied to the variable capacitance element based on whether the PLL synthesizer is locked;
The PLL synthesizer according to claim 7.