JP2015082063A - Display device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress degradation of gradation expression by enlargement and high resolution of a display device.SOLUTION: The driving method of a display device having pixels provided corresponding to intersections where a plurality of data signal lines connected with a data driver intersect a plurality of scan lines connected with a scan driver comprises: obtaining a gradation voltage specifying the gradation of a pixel; calculating a first delay correction value on the basis of a voltage held by a data signal line outputting the obtained gradation voltage and the gradation voltage; and determining timing outputting the gradation voltage to the data signal line on the basis of the first delay correction value.

Description

  The present invention relates to a technique for driving an active matrix display device.

  In recent years, display devices such as liquid crystal displays and organic EL displays have been increased in size and resolution. For this reason, the wiring load of the signal line for controlling each pixel increases, and the signal supplied from the driver becomes dull. The effect of this dullness increases as the distance from the driver increases. When writing a gradation voltage that specifies the gradation of a pixel to the pixel circuit, the greater the effect of dullness, the longer it takes to approach the target gradation voltage. It is written in the circuit, and the gradation expression is lowered. This drop in gradation expression appears as a dependency on the distance from the driver.

  If the update time of the gradation voltage for each pixel can be lengthened, it can be brought closer to the target gradation voltage, so that the influence of dullness can be reduced. However, in the present situation where higher resolution is also desired, the grayscale voltage update time is further shortened and tends to be greatly affected by dullness.

  In order to solve such a problem, for example, in Patent Document 1, another capacitor is added so as to cancel the difference in wiring capacitance due to a difference in distance from the driver, and the driver can connect each pixel. A technique for reducing the distance dependency of the capacity is disclosed.

JP 2012-237806 A

  In the technique described in Patent Document 1, circuit arrangement with a different layout is required for each pixel, which may cause display variations depending on the layout, resulting in a reduction in gradation expression. Further, the larger the difference between the gray scale voltage written in the immediately preceding horizontal period and the gray scale voltage to be written in the current horizontal period, the greater the difference between the gray scale voltage to be written into the pixel circuit. This influence causes a reduction in gradation expression, and becomes more noticeable as the gradation voltage update time is shorter.

  One of the objects of the present invention is to suppress deterioration in gradation expression due to an increase in the size and resolution of a display device.

  According to one embodiment of the present invention, a plurality of data signal lines connected to a data driver and a plurality of scanning lines connected to a scan driver intersect, and a display device having pixels provided corresponding to the intersection And means for acquiring a gradation voltage for designating a gradation of the pixel, a voltage held by the data signal line to which the acquired gradation voltage is output, and the gradation voltage. A display device comprising: means for calculating a first delay correction value; and means for determining a timing for outputting the gradation voltage to the data signal line based on the first delay correction value. Provided.

  According to this display device, it is possible to suppress a reduction in gradation expression due to an increase in size and resolution of the display device.

  In another preferred embodiment, the data signal further comprises means for calculating a second delay correction value based on a position of a scanning line corresponding to the pixel whose gradation is designated by the acquired gradation voltage. The timing for outputting the gradation voltage to the line may be determined based on the first delay correction value and the second delay correction value.

  According to this display device, it is possible to further suppress a reduction in gradation expression due to an increase in the size and resolution of the display device.

  In another preferable aspect, the second delay correction value may be calculated based on a CR time constant of the data signal line.

  According to this display device, it is possible to suppress deterioration in gradation expression due to the capacity of the data signal line.

  In another preferred embodiment, the voltage held by the data signal line may indicate a voltage based on a grayscale voltage output last time to the data signal line.

  According to this display device, it is possible to further suppress a reduction in gradation expression with an easy configuration.

  In another preferred aspect, the data signal line further includes means for outputting a precharge voltage before outputting the gradation voltage to the data signal line, and the voltage held by the data signal line includes the precharge voltage. May be shown.

  According to this display device, it is possible to further suppress a reduction in gradation expression with an easy configuration.

  According to one embodiment of the present invention, a plurality of data signal lines connected to a data driver and a plurality of scanning lines connected to a scan driver intersect, and a display device having pixels provided corresponding to the intersection The grayscale voltage designating the grayscale of the pixel is acquired, the voltage held by the data signal line to which the acquired grayscale voltage is output, and the grayscale voltage A display device driving method is provided, wherein a first delay correction value is calculated based on the first delay correction value, and a timing for outputting the gradation voltage to the data signal line is determined based on the first delay correction value. .

  According to the driving method of the display device, it is possible to further suppress the reduction in gradation expression due to the increase in size and resolution of the display device.

  In another preferable aspect, the method further includes calculating a second delay correction value based on a position of a scanning line corresponding to the pixel to which the acquired gradation voltage is output, and The timing for outputting the gradation voltage may be determined based on the first delay correction value and the second delay correction value.

  According to the driving method of the display device, it is possible to further suppress the reduction in gradation expression due to the increase in size and resolution of the display device.

  In another preferable aspect, the second delay correction value may be calculated based on a CR time constant of the data signal line.

  According to this display device driving method, it is possible to suppress deterioration in gradation expression due to the capacity of the data signal line.

  In another preferred embodiment, the voltage held by the data signal line may indicate a voltage based on a grayscale voltage output last time to the data signal line.

  According to this display device driving method, it is possible to further suppress a reduction in gradation expression with an easy configuration.

  In another preferred aspect, the method further includes outputting a precharge voltage before outputting the grayscale voltage to the data signal line, and the voltage held by the data signal line includes the precharge voltage. May be shown.

  According to this display device driving method, it is possible to further suppress a reduction in gradation expression with an easy configuration.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a gradation expressivity falls by the enlargement of a display apparatus and high resolution.

It is the schematic which shows the structure of the electronic device 1 in 1st Embodiment of this invention. 1 is a circuit diagram illustrating a configuration of a pixel circuit 100 according to a first embodiment of the present invention. It is a block diagram which shows the structure of the data driver 20 in 1st Embodiment of this invention. FIG. 2 is a block diagram showing a configuration of a data driver output control circuit 21 in the first embodiment of the present invention. It is a timing chart of each signal in a 1st embodiment of the present invention. It is a figure explaining the column direction panel position dependence of the voltage change (when a gradation change is constant) at the time of data writing in a prior art. It is a figure explaining the column direction panel position dependence of the voltage change (when a gradation change is constant) at the time of the data writing in 1st Embodiment of this invention. It is a figure explaining the relationship between delay time TS and column direction panel position in 1st Embodiment of this invention. It is a figure explaining the gradation voltage difference dependence of the voltage change at the time of the data writing in a prior art (when a column direction panel position is constant). It is a figure explaining the gradation voltage difference dependence of the voltage change at the time of the data writing in 1st Embodiment of this invention (when a column direction panel position is constant). It is a figure explaining the gradation voltage difference in 1st Embodiment of this invention. It is a figure explaining the relationship between delay time TD and a gradation voltage difference in 1st Embodiment of this invention. It is a block diagram which shows the structure of the data driver 20A in 2nd Embodiment of this invention. It is a block diagram which shows the structure of 21 A of data driver output control circuits in 2nd Embodiment of this invention. It is a timing chart of each signal in a 2nd embodiment of the present invention. It is a figure explaining the gradation voltage difference dependence of the voltage change at the time of the data writing in 2nd Embodiment of this invention (when a column direction panel position is constant). It is a figure explaining the gradation voltage difference in 2nd Embodiment of this invention. It is a figure explaining the relationship between delay time TD and a gradation voltage difference in 2nd Embodiment of this invention.

  Hereinafter, electronic devices according to embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are examples of the embodiments of the present invention, and the present invention is not construed as being limited to these embodiments, and various modifications can be made. Further, in the drawings referred to in this embodiment, the same reference numerals or similar reference numerals (for example, A, B, (1), (2), etc. are added after numbers) to the same parts or parts having similar functions. May be omitted, and repeated description thereof may be omitted.

<First Embodiment>
An electronic apparatus according to a first embodiment of the present invention will be described in detail with reference to the drawings.

[overall structure]
FIG. 1 is a schematic diagram showing a configuration of an electronic apparatus 1 according to the first embodiment of the present invention. The electronic device 1 is a device having a display unit that displays an image, such as a smartphone, a mobile phone, a personal computer, or a television. The electronic device 1 includes a display device 10, a control unit 80, and a power source 90. The display device 10 includes a pixel circuit 100 for each pixel arranged in a matrix. The display device 10 is an organic EL display that constitutes a display unit by displaying an image by causing a light emitting diode to emit light at a gradation corresponding to a gradation voltage written in each pixel circuit 100. Note that the display device 10 may be a liquid crystal display instead of an organic EL display, and may be any device that displays an image expressed with a gradation corresponding to a gradation voltage written in each pixel circuit 100.

  The control unit 80 includes a CPU (Central Processing Unit), a memory, and the like, and is a controller that controls the operation of the display device 10. The control unit 80 controls the data driver 20 and the scan driver 30. In addition, the control unit 80 receives gradation data indicating the gradation of each pixel of the image displayed on the display unit of the electronic device 1, and determines the gradation of each pixel based on the input gradation data. Then, the control unit 80 controls the data driver 20 and the scan driver 30 so that the gradation voltage corresponding to the gradation is written in the pixel circuit 100 to cause the light emitting diode EL of each pixel circuit 100 to emit light.

  The power supply 90 supplies power to each unit of the electronic device 1 such as the display device 10 and the control unit 80. The current from the anode to the cathode of the light emitting diode EL of each pixel circuit 100 in the display device 10 is supplied from the power supply 90. At this time, the power supply 90 applies, for example, an anode voltage ELVDD and a cathode voltage ELVSS described later.

[Configuration of Display Device 10]
The display device 10 includes the pixel circuit 100, the data driver 20, and the scan driver 30 described above. Each pixel provided with the pixel circuit 100 is provided corresponding to the intersection of the plurality of scanning lines 140 and the plurality of data signal lines 150, and is arranged in a matrix of n rows and m columns. Now, as shown in FIG. 1, it is assumed that they are arranged in a matrix of 3 rows and 3 columns in a simplified manner. In FIG. 1, the wiring load of the data signal line 150 is schematically indicated by a capacitor C and a resistor R. In FIG. 1, pixel circuits 100a, 100b, and 100c are shown in order from the pixel circuit closest to the data driver 20, but are simply referred to as the pixel circuit 100 when they are not particularly distinguished. Details of the display device 10 will be described later.

  The data driver 20 receives signals such as a latch signal LAT, a clock signal CLK, and display data under the control of the control unit 80, and each pixel circuit is connected to a data signal line 150 provided corresponding to the pixel circuit 100 in each column. A data signal DT for writing the gradation voltage Vd to 100 is supplied. The display data is data generated by the control unit 80 based on the gradation data, and is data indicating the gradation voltage of each pixel. The data signal DT (q) is a signal supplied to the q-th column (q = 1, 2, 3). DTa, DTb, and DTc indicate data signals of portions connected to the pixel circuits 100a, 100b, and 100c of the data signal line 150 (see FIG. 6 and the like). As described above, due to the influence of the wiring load on the data signal line 150, the data signal DT becomes the signals DTa, DTb, and DTc that are dulled by the time constants of the wiring resistance R and the wiring capacitance C as the distance from the data driver 20 increases. .

  The scan driver 30 sequentially and exclusively selects the rows of the pixel circuits 100 to which the gradation voltage is written by the scan signal SCAN supplied to the scanning line 140 provided corresponding to the image circuit 100. In this way, the gradation voltage Vd indicated by the data signal DT supplied to the data signal line 150 is written into the pixel circuit 100 in the selected row. The scan signal SCAN (p) is a signal supplied to the p-th row (p = 1, 2, 3). The scan signal SCAN corresponding to the pixel circuit 100 in the selected row becomes L level, and the corresponding scan signal SCAN corresponding to the pixel circuit 100 in the unselected row becomes H level.

[Configuration of Pixel Circuit 100]
FIG. 2 is a circuit diagram showing a configuration of the pixel circuit 100 according to the first embodiment of the present invention. The pixel circuit 100 includes a light emitting diode EL that is an organic EL. The cathode of the light emitting diode EL is connected to the power supply line of the cathode voltage ELVSS. The pixel circuit 100 includes two transistors M1 and M2 and one capacitor element C1. These transistors are p-type TFTs (thin film transistors). Note that the transistor may be n-type, and in that case, a circuit may be configured so that a similar operation can be realized in the n-type transistor.

  One terminal of the source / drain terminal of the transistor M1 is connected to the anode of the light emitting diode EL, and the other terminal is connected to the power supply line of the anode voltage ELVDD. The other terminal is connected to the gate terminal of the transistor M1 through the capacitive element C1. The gate terminal of the transistor M1 and the data signal line 150 are connected via the transistor M2. The gate terminal of the transistor M2 is connected to the scanning line 140.

  When the scanning line 140 is selected, the transistor M2 is turned on, the data signal line 150 is connected to the gate terminal of the transistor M1, and the gradation voltage is written. When the gradation voltage is set to the gate voltage VG, a current amount corresponding to the gradation voltage flows through the transistor M1, and the light emitting diode EL emits light with an intensity corresponding to the current amount. Thereby, the gradation expressed in each pixel is a gradation corresponding to the gradation voltage set to the gate voltage VG.

  Note that the above-described configuration of the pixel circuit 100 is an example, and any circuit may be used as long as gradation is expressed according to the gradation voltage written in the pixel circuit 100. When the display device 10 is a liquid crystal display, the pixel circuit 100 may be a circuit that applies the written gradation voltage to the liquid crystal element. A known technique may be used for such a circuit.

[Configuration of Data Driver 20]
FIG. 3 is a block diagram showing the configuration of the data driver 20 in the first embodiment of the present invention. The data driver 20 is provided with a data driver output control circuit 21 corresponding to each data signal line 150. Note that (1), (2), and (3) attached to the back of the code indicate that they are related to the data signal lines 150 in the first, second, and third columns, respectively. If there is no particular distinction between them, this will be omitted.

  The data driver output control circuit 21 takes in display data indicating a gradation voltage to be written in each pixel circuit 100 in synchronization with the clock signal CLK, and adjusts the timing for outputting the gradation voltage to the data signal line 150. . LAT is a signal that serves as a reference for timing of outputting a gradation voltage. This reference is represented by an L level signal, for example. Hereinafter, this L level signal is referred to as LAT (in).

  When the timing for outputting the gradation voltage to the data signal line 150 is not adjusted as in the prior art, the gradation expression is degraded due to the dullness of the data signal DT. This data driver output control circuit By adjusting the output timing 21, in the first embodiment of the present invention, a reduction in gradation expression due to the influence of the dullness of the data signal DT is suppressed.

  DELAY (LINE) input to the data driver output control circuit 21 is information related to the position of the scanning line 140 connected to the pixel circuit 100 to which the gradation voltage is written next (that is, the gradation voltage from the data driver 20). Information corresponding to the distance to the pixel circuit 100 to be written). In this example, DELAY (LINE) is information (delay correction value) corresponding to a delay time TS to be described later, and indicates a smaller value as the pixel circuit 100 to which the gradation voltage is written is farther from the data driver 20. The specific relationship between the distance from the data driver 20 and the delay time TS will be described later.

[Configuration of Data Driver Output Control Circuit 21]
FIG. 4 is a block diagram showing a configuration of the data driver output control circuit 21 in the first embodiment of the present invention. The data driver output control circuit 21 includes a data latch circuit A 211, a data latch circuit B 213, an output control circuit 215, an output buffer 217, a data comparison circuit 221, a delay time calculation circuit 223, and a delay control circuit 225.

  The data latch circuit A211 takes in display data (gradation voltage) and holds (latches) it in synchronization with the clock signal CLK. The data latch circuit B 213 outputs the held gradation voltage to the data signal line 150 via the output control circuit 215 and the output buffer 217 based on DELAY (OUT) obtained by delaying LAT (in). The gradation voltage output from the data latch circuit B 213 is also input to the data comparison circuit 221. The output control circuit 215 is, for example, a digital analog converter (DAC).

  The data latch circuit B213 takes in and holds the grayscale voltage held in the data latch circuit A211. As described above, the gradation voltage held in the data latch circuit B 213 indicates the voltage output to the data signal line 150 next, and the gradation voltage held in the data latch circuit A 211 is further applied to the data signal line next. The voltage output to 150 is shown.

  The data comparison circuit 221 includes the gradation voltage output from the data latch circuit B 213 (that is, the gradation voltage currently held in the data signal line 150) and the gradation voltage output next to the data signal line 150. (That is, the gradation voltage held in the data latch circuit B 213) and information DELAY (DATA) corresponding to the absolute value of the difference (hereinafter referred to as gradation voltage difference) to the delay time arithmetic circuit 223. Output. In this example, DELAY (DATA) is information (delay correction value) corresponding to a delay time TD described later, and indicates a smaller value as the grayscale voltage difference is larger. A specific relationship between the gradation difference voltage and the delay time TD will be described later.

  Based on DELAY (LINE) and DELAY (DATA), the delay time calculation circuit 223 calculates a time for delaying the output of the gradation voltage from the data latch circuit B213, and delay-controls information DELAY_SET corresponding to the delay time. Output to the circuit 225. This calculation is expressed as a product of DELAY (LINE) and DELAY (DATA), for example, DELAY_SET = DELAY (LINE) × DELAY (DATA).

  Therefore, DELAY_SET becomes smaller as the pixel circuit 100 to which the gradation voltage is written is farther from the data driver 20 and the gradation voltage difference is larger, and the gradation voltage difference is smaller as the pixel circuit 100 is closer to the data driver 20. As DELAY_SET increases. If DELAY_SET is calculated using DELAY (LINE) and DELAY (DATA) so that these relationships are satisfied, it is not necessarily limited to the product operation, and other calculation methods may be used. Good.

  The delay control circuit 225 outputs DELAY (OUT) obtained by delaying LAT (in) based on DELAY_SET to the data latch circuit B213. As described above, the data latch circuit B213 outputs a gradation voltage based on DELAY (OUT). Therefore, the timing at which the gradation voltage is output to the data signal line 150 is adjusted to a timing obtained by delaying the time corresponding to DELAY_SET with reference to LAT (in).

[Operation of Data Driver 20]
FIG. 5 is a timing chart of each signal in the first embodiment of the present invention. As for LAT, one horizontal period is defined in LAT (in) which becomes L level. DELAY (OUT) (q) corresponds to the data signal line 150 in the q-th column (q = 1, 2, 3). In the same horizontal period, DELAY (LINE) is the same in any column. Therefore, the relative timing shift of DELAY (OUT) shown in FIG. 5 is the difference between the gradation voltage written in the pixel circuit 100 in the immediately preceding horizontal period and the gradation voltage written in the pixel circuit 100 in the current horizontal period. This is based on the difference (grayscale voltage difference).

  Since the grayscale voltage Vd held in the data latch circuit B213 is output to the data signal line 150 at the timing when DELAY (OUT) becomes L level, the data signal DT is output from the timing at the next grayscale voltage Vd. To change.

  Subsequently, as described above, the effect of adjusting the output timing of the gradation voltage Vd to the data signal line 150 will be described in comparison with the operation of the prior art.

[Operation example of conventional technology (column direction panel position dependency)]
First, the panel position dependency of the write voltage in the column direction in the operation of the prior art will be described.

  FIG. 6 is a diagram for explaining the column-direction panel position dependency of voltage change (when gradation change is constant) during data writing in the prior art. Changes in the data signal DT and the gate voltage VG shown in FIG. 6 change from a high voltage to a low voltage when the gradation voltage changes from a low voltage to a high voltage (DT (Low Level) → DT (High Level)). The case (DT (High Level) → DT (Low Level)) is shown separately. Here, the amount of change in gradation voltage is the same.

  As can be seen from the comparison of the data signals DTa, DTb, and DTc, due to the wiring load of the data signal line 150, the signal becomes dull when the gradation voltage changes, and the level of dullness varies depending on the time constant. As the data signal DTc at a position farther from the data driver 20, the gradation voltage changes more slowly than the data signal DTa at a closer position. Therefore, since the amount of change from the start of change to the timing (sampling timing) written to the pixel circuit 100 is different, the gradation voltage written to the pixel circuit 100, that is, the gate voltage VG varies. VGa, VGb, and VGc correspond to gate voltages in the pixel circuits 100a, 100b, and 100c.

  Therefore, in the prior art, the gradation actually represented by the pixel position (panel position in the column direction) varies with respect to the gradation voltage to be written (ideal gradation voltage), and the column direction As a result, luminance unevenness with the panel position dependency occurs, so that gradation expression is degraded.

[Operation example of first embodiment (column direction panel position dependency)]
Subsequently, in the operation of the first embodiment of the present invention, the dependency of the write voltage on the panel position in the column direction will be described.

  FIG. 7 is a diagram for explaining the column-direction panel position dependency of voltage change (when gradation change is constant) during data writing in the first embodiment of the present invention. As shown in FIG. 7, the data signal DTc is delayed from TS1 to LAT (in), and the change of the gradation voltage is started. Similarly, the data signal DTb is delayed by TS2, and the data signal DTa is delayed by TS3, so that the change of the gradation voltage is started. The signal with less dullness in the data signal DT has a faster change in the gradation voltage. Therefore, the delay time is increased and the timing at which the change in the gradation voltage is started is delayed.

  In this way, by varying the timing at which the change in the gradation voltage is started, the data signals DTa, DTb, and DTc are set to substantially the same voltage level at the timing (sampling timing) written to the pixel circuit 100. be able to. In this way, the gradation voltage written to the pixel circuit 100, that is, the gate voltage VG can be made substantially the same in each pixel circuit 100, and variations are reduced. Therefore, it is possible to suppress a decrease in gradation expression.

  FIG. 8 is a diagram illustrating the relationship between the delay time TS and the column direction panel position in the first embodiment of the present invention. Reference numerals 100a, 100b, and 100c in the column direction panel positions correspond to the pixel circuits, and the pixel origin side (the left side in the figure) indicates the pixel circuit far from the data driver 20. As the pixel circuit 100 is farther from the data driver 20 as shown in FIG. 8, the time constant of the wiring load of the data signal line 150 is larger, so the delay time TS becomes smaller. The closer the pixel circuit 100 is to the data driver 20, the data signal line Since the time constant of the 150 wiring load is small, the delay time TS is increased. In this way, DELAY (LINE) is determined. In this example, DELAY (LINE) is TS1 for the pixel circuit 100c (SCAN (1)), TS2 for the pixel circuit 100b (SCAN (2)), and for the pixel circuit 100a (SCAN (3)). It is decided like TS3.

[Operation example of conventional technology (grayscale voltage difference dependency)]
Next, the gradation voltage difference dependency of the writing voltage in the operation of the prior art will be described.

  FIG. 9 is a diagram for explaining the dependence of the voltage change (when the column direction panel position is constant) on data writing in the prior art on the gradation voltage difference. Changes in the data signal DT and the gate voltage VG shown in FIG. 9 change from a high voltage to a low voltage when the gradation voltage changes from a low voltage to a high voltage (Vd (p−1) <Vd (p)). The case (Vd (p-1)> Vd (p)) is shown separately. In each case, three stages with different degrees of change are illustrated. Note that p indicates a row of the pixel circuits 100 arranged in a matrix, and the gradation voltage Vd (p−1) is a data signal line when the previous row of the gradation voltage Vd (p) is selected. This corresponds to the gradation voltage output to 150, that is, the gradation voltage held by the data signal line 150 before the gradation voltage Vd (p) is output. Here, the pixel circuits 100 to which the gradation voltage is written are all in the same row.

  As can be seen from the comparison of the respective data signals DT, the amount of change in gradation voltage varies depending on the gradation voltage difference between Vd (p−1) and Vd (p). Since the larger the gradation voltage difference, the larger the change is required. If the time from the start of the change to the timing (sampling timing) written to the pixel circuit 100 is the same, the gradation voltage written to the pixel circuit 100 is the same. That is, the gate voltage VG varies.

  Therefore, in the prior art, the gray scale actually expressed by the gray scale voltage difference varies with respect to the gray scale voltage to be written (ideal gray scale voltage). The image quality is deteriorated due to the voltage-dependent crosstalk phenomenon, and the gradation expression is lowered.

[Operation Example of First Embodiment (Grayscale Voltage Difference Dependency)]
Next, the dependence of the write voltage on the gradation voltage difference in the operation of the first embodiment of the present invention will be described.

  FIG. 10 is a diagram illustrating the grayscale voltage difference dependency of the voltage change (when the column direction panel position is constant) at the time of data writing in the first embodiment of the present invention. As shown in FIG. 10, with respect to the gradation voltage difference VD1, a change in gradation voltage is started with a delay of TD1 from LAT (in). Similarly, the gradation voltage difference VD2 is delayed by TD2, and the gradation voltage difference VD3 is delayed by TD3 to start the gradation voltage change. The smaller the gradation voltage difference is, the faster the target gradation voltage Vd (p) is reached. Therefore, the delay time is increased to delay the start of the gradation voltage change.

  In this way, by varying the timing at which the change in the gradation voltage is started, the data signal DT becomes substantially the same voltage level regardless of the gradation voltage difference at the timing of writing to the pixel circuit 100 (sampling timing). Can be. In this way, the gradation voltage written to the pixel circuit 100, that is, the gate voltage VG can be made substantially the same in each pixel circuit 100, and variations are reduced. Therefore, it is possible to suppress a decrease in gradation expression.

  FIG. 11 is a diagram for explaining the gradation voltage difference in the first embodiment of the present invention. The gradation data Vi input to the display device 10 is converted into a gradation voltage Vd based on a γ curve as shown in FIG. Therefore, in this example, the difference in the gradation voltage Vd obtained from the gradation difference indicated by the gradation data Vi based on the γ curve is defined as the gradation voltage difference.

  FIG. 12 is a diagram for explaining the relationship between the delay time TD and the gradation voltage difference in the first embodiment of the present invention. As shown in FIG. 12, since the target gradation voltage Vd (p) is reached earlier as the gradation voltage difference | Vd (p) −Vd (p−1) | is smaller, the delay time TD increases. is there. In this way, DELAY (DATA) is determined. In this example, DELAY (DATA) is determined as TD1 for VD1, TD2 for VD2, and TD3 for VD3.

Second Embodiment
In the second embodiment, a case will be described in which a precharge voltage is applied in the process of change when the grayscale voltage changes as the horizontal period shifts. Hereinafter, parts different from the first embodiment will be described in detail, and description of other parts will be omitted.

[Configuration of Data Driver 20A]
FIG. 13 is a block diagram showing the configuration of the data driver 20A in the second embodiment of the present invention. The data driver 20A is provided with a data driver output control circuit 21A corresponding to the data signal line 150 of each column.

  The data driver output control circuit 21A receives a precharge voltage VPRE and a precharge timing signal TPRE in addition to the signals input to the data driver output control circuit 21 in the first embodiment. VPRE represents a precharge voltage. In this example, VPRE is set to the median value of the range of the gradation voltage, but may be set to a constant voltage. TPRE is a signal that defines the timing at which the precharge voltage is output to the data signal line 150.

[Configuration of Data Driver Output Control Circuit 21A]
FIG. 14 is a block diagram showing a configuration of the data driver output control circuit 21A in the second embodiment of the present invention. The data driver output control circuit 21A includes a data latch circuit A211, a data latch circuit B213A, an output control circuit 215, an output buffer 217, a precharge control circuit 219, a delay time calculation circuit 223A, and a delay control circuit 225.

  Based on LAT (in), the data latch circuit B 213A outputs the held gradation voltage to the data signal line 150 via the output control circuit 215, the precharge control circuit 219, and the output buffer 217. In this example, the gradation voltage output from the output control circuit 215 is held in the precharge control circuit 219.

  The precharge control circuit 219 outputs the precharge voltage VPRE to the data signal line 150 via the output buffer 217 when TPRE becomes L level. Specifically, during one horizontal period, the period from the LAT (in) to the next LAT (in) in which the SCAN signal is at the L level includes a period during which TPRE is at the L level.

  Further, as described above, the precharge control circuit 219 also holds the gradation voltage output from the output control circuit 215, and based on DELAY (OUT) obtained by delaying LAT (in) via the output buffer 217. The held gradation voltage is output to the data signal line 150.

  The delay time calculation circuit 223A calculates a time for delaying the output of the gradation voltage from the precharge control circuit 219 based on DELAY (DATA) determined from DELAY (LINE) and the gradation voltage Vd. The corresponding information DELAY_SET is output to the delay control circuit 225. The gradation voltage Vd indicates the gradation voltage (that is, the gradation voltage held in the precharge control circuit 219) that is next output to the data signal line 150.

  The delay time calculation circuit 223A calculates a difference between the input gradation voltage Vd (the gradation voltage held in the precharge control circuit 219) and a predetermined precharge voltage VPRE as a gradation voltage difference, Further, this gradation voltage difference is converted into DELAY (DATA). The fact that DELAY (DATA) shows a smaller value as the gradation voltage difference is larger is the same as the content described in the first embodiment. The same applies to the calculation of DELAY_SET. In the second embodiment, since the gradation voltage difference is determined with respect to the precharge voltage VPRE, the data comparison circuit 221 described in the first embodiment can be omitted.

  The delay control circuit 225 outputs DELAY (OUT) obtained by delaying LAT (in) based on DELAY_SET to the precharge control circuit 219. As described above, the precharge control circuit 219 outputs a gradation voltage based on DELAY (OUT). Therefore, the timing at which the gradation voltage is output to the data signal line 150 is adjusted to a timing obtained by delaying the time corresponding to DELAY_SET with reference to LAT (in), as in the first embodiment. Prior to the timing at which this gradation voltage is output from the precharge control circuit 219 to the data signal line 150, the precharge voltage VPRE is output based on TPRE in advance.

[Operation of Data Driver 20A]
FIG. 15 is a timing chart of each signal in the second embodiment of the present invention. When TPRE input to the precharge control circuit 219 becomes L level, the precharge voltage VPRE is output to the data signal line 150. Data signal DT changes to precharge voltage VPRE. Then, since the gradation voltage Vd held in the precharge control circuit 219 is output to the data signal line 150 at the timing when DELAY (OUT) becomes L level, the data signal DT at the precharge voltage VPRE is output. Changes from the timing to the next gradation voltage Vd.

[Operation Example of Second Embodiment (Grayscale Voltage Difference Dependency)]
Next, the dependency of the writing voltage on the gradation voltage difference in the second embodiment will be described. The column direction panel position dependency is the same as in the first embodiment, and a description thereof will be omitted.

  FIG. 16 is a diagram for explaining the gradation voltage difference dependency of the voltage change (when the column direction panel position is constant) at the time of data writing in the second embodiment of the present invention. The changes in the data signal DT and the gate voltage VG shown in FIG. 16 change from the precharge voltage VPRE to the high gradation voltage Vd (VPRE <Vd) and from the precharge voltage VPRE to the low gradation voltage Vd ( VPRE> Vd). In each case, two levels with different gradation voltages Vd are illustrated.

  As shown in FIG. 16, with respect to the gradation voltage difference VD1, a change in gradation voltage is started with a delay of TD1 from LAT (in). Similarly, the gradation voltage difference VD2 is delayed by TD2, and the change of the gradation voltage is started. As shown in each data signal DT, the smaller the grayscale voltage difference is, the faster the target grayscale voltage Vd is reached. Therefore, the delay time TD is increased to delay the start of the grayscale voltage change. .

  When adjustment of the output timing of the gradation voltage is not performed as in the prior art, the ratio of the actually written gradation voltage (gate voltage VG) to the gradation voltage to be originally written is written. It differs depending on the power gradation voltage (more specifically, the gradation voltage difference with respect to the precharge voltage).

  On the other hand, as in the second embodiment of the present invention, the data signal DT at the sampling timing can be written regardless of the gradation voltage to be written by changing the timing at which the change of the gradation voltage is started. It can be brought close to the power gradation voltage (ideal gradation voltage) to the same extent. That is, the ratio of the actually written gradation voltage (gate voltage VG) to the originally written gradation voltage depends on the gradation voltage to be written (more specifically, the gradation voltage difference with respect to the precharge voltage). It is possible to suppress the difference. Therefore, it is possible to suppress a decrease in gradation expression.

  FIG. 17 is a diagram for explaining the gradation voltage difference in the second embodiment of the present invention. The gradation data Vi input to the display device 10 is converted into the gradation voltage Vd by the control unit 80 based on the γ curve as shown in FIG. Therefore, in this example, the gradation voltage Vd is calculated from the gradation data Vi based on the γ curve, and the difference between the precharge voltage VPRE and the gradation voltage Vd is the gradation voltage difference.

  FIG. 18 is a diagram for explaining the relationship between the delay time TD and the gradation voltage difference in the second embodiment of the present invention. As shown in FIG. 18, since the target gradation voltage Vd is reached earlier as the gradation voltage difference | VPRE−Vd | is smaller, the delay time TD increases. In this way, DELAY (DATA) is determined. In this example, DELAY (DATA) is determined as TD1 for VD1 and TD2 for VD2.

  As can be seen from FIG. 17, in the second embodiment, the gradation voltage difference VD is based on the precharge voltage VPRE. When the precharge voltage VPRE is the median value of the gradation voltage Vd, the maximum value of the gradation voltage difference VD (= | VPRE−Vd |) is the maximum value (gradation of the gradation voltage difference VD of the first embodiment. The difference between the maximum value and the minimum value of the voltage Vd is half. Therefore, in the second embodiment, the change amount of the gradation voltage is smaller than in the first embodiment, and the maximum value of the delay time TD can be reduced.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 10 ... Display apparatus, 20 ... Data driver, 21 ... Data driver output control circuit, 30 ... Scan driver, 80 ... Control part, 90 ... Power supply, 100 ... Pixel circuit, 140 ... Scan line, 150 ... Data Signal line 211 ... Data latch circuit A, 213 ... Data latch circuit B, 215 ... Output control circuit, 217 ... Output buffer, 219 ... Precharge control circuit, 221 ... Data comparison circuit, 223 ... Delay time calculation circuit, 225 ... Delay control circuit

Claims (10)

A plurality of data signal lines connected to the data driver and a plurality of scanning lines connected to the scan driver intersect, and a display device having pixels provided corresponding to the intersection,
Means for obtaining a gradation voltage for designating a gradation of the pixel;
Means for calculating a first delay correction value based on the voltage held by the data signal line to which the acquired gradation voltage is output and the gradation voltage;
Means for determining a timing of outputting the gradation voltage to the data signal line based on the first delay correction value;
A display device comprising: Means for calculating a second delay correction value based on the position of the scanning line corresponding to the pixel whose gradation is designated by the acquired gradation voltage;
The display device according to claim 1, wherein timing for outputting the gradation voltage to the data signal line is determined based on the first delay correction value and the second delay correction value.   The display device according to claim 2, wherein the second delay correction value is calculated based on a CR time constant of the data signal line.   4. The display according to claim 1, wherein the voltage held by the data signal line indicates a voltage based on a gradation voltage previously output to the data signal line. apparatus. Means for outputting a precharge voltage before outputting the gradation voltage to the data signal line;
4. The display device according to claim 1, wherein the voltage held by the data signal line indicates the precharge voltage. A plurality of data signal lines connected to a data driver and a plurality of scanning lines connected to a scan driver intersect, and a driving method of a display device having a pixel provided corresponding to the intersection,
Obtaining a gradation voltage specifying the gradation of the pixel;
Calculating a first delay correction value based on the voltage held by the data signal line from which the acquired gradation voltage is output and the gradation voltage;
A method of driving a display device, comprising: determining a timing of outputting the gradation voltage to the data signal line based on the first delay correction value. Calculating a second delay correction value based on a position of a scanning line corresponding to the pixel from which the acquired gradation voltage is output;
7. The method of driving a display device according to claim 6, wherein the timing of outputting the gradation voltage to the data signal line is determined based on the first delay correction value and the second delay correction value. .   8. The method of driving a display device according to claim 7, wherein the second delay correction value is calculated based on a CR time constant of the data signal line.   9. The display according to claim 6, wherein the voltage held by the data signal line indicates a voltage based on a gradation voltage previously output to the data signal line. Device driving method. Outputting a precharge voltage before outputting the gradation voltage to the data signal line;
9. The display device driving method according to claim 6, wherein the voltage held by the data signal line indicates the precharge voltage.

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