JP2015076510A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flexibility of circuit layout in a semiconductor device.SOLUTION: A semiconductor device comprises: an SOI substrate 101 composed of first and second silicon layers 1012, 1011 with an insulation layer 1013 being sandwiched; circuits 1, 2 formed in the first silicon layer on the SOI substrate; and thermal coupling part 3 which pierces the first silicon layer and the insulation layer to extend to the second silicon layer, for thermally coupling the circuits with the second silicon layer.

Description

  The present invention relates to a semiconductor device using an SOI (Silicon On Insulator) substrate.

  In a semiconductor substrate having an SOI structure, it is known that a region for forming an element is separated by forming a trench made of an insulating film. For example, a semiconductor device in which switching elements are insulated and isolated by a trench isolation part is known. In this semiconductor device, a switching element and an internal circuit configured to perform a predetermined operation are formed on one surface side (main surface side) of a semiconductor substrate having an SOI structure. The internal circuit includes, for example, a power supply circuit that generates output power required from input power, and an oscillation circuit that outputs a carrier wave having a set frequency (see Patent Document 1).

JP2012-243801A

  However, the above-described patent document describes that when the switching element generates heat rapidly, the temperature in the vicinity of the arrangement area of the switching element also increases rapidly. That is, when the switching element generates heat rapidly, the temperature distribution on the main surface side of the semiconductor substrate becomes non-uniform. For this reason, it is necessary to dispose a circuit whose characteristics fluctuate with respect to temperature fluctuations away from the switching element, which restricts the circuit layout.

  A semiconductor device according to the present invention includes an SOI substrate comprising first and second silicon layers with an insulating layer interposed therebetween, a circuit formed on the first silicon layer on the SOI substrate, and the first silicon layer and the insulating layer. A thermal coupling portion extending through the second silicon layer and thermally coupling the circuit to the second silicon layer.

  According to the present invention, the degree of freedom of circuit layout in a semiconductor device can be improved.

1 is a schematic layout diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1. It is an example of the figure which shows the whole structure of a 1st circuit and a 2nd circuit. It is an example of the circuit diagram of an over temperature detection circuit. It is an example of the circuit diagram of a predriver. It is an example of the figure explaining a prior art. It is a schematic diagram which shows the example of arrangement | positioning in a semiconductor device. FIG. 6 is a schematic layout diagram of a semiconductor device according to a second embodiment. It is an example of the figure which shows the whole structure of a 1A circuit and a 1B circuit. It is an example of the circuit diagram of an oscillation circuit. It is an example of the circuit diagram of a temperature detection circuit. It is a schematic diagram which shows the example of arrangement | positioning in a semiconductor device. It is a schematic diagram which shows the example of arrangement | positioning in a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

--- First embodiment ---
In the first embodiment of the present invention, a semiconductor device capable of improving the degree of freedom of layout without depending on the positional relationship between a circuit whose characteristics fluctuate with respect to temperature fluctuations and a circuit whose heat generation amount fluctuates with time. The configuration and operation will be described.

  FIG. 1 is a schematic layout diagram of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the semiconductor device shown in FIG. A semiconductor device 100 shown in FIGS. 1 and 2 is, for example, a semiconductor package in which an SOI substrate chip 101 is sealed with a resin. The SOI substrate chip 101, a first circuit 1 formed on the SOI substrate chip 101, and a second circuit are illustrated. 2, a thermal coupling portion 3, an element isolation film 4, and a sealing resin (not shown).

  The SOI substrate chip 101 includes an active layer 1012 that is a first silicon layer, a base material 1011 that is a second silicon layer, and an insulating film 1013 that is an insulating layer interposed between the base material 1011 and the active layer 1012. Have. The first circuit 1 and the second circuit 2 are formed in the active layer 1012.

  The first circuit 1 is a circuit whose characteristics fluctuate with respect to temperature fluctuations. The second circuit 2 is a circuit in which the amount of generated heat is not constant and varies with time. Specific configurations of the first circuit 1 and the second circuit 2 will be described later.

  The thermal coupling portion 3 is a portion that thermally couples the first circuit 1 and the base material 1011. The thermal coupling portion 3 is filled in the through hole 31 and the through hole 31 provided adjacent to the first circuit 1. And a heat transfer material 32. The through hole 31 is a through hole that reaches the base material 1011 through the active layer 1012 and the insulating film 1013. The heat transfer material 32 filled inside the through hole 31 is made of a material having high thermal conductivity and excellent electrical insulation. The element isolation film 4 is an insulating film formed around the second circuit 2.

  For example, as shown in FIG. 3A, the first circuit 1 includes a reference voltage generation circuit 11 that receives a power supply voltage VDD and outputs a reference voltage Vref. For example, as shown in FIG. 3A, the second circuit 2 includes an overtemperature detection circuit 21 that outputs a signal EN, a pre-driver 22 that receives the signal EN and the signal Vctrl as input signals, and a voltage that the pre-driver 22 outputs. The high voltage NMOS transistor 23 is controlled to be turned on and off by Vgate. In addition, the load 5 is described as a driving target of the high breakdown voltage NMOS transistor 23. The load 5 is composed of an inductor element, for example. The load 5 is connected, for example, between the high voltage power supply VH and the high voltage NMOS transistor 23 which are larger than the power supply voltage VDD.

  Around the second circuit 2, an element isolation film 4 having a trench structure surrounding the second circuit 2 and having an insulating layer is formed. One reason for providing the element isolation film 4 is to suppress noise propagation that suppresses noise generated during the operation of the high voltage NMOS transistor 23 mounted in the second circuit 2 from propagating to surrounding circuits. The element isolation film 4 is made of, for example, silicon dioxide (SiO2). The thermal conductivity of SiO2 is about 1/100 compared with silicon (Si) which is a material of the SOI substrate. Therefore, the heat generated in the second circuit 2 is easily trapped inside the element isolation film 4.

  As shown in FIG. 4, for example, the overtemperature detection circuit 21 of the second circuit 2 includes a comparator 211 that receives a diode 211, a constant current source 212, and a reference voltage Vref as input signals and a signal EN as an output signal. Consists of

  The overtemperature detection circuit 21 outputs the result of comparing the forward voltage Vf of the diode 211 and the reference voltage Vref by the comparator 213 as a high or low level signal EN. The signal EN indicates a high level when Vf> Vref, and the signal EN indicates a low level when Vf <Vref.

  Here, the temperature coefficient of Vf has a negative value, and Vf decreases as the temperature increases. When a transition is made from Vf> Vref to Vf <Vref at a certain temperature T1, the voltage level of the output EN transitions from a high level to a low level. That is, in this case, T1 is a threshold value for overtemperature detection.

  For example, as shown in FIG. 5, the pre-driver 22 of the second circuit 2 includes a NAND circuit 221, a level shift circuit 222, and an inverter circuit 223. The NAND circuit 221 is a NAND circuit that outputs a NAND signal of the signal Vctrl and the enable signal EN. The level shift circuit 222 is a level shift circuit that converts the voltage value of the high level output of the NAND circuit 221 from VDD to VH and outputs it. The inverter circuit 223 is an inverter circuit composed of a P-type transistor 223H and an N-type transistor 223L. Here, for example, VDD = 3.3V and VH = 14V. The signal Vctrl is a load drive signal output from another controller (not shown).

  When the signal EN is at a high level, the pre-driver 22 outputs the signal polarity of the signal Vctrl as it is to the signal Vgate. However, the high level voltages of Vctrl and Vgate are different, and the high level voltage of Vctrl is VDD, whereas the high level voltage of Vgate is VH. Therefore, a level shift circuit 222 is provided inside the pre-driver 22. When the signal EN is at a low level, the output of the NAND circuit 221 included in the pre-driver 22 is always at a high level regardless of the state of the signal Vctrl, and a low level is always output as the signal Vgate.

  Below, the power loss in the 1st circuit 1 and the 2nd circuit 2 when not in an over-temperature detection state is demonstrated. Here, the case of not being in the overtemperature detection state is a state below the threshold temperature T1 of the overtemperature detection circuit 21, as described above, and the signal EN output from the overtemperature detection circuit 21 indicates a high level.

The reference voltage generation circuit 11 receives the power supply voltage VDD as described above and outputs the reference voltage Vref. When the internal current consumption of the reference voltage generation circuit 11 is I1A and the output current to the outside is I1B, the power loss P11 in the reference voltage generation circuit 11 is expressed by the following equation (1).
P11 = VDD × I1A + (VDD−Vref) × I1B (1)
From equation (1), it can be seen that P11 is proportional to VDD.

  The pre-driver circuit 22 outputs a signal Vgate according to the signal Vctrl. The signal Vgate is the gate drive voltage of the high breakdown voltage NMOS transistor 23 in the subsequent stage, that is, the high breakdown voltage NMOS transistor 23 is turned on or off according to Vgate.

  In FIG. 3A, when the high breakdown voltage NMOS transistor 23 is in the OFF state, the power loss P23 in the NMOS 23 is zero if the leakage current is ignored.

When the high breakdown voltage NMOS transistor 23 is in the on state, the power loss P23 in the NMOS 23 is expressed as follows using the impedance Z of the load 5, the NMOS on resistance Ron, the voltage value VH, and the drain current ID of the NMOS 23: 2) It is expressed by the formula.
P23 = Ron / (Z + Ron) × VH × ID (2)
From equation (2), it can be seen that P23 is proportional to VH.

  From the above, the power loss P23 in the high voltage NMOS transistor 23 varies with the signal Vctrl. P11 is proportional to VDD (= 3.3V), and P23 is proportional to VH (= 14V). Therefore, the power loss P23 is larger than P11 and fluctuates with time.

Next, the layout of the first circuit 1 and the second circuit 2 will be described.
As shown in FIG. 6A, consider a case where the thermal coupling portion 3 does not exist and the first circuit 1 is disposed in the vicinity of the second circuit 2 and the element isolation film 4. As described above, the heat generation amount of the second circuit 2 is larger than that of the first circuit 1 and fluctuates with time. At this time, the increase / decrease in the thermal energy caused by the thermal fluctuation generated in the second circuit 2 propagates to the surroundings through the element isolation film 4, and the first circuit 1 disposed in the vicinity is affected by the thermal fluctuation and outputs Characteristics also vary.

  A conventional method for preventing this is to separate the circuit 1 from the circuit 2 as shown in FIG. However, an increase in wiring area and arrangement area in the semiconductor device 100 is caused.

  In contrast, in the present embodiment shown in FIG. 1, the thermal coupling portion 3 is provided in the vicinity of the first circuit 1. This will be described below. The thermal coupling unit 3 reaches the base material 1011 on the back surface of the SOI substrate, and thereby thermally couples the first circuit 1 and the base material 1011. Since the base material 1011 extends over the entire surface of the SOI substrate chip 101, its total heat capacity is large. Therefore, the temperature of the base material 1011 does not depend on local heat generation, and indicates the average temperature of the semiconductor device 100.

  Similarly, the first circuit 1 that is thermally coupled to the base material 1011 can also operate according to the average temperature of the semiconductor device 100 and is less susceptible to thermal fluctuations from the second circuit 2 disposed in the vicinity. be able to. Thus, the degree of freedom of circuit layout in the semiconductor device 100 can be improved without depending on the positional relationship between the circuit whose characteristics change with respect to temperature fluctuations and the circuit whose heat generation amount changes with time.

  Since the reference voltage Vref output from the reference voltage generation circuit 11 thermally coupled to the base material 1011 is input to the overtemperature detection circuit 21, the operation accuracy of the overtemperature detection circuit 21 is improved, The occurrence of problems due to the temperature rise of the pre-driver 22 can be effectively suppressed. Therefore, the reliability of the semiconductor device 100 can be improved.

  The semiconductor device 100 described above includes a semiconductor package in which an SOI substrate chip 101 formed with the first circuit 1, the second circuit 2, the thermal coupling portion 3, and the element isolation film 4 as shown in FIG. did. However, the semiconductor device 100 may be one in which the SOI substrate chip 101 is directly mounted on a printed board.

  As shown in FIG. 7, the semiconductor device 100 may be a semiconductor package that is sealed together with other modules 102 as well as the SOI substrate chip 101. At this time, the module 102 does not need to be an SOI substrate chip, and may be a substrate chip made of another intrinsic semiconductor or compound semiconductor. Alternatively, a module in which passive elements are integrated may be used. Regardless of the form of mounting of the SOI substrate chip 101, the same effects as the above-described effects can be obtained.

  In the above description, as shown in FIG. 1, the thermal coupling portion 3 is provided adjacent to the first circuit 1 in the region between the first circuit 1 and the second circuit 2. The invention is not limited to this. If the thermal coupling unit 3 thermally couples the first circuit 1 and the base material 1011, the thermal coupling unit 3 is provided in a region other than the region between the first circuit 1 and the second circuit 2. May be.

  Further, if the thermal coupling portion 3 is provided in the vicinity of the first circuit 1 and the first circuit 1 and the base material 1011 are thermally coupled, the thermal coupling portion 3 is not necessarily adjacent to the first circuit 1. It does not have to be.

  Although the high breakdown voltage NMOS transistor 23 is mounted on the second circuit 2, for example, as shown in FIG. 3B, a high breakdown voltage PMOS transistor 24 may be mounted instead of the high breakdown voltage NMOS transistor 23. Well, there are the same effects as the above-mentioned effects.

--- Second Embodiment ---
A second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and different points will be mainly described. Points that are not particularly described are the same as those in the first embodiment. This embodiment is different from the first embodiment mainly in that temperature information is shared among a plurality of circuits.

  FIG. 8 is a diagram schematically illustrating an example of the layout of the semiconductor device 100A according to the second embodiment. The semiconductor device 100A of the second embodiment is a semiconductor package in which an SOI substrate chip 103 is sealed with a resin, for example, as in the first embodiment. The semiconductor device 100A includes an SOI substrate chip 103, a first A circuit 110, a first B circuit 111, a second A circuit 210, thermal coupling portions 3a, 3b, 3c, an element isolation film 4, and a temperature detection circuit 6. And.

  The first A circuit 110 and the first B circuit 111 are circuits whose characteristics fluctuate with respect to temperature fluctuations. The second A circuit 210 is a circuit in which the heat generation amount is not constant and varies with time. The temperature detection circuit 6 is a circuit that detects the average temperature of the semiconductor device 100A. The thermal coupling portions 3a, 3b, and 3c are provided in the vicinity of the first A circuit 110, the first B circuit 111, and the temperature detection circuit 6, respectively. An element isolation film 4 is formed around the second A circuit 210.

  In the present embodiment, the first A circuit 110 and the first B circuit 111 include, for example, a current correction circuit 13 that receives a temperature information signal TEMP and outputs a current control signal Ictrl, a power supply voltage VDD, and current control as shown in FIG. The oscillation circuit 12 is configured to receive the signal Ictrl and output the oscillation signal OSC. Here, for example, as shown in FIG. 10, the oscillation circuit 12 includes inverter elements 121a to 121c and current sources 122a to 122f whose current values can be adjusted by a current control signal Ictrl.

  For example, as shown in FIG. 11, the temperature detection circuit 6 includes a diode 61 that generates a forward voltage by applying a current, a constant current source 62 that applies a current to the diode 61, and a forward voltage Vf of the diode 61. Is formed of an operational amplifier 63 that constitutes a voltage follower and outputs a temperature information signal TEMP.

  In the temperature detection circuit 6, the forward voltage Vf of the diode 61 generated by applying a current from the constant current source 62 to the diode 61 is input to the operational amplifier 63. The operational amplifier 63 forms a voltage follower as described above, and the temperature information signal TEMP that is the output follows the forward voltage Vf of the input diode 61. Here, the temperature coefficient of the forward voltage Vf of the diode 61 has a negative value, and the forward voltage Vf of the diode 61 decreases as the temperature increases. Therefore, the temperature information signal TEMP that is the output of the operational amplifier 63 also has a negative temperature coefficient, like the forward voltage Vf of the diode 61. That is, temperature information is included in the temperature information signal TEMP.

  The first A circuit 110 and the first B circuit 111 acquire the temperature information signal TEMP that is an input from the temperature detection circuit 6. The input temperature information signal TEMP is input to the oscillation circuit 12 through the current correction circuit 13 as a current control signal Ictrl. In the current sources 122a to 122f included in the oscillation circuit 12, the current value can be adjusted by the current control signal Ictrl. Here, the oscillation frequency of the oscillation signal OSC that is the output of the oscillation circuit 12 is variable depending on the current values of the current sources 122a to 122f. Therefore, the frequency characteristic of the oscillation signal OSC can be controlled by the current control signal Ictrl. Therefore, the oscillation frequency of the oscillation signal OSC can be corrected based on the temperature information signal TEMP.

  In the present embodiment, the thermal coupling portion 3 a provided in the vicinity of the first A circuit 110 thermally couples the first A circuit 110 and the base material 1011. The thermal coupling portion 3 b provided in the vicinity of the first B circuit 111 thermally couples the first B circuit 111 and the base material 1011. The thermal coupling portion 3 c provided in the vicinity of the temperature detection circuit 6 thermally couples the temperature detection circuit 6 and the base material 1011.

  As described above, the temperature of the base material 1011 does not depend on local heat generation, and indicates the average temperature of the semiconductor device 100A. Here, the temperature detection circuit 6 thermally coupled to the base material 1011 by the thermal coupling portion 3c also operates according to the average temperature of the semiconductor device 100A. That is, the temperature detection circuit 6 can detect the average temperature of the semiconductor device 100A.

  The average temperature of the semiconductor device 100A is equal at any point in the semiconductor device 100A. Therefore, it is sufficient that at least one temperature detection circuit 6 for detecting the average temperature of the semiconductor device 100A exists in the semiconductor device 100A. That is, even when the semiconductor device 100A is provided with a plurality of circuits whose characteristics vary with respect to temperature variations, such as the first A circuit 110 and the first B circuit 111, it is not necessary to provide a plurality of temperature detection circuits 6.

  As described above, the first A circuit 110 and the first B circuit 111 correct the oscillation frequency of the oscillation signal OSC based on the temperature information signal TEMP that is information on the average temperature of the semiconductor device 100A detected by the temperature detection circuit 6. And output. Thereby, the operation accuracy of the semiconductor device 100A can be improved.

  Note that the first A circuit 110 and the first B circuit 111 may be the same circuit or different circuits as long as the characteristics fluctuate with respect to temperature fluctuations.

  The SOI substrate chip in which the semiconductor device 100A is formed with the first A circuit 110, the fourth circuit 111, the second A circuit 210, the thermal coupling portions 3a to 3c, the element isolation film 4, and the temperature detection circuit 6 as shown in FIG. A semiconductor package 103 was sealed with resin. However, the semiconductor device 100A of the present embodiment may be one in which the SOI substrate chip 103 is directly mounted on a printed board.

  Further, as illustrated in FIG. 12, the semiconductor device 100 </ b> A may be a semiconductor package that is sealed together with a module 102 other than the SOI substrate chip 103. At this time, the module 102 does not need to be an SOI substrate chip, and may be a substrate chip made of another intrinsic semiconductor or compound semiconductor. Alternatively, a module in which passive components are integrated may be used. Alternatively, as shown in FIG. 13, the SOI substrate chip 101 and the SOI substrate chip 103 may be sealed with resin. Regardless of the mounting form of the SOI substrate chip 103, the same effects as the above-described effects can be obtained.

  According to the semiconductor device of the second embodiment and the modification described above, as in the first embodiment, a circuit whose characteristics fluctuate with respect to temperature fluctuations and a circuit whose calorific value fluctuates with time. The degree of freedom in layout can be improved without depending on the positional relationship between the two. Moreover, by sharing temperature information among a plurality of circuits, the number of temperature detection circuits can be reduced, and the circuit area can be reduced.

In addition, this invention is not limited to said Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
In addition, control lines and signal lines are those that are considered necessary for the explanation, and not all control lines and signal lines are necessarily shown in the product.

DESCRIPTION OF SYMBOLS 1 1st circuit, 2nd circuit, 3 thermal coupling part, 4 element isolation film, 6 temperature detection circuit, 31 through-hole, 32 heat transfer material, 100,100A semiconductor device, 101,103 SOI substrate chip, 110 1st 1A circuit, 111 1B circuit

Claims (8)

An SOI substrate comprising first and second silicon layers with an insulating layer interposed therebetween;
A circuit formed in the first silicon layer on the SOI substrate;
A semiconductor device comprising: a thermal coupling portion that extends through the first silicon layer and the insulating layer to the second silicon layer and thermally couples the circuit to the second silicon layer. The semiconductor device according to claim 1,
The circuit includes a first circuit whose characteristics fluctuate with respect to temperature fluctuations and a second circuit whose calorific value fluctuates with time
The thermal coupling unit is a semiconductor device that thermally couples the first circuit to the second silicon layer. The semiconductor device according to claim 2,
A semiconductor device in which the output of the first circuit is input to the second circuit. The semiconductor device according to claim 1,
The circuit includes a temperature detection circuit that detects the temperature of the SOI substrate, and a second circuit in which a heat generation amount varies with time,
The thermal coupling unit is a semiconductor device that thermally couples the temperature detection circuit to the second silicon layer. The semiconductor device according to claim 4,
The circuit further includes a first circuit whose characteristic varies with temperature variation,
An output of the temperature detection circuit is a semiconductor device that is input to the first circuit. The semiconductor device according to claim 2,
The second circuit is a semiconductor device having a high voltage transistor connected to a high voltage power source and driving a load connected to the ground. The semiconductor device according to claim 2,
The second circuit includes a high voltage transistor connected to a ground, and drives a load connected to a high voltage power source. In the semiconductor device according to any one of claims 1 to 7,
A semiconductor device in which the SOI substrate is packaged by itself or with other substrates by resin sealing.

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