JP2015050870A - Battery pack - Google Patents

Abstract

In a battery pack including a plurality of voltage monitoring circuits for monitoring a battery voltage, it is possible to detect that an abnormality has occurred in any of the plurality of voltage monitoring circuits. A battery pack includes a first voltage monitoring circuit and a second voltage monitoring circuit for independently monitoring cell voltages Vc1 to Vc5 of cells 11 to 15 constituting the battery. Yes. Then, the battery control circuit 40 compares the cell voltage monitoring results of the voltage monitoring circuits 20 and 30, and if the monitoring results do not match, it is determined that one of the voltage monitoring circuits 20 and 30 is abnormal. Then, charging / discharging of the battery 10 is stopped by the protection circuit 46. [Selection] Figure 2

Description

  The present invention relates to a battery pack provided with a voltage monitoring circuit for monitoring battery voltage.

A battery pack is known that monitors battery voltage in order to prevent overcharging of the battery, and stops charging when the battery voltage reaches a specified voltage during charging.
In addition, in this type of battery pack, in order to improve safety, a plurality of voltage monitoring circuits for independently monitoring battery voltages are provided, and even if one voltage monitoring circuit fails, another voltage monitoring circuit can be used. It has also been proposed that overcharge can be detected (see, for example, Patent Document 1).

  For example, the battery pack described in Patent Document 1 includes first battery voltage detection means for stopping charging when the battery voltage reaches the first specified voltage, and the battery voltage is higher than the first specified voltage. Two types of voltage monitoring circuits are provided for the second abnormality detection means for informing the outside of the battery abnormality when the second specified voltage is reached.

  For this reason, according to the battery pack described in Patent Document 1, even if the first battery voltage detecting means fails and the charging cannot be stopped when the battery voltage is abnormal, the second battery voltage detecting means It is possible to detect an abnormality in the battery voltage and notify the user to that effect.

Japanese Patent Laid-Open No. 2000-14020

  However, in the above prior art, the monitoring of the battery voltage is merely duplicated, and each voltage monitoring circuit operates independently, so that the failure of each voltage monitoring circuit cannot be detected. was there.

  That is, in the battery pack described in Patent Document 1, when the first battery voltage detection unit is operating normally and the second battery voltage detection unit is out of order, the second battery voltage detection unit is detected. The failure of the means cannot be detected.

  Therefore, after that, when the first battery voltage detection means fails and the battery voltage reaches the second base voltage, the second battery voltage detection means cannot notify the abnormality, and the battery There is a problem that the safety of the pack cannot be ensured.

  The present invention has been made in view of these problems, and in a battery pack including a plurality of voltage monitoring circuits that independently monitor battery voltages, when an abnormality occurs in any of the plurality of voltage monitoring circuits. The purpose of this is to improve the reliability of the battery pack by making it possible to detect this.

  The battery pack according to claim 1 is provided with a first voltage monitoring circuit and a second voltage monitoring circuit for monitoring the voltage of the battery, respectively, and the control means is based on the monitoring results of these voltage monitoring circuits, Controls charging / discharging of the battery.

  Further, the control means compares the monitoring results of the first voltage monitoring circuit and the second voltage monitoring circuit, and determines that the first voltage monitoring circuit or the second voltage monitoring circuit is abnormal when the monitoring results are different. To do.

  Therefore, according to the battery pack of the first aspect, when one of the two voltage monitoring circuits breaks down, the fact is detected and a predetermined response such as stopping charging or notifying the user is performed. As a result, the reliability of the battery pack can be improved.

  Incidentally, the abnormality determination of the voltage monitoring circuit by the control means may be executed when a battery voltage abnormality is detected from the monitoring result of one of the first voltage monitoring circuit and the second voltage monitoring circuit. However, this makes it impossible to frequently determine abnormality of the voltage monitoring circuit, and it is not possible to quickly detect abnormality of the first voltage monitoring circuit or the second voltage monitoring circuit.

  Therefore, as described in claim 2, the control means is configured so that at least one of the battery voltages monitored by the first voltage monitoring circuit and the second voltage monitoring circuit is under a normal charging / discharging condition of the battery (in other words, It is preferable that the monitoring results of the first voltage monitoring circuit and the second voltage monitoring circuit are compared when they are within the upper and lower limit voltage ranges during normal operation of the battery.

  In other words, in this way, the abnormality determination of the voltage monitoring circuit by the control means can be performed at the normal time when the battery voltage is within the upper limit / lower limit voltage range, and the frequency of the abnormality determination is increased. Thus, the abnormality of the voltage monitoring circuit can be detected earlier.

  The upper limit of the upper limit / lower limit voltage range is the charge completion voltage to prevent overcharge when charging the battery and to ensure the life, and the lower limit is to prevent overdischarge when discharging from the battery. The discharge end voltage for ensuring the life.

  More ideally, the upper limit is set to the lowest charge completion voltage when charging is completed to prevent overcharging when charging the battery, and the lower limit is set to discharge to prevent overdischarge when discharging from the battery. It is better to set the highest discharge end voltage at the end.

Next, in the battery pack according to the third aspect, the second voltage monitoring circuit outputs a comparison result between the battery voltage and the reference voltage to the control means as a monitoring result.
In other words, the voltage monitoring circuit is usually configured by an analog circuit that measures the battery voltage. However, according to the battery pack of claim 3, the second voltage monitoring circuit calculates the battery voltage and the reference voltage. It is comprised by the comparison circuit to compare.

  For this reason, according to the battery pack of the third aspect, the configuration can be simplified and the cost of the battery pack can be reduced as compared with the case where the two voltage monitoring circuits are configured by analog circuits for voltage measurement. Can be achieved.

  Further, the second voltage monitoring circuit is configured by the comparison circuit in this way, and the first voltage monitoring circuit is configured by the analog circuit that detects the voltage of the battery and outputs the detection result to the control means as the monitoring result. In this case, the control means may be configured as described in claim 4.

  That is, in the battery pack according to claim 4, when the output of the second voltage monitoring circuit changes, the control unit compares the reference voltage of the second voltage monitoring circuit with the monitoring result of the first voltage monitoring circuit. .

  Therefore, according to the battery pack of claim 4, when the voltage of the battery crosses the reference voltage by the second voltage monitoring circuit and becomes equal to or higher than the reference voltage or lower than the reference voltage, the monitoring result by the second voltage monitoring circuit By comparing the (reference voltage) and the monitoring result (battery voltage) by the first voltage monitoring circuit, an abnormality of the first voltage monitoring circuit or the second voltage monitoring circuit can be determined.

  In order to increase the execution frequency of the abnormality determination of the voltage monitoring circuit by the control means by applying the invention according to claim 2 to the battery pack according to claim 4, the second voltage monitoring circuit is connected to the battery voltage. The reference voltage to be compared with may be set as described in claim 5.

  That is, in the battery pack according to claim 5, the reference voltage is an average value of a full charge stop voltage at which the control unit stops charging the battery and a discharge stop voltage at which the control unit stops discharging from the battery. Based on this, the voltage value is set to be substantially the same as the average value.

As a result, the output from the second voltage monitoring circuit frequently changes during normal use of the battery, and the frequency of executing the abnormality determination of the voltage monitoring circuit can be increased.
Next, in the battery pack according to claim 6, the first voltage monitoring circuit and the second voltage monitoring circuit are configured to monitor the cell voltage for each of a plurality of cells constituting the battery. And a control means compares the monitoring result of the cell voltage by a 1st voltage monitoring circuit and a 2nd voltage monitoring circuit for every several cell.

  Therefore, according to the battery pack of claim 6, in the control means, not only can the abnormality of the first voltage monitoring circuit or the second voltage monitoring circuit be determined, but also based on the monitoring result by each voltage monitoring circuit, A cell abnormality can be detected for each cell constituting the battery.

  By the way, in the battery pack according to claim 6, when the invention according to claim 4 is applied, the cell voltage and the reference voltage are compared for each cell constituting the battery in the second voltage monitoring circuit. A plurality of comparison circuits are provided.

  In this case, if the output from each comparison circuit is input to the control means as it is, the reference voltage when the output from the comparison circuit changes for each cell and the first voltage monitoring circuit detects it. By comparing the cell voltage, an abnormality of the first voltage monitoring circuit or the second voltage monitoring circuit can be determined.

  However, if the outputs from the plurality of comparison circuits constituting the second voltage monitoring circuit are individually input to the control means, the signal path and the signal input port to the control means are set to the number of comparison circuits (in other words, For example, the number of cells constituting the battery needs to be prepared, which may increase the cost of the battery pack.

Therefore, in order to prevent such a problem, the second voltage monitoring circuit may be configured as described in claim 7.
That is, in the battery pack according to claim 7, the second voltage monitoring circuit includes a plurality of comparison circuits that compare the cell voltage of each cell with a reference voltage set to a different value for each cell, and The circuit comparison results are combined into one output and output to the control means.

  As a result, according to the battery pack described in claim 7, not only the invention described in claim 4 can be applied to the battery pack described in claim 6, but also from the second voltage monitoring circuit to the control means. The signal path can be reduced.

  Therefore, according to the battery pack of the seventh aspect, even if the second voltage monitoring circuit is constituted by a plurality of comparison circuits corresponding to the respective cells constituting the battery, the second voltage monitoring circuit is transferred to the control means. The signal path and the signal input port of the control means can be prevented from increasing according to the number of cells constituting the battery.

  According to the battery pack described in claim 7, the reference voltages of the plurality of comparison circuits constituting the second voltage monitoring circuit are set to different voltage values. This is because the cell in which the comparison result (in other words, the output) has changed can be identified.

  That is, since the reference voltage is set to a different cell voltage, the comparison result (in other words, the output) by the comparison circuit changes in order according to the set reference voltage. For this reason, when one comparison result (in other words, output) of the comparison circuit changes and a signal indicating that change is input to the control means via a signal path common to each comparison circuit, the comparison is performed on the control means side. Based on the order in which the results have changed, the cells in which the comparison results have changed can be identified.

  If the cell can be specified, an abnormality occurs in the first voltage monitoring circuit or the second voltage monitoring circuit by comparing the reference voltage corresponding to the cell with the cell voltage detected by the first voltage monitoring circuit. It can be determined whether or not.

  Next, in the battery pack according to claim 8, the first voltage monitoring circuit and the second voltage monitoring circuit include impedances on each voltage monitoring circuit side from positive electrodes and negative electrodes of a plurality of cells constituting the battery. Each cell voltage is input through the element.

  For this reason, even if a resistance short-circuit failure occurs between the wires that input the cell voltage to one of the voltage monitoring circuits, the effect of the failure is limited to only one voltage monitoring circuit in which the resistance short-circuit failure has occurred. Since this voltage monitoring circuit operates normally, an abnormality of the voltage monitoring circuit can be detected.

  That is, when the battery pack is provided with the first voltage monitoring circuit and the second voltage monitoring circuit as in the present invention, a voltage monitoring signal line is drawn out from each cell of the battery pack via a resistor, and the signal line is A method of distributing to the system and connecting to each voltage detection circuit is also conceivable.

  In this case, when a resistance short-circuit fault occurs due to foreign matter adhering between the cell voltage input terminals on one of the first voltage monitoring circuit and the second voltage monitoring circuit, the terminals are The voltage value is lower than the cell voltage of the cell, and the cell voltage of adjacent cells is also affected.

  Such cell voltage changes occur not only in the voltage monitoring circuit where the resistance short-circuit failure has occurred, but also in the other voltage monitoring circuit. Cannot be detected.

  Further, when the cell voltage changes due to a resistance short-circuit failure, the safety of the battery pack can be ensured if a cell abnormality can be detected from the cell voltage monitoring result by each voltage monitoring circuit. However, when the control means is configured to perform so-called cell balance, which controls so that each cell voltage becomes equal when voltage imbalance occurs between cells, a voltage monitoring circuit having a resistance short-circuit fault The cell balance is executed from the cell voltage monitoring result of, and apparently the voltage of each cell has the same monitoring result, so that the cell abnormality cannot be detected.

Further, in this case, due to the cell balance, the cell in which the resistance short-circuit failure has occurred is charged, so that the cell may fall into an overcharged state.
However, if configured as described in claim 8, it is possible to prevent such a problem and to detect an abnormality of the voltage monitoring circuit due to a resistance short-circuit failure, thereby improving the reliability of the battery pack. it can.

It is a perspective view showing the external appearance of the battery pack of 1st Embodiment. It is a circuit diagram showing the circuit structure of the battery pack and charger of 1st Embodiment. It is a flowchart showing the charge control process performed in a charge control circuit. It is a flowchart showing the interruption process at the time of charge performed in a charge control circuit. It is a circuit diagram showing the structure of a 1st voltage monitoring circuit. It is a circuit diagram showing the structure of a 2nd voltage monitoring circuit. It is a flowchart showing the abnormality determination process performed in a battery control circuit. It is a circuit diagram showing the structure of the 2nd voltage monitoring circuit of 2nd Embodiment. It is a flowchart showing the abnormality determination process of 2nd Embodiment. It is a flowchart showing the modification of the abnormality determination process in 1st Embodiment. It is a flowchart showing the modification of the abnormality determination process in 2nd Embodiment.

Embodiments and modifications of the present invention will be described below with reference to the drawings.
[First Embodiment]
As shown in FIG. 1, the battery pack 2 of this embodiment is detachably mounted on various rechargeable electric devices such as a rechargeable electric tool, a rechargeable vacuum cleaner, a rechargeable mower, etc., and supplies power. In addition, a mounting portion 3 that is detachably mounted on the electric device main body is formed on one side surface of the housing.

  The mounting portion 3 is provided with a battery-side terminal 4 that is electrically connected to a terminal of the electric device main body or the charger. The battery side terminal 4 is provided with a positive terminal 6 and a negative terminal 7 through which a charge / discharge current is passed, and an input / output terminal 8 for signal input / output.

  As shown in FIG. 2, a battery 10 in which a plurality of chargeable / dischargeable (five in the figure) cells 11, 12, 13, 14, 15 are connected in series is housed in the battery pack 2. The positive side of the battery 10 is connected to the positive terminal 6, and the negative side of the battery 10 is connected to the negative terminal 7. In the present embodiment, the battery 10 is a lithium ion battery.

  Further, the battery pack 2 is provided with a first voltage monitoring circuit 20, a second voltage monitoring circuit 30, a battery control circuit 40, a temperature detection circuit 42, a current detection circuit 44, and a protection circuit 46.

  Here, the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 monitor the cell voltages Vc <b> 1 to Vc <b> 5 of the cells 11 to 15 constituting the battery 10, and output the monitoring results to the battery control circuit 40. Each of these voltage monitoring circuits 20 and 30 is a main part of the present invention and will be described in detail later.

  Further, the temperature detection circuit 42 detects the internal temperature (cell temperature) of the battery 10 via a temperature detection element (not shown) built in the battery 10 in order to prevent overheating of the battery 10, and detects the detection. The result is output to the battery control circuit 40.

  The current detection circuit 44 is provided in an energization path from the negative electrode terminal 7 to the negative electrode of the battery 10 and detects a current flowing through this path. For example, a current detection circuit 44 includes a resistor provided in series with the energization path. And a detection circuit that outputs the voltage across the resistor to the battery control circuit 40 as a current detection result.

  Further, the protection circuit 46 is constituted by, for example, a power semiconductor switch provided in an energization path from the positive electrode of the battery 10 to the positive electrode terminal 6, and interrupts the energization path in accordance with a command from the battery control circuit 40.

On the other hand, the battery control circuit 40 is configured by a microcomputer (microcomputer) mainly including a CPU, a ROM, a RAM, and the like.
The battery control circuit 40 includes an analog input port Pa1 for A / D converting and capturing the monitoring results of the cell voltages Vc1 to Vc5 by the first voltage monitoring circuit 20, and the cell voltages Vc1 to Vc1 by the second voltage monitoring circuit 30. Digital input ports Pd1 to Pd5 for capturing the monitoring results of Vc5 are provided.

  Further, the battery control circuit 40 includes an output port Po1, a temperature detection circuit 42, and a current for outputting a control signal for selecting the monitoring result output from the first voltage monitoring circuit 20 from the cell voltages Vc1 to Vc5. Analog input ports Pa2 and Pa3 for taking in a detection signal from the detection circuit 44 are provided.

  The battery control circuit 40 receives the monitoring results of the cell voltages Vc1 to Vc5 by the voltage monitoring circuits 20 and 30 and the temperature detection circuit 42, which are input via the input ports Pd1 to Pd5 and Pa1 to Pa3. The detection result by the current detection circuit 44 is taken in, and charging / discharging of the battery 10 is controlled based on the taken-in parameters.

  The battery control circuit 40 has an output port Po2 for outputting a control signal for switching the conduction / cutoff state of the energization path by the protection circuit 46, and an electric device main body (not shown) to which the battery pack 2 is attached. Alternatively, a communication port Prx for performing communication with the charger 50 is also provided. The communication port Prx is connected to the input / output terminal 8 via a communication line.

  When the battery control circuit 40 detects an abnormality such as a cell voltage, a charge / discharge current, or a temperature based on the above parameters, the battery control circuit 40 outputs a cutoff signal from the output port Po2, thereby blocking the protection circuit 46 and charging / discharging. By stopping and outputting a communication signal indicating that from the communication port Prx, the electric device main body or the charger 50 is notified of the stop of charging / discharging.

  Further, the battery control circuit 40 compares the monitoring results of the cell voltages Vc1 to Vc5 by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 when the battery 10 is charged / discharged, so that the first voltage monitoring circuit 20 or The abnormality of the second voltage monitoring circuit 30 is determined.

  Even when the abnormality of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is determined, the battery control circuit 40 stops charging / discharging by the protection circuit 46 and also causes the electric device main body or the charger 50 to Notify that.

  Further, when the battery control circuit 40 determines that the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal, the battery control circuit 40 informs the nonvolatile memory (not shown) built in the battery control circuit 40 to that effect. By memorize | storing, charging / discharging of the battery 10 is prohibited after that.

The abnormality determination operation of the voltage monitoring circuit by the battery control circuit 40 is a main operation according to the present invention, and will be described in detail later.
The battery pack 2 is also provided with a power supply circuit (not shown) that receives power supply from the battery 10 and generates a power supply voltage (DC constant voltage) Vcc for driving an internal circuit such as the battery control circuit 40. ing.

  Next, the charger 50 includes power supply terminals 52 and 54 for receiving power supply from an external power source (not shown) (for example, commercial power source), and charges the battery 10 in the battery pack 2 by the power supplied from the external power source. Is for.

  Therefore, when the battery pack 2 is attached to the charger 50, the positive terminal 56, the negative terminal 57, and the negative terminal 57, which are connected to the positive terminal 6, the negative terminal 7, and the input / output terminal 8 of the battery pack 2, respectively. In addition, an input / output terminal 58 is provided.

  The charger 50 includes a rectifier circuit 60 for full-wave rectification of an AC voltage supplied from an external power source to the power terminals 52 and 54, a capacitor C1 for smoothing the DC voltage rectified by the rectifier circuit 60, In addition, an insulating transformer 62 having a primary winding connected in parallel to the capacitor C1 through the switching element 64 is provided.

The insulation transformer 62 is for insulating between the external power supply and the internal circuit, and for stepping down the DC voltage smoothed by the capacitor C1 and taking it into the charger 50.
In other words, the switching element 64 is provided between one end of the primary winding and the ground, and is connected to one end of the capacitor C1 grounded to the ground. A step-down AC power is generated in the next winding. The switching element 64 is composed of, for example, an n-channel MOSFET, and is turned on when a high level signal is input to the gate via the resistor Rc.

  A capacitor C <b> 2 is connected in parallel to the secondary winding of the insulating transformer 62 via a rectifying diode 66. The capacitor C <b> 2 is charged with a DC voltage by switching of the switching element 64, and the DC voltage is used as a charging voltage for the battery 10.

For this reason, the positive electrode side and the negative electrode side of the capacitor C2 are connected to the positive electrode terminal 56 and the negative electrode terminal 57, respectively.
In addition, a charging switch 68 is provided in the energization path between the positive electrode side of the capacitor C2 and the positive electrode terminal 56 to conduct / cut off the path.

  The charge switch 68 is a power semiconductor switch composed of a pair of FETs 68a and 68b. The gates of the FETs 68a and 68b are connected to the current-carrying path on the positive electrode side via the resistor Ra, and the resistor Rb and the switching element. 69 is connected to the current-carrying path on the negative electrode side.

  The FETs 68a and 68b are composed of p-channel MOSFETs. The resistors Ra and Rb and the switching element 69 are energized on the positive side by setting the gate potential of each FET 68a and 68b to a low level when the switching element 69 is turned on. Make the path conductive. Further, when the switching element 69 is turned off, the gate potentials of the FETs 68a and 68b are set to a high level to cut off the positive-side energization path.

  The diodes Da and Db shown in FIG. 2 are parasitic diodes of the FETs 68a and 68b. Further, the switching element 69 is composed of, for example, an n-channel MOSFET, and is turned off when the gate potential is at a low level, and turned on when the gate potential is at a high level.

Next, a current detection circuit 78 for detecting a charging current that flows during charging of the battery 10 is provided in the negative-side energization path between the capacitor C <b> 2 and the negative terminal 57.
The current detection circuit 78 is, for example, a detection that outputs, as a current detection result, a resistor provided in series with the current-carrying path on the negative electrode side and a voltage across the resistor, as with the current detection circuit 44 in the battery pack 2. Circuit.

The detection signal from the current detection circuit 78 is input to a current control circuit 76 that controls the charging current in accordance with a command from the charging control circuit 80.
The current control circuit 76 outputs a switching signal to the drive circuit 72 that drives the switching element 64 via the photocoupler 74, thereby turning the switching element 64 on and off, and charging current to the battery 10. Control.

  The photocoupler 74 is a well-known one composed of, for example, a light emitting diode Dr and a phototransistor Tf, and a forward voltage is applied from the current control circuit 76 to the light emitting diode Dr via the resistor Rd. The light emitting diode Dr emits light, and the phototransistor Tf is turned on.

Therefore, the internal circuit of the charger 50 and the external power supply side are also insulated by the photocoupler 74.
Next, a charger output voltage detection circuit 84 that detects the voltage Va of the path as a charger output voltage is connected to the energization path between the charging switch 68 and the capacitor C2.

A battery voltage detection circuit 82 that detects the voltage Vb of the path as a battery voltage is connected to the energization path between the charging switch 68 and the positive terminal 56.
The detected voltages Va and Vb from these voltage detection circuits 82 and 84 are input to the charge control circuit 80.

  The charge control circuit 80 controls the charging current controlled by the current control circuit 76 based on the battery voltage Vb detected by the battery voltage detection circuit 82 in accordance with the state of charge of the battery 10. It is composed of a microcomputer (microcomputer) centered on ROM, RAM and the like.

The charging control circuit 80 generates a pulse width modulation signal (PWM signal) as a command signal for causing the current control circuit 76 to control the charging current, and outputs the pulse width modulation signal (PWM signal) to the output circuit 79.
The output circuit 79 is an integrating circuit constituted by a resistor Re and a capacitor C3, converts a PWM signal into an analog voltage value, and converts this into a current control circuit via a buffer circuit composed of an operational amplifier OP1 and a resistor Rf. Output to 76.

  In addition, when charging the battery 10, the charging control circuit 80 turns on the charging switch 68 via the switching element 69 and makes the charging path to the battery 10 conductive, but the charging current to the battery 10 is excessive (that is, excessive). Current), the charging switch 68 is turned off to stop charging.

  In addition, an input / output terminal 58 is connected to the charging control circuit 80. When charging is stopped by detecting an overcurrent, the battery control circuit 40 is notified to that effect via the input / output terminals 58 and 8. To be notified. Note that the charging control circuit 80 also stops charging the battery 10 when receiving an abnormal signal from the battery control circuit 40.

  In the present embodiment, since the battery 10 is a lithium ion battery, the charging control circuit 80 performs constant current charging until the battery voltage Vb reaches the predetermined voltage Vx after the charging of the battery 10 is started. When the predetermined voltage Vx is reached, charging is performed by constant voltage charging until the battery 10 is fully charged.

Next, the charging control process executed by the charging control circuit 80 in this way will be described along the flowchart shown in FIG.
As shown in FIG. 3, in the charging control process, it is first determined in S110 (S represents a step) whether or not the battery 10 is connected to the positive terminal 56 and the negative terminal 57.

  If the battery 10 is not connected, the process of S110 is executed to wait for the battery 10 to be connected. If the battery 10 is connected, the process proceeds to S120 and the charge switch 68 is turned on. The battery 10 is put into a state and constant current charging to the battery 10 is started.

In the constant current charging, the charging current to the battery 10 is controlled to a preset constant current, so that a PWM signal having a preset duty ratio is output to the output circuit 79.
As a result, an analog control signal for controlling the charging current to a constant current is output from the output circuit 79 to the current control circuit 76, and the current control circuit 76 converts the detected voltage from the current detection circuit 78 into the analog control signal. The drive circuit 72 is operated so as to obtain a corresponding constant voltage.

When constant current charging is started in S120, it is determined in S130 whether or not a current abnormality flag is set.
The current abnormality flag is set when an abnormality in the charging current is detected in the interruption process during charging (see FIG. 4) executed every predetermined time by the charging control circuit 80 after the charging of the battery 10 is started. Flag to be

  If it is determined in S130 that the current abnormality flag is set, the process proceeds to S210, and the charging switch 68 is turned off to abnormally terminate the charging of the battery 10.

  On the other hand, if it is determined in S130 that the current abnormality flag is not set, the process proceeds to S140, and it is determined whether or not the battery voltage Vb detected by the battery voltage detection circuit 82 has become equal to or higher than the predetermined voltage Vx. To do.

  If the battery voltage Vb has not reached the predetermined voltage Vx, the process proceeds to S120 again to continue constant current charging to the battery 10, and if the battery voltage Vb is equal to or higher than the predetermined voltage Vx, the process proceeds to S150. Then, the charging method for the battery 10 is switched from constant current charging to constant voltage charging.

  In this constant voltage charging, the battery current is supplied to the current control circuit 76 so that the charging voltage to the battery 10 becomes a substantially constant voltage Vx by gradually decreasing the duty ratio of the PWM signal in S180 described later. Let me control.

When the charging method for battery 10 is switched to constant voltage charging in S150, the process proceeds to S160 to determine whether or not the current abnormality flag is set.
If the current abnormality flag is set, the process proceeds to S210 to end the charging of the battery 10, and if the current abnormality flag is not set, the process proceeds to S170 and is detected by the battery voltage detection circuit 82. Whether the battery voltage Vb is equal to or higher than the predetermined voltage Vx + α is determined. Α is a variation allowable value of the battery voltage Vb.

  If it is determined in S170 that the battery voltage Vb is equal to or higher than the predetermined voltage Vx + α, the process proceeds to S180, the duty ratio (PWM value) of the PWM signal is decreased by a predetermined correction amount, and the process proceeds to S190. If it is determined in S170 that the battery voltage Vb is not equal to or higher than the predetermined voltage Vx + α, the process proceeds to S190 as it is.

In S190, it is determined whether or not the duty ratio (PWM value) of the PWM signal is less than a preset threshold value (for example, a value corresponding to a charging current of 100 mA).
If the PWM value is not less than the threshold value, the process proceeds to S150 again, and constant voltage charging is continued. If the PWM value is less than the threshold value, it is determined that the battery 10 is fully charged. The process proceeds to S200, and the charging switch 68 is turned off to complete the charging of the battery 10.

  Next, in the interruption process at the time of charging shown in FIG. 4, first, in S310, the energization path voltage on both sides of the charging switch 68 (that is, the battery voltage) via the battery voltage detection circuit 82 and the charger output voltage detection circuit 84. Vb and charger output voltage Va) are read.

  Next, in S320, based on the difference (Va−Vb) between the read voltages Va and Vb, the on-resistance Rfeton of the FETs 68a and 68b constituting the charge switch 68, and the correction coefficient β, the positive-side energization path is determined. A flowing current value (specifically, a charging current equivalent value) is calculated, and it is determined whether or not this current value is equal to or greater than a preset threshold value.

  That is, in S320, the charging current to the battery 10 is obtained based on the voltages Va and Vb on both sides of the charging switch 68, and it is determined whether or not the current value is greater than or equal to the threshold value. Is not an abnormal value (that is, overcurrent).

  If it is determined in S320 that the current value is equal to or greater than the threshold value, the process proceeds to S330, the current abnormality flag is set, and the charging interruption process is terminated. If it is determined in S320 that the current value is less than the threshold value, the process proceeds to S340, the current abnormality flag is cleared (reset), and the charging interruption process is terminated.

  As described above, the charging control circuit 80 sequentially performs constant current charging and constant voltage charging to charge the battery 10, and if the charging current becomes excessive at the time of charging, the current abnormality flag is set. Then, charging the battery 10 is stopped.

  Next, based on the configuration of the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 provided in the battery pack 2 and the monitoring results by the voltage monitoring circuits 20 and 30, the battery control circuit 40 is connected to the voltage monitoring circuit. An abnormality determination operation for performing abnormality determination will be described.

  As shown in FIG. 5, the first voltage monitoring circuit 20 has input terminals Ti10 to Ti10 connected to the positive and negative electrodes of the cells 11 to 15 constituting the battery 10 through resistors R10 to R15, respectively, which are impedance elements. Ti15 is provided.

  Further, in the first voltage monitoring circuit 20, positive electrodes Sa1 to Sa5 for selectively taking in positive potentials of the cells 11 to 15 from the input terminals Ti11 to Ti15, and each cell 11 to 11 from the input terminals Ti10 to Ti14. Negative electrode switches Sb1 to Sb5 for selectively taking in the negative electrode potential of 15 are provided. The positive switches Sa1 to Sa5 and the negative switches Sb1 to Sb5 are constituted by analog switches.

  And the positive electrode side potential and the negative electrode side potential of each cell 11-15 selectively taken in via these positive electrode switches Sa1-Sa5 and negative electrode switches Sb1-Sb5 are inputted (charged) to the capacitor C4, and further, the capacitor C4 (Cell voltages Vc1 to Vc5) are amplified and input to the amplifier circuit 24 that outputs the output terminal To1 to the analog input port Pa1 of the battery control circuit 40.

Further, the first voltage monitoring circuit 20 is provided with an input terminal Tc1 for inputting a control signal output from the output port Po1 of the battery control circuit 40.
The control signal input to the input terminal Tc1 is input to the switch controller 22, and is used to set the positive switches Sa1 to Sa5 and the negative switches Sb1 to Sb5 that are selectively turned on by the switch controller 22. .

As a result, one of the cell voltages Vc1 to Vc5 of the plurality of cells 11 to 15 is selectively output from the first voltage monitoring circuit 20 to the battery control circuit 40.
Moreover, between the input terminals Ti10-Ti15 of the 1st voltage monitoring circuit 20, discharge switch Sc1-Sc5 which discharges each cell 11-15 by short-circuiting between adjacent input terminals Ti10-Ti15, respectively is provided. ing. The discharge switches Sc1 to Sc5 are configured by analog switches like the positive switches Sa1 to Sa5 and the negative switches Sb1 to Sb5.

  The discharge switches Sc <b> 1 to Sc <b> 5 are used for the cell balance described above, and are turned on / off by the switch controller 22 when the battery control circuit 40 performs the cell balance. That is, the switch controller 22 performs cell balancing by turning on the discharge switches Sc1 to Sc5 in accordance with the control signal input from the battery control circuit 40.

  The first voltage monitoring circuit 20 is also provided with a ground terminal Tg1 that is grounded to the ground of the battery pack 2. Therefore, the switch controller 22 connects the negative input line of the amplifier circuit 24 to the ground terminal Tg1 via the switch Sg0, so that the ground potential of the first voltage monitoring circuit 20 and the ground potential of the battery control circuit 40 are connected. Can be matched.

  Next, as illustrated in FIG. 6, the second voltage monitoring circuit 30 includes resistors R <b> 20 to R <b> 20 that are impedance elements in the positive and negative electrodes of the cells 11 to 15 that constitute the battery 10, as in the first voltage monitoring circuit 20. Input terminals Ti20 to Ti25 that are respectively connected via R25 are provided.

  In the second voltage monitoring circuit 30, among the input terminals Ti20 to Ti25, cell voltages Vc1 to Vc5 of the cells 11 to 15 generated between adjacent input terminals and a reference voltage Vt0 (for example, 3.7 V). Are provided with comparison circuits (that is, comparators) CMP1 to CMP5.

  The comparators CMP1 to CMP5 are configured to output a high level detection signal when the corresponding cell voltages Vc1 to Vc5 are equal to or higher than the reference voltage Vt0. The detection signals from the comparators CMP1 to CMP5 are output from the output terminals To21 to To25 to the digital input ports Pd1 to Pd5 of the battery control circuit 40, respectively.

  Therefore, the battery control circuit 40 can detect the cell voltages Vc1 to Vc5 and the battery voltages of the cells 11 to 15 constituting the battery 10 via the first voltage monitoring circuit 20, and the battery voltage is fully charged during charging. When the charge stop voltage is reached, or when the battery voltage drops to the discharge stop voltage when discharging to the electric device main body, charging / discharging of the battery 10 can be stopped via the protection circuit 46.

  The reference voltage of each of the comparators CMP1 to CMP5 in the second voltage monitoring circuit 30 is from the discharge stop voltage to the full charge stop voltage so that it is within the upper limit / lower limit voltage range under the normal charge / discharge conditions of the battery 10. Is set to an intermediate value (in this embodiment, an average value of the discharge stop voltage and the full charge stop voltage).

Next, the abnormality determination process executed in the battery control circuit 40 to determine the abnormality of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is executed according to the procedure shown in FIG.
That is, in this abnormality determination process, first, in S410, it is determined whether or not there is a cell in which the detection signal output from the second voltage monitoring circuit 30 has changed from the low level to the high level.

  If it is not determined that there is a cell whose detection signal has changed in S410, the process waits for the detection signal from the second voltage monitoring circuit 30 to change by executing S410 again. If it is determined that there is a changed cell, the process proceeds to S420.

  In S420, the cell voltage of the cell (detection cell) in which the detection signal has changed is measured via the first voltage monitoring circuit 20, and in S430, the measured cell voltage is an allowable range centered on the reference voltage Vt0. It is determined whether it is within (Vt0 ± dV).

  That is, when the detection signal output from the second voltage monitoring circuit 30 changes from the low level to the high level, the cell voltage of the cell corresponding to the detection signal is the reference voltage Vt0 in the second voltage monitoring circuit 30. Since it is when it is detected, in S430, the first voltage monitoring circuit 20 also determines whether or not the cell voltage of the cell is detected as the reference voltage Vt0.

  In S430, when it is determined that the cell voltage measured by the first voltage monitoring circuit 20 is substantially the same as the reference voltage Vt0, the cell voltage measured by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 is determined. Assuming that the measurement results are the same and that each of the voltage monitoring circuits 20 and 30 is operating normally, the abnormality determination process is temporarily terminated, and then the processes after S410 are executed again.

  On the other hand, if it is determined in S430 that the cell voltage measured by the first voltage monitoring circuit 20 is not within the allowable range (Vt0 ± dV) around the reference voltage Vt0, the first voltage monitoring circuit 20 and the first voltage monitoring circuit 20 It is determined that any one of the two voltage monitoring circuits 30 is abnormal, and the process proceeds to S440.

  In S440, the protective circuit 46 cuts off the energization path, performs an error output process for prohibiting the charger 50 or the electric device main body from being charged or discharged, and further stores the first voltage monitoring circuit 20 or the nonvolatile memory. The fact that there is an abnormality in any of the second voltage monitoring circuits 30 is stored, and the abnormality determination process ends.

  After the execution of S440, the abnormality of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is stored in the non-volatile memory. Therefore, charging / discharging of the battery 10 is prohibited, and the abnormality determination process is executed again. Never happen.

  As described above, the battery pack 2 of the present embodiment includes the two voltage monitoring circuits of the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30, and the battery control circuit 40 includes each of these voltage monitoring circuits. By comparing the cell voltage monitoring results of the voltage monitoring circuits 20 and 30, the abnormality of the voltage monitoring circuit 20 or 30 is determined.

  Therefore, according to the battery pack 2 of the present embodiment, when one of the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 fails, the fact is detected and the charging / discharging of the battery 10 is stopped. As a result, the reliability of the battery pack 2 can be improved.

  The second voltage monitoring circuit 30 includes comparators CMP1 to CMP5 that compare the cell voltages of the cells 11 to 15 with the reference voltage Vt0. Therefore, the first voltage for detecting the cell voltages Vc1 to Vc5 is used. Compared to the monitoring circuit 20, the configuration can be simplified.

  The reference voltage Vt0 is not a voltage value for detecting an abnormality in the cell voltages Vc1 to Vc5, but a voltage value within the upper and lower limit voltage ranges under the normal charging / discharging conditions of the battery 10 (specifically, the discharge is stopped) The average value of the voltage and the full charge stop voltage) is set.

  For this reason, the detection signal from the second voltage monitoring circuit 30 frequently changes during normal use of the battery 10, and the frequency of abnormality determination of the voltage monitoring circuits 20 and 30 executed in accordance with the change is determined. Can be increased.

  Therefore, according to the battery pack 2 of the present embodiment, when an abnormality occurs in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, it is possible to detect that fact earlier, and the battery pack The safety at the time of use of 2 can be improved.

  In this embodiment, resistors R10 to R15 and R20 to R25, which are impedance elements, are connected to the input terminals Ti10 to Ti15 and Ti20 to Ti25 of the voltage monitoring circuits 20 and 30, respectively. , R20 to R25, the cell voltages Vc1 to Vc5 of the cells 11 to 15 are taken in.

  For this reason, in each voltage monitoring circuit 20, 30, even if a foreign substance adheres between the input terminals Ti10 to Ti15 or between the input terminals Ti20 to Ti25 and a resistance short-circuit failure occurs, the effect of the failure is resistance. Only one voltage monitoring circuit 20 or 30 in which a short-circuit failure has occurred remains, and the other voltage monitoring circuit 30 or 20 operates normally.

  For this reason, according to the battery pack 2 of the present embodiment, when a resistance short-circuit failure occurs in one of the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30, the abnormality determination process shown in FIG. Thus, the abnormality of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 can be determined.

  Therefore, according to the battery pack 2 of the present embodiment, when the voltage monitoring circuits 20 and 30 are configured to input the cell voltages Vc1 to Vc5 of the cells 11 to 15 via the common resistance, In comparison, the reliability of the battery pack 2 can be improved.

In the present embodiment, the battery control circuit 40 corresponds to the control means of the present invention.
[Second Embodiment]
In the first embodiment, outputs from the comparators CMP1 to CMP5 constituting the second voltage monitoring circuit 30 are input to the digital input ports Pd1 to Pd5 of the battery control circuit 40, respectively.

  However, in this case, not only the signal path between the second voltage monitoring circuit 30 and the battery control circuit 40 is increased, but the number of input ports of the battery control circuit 40 is also increased as compared with the first voltage monitoring circuit 20. There is a problem that the battery control circuit 40 cannot be realized with a microcomputer having a large number of input ports.

  Therefore, in the second embodiment, the configuration of the second voltage monitoring circuit 30 suitable for reducing the signal path between the second voltage monitoring circuit 30 and the battery control circuit 40 and the number of input ports of the battery control circuit 40. The abnormality determination process will be described.

  As shown in FIG. 8, the second voltage monitoring circuit 30 of the present embodiment is provided with only one output terminal To2, and input terminals Ti21 to Ti25 connected to the positive side of each of the cells 11 to 15; The output terminal To2 is connected via output switches So1 to So5 which are analog switches.

  Further, between the output switches So1 to So4 corresponding to the cells 11 to 14 and the output terminal To2, current is prevented from flowing from the output terminal To2 side to the input terminals Ti21 to Ti24 via the output switches So1 to So4. , Diodes Do1 to Do4 for backflow prevention are provided.

  Further, the second voltage monitoring circuit 30 of the present embodiment is provided with comparators CMP1 to CMP5, similar to that shown in FIG. 6, but the reference voltages of the comparators CMP1 to CMP5 are different from each other. The voltages Vt1 to Vt5 are set.

  The reference voltages Vt1 to Vt5 are such that, of the five cells 11 to 15, the comparator corresponding to the negative electrode side has a lower reference voltage, and the comparator corresponding to the positive electrode side has a higher reference voltage. Is set.

  For example, the reference voltage Vt1 of the comparator CMP1 is 3.6V, the reference voltage Vt2 of the comparator CMP2 is 3.7V similar to the above embodiment, the reference voltage Vt3 of the comparator CMP3 is 3.8V, and the reference voltage Vt4 of the comparator CMP4 is 3. 9V and the reference voltage Vt5 of the comparator CMP5 are set to 4.0V, respectively.

  The output switches So1 to So5 are switched on when the outputs of the comparators CMP1 to CMP5 are at a high level, that is, when the cell voltages Vc1 to Vc5 are equal to or higher than the corresponding reference voltages Vt1 to Vt5, respectively.

  As a result, in the second voltage monitoring circuit 30, the positive electrode of the cell corresponding to the output switch whose potential at the output terminal To2 is located on the highest potential side of the ground potential among the output switches So1 to So5 in the on state. It almost coincides with the side potential.

  Therefore, from the potential of the output terminal To2 of the second voltage monitoring circuit 30, the position of the output switch that has changed from the off state to the on state, in other words, the cell whose cell voltage is equal to or higher than the reference voltages Vt1 to Vt5 is specified. Can do.

Next, a voltage change detection circuit 32 and a cell voltage output circuit 34 are provided in a signal path from the second voltage monitoring circuit 30 to the battery control circuit 40.
The voltage change detection circuit 32 generates a trigger signal when any of the output switches So1 to So5 is switched on in the second voltage monitoring circuit 30 and the output voltage from the output terminal To2 changes (rises). This is a so-called one-shot circuit.

That is, the voltage change detection circuit 32 includes two comparators CMPa and CMPb whose output terminals are connected to the digital input port Pd of the battery control circuit 40.
A high potential and a low potential reference voltage are applied to the non-inverting input terminal of the comparator CMPa and the inverting input terminal of the comparator CMPb via resistors R22 to R24 that respectively divide the power supply voltage Vcc.

  The inverting input terminal of the comparator CMPa and the non-inverting input terminal of the comparator CMPb are connected to the output terminal To2 of the second voltage monitoring circuit 30 via the capacitor C21, and to the ground via the resistor R21 and the reference voltage source. Is grounded.

  The voltage Vtd of the reference voltage source is lower than the high potential reference voltage applied to the non-inverting input terminal of the comparator CMPa and higher than the low potential reference voltage applied to the inverting input terminal of the comparator CMPb. The voltage is set.

For this reason, the potentials of the inverting input terminal of the comparator CMPa and the non-inverting input terminal of the comparator CMPb are normally held at the voltage Vtd of the reference voltage source.
When one of the output switches is turned on in the second voltage monitoring circuit 30 and the voltage at the output terminal To2 rises, the inversion of the comparator CMPa is performed by the operation of the differentiation circuit composed of the capacitor C21 and the resistor R21. The potential of the input terminal and the non-inverting input terminal of the comparator CMPb temporarily rises, and the output of the comparator CMPa is inverted to a high level.

  Since the output of the comparator CMPb is held at a high level and does not change even if the potential of the non-inverting input terminal rises, the digital input port Pd of the battery control circuit 40 is connected to the second voltage monitoring circuit 30. Only when the potential of the output terminal To2 rises, it temporarily becomes high level.

  That is, the trigger signal is input to the digital input port Pd of the battery control circuit 40 only when the potential of the output terminal To2 of the second voltage monitoring circuit 30 rises. Therefore, the battery control circuit 40 side can detect that there is a cell whose cell voltage is equal to or higher than the reference voltages Vt1 to Vt5 by the input of the trigger signal.

  On the other hand, the cell voltage output circuit 34 is provided on the battery control circuit 40 side in order to be able to specify which of the cells 11 to 15 is the cell whose cell voltage is equal to or higher than the reference voltages Vt1 to Vt5. The output voltage Vo2 (the potential of the output terminal To2) from the second voltage monitoring circuit 30 is input to the analog input port Pa of the battery control circuit 40.

  That is, the cell voltage output circuit 34 is divided by the output voltage dividing resistors R25 and R26 provided between the output terminal To2 of the second voltage monitoring circuit 30 and the ground, and the resistors R25 and R26. The capacitor C22 is smoothed and input to the analog input port Pa of the battery control circuit 40.

  Next, the abnormality determination process executed by the battery control circuit 40 when the second voltage monitoring circuit 30 and the signal path from the second voltage monitoring circuit 30 to the battery control circuit 40 are configured as shown in FIG. A description will be given along the flowchart shown in FIG.

  In the abnormality determination process shown in FIG. 9, in S510, it is determined whether a trigger signal is input from the voltage change detection circuit 32 to the digital input port Pd, thereby waiting for the trigger signal to be input.

  When it is determined in S510 that the trigger signal has been input, the process proceeds to S520, where the voltage is divided from the cell voltage output circuit 34 and is input to the analog input port Pa from the second voltage monitoring circuit 30. The output voltage Vo2 is measured.

  Next, in S530, it is determined whether or not the output voltage Vo2 from the second voltage monitoring circuit 30 measured in S520 is within an allowable range (Vt1 ± dV1) centered on the reference voltage Vt1 of the comparator CMP1. .

  Then, when the output voltage Vo2 is within the allowable range (Vt1 ± dV1), it is determined that the current output has changed to the high level is the comparator CMP1, and the process proceeds to S540.

  In S540, the cell voltage Vc1 of the cell 11 corresponding to the comparator CMP1 is measured via the first voltage monitoring circuit 20, and in S550, the measured cell voltage Vc1 is within an allowable range centered on the reference voltage Vt1. It is determined whether or not (Vt1 ± dVc1).

  When the cell voltage Vc1 is within the allowable range (Vt1 ± dVc1), the measurement results of the cell voltage Vc1 by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 match, and each voltage monitoring circuit Assuming that 20 and 30 are operating normally, the abnormality determination process is temporarily terminated, and then the processes after S510 are executed again.

  On the other hand, if it is determined in S550 that the cell voltage Vc1 is not within the allowable range (Vt1 ± dVc1), it is determined that either the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal. , The process proceeds to S600.

  In S600, the protective circuit 46 cuts off the energization path, performs an error output process for prohibiting the charger 50 or the electric device main body from being charged or discharged, and further causes the nonvolatile memory to store the first voltage monitoring circuit 20 or The fact that there is an abnormality in any of the second voltage monitoring circuits 30 is stored, and the abnormality determination process ends.

  Next, in S530, when it is determined that the output voltage Vo2 from the second voltage monitoring circuit 30 is not within the allowable range (Vt1 ± dV1), the process proceeds to S560 and the second voltage monitoring circuit 30 It is determined whether the output voltage Vo2 is within an allowable range (Vt2 × 2 ± dV2) centered on a voltage value (Vt2 × 2) obtained by doubling the reference voltage Vt2 of the comparator CMP2.

  If the output voltage Vo2 is within the allowable range (Vt2 × 2 ± dV2), it is determined that the current output has changed to the high level is the comparator CMP2, and the process proceeds to S570.

  In S570, the cell voltage Vc2 of the cell 12 corresponding to the comparator CMP2 is measured via the first voltage monitoring circuit 20, and in S580, the measured cell voltage Vc2 is within an allowable range centered on the reference voltage Vt2. It is determined whether or not (Vt2 ± dVc2).

  When the cell voltage Vc2 is within the allowable range (Vt2 ± dVc2), the measurement results of the cell voltage Vc2 by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 match, and each voltage monitoring circuit Assuming that 20 and 30 are operating normally, the abnormality determination process is temporarily terminated, and then the processes after S510 are executed again.

  If it is determined in S580 that the cell voltage Vc2 is not within the allowable range (Vt2 ± dVc2), it is determined that either the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal. , S600 is executed, and the abnormality determination process is terminated.

  Next, when it is determined in S560 that the output voltage Vo2 from the second voltage monitoring circuit 30 is not within the allowable range (Vt2 × 2 ± dV2), the same procedure as in S560 is performed. Whether or not the output voltage Vo2 from the two-voltage monitoring circuit 30 is within an allowable range (Vt3 × 2 ± dV3) centered on a voltage value (Vt2 × 3) that is three times the reference voltage Vt3 of the comparator CMP3. “Whether the output voltage Vo2 from the second voltage monitoring circuit 30 is within an allowable range (Vt4 × 2 ± dV4) centered on a voltage value (Vt2 × 4) that is four times the reference voltage Vt4 of the comparator CMP4 ”In order, it is determined whether or not it is the comparator CMP3 or CMP4 that the output has changed to the high level this time.

  Then, when it is determined that the output has changed to the high level this time is the comparator CMP3 or CMP4, it corresponds to the comparators CMP3 and CMP4 via the first voltage monitoring circuit 20 in the same procedure as S570. The cell voltages Vc3 and Vc3 of the cells 13 and 14 are measured, and the measured cell voltages Vc3 and Vc4 are within an allowable range (Vt3 ± dVc3, Vt4 ± dVc4) centered on the reference voltages Vt3 and Vt4. Judging.

  When the cell voltage Vc3 or Vc4 is within the allowable range (Vt3 ± dVc3 or Vt4 ± dVc4), the measurement results of the cell voltages Vc3 and Vc4 by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 are one. Therefore, assuming that the voltage monitoring circuits 20 and 30 are operating normally, the abnormality determination process is temporarily terminated, and then the processes after S510 are executed again.

  If it is determined that the cell voltage Vc3 or Vc4 is not within the allowable range (Vt3 ± dVc3 or Vt4 ± dVc4), it is determined that either the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal. Then, the process of S600 is executed, and the abnormality determination process ends.

On the other hand, if it is determined that the output has changed to the high level this time, not the comparators CMP3 and CMP4, the process proceeds to S610.
In S610, the output voltage Vo2 from the second voltage monitoring circuit 30 is within an allowable range (Vt5 × 5 ± dV5) centered on a voltage value (Vt5 × 5) obtained by multiplying the reference voltage Vt5 of the comparator CMP5 by five. By determining whether or not there is, it is determined whether or not it is the comparator CMP5 that the output has changed to the high level this time.

  If it is determined that the output has changed to the high level at this time is the comparator CMP5, the process proceeds to S620, and the cell voltage Vc5 of the cell 15 corresponding to the comparator CMP5 is set via the first voltage monitoring circuit 20. taking measurement.

In subsequent S630, it is determined whether or not the measured cell voltage Vc5 is within an allowable range (Vt5 ± dVc5) around the reference voltage Vt5.
When the cell voltage Vc5 is within the allowable range (Vt5 ± dVc5), the measurement results of the cell voltage Vc5 by the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 match, and each voltage monitoring circuit Assuming that 20 and 30 are operating normally, the abnormality determination process is temporarily terminated, and then the processes after S510 are executed again.

  If it is determined that the cell voltage Vc5 is not within the allowable range (Vt5 ± dVc5), it is determined that either the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal, and the process of S600 is performed. Is executed to end the abnormality determination process.

  If it is determined in S610 that the output voltage Vo2 from the second voltage monitoring circuit 30 is not within the allowable range (Vt5 × 5 ± dV5), the output voltage Vo2 from the second voltage monitoring circuit 30 is determined. Is not within the above-described allowable ranges and is abnormal, the process of S600 is executed, and the abnormality determination process ends.

  As described above, even if the second voltage monitoring circuit 30 and the signal path from the second voltage monitoring circuit 30 to the battery control circuit 40 are configured as shown in FIG. If the abnormality determination process shown is executed, the same effect as in the first embodiment can be obtained.

  According to this embodiment, the signal path from the second voltage monitoring circuit 30 to the battery control circuit 40 is divided into two systems, and the battery control circuit 40 has two analog input ports Pa and digital input ports Pb. An input port may be provided. For this reason, according to this embodiment, the number of input ports of the battery control circuit 40 can be reduced, and cost reduction can be achieved.

  As mentioned above, although two embodiment of this invention was described, this invention is not limited to the said 1st Embodiment and 2nd Embodiment, In the range which does not deviate from the summary of this invention, various aspects. Can be taken.

  For example, in each of the above embodiments, the second voltage monitoring circuit 30 is provided with comparison circuits (comparators CMP1 to CMP5) for comparing the cell voltage and the reference voltage, respectively, and the output changes when the output of the comparison circuit changes. The abnormality of the voltage monitoring circuits 20 and 30 is judged by comparing the reference voltage of the comparison circuit and the cell voltage measured by the first voltage monitoring circuit 20.

  However, if any of the comparison circuits constituting the second voltage monitoring circuit 30 fails and the output of the comparison circuit does not change, the battery control circuit 40 may make an abnormality determination in response to the output change. become unable.

  Therefore, in order to prevent such a problem, in each of the above embodiments, the battery control circuit 40 may perform the abnormality determination process according to the procedure shown in FIGS.

  Note that the abnormality determination process shown in FIGS. 10 and 11 may be executed in place of the abnormality determination process shown in FIG. However, only the abnormality determination process shown in FIGS. 10 and 11 cannot make a normal abnormality determination when the first voltage monitoring circuit 20 fails.

  Therefore, in the first embodiment, both of the abnormality determination process shown in FIG. 7 and the abnormality determination process shown in FIG. 10 are executed. In the second embodiment, the abnormality determination process shown in FIG. It is preferable to execute both the abnormality determination process shown.

Hereinafter, the abnormality determination process illustrated in FIGS. 10 and 11 will be described.
The abnormality determination process shown in FIG. 10 is an abnormality determination process suitable for execution by the battery control circuit 40 of the first embodiment.

When this abnormality determination process is started, first, the cell voltage Vc1 of the cell 11 is measured via the first voltage monitoring circuit 20 in S710.
Next, in S712, the cell voltage Vc1 measured in S710 is higher than the determination voltage (Vt0−dV1) obtained by subtracting the allowable fluctuation range dV1 from the reference voltage Vt0 of each of the comparators CMP1 to CMP5 in the second voltage monitoring circuit 20. Determine whether or not.

  When the cell voltage Vc1 is higher than the determination voltage (Vt0-dV1), the process proceeds to S716, and when the cell voltage Vc1 is equal to or lower than the determination voltage (Vt0-dV1), the process proceeds to S714.

In S714, it is determined whether or not the determination result of the cell voltage Vc1 in the second voltage monitoring circuit 30 (that is, the output from the comparator CMP1) is at a low level.
If the output from the comparator CMP1 is not low level, it does not coincide with the determination result of the cell voltage Vc1 in S712, so it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, The process proceeds to S760.

Then, in S760, the same error output / storage process as in S440 and S600 is performed, and the abnormality determination process is terminated.
On the other hand, if it is determined in S714 that the output from the comparator CMP1 is at a low level, the process proceeds to S716.

  In S716, it is determined whether or not the cell voltage Vc1 measured in S710 is lower than a determination voltage (Vt0 + dV1) obtained by adding the allowable variation width dV1 to the reference voltage Vt0 of the comparator CMP1.

  If the cell voltage Vc1 is lower than the determination voltage (Vt0 + dV1), the process proceeds to S720. If the cell voltage Vc1 is equal to or higher than the determination voltage (Vt0 + dV1), the process proceeds to S718.

In S718, it is determined whether or not the output from the comparator CMP1 is at a high level. If the output from the comparator CMP1 is at a high level, the process proceeds to S720.
On the other hand, if it is determined in S718 that the output from the comparator CMP1 is not at the high level, it does not coincide with the determination result of the cell voltage Vc1 in S716, so that the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal. If it is determined that there is, there is a transition to S760.

  Next, in S720, the cell voltage Vc2 of the cell 12 is measured via the first voltage monitoring circuit 20, and in the subsequent S722, the cell voltage Vc2 is determined by subtracting the allowable fluctuation range dV1 from the reference voltage Vt0 ( It is determined whether it is higher than Vt0-dV1).

  When the cell voltage Vc2 is higher than the determination voltage (Vt0-dV1), the process proceeds to S726. When the cell voltage Vc2 is equal to or lower than the determination voltage (Vt0-dV1), the process proceeds to S724.

In S724, it is determined whether or not the determination result of the cell voltage Vc2 in the second voltage monitoring circuit 30 (that is, the output from the comparator CMP2) is at a low level.
If the output from the comparator CMP2 is not low level, it does not coincide with the determination result of the cell voltage Vc2 in S722, so it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, The process proceeds to S760.

On the other hand, if it is determined in S724 that the output from the comparator CMP2 is at a low level, the process proceeds to S726.
In S726, it is determined whether or not the cell voltage Vc2 measured in S720 is lower than a determination voltage (Vt0 + dV1) obtained by adding the allowable variation width dV1 to the reference voltage Vt0.

  If it is determined in S726 that the cell voltage Vc2 is equal to or higher than the determination voltage (Vt0 + dV1), the process proceeds to S728, and it is determined whether or not the output from the comparator CMP2 is at a high level.

  If the output from the comparator CMP2 is not high level, it does not coincide with the determination result of the cell voltage Vc2 in S726, so it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, and S760 Migrate to

  On the other hand, if it is determined in S726 that the cell voltage Vc2 is lower than the determination voltage (Vt0 + dV1), or if it is determined in S728 that the output from the comparator CMP2 is high, S710 to S718, The cell voltages Vc3, Vc4, and Vc5 are measured in the same procedure as S720 to S728, and abnormality determination of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is performed.

  That is, for example, when the cell voltage Vc5 is measured (S750), “when the cell voltage Vc5 is equal to or lower than the determination voltage (Vt0-dv1) (S752-NO), and the output from the comparator CMP5 is high level ( S754-NO) ”and“ when the cell voltage Vc5 is equal to or higher than the determination voltage (Vt0 + dv1) (S756-NO) and the output from the comparator CMP5 is at a low level (S758-NO) ”. It is determined that there is an abnormality in the circuit 20 or the second voltage monitoring circuit 30, and the error output / storage process of S760 is executed.

  As described above, in the abnormality determination process illustrated in FIG. 10, the cell voltages Vc1 to Vc5 of the cells 11 to 15 measured by the first voltage monitoring circuit 20 are equal to or lower than the determination voltage (Vt0−dv1), or When the voltage is equal to or higher than the determination voltage (Vt0 + dv1), whether the outputs from the comparators CMP1 to CMP5 of the second voltage monitoring circuit 30 match the determination result (that is, whether the output is low level or high level). When these do not match, an abnormality of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is detected.

  Therefore, according to the abnormality determination process illustrated in FIG. 10, no signal is output from at least one of the comparators CMP <b> 1 to CMP <b> 5 configuring the second voltage monitoring circuit 30, and the abnormality determination process illustrated in FIG. Even when the operation cannot be performed normally, the abnormality determination can be performed based on the measurement results of the cell voltages Vc1 to Vc5 by the first voltage monitoring circuit 20.

Next, the abnormality determination process shown in FIG. 11 is an abnormality determination process suitable for implementation in the battery control circuit 40 of the second embodiment.
When this abnormality determination process is started, first, the cell voltage Vc1 of the cell 11 is measured via the first voltage monitoring circuit 20 in S810.

  Next, in S812, whether or not the cell voltage Vc1 measured in S810 is lower than a determination voltage (Vt1−dVc1) obtained by subtracting the allowable fluctuation range dVc1 from the reference voltage Vt1 of the comparator CMP1 in the second voltage monitoring circuit 20. Judging.

  If the cell voltage Vc1 is lower than the determination voltage (Vt1-dVc1), the process proceeds to S814, where the output voltage Vo2 of the second voltage monitoring circuit 30 is measured via the cell voltage output circuit 34, and the process proceeds to S816. Transition.

In S816, it is determined whether or not the output voltage Vo2 of the second voltage monitoring circuit 30 is at a low level (that is, approximately ground voltage).
If the output voltage Vo2 of the second voltage monitoring circuit 30 is not low level, the output of any of the comparators CMP1 to CMP5 in the second voltage monitoring circuit 30 (see FIG. 8) is high level. Since it does not coincide with the determination result of the cell voltage Vc1, it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, and the process proceeds to S870.

Then, in S870, the same error output / storage processing as in S440, S600, and S760 is performed, and the abnormality determination processing is terminated.
On the other hand, when it is determined in S812 that the cell voltage Vc1 is equal to or higher than the determination voltage (Vt1-dVc1), or in S816, it is determined that the output voltage Vo2 of the second voltage monitoring circuit 30 is at a low level. In the case where it is determined, the process proceeds to S820, and the cell voltage Vc2 of the cell 12 is measured via the first voltage monitoring circuit 20.

  In subsequent S822, the cell voltage Vc1 measured in S810 is higher than the determination voltage (Vt1 + dVc1) obtained by adding the allowable variation width dVc1 to the reference voltage Vt1 of the comparator CMP1, and the cell voltage Vc2 measured in S820 is the same. Then, it is determined whether or not it is lower than a determination voltage (Vt2-dVc2) obtained by subtracting the allowable fluctuation range dVc2 from the reference voltage Vt2 of the comparator CMP2.

  If it is determined in S822 that the cell voltage Vc1 is higher than the determination voltage (Vt1 + dVc1) and the cell voltage Vc2 is lower than the determination voltage (Vt2-dVc2), the process proceeds to S824.

  In S824, the output voltage Vo2 of the second voltage monitoring circuit 30 is measured via the cell voltage output circuit 34. In the subsequent S826, the absolute value (| Vc1−) of the difference between the measured output voltage Vo2 and the cell voltage Vc1. It is determined whether or not Vo2 |) is smaller than the abnormality determination value dVo1.

  Here, the abnormality determination value dVo1 is based on the absolute value (| Vc1-Vo2 |) of the difference between the output voltage Vo2 of the second voltage monitoring circuit 30 and the cell voltage Vc1, and the output of the comparator CMP1 in the second voltage monitoring circuit 30. Is for determining that the outputs of the comparators CMP2 to CMP5 on the higher voltage side than the comparator CMP1 are at the low level.

  In S826, when the absolute value (| Vc1-Vo2 |) of the difference between the output voltage Vo2 and the cell voltage Vc1 is equal to or greater than the abnormality determination value dVo1, the determination result in S822 and the second voltage monitoring circuit 30 The determination result does not match, and it is determined that the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is abnormal, and the process proceeds to S870.

  On the other hand, when it is determined in S822 that the cell voltage Vc1 is equal to or lower than the determination voltage (Vt1 + dVc1), or the cell voltage Vc2 is equal to or higher than the determination voltage (Vt2-dVc2), or in S826, the output voltage When it is determined that the absolute value (| Vc1−Vo2 |) of the difference between Vo2 and the cell voltage Vc1 is smaller than the abnormality determination value dVo1, the cell voltages Vc3, Vc4, and Vc5 are performed in the same procedure as S820 to S826. And the abnormality determination of the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30 is performed.

  That is, for example, when the cell voltage Vc5 is measured (S850), “when the cell voltage Vc4 is higher than the determination voltage (Vt4 + dVc4) and the cell voltage Vc5 is lower than the determination voltage (Vt5−dVc5)” ( In S852-YES), the output voltage Vo2 of the second voltage monitoring circuit 30 is measured (S854).

  Then, it is determined whether the absolute value (| Vc4-Vo2 |) of the difference between the measured output voltage Vo2 and the cell voltage Vc4 is smaller than the abnormality determination value dVo4 (S856), and the output voltage Vo2 and the cell voltage are determined. If the absolute value (| Vc4-Vo2 |) of the difference from Vc4 is equal to or greater than the abnormality determination value dVo4, it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, and the process proceeds to S870. To do.

  The abnormality determination value dVo4 is based on the absolute value (| Vc4-Vo2 |) of the difference between the output voltage Vo2 of the second voltage monitoring circuit 30 and the cell voltage Vc4, and the output of the comparator CMP4 in the second voltage monitoring circuit 30 is This is for determining that the output of the comparator CMP5 on the higher voltage side than the high level comparator CMP4 is at the low level.

  If no abnormality is determined in the series of processes, that is, in S852, the cell voltage Vc4 is equal to or lower than the determination voltage (Vt4 + dVc4), or the cell voltage Vc5 is equal to or higher than the determination voltage (Vt5-dVc5). If it is determined that the absolute value (| Vc4-Vo2 |) of the difference between the output voltage Vo2 and the cell voltage Vc4 is smaller than the abnormality determination value dVo4 in S856, The process proceeds to S860.

  In S860, it is determined whether or not the cell voltage Vc5 is higher than a determination voltage (Vt5 + dVc5) obtained by adding the allowable variation width dVc5 to the reference voltage Vt5 of the comparator CMP5. The cell voltage Vc5 is equal to or lower than the determination voltage (Vt5 + dVc5). If there is, the abnormality determination process ends.

  On the other hand, when it is determined in S860 that the cell voltage Vc5 is higher than the determination voltage (Vt5 + dVc5), the process proceeds to S862, and the output voltage Vo2 of the second voltage monitoring circuit 30 is measured.

  In S864, it is determined whether the absolute value (| Vc5-Vo2 |) of the difference between the output voltage Vo2 measured in S862 and the cell voltage Vc5 is smaller than the abnormality determination value dVo5, and the output voltage Vo2 and the cell voltage are determined. If the absolute value (| Vc5-Vo2 |) of the difference from the voltage Vc5 is equal to or greater than the abnormality determination value dVo5, it is determined that there is an abnormality in the first voltage monitoring circuit 20 or the second voltage monitoring circuit 30, and the process proceeds to S870. To do.

  In S864, if the absolute value (| Vc5-Vo2 |) of the difference between the output voltage Vo2 and the cell voltage Vc5 is smaller than the abnormality determination value dVo5, the first voltage monitoring circuit 20 and the second voltage monitoring circuit 30 It judges that it is normal, and ends the abnormality determination process.

  As described above, in the abnormality determination process illustrated in FIG. 11, each comparator CMP <b> 1 is supplied from the second voltage monitoring circuit 30 based on the cell voltages Vc <b> 1 to Vc <b> 5 of the cells 11 to 15 measured by the first voltage monitoring circuit 20. The first voltage monitoring circuit 20 or the second voltage monitoring circuit is determined by determining whether or not the output voltage Vo2 output in accordance with the determination result of CMP5 is within the voltage range corresponding to the cell voltages Vc1 to Vc5. 30 abnormalities are detected.

  Therefore, according to the abnormality determination process shown in FIG. 11, no signal is output from at least one of the comparators CMP1 to CMP5 constituting the second voltage monitoring circuit 30, and the abnormality determination process shown in FIG. Even when the operation cannot be performed normally, the abnormality determination can be performed based on the measurement results of the cell voltages Vc1 to Vc5 by the first voltage monitoring circuit 20.

  Next, in the second embodiment, the voltage change detection circuit 32 and the cell voltage output circuit 34 are provided between the second voltage monitoring circuit 30 and the battery control circuit 40, and a trigger signal is input from the voltage change detection circuit 32. Then, the battery control circuit 40 specifies a comparison circuit (and thus a cell) whose output has changed in the second voltage detection circuit 30 based on the voltage from the cell voltage output circuit 34.

However, in the second embodiment, the reference voltages of the comparison circuits (comparators CMP1 to CMP5) constituting the second voltage monitoring circuit 30 are set to different values.
Therefore, for example, when the battery 10 is charged from the discharged state, the output sequentially changes from the comparison circuit (comparator CMP1) having a low reference voltage to the comparison circuit (comparator CMP5) having a high reference voltage.

For this reason, when the battery 10 is charged from the discharged state, the comparison circuit whose output has changed can be specified by the number of times the trigger signal is input.
Therefore, in the second embodiment, it is not always necessary to provide the cell voltage output circuit 34 in order to specify the comparison circuit whose output has changed. In the abnormality determination process shown in FIG. The comparison circuit whose output has changed may be specified.

  Next, in the configuration of the first embodiment (see FIG. 2), the cell voltage measurement result by the first voltage monitoring circuit 20 is output only to the battery control circuit 40 in the battery pack 2. In addition to the battery control circuit 40, the battery pack 2 may be output to a charger 50 or a rechargeable electric device to which the battery pack 2 is connected.

  And if it does in this way, when controlling the charge to the battery 10 or the discharge from the battery 10 to the electric device in the charger 50 or the rechargeable electric device, the battery voltage (or cell voltage) is directly monitored. It becomes possible to improve safety when using the battery.

  Next, in each of the above embodiments, the first voltage monitoring circuit 20 is configured by a voltage detection circuit capable of detecting the cell voltages Vc1 to Vc5 of the cells 11 to 15 constituting the battery 10, and the second voltage monitoring circuit The circuit 30 has been described as configured by the comparators CMP1 to CMP5 that compare the cell voltages Vc1 to Vc5 with the reference voltage.

  However, the present invention is a voltage monitor comprising a voltage detection circuit that can selectively detect the cell voltages Vc1 to Vc5 as in the first voltage monitoring circuit 20, or a voltage detection circuit that can simultaneously detect the cell voltages Vc1 to Vc5. Even a battery pack having two or more circuits can be applied.

  That is, in this case, the battery control circuit 40 periodically measures the cell voltage via each voltage monitoring circuit, and determines whether or not the measured cell voltages match, thereby determining the voltage monitoring circuit. What is necessary is just to judge abnormality.

  The present invention can also be applied to a battery pack including two or more voltage monitoring circuits configured by the comparators CMP1 to CMP5, such as the second voltage monitoring circuit 30.

In this case, it can be detected that the cell voltages Vc1 to Vc5 cross the reference voltage, but the voltage values of the cell voltages Vc1 to Vc5 cannot be detected.
Therefore, in this case, the timing at which the output from the other voltage monitoring circuit changes is estimated from the timing at which the output from one voltage monitoring circuit changes and the integrated value of the charge / discharge current, and the estimated timing. When the deviation from the actual change timing becomes equal to or greater than a predetermined threshold, it may be determined that one of the voltage monitoring circuits is abnormal.

  In each of the above embodiments, the voltage monitoring circuits 20 and 30 measure the cell voltages Vc1 to Vc5 for each of the cells 11 to 15 constituting the battery 10 or compare them with a reference voltage. , 30 has been described as being performed for each cell 11-15.

  However, even if each voltage monitoring circuit 20, 30 measures the voltage across the battery 10 (battery voltage) or compares the battery voltage with a reference voltage, It can be applied in the same way as the form.

  DESCRIPTION OF SYMBOLS 2 ... Battery pack, 3 ... Mounting part, 4 ... Battery side terminal, 6 ... Positive electrode terminal, 7 ... Negative electrode terminal, 8 ... Input / output terminal, 10 ... Battery, 11-15 ... Cell, 20 ... 1st voltage monitoring circuit, R10 to R15... Resistor, Ti10 to Ti15... Input terminal, Sa1 to Sa5... Positive switch, Sb1 to Sb5... Negative electrode switch, Sc1 to Sc5 ... Discharge switch, 22 ... Switch controller, 24 ... Amplifier circuit, To1 ... Output terminal, Tc1 ... input terminal, 30 ... second voltage monitoring circuit, R20-R25 ... resistor, Ti20-Ti25 ... input terminal, CMP1-CMP5 ... comparator, To2, To21-To25 ... output terminal, So1-So5 ... output switch, Do1-Do4 ... Diode, 32 ... Voltage change detection circuit, 34 ... Cell voltage output circuit, 40 ... Battery control circuit, 42 ... Degree detecting circuit, 44 ... current detection circuit, 46 ... protection circuit.

Claims (8)

Battery,
A first voltage monitoring circuit and a second voltage monitoring circuit that respectively monitor the voltage of the battery;
Control means for controlling charging / discharging of the battery based on monitoring results of the first voltage monitoring circuit and the second voltage monitoring circuit;
The control means compares the monitoring results of the first voltage monitoring circuit and the second voltage monitoring circuit, and when there is a difference between the monitoring results, the first voltage monitoring circuit or the second voltage monitoring circuit A battery pack characterized in that the battery pack is determined to be abnormal.   In the control means, at least one of the voltages of the battery monitored by the first voltage monitoring circuit and the second voltage monitoring circuit is within an upper limit / lower limit voltage range under normal charge / discharge conditions of the battery. The battery pack according to claim 1, wherein the monitoring results of the first voltage monitoring circuit and the second voltage monitoring circuit are compared.   3. The battery pack according to claim 1, wherein the second voltage monitoring circuit outputs a comparison result between the voltage of the battery and a reference voltage to the control unit as the monitoring result. 4. The first voltage monitoring circuit detects the voltage of the battery, and outputs the detection result to the control unit as the monitoring result;
The control means, when the output of the second voltage monitoring circuit changes, compares the reference voltage of the second voltage monitoring circuit with the monitoring result of the first voltage monitoring circuit. Item 4. The battery pack according to item 3.   The reference voltage is based on an average value of a full charge stop voltage at which the control unit stops charging the battery and a discharge stop voltage at which the control unit stops discharging from the battery. The battery pack according to claim 3 or 4, wherein the same voltage value is set. The first voltage monitoring circuit and the second voltage monitoring circuit are configured to monitor a cell voltage for each of a plurality of cells constituting the battery,
The said control means compares the monitoring result of the said cell voltage by the said 1st voltage monitoring circuit and the said 2nd voltage monitoring circuit for every said some cell, The any one of Claims 1-5 characterized by the above-mentioned. The battery pack according to item 1.   The second voltage monitoring circuit includes a plurality of comparison circuits that compare a cell voltage of each cell with a reference voltage set to a different value for each cell, and summarizes the comparison results of each comparison circuit into one output. The battery pack according to claim 6, wherein the battery pack is output to the control means.   Each cell voltage is input to the first voltage monitoring circuit and the second voltage monitoring circuit from the positive and negative electrodes of a plurality of cells constituting the battery via impedance elements on the voltage monitoring circuit side, respectively. The battery pack according to claim 6 or 7, wherein the battery pack is provided.

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