JP2015050291A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable free setting of a work function of a gate electrode to adjust a threshold voltage Vt of a transistor.SOLUTION: A semiconductor device comprises a gate electrode which includes: a gate electrode groove 14 provided on a surface layer of a semiconductor substrate 1; a gate insulation film 5 provided on the gate electrode groove; a laminated barrier film 4 which is provided on the gate insulation film and in which barrier films and work function adjustment films are alternately laminated one by one; and a gate electrode layer 6 provided on the laminated barrier film.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Along with miniaturization of semiconductor devices, wiring resistance has become a problem due to the reduction in the width and thinning of the wiring width of the gate electrode in the transistor constituting the semiconductor device. In order to cope with such a problem, a gate electrode provided with a barrier film is used, and metal is used for the gate electrode. For example, titanium nitride TiN is used for the barrier film, and tungsten W is used for the gate electrode. Such a gate electrode is called a metal gate electrode.

  However, in the metal gate electrode, the threshold voltage Vt of the transistor (hereinafter referred to as the threshold Vt) is determined by the work function inherent to the metal, and there is a limit to the range that can be adjusted even if the threshold Vt is adjusted by channel doping.

  In Patent Document 1, a single layer film made of any one of Ta, TaN, TaSiN, TaAl, TaAlN, TaSi, TaAlSiN, TaC and TaCN or a laminated film made of at least two are deposited on the metal gate electrode, It is disclosed that the work function of a TaN film or the like is changed by changing the amount of nitrogen.

  Patent Document 2 discloses that a high dielectric film made of a high dielectric material is formed on a semiconductor region, and nitrogen is introduced into a predetermined region of the high dielectric film as a threshold Vt adjusting impurity. Yes.

JP2007-288096, [0007], [0018] JP 2010-1557587 A, [0012], [0013]

  However, the methods disclosed in Patent Documents 1 and 2 have limitations in adjusting the threshold value Vt.

  The inventor has found that the work function of the gate electrode can be changed and the threshold value Vt can be shifted by stacking a plurality of TiN barrier films and SiN films and changing Si atm%.

  According to the first aspect of the present invention, the laminated barrier film provided on the surface of the semiconductor substrate and the laminated barrier film provided on the gate insulating film and alternately laminated with the barrier film and the work function adjusting film. And a conductive film provided on the laminated barrier film, and a semiconductor device provided with a gate electrode.

  According to the second aspect of the present invention, the gate groove provided on the surface layer of the semiconductor substrate, the gate insulating film provided on the gate groove, the barrier film and the work function adjusting film provided on the gate insulating film And a conductive film layer provided on the stacked barrier film is provided in a gate electrode.

  According to the third aspect of the present invention, the step of forming the gate insulating film on the surface of the semiconductor substrate and the step of forming the barrier film and the step of forming the work function adjusting film on the gate insulating film are alternately performed. And a step of forming a laminated barrier film, and a step of forming a conductive film layer on the laminated barrier film.

  According to the present invention, the work function of the gate electrode can be freely set, and the threshold voltage Vt of the transistor can be adjusted.

FIG. 2 is a plan view (FIG. A) of a cell region and a plan view (FIG. B) of a peripheral circuit region in a semiconductor device (DRAM memory cell) according to an embodiment of the present invention. It is the figure which showed the A-A 'cross section (right side of a figure) of FIG.1 (b), and the B-B' cross section of FIG.1 (a). It is sectional drawing for demonstrating the process of forming the gate electrode groove | channel for forming a gate electrode in the cell area | region in a semiconductor substrate. FIG. 4 is a cross-sectional view for explaining a step of forming a gate insulating film by oxidizing the inside of the gate electrode groove following FIG. 3. FIG. 5 is a cross-sectional view for explaining a step of forming a laminated barrier film and a gate electrode functioning as a word line in the gate electrode groove following FIG. 4. It is sectional drawing for demonstrating the film-forming method of the lamination | stacking barrier film | membrane in FIG. It is the graph which showed Si concentration dependence in the TiSiN film | membrane of the threshold voltage Vt shift amount of a transistor. FIG. 6 is a cross-sectional view for explaining a step of forming a gate electrode (word line) in a gate electrode groove by etching back the metal gate electrode in FIG. 5. It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 10 is a cross-sectional view for explaining the interlayer insulating film formation step subsequent to FIG. 9. FIG. 11 is a cross-sectional view for describing a processing step on the peripheral circuit region side following FIG. 10. FIG. 12 is a cross-sectional view for describing a processing step on the peripheral circuit region side following FIG. 11. FIG. 13 is a cross-sectional view for describing a processing step on the peripheral circuit region side following FIG. 12. FIG. 14 is a cross-sectional view for describing a processing step on the peripheral circuit region side following FIG. 13. FIG. 15 is a cross-sectional view for describing a processing step on the peripheral circuit region side following FIG. 14. FIG. 16 is a cross-sectional view for explaining the bit line forming step on the cell region side following FIG. 15. FIG. 17 is a cross-sectional view for explaining a bit line formation step on the cell region side following FIG. 16. FIG. 18 is a cross-sectional view for explaining the bit line forming step on the cell region side following FIG. 17. FIG. 19 is a cross-sectional view for illustrating the manufacturing process following FIG. 18. FIG. 20 is a cross-sectional view for explaining the manufacturing process following FIG. 19.

  An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS.

  A schematic configuration of an embodiment of a semiconductor device according to the present invention is as follows.

  A laminated barrier in which a gate electrode groove provided on a surface layer of a semiconductor substrate, a gate insulating film provided on the gate electrode groove, and a barrier film and a work function adjusting film provided alternately on the gate insulating film are laminated. A semiconductor device comprising a film and a conductive film layer provided on the stacked barrier film as a gate electrode.

  Among the above components, the semiconductor device according to the present embodiment is characterized by the stacked barrier film. In the following description, the laminated barrier film may be referred to as a laminated film, and the conductive layer film may be referred to as a word line.

  FIG. 1 is a cell region plan view (FIG. A) and a peripheral circuit region plan view (FIG. B) of a semiconductor device according to an embodiment of the present invention. It is a top view at the time of formation. FIG. 1A shows an X direction and a Y direction perpendicular to each other, and an X ′ direction forming an angle in the X direction within a plane including the X direction.

  FIG. 2 is a diagram showing an A-A ′ section (right side of the figure) in FIG. 1B and a B-B ′ section (left side in the figure) in FIG.

  First, the semiconductor device 100 will be described with reference to FIG. The semiconductor device 100 is a dynamic random access memory (DRAM) cell.

  The cell region of FIG. 1A will be described. On the semiconductor substrate (silicon substrate) 1, the element isolation region 12 continuously extending in the X ′ direction and the active region extending continuously in the X ′ direction. A plurality of regions 13 are arranged alternately at equal intervals and at equal pitches in the Y direction. The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. Embedded word lines (hereinafter, word lines) WL10a, WL10b, WL10c, and WL10d extending continuously in the Y direction are arranged across the plurality of element isolation regions 12 and the plurality of active regions 13.

  Further, a buried dummy word line (hereinafter referred to as a dummy word line) DWL10 is arranged so as to be sandwiched between the word line WL10b and the word line WL10c. The dummy word line DWL10 separates cell transistors adjacent to each other in the extending direction of each active region 13 by keeping the parasitic transistor in an off state, and the continuous band-like active region 13 is divided into a plurality of independent active regions. It has the function to divide into. Specifically, the active region 13 located on the left side of the dummy word line DWL10 is divided into a first active region 13a, and the active region 13 located on the right side of the dummy word line DWL10 is divided into a second active region 13b.

  The first active region 13a includes a second capacitor contact region 37b disposed adjacent to the left side of the dummy word line DWL10, a word line WL10b disposed adjacent to the second capacitor contact region 37b, and the word line WL10b. An adjacent bit line (BL) contact region 32a, a word line WL10a disposed adjacent to the bit line contact region 32a, and a first capacitor contact region 37a disposed adjacent to the word line WL10a , Is composed of. The first cell contact region 37a, the word line WL10a, and the bit line contact region 32a constitute a first cell transistor Tr1. The bit line contact region 32a, the word line WL10b, and the second capacitor contact region 37b constitute a second cell transistor Tr2.

  Similarly, third and fourth cell transistors Tr3 and Tr4 are configured on the second active region 13b side.

  The peripheral circuit region in FIG. 1B includes an N channel transistor region for an N channel peripheral transistor (hereinafter, Nch-Tr region) and a P channel transistor region for a P channel peripheral transistor (hereinafter, Pch-Tr region). Including. In each channel transistor region, a peripheral transistor gate and a peripheral contact are formed in the active region, and wiring is connected to the peripheral contact.

  Next, the cell region side shown on the left side of FIG. 2 will be described with reference to FIG. Referring to the left side of FIG. 2, the semiconductor substrate 1 is provided with a gate electrode groove 14 for a word line that also serves as a gate electrode of a cell transistor. The word line WL10a and the word line WL10b made of tungsten are connected to each other through a gate insulating film (oxide film) 5 and a laminated barrier film (laminated film) 4 formed of a thermal oxide film covering the inner surface of each gate electrode trench 14, respectively. It is provided in the gate electrode trench 14. A cap insulating film 27 is provided so as to cover each word line and bury each gate electrode trench 14. The gate insulating film 5 can include, for example, a silicon oxide film, and may further include a high dielectric constant film on the silicon oxide film. The laminated barrier film 4 is formed by laminating a barrier metal TiN film (a barrier film described in a schematic configuration) and a SiN film (a work function adjusting film described in a schematic configuration). explain.

  The semiconductor pillar located on the left side of the word line WL10a becomes the first capacitor contact region 37a (FIG. 1a), and the impurity diffusion layer 28a serving as one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located between the word line WL10a and the word line WL10b becomes a bit line (BL) contact region 32a, and an impurity diffusion layer 29a serving as the other one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located on the right side of the word line WL10b serves as the second capacitor contact region 37b, and an impurity diffusion layer 29b serving as one of source / drain is provided on the upper surface thereof.

  The impurity diffusion layer 28a, the gate insulating film 5, the first word line WL10a, and the impurity diffusion layer 29a constitute a first transistor Tr1 (FIG. 1a). The impurity diffusion layer 29a, the gate insulating film 5, the second word line WL10b, and the impurity diffusion layer 29b constitute the second transistor Tr2 (FIG. 1a). A cap insulating film 27 is provided so as to cover the upper surface of each word line.

  An interlayer insulating film 30 made of a silicon nitride film is provided on the upper surface of the element isolation region 12 and the upper surface of the semiconductor substrate 1 on which the impurity diffusion layers 28a and 29b are formed.

  On the cap insulating film 27, a bit line (BL) 26 made of tungsten connected to the impurity diffusion layer 29a through the poly Si film 31-1 and the WSi film 31-2 in the bit line contact region 32a is provided. A hard mask silicon nitride film (cover insulating film) 33 is provided on the upper surface of the bit line 26. A liner silicon nitride film (liner insulating film) 34 is provided on the entire surface so as to cover the side wall of the bit line 26. On the liner insulating film 34, an interlayer SOD (Spin On Dielectric) film 35 is provided to fill a recessed space formed between adjacent bit lines.

  Two capacitor contact holes are provided through the interlayer SOD film 35, the liner silicon nitride film 34, and the interlayer insulating film 30. The first and second capacitor contact plugs 38a and 38b are connected to the first and second capacitor contact regions 37a and 37b, respectively, through these capacitor contact holes. First and second capacitor contact pads 42a and 42b are connected to the upper portions of the first and second capacitor contact plugs 38a and 38b, respectively. A capacitor lower electrode 44 is provided on the first and second capacitor contact pads 42a and 42b. A capacitor insulating film 45 covering the surface of the capacitor lower electrode 44 is provided, and a capacitor upper polysilicon electrode 46 and a capacitor upper tungsten electrode 47 are provided on the capacitor insulating film 45. Reference numeral 48 denotes a capacitor support film for supporting the capacitor lower electrode 44.

  Next, the peripheral circuit region side shown on the right side of FIG. 2 will be described. Referring to FIG. 1B and the right side of FIG. 2, N-type and P-type planar transistors are formed in the peripheral circuit region. On the semiconductor substrate (silicon substrate) 1, a first active region and a second active region surrounded by the element isolation region 12 are disposed. The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. An N-type field effect transistor 24 is configured in the first active region, and a P-type field effect transistor 25 is configured in the second active region. A gate electrode 11 extending continuously in the Y direction is disposed across the first active region, the second active region, and the element isolation region 12.

  The N-type transistor 24 includes a gate electrode 11 in the first active region and an N-type source / drain region 15 disposed adjacent to both sides of the gate electrode 11. The P-type transistor 25 includes a gate electrode 11 in the second active region and a P-type source / drain region 16 disposed adjacent to both sides of the gate electrode 11.

  In the N-type transistor 24, a P well region PW is provided in the semiconductor substrate 1. A gate electrode 11 is provided through a gate insulating film 5N for N-type transistor and a laminated film 3N covering the upper surface of the semiconductor substrate 1. The semiconductor substrate 1 has a structure including a source / drain region 15 and an LDD (Lightly Doped Drain) implantation region 22 at a position that is self-aligned with the gate electrode 11. A liner insulating film 18 is provided on the semiconductor substrate 1 with silicon nitride or the like so as to cover the gate electrode 11, the sidewalls 17, and the like. An interlayer SOD film (interlayer insulating film) 35 is provided on the liner insulating film 18.

  A contact hole is provided through the interlayer SOD film 35 and the liner insulating film 18. A contact plug 20 is connected to the source / drain region 15 by this contact hole. A tungsten wiring 21 is connected on the contact plug 20.

  On the other hand, in the P-type transistor 25, an N well region NW is provided in the semiconductor substrate 1. A gate electrode 11 is provided via a gate insulating film 5P for a P-type transistor that covers the upper surface of the semiconductor substrate 1. In the semiconductor substrate 1, the source / drain region 16 and the LDD implantation region 23 are provided at a position that is self-aligned with the gate electrode 11. A liner insulating film 18 is provided on the semiconductor substrate 1 with silicon nitride or the like so as to cover the gate electrode 11, the sidewalls 17, and the like. An interlayer SOD film (interlayer insulating film) 35 is provided on the liner insulating film 18.

  A contact hole is provided through the interlayer SOD film 35 and the liner insulating film 18, and the contact plug 20 is connected to the source / drain region 16 through the contact hole. A tungsten wiring 21 is connected to the contact plug 20.

  Next, the manufacturing process of the semiconductor device will be described in order with reference to FIGS.

  An outline of an embodiment of a method of manufacturing a semiconductor device according to the present invention is as follows.

  Forming a gate insulating film on a surface of a semiconductor substrate; forming a barrier film on the gate insulating film; and forming a laminated barrier film by alternately performing a process of forming a barrier film and a process of forming a work function adjusting film; And a step of forming a conductive film layer on the laminated barrier film, and a method for manufacturing a semiconductor device, wherein a gate electrode is formed.

  Among the above steps, the semiconductor device manufacturing method according to the present embodiment is characterized in that the laminated barrier film is formed. Therefore, steps other than the step of forming the laminated barrier film are not limited to the methods described below. Therefore, the steps other than the step of forming the laminated barrier film are simplified.

  FIG. 3 is a diagram for explaining a process of forming a gate electrode groove 14 for forming a gate electrode in a cell region in the semiconductor substrate 1. Before forming the gate electrode trench 14, a plurality of element isolation regions 12 are formed in the semiconductor substrate 1, and a P well region PW and an N well region NW are formed in regions surrounded by the element isolation regions in the peripheral circuit region. Is formed. A silicon oxide film (thermal oxide film) and a silicon nitride film are formed on the cell region excluding the element isolation region 12 and on the peripheral circuit region.

  Referring to FIG. 4, following FIG. 3, the gate electrode groove 14 is oxidized to form a gate insulating film (gate oxide film) 5 on the inner wall of the gate electrode groove 14.

  FIG. 5 is a diagram for explaining a process of forming the laminated barrier film 4 and the gate electrode functioning as a word line in the gate electrode trench 14 following FIG.

  The laminated barrier film 4 includes a barrier film and a work function adjusting film. The barrier metal for the barrier film is, for example, titanium nitride TiN, and the work function adjusting film is, for example, the silicon nitride film SiN, thereby forming the laminated barrier film TiSiN. For example, tungsten W is used as the gate electrode. In FIG. 5, a gate electrode made of metal is formed in the entire cell region and peripheral circuit region, and this gate electrode is referred to as a metal gate electrode for convenience in order to distinguish it from the original gate electrode in the gate electrode trench 14. .

  The laminated barrier film TiSiN is formed by using SFD (Sequential Flow Deposition) technology, which is a kind of CVD method, with one cycle of gas supply and purging and repeating several cycles. For example, when Si is formed at a concentration of 8 atm%, the film thickness in one cycle is TiN: 0.7 nm and SiN: 0.1 nm.

  The combination of the barrier film and the work function adjusting film is not limited to TiN and SiN, and Ti, TiN, Pt, WN, or the like can be used as the metal for the barrier film. As the work function adjusting film, SiN, AlO2, AlN, TiO2, CN, or the like can be used. In addition, a laminated barrier film in which these are combined can be used.

  With reference to FIG. 6, a method of forming the laminated barrier film TiSiN will be described.

  TiSiN uses SFD technology to stack titanium nitride TiN as a barrier film and a work function adjusting film made of SiN. An ALD (Atomic Layer Deposition) technique may be used instead of the SFD technique. The step of alternately stacking the barrier film and the work function adjusting film is 1 cycle, and in FIG. 6, the stacked barrier film TiSiN is formed by repeating 4 cycles.

  FIG. 7 is a graph showing the dependence of the threshold voltage Vt shift amount of the transistor on the Si concentration in the TiSiN film.

  By increasing the ratio of the TiN and SiN films from the TiN-only barrier film, the Si concentration in the TiSiN film can be increased.

  As is apparent from FIG. 7, the threshold voltage Vt shift amount increases as the Si concentration in the TiSiN film increases.

  FIG. 8 is a cross-sectional view showing a step of forming the gate electrode layer 6 (word line WL10) in the gate electrode trench 14 by etching back the metal gate electrode in FIG. The metal gate electrode in the peripheral circuit region is completely removed.

  In FIG. 9, after the liner silicon nitride film 7 and the SOD film 8 are formed so as to cover the gate electrode layer 6 in the gate electrode trench, the silicon nitride film formed in FIG. 3 is formed by CMP (Chemical Mechanical Polishing). Flatten until exposed.

  In FIG. 10, the liner silicon nitride film 7 and the SOD film 8 formed in FIG. 9 are removed by dry etching, and a part of the hard mask silicon nitride film is removed by wet etching, leaving the portion shown in FIG. Subsequently, an interlayer insulating film 30 is formed on the entire surface of the cell region and the peripheral circuit region.

  In FIG. 11, a photoresist process is performed on the peripheral circuit region and etching is performed to expose the diffusion layer in the peripheral circuit region.

  In FIG. 12, a gate oxide film is formed as the peripheral Nch-Tr gate insulating film 5N, and an HfO2 / SiO2 film is formed thereon using HfO2 as a high dielectric constant film. Subsequently, a laminated film TiSiN of barrier metal TiN and SiN for peripheral Nch-Tr laminated by the ALD technique is formed, and a protective silicon oxide film I is further formed.

  In FIG. 13, the peripheral Nch-Tr region is protected by a photoresist, and the protective silicon oxide film I, the peripheral Nch-Tr barrier metal TiSiN, and the peripheral Nch-Tr gate oxide film other than the protective region are removed.

  In FIG. 14, a gate oxide film is formed as the peripheral Pch-Tr gate insulating film 5P, and an HfO2 / SiO2 film is formed thereon using HfO2 as a high dielectric constant film. Subsequently, a barrier metal TiAlN for peripheral Pch-Tr in which TiN and AlO 2 are laminated by ALD technology is formed, and further a protective silicon oxide film II is formed.

  Here, as the high dielectric constant film used in FIGS. 12 and 14, in addition to HfO2, HfSiO, HfSiON, HfAlOx, ZrO2, Ta2O5, Nb2O5, Al2O3, ScO3, Y2O3, La2O3, CeO3, Pr2O3, Nd2O3, Sm2 Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, and Lu2O3 can be used.

  In FIG. 15, the peripheral Pch-Tr region is protected with a photoresist, and after removing the protective silicon oxide film II and the peripheral Pch-Tr barrier metal TiAlN other than the protective region, the photoresist is peeled off.

  In FIG. 16, returning to the processing on the cell region side, the bit contact opening 26a for forming the bit line 26 (FIG. 2) is formed.

  In FIG. 17, polycrystalline silicon (poly-Si) 31-1 to be a bit line is formed by ALD technology.

  In FIG. 18, the cell region is protected with a photoresist, the barrier metal TiSiN in the peripheral Nch-Tr and Pch-Tr portions in the peripheral circuit region is removed, and then the photoresist is peeled off to remove the protective silicon oxide films I and II. To do.

  In FIG. 19, the bit line gate electrode WSi 31-2, tungsten, and a hard mask silicon nitride film are formed in this order. Here, a W / WSi stack is illustrated, but instead of a W / WSi stack, a poly-Si single layer, a W single layer, a Ta single layer, a Ru single layer, an Al single layer, a W / WN layer, a W / WN layer, A TiN layer, a combination thereof, or the like can be used.

  In FIG. 20, the poly Si 31-1, WSi 31-2, tungsten, and hard mask silicon nitride film are dry-etched to form the bit line 26 (FIG. 2). On the other hand, the gate electrodes 11 of the transistors 24 and 25 in the peripheral circuit region are formed. Thereafter, the diffusion layers 15 and 16 and the sidewalls 17 described with reference to FIG. 2 are formed in the transistor portion in the peripheral circuit region. However, since these formations are not the gist of the present invention, the description thereof is omitted.

  Subsequently, after forming an interlayer SOD film 35 (FIG. 2), contact holes are opened, and contact plugs 38a, 38b, 20 and wirings are formed.

  As described above, in the above embodiment, metal wiring is used as the electrode and wiring material of the transistor on the cell region side.

  Conventionally, TiN is used as the barrier metal of the metal wiring. In this case, as described above, the work function of the transistor is constant, and there is a limit to the adjustment even if the threshold voltage Vt of the transistor is adjusted by channel doping. is there.

  On the other hand, in the present invention, a laminated barrier film in which TiN and SiN are laminated is used as the barrier metal of the gate electrode. Therefore, the work function can be freely set by changing the Si concentration in the barrier metal film. This makes it easier to adjust the threshold voltage Vt of the transistor.

  While the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims.

  For example, in the above-described embodiment, the description is applied to the gate electrode in the gate electrode groove, but it is needless to say that the present invention is not limited to this.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 11 Gate electrode 12 Element isolation region 14 Gate electrode groove | channel 15,16 Source / drain region 17 Side wall 18 Liner insulating film 26 Bit line 100 Semiconductor device Tr1-Tr4 Transistor

Claims (23)

A gate insulating film provided on the surface of the semiconductor substrate;
A laminated barrier film provided on the gate insulating film, in which barrier films and work function adjusting films are alternately laminated;
A conductive layer provided on the laminated barrier film;
A semiconductor device comprising a gate electrode.   The semiconductor device according to claim 1, wherein the laminated barrier film includes a plurality of films each including the barrier film and the work function adjusting film.   The semiconductor device according to claim 1, wherein the barrier film is a film including at least one material selected from the group consisting of Ti, TiN, Pt, and WN.   The semiconductor device according to claim 1, wherein the work function adjusting film is a film including at least one material selected from the group consisting of SiN, AlO 2, AlN, TiO 2, and CN.   The semiconductor device according to claim 1, wherein the gate insulating film includes a silicon oxide film.   The semiconductor device according to claim 5, wherein the gate insulating film further includes a high dielectric constant film on the silicon oxide film.   The high dielectric constant films are HfO2, HfSiO, HfSiON, HfAlOx, ZrO2, Ta2O5, Nb2O5, Al2O3, ScO3, Y2O3, La2O3, CeO3, Pr2O3, Nd2O3m, Sm2O3, Eu2O3T, Gd2O3T, Eu2O3T, Gd2O3 The semiconductor device according to claim 6, wherein the semiconductor device is a film including at least one material selected from the group consisting of Yb 2 O 3 and Lu 2 O 3.   8. The film according to claim 1, wherein the conductive film layer is a film containing at least one material selected from the group consisting of polycrystalline silicon, W, WN, WSi, Ta, Ru, and Al. Semiconductor device.   The semiconductor device according to claim 1, wherein the barrier film includes TiN, and the work function adjustment film includes SiN. A gate groove provided on the surface layer of the semiconductor substrate;
A gate insulating film provided on the gate trench;
A laminated barrier film provided on the gate insulating film, in which barrier films and work function adjusting films are alternately laminated;
A conductive layer provided on the laminated barrier film;
A semiconductor device comprising a gate electrode.   The semiconductor device according to claim 10, wherein the laminated barrier film includes a plurality of films each including the barrier film and the work function adjusting film.   The semiconductor device according to claim 10, wherein the barrier film is a film containing at least one material selected from the group consisting of Ti, TiN, Pt, and WN.   The semiconductor device according to claim 10, wherein the work function adjusting film is a film including at least one material selected from the group consisting of SiN, AlO 2, AlN, TiO 2, and CN.   The semiconductor device according to claim 10, wherein the gate insulating film includes a silicon oxide film.   15. The film according to claim 10, wherein the conductive film layer is a film containing at least one material selected from the group consisting of polycrystalline silicon, W, WN, WSi, Ta, Ru, and Al. Semiconductor device. Forming a gate insulating film on the surface of the semiconductor substrate;
A step of forming a laminated barrier film by alternately performing a step of forming a barrier film and a step of forming a work function adjusting film on the gate insulating film;
Forming a conductive film layer on the laminated barrier film;
A method of manufacturing a semiconductor device comprising a gate electrode.   The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the laminated barrier film includes a plurality of steps of forming the barrier film and forming the work function adjusting film.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the barrier film is a film containing at least one material selected from the group consisting of Ti, TiN, Pt, and WN.   The method of manufacturing a semiconductor device according to claim 16, wherein the work function adjusting film is a film including at least one material selected from the group consisting of SiN, AlO 2, AlN, TiO 2, and CN. .   The method for manufacturing a semiconductor device according to claim 16, wherein the gate insulating film includes a silicon oxide film.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the gate insulating film further includes a high dielectric constant film on the silicon oxide film.   The high dielectric constant films are HfO2, HfSiO, HfSiON, HfAlOx, ZrO2, Ta2O5, Nb2O5, Al2O3, ScO3, Y2O3, La2O3, CeO3, Pr2O3, Nd2O3m, Sm2O3, Eu2O3T, Gd2O3T, Eu2O3T, Gd2O3 The method of manufacturing a semiconductor device according to claim 21, wherein the film includes at least one material selected from the group consisting of Yb 2 O 3 and Lu 2 O 3.   23. The film according to claim 16, wherein the conductive film layer is a film containing at least one material selected from the group consisting of polycrystalline silicon, W, WN, WSi, Ta, Ru, and Al. A method for manufacturing a semiconductor device.

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