JP2015041765A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in a field effect transistor in which a gate electrode for inputting electric signal, is provided between a source electrode and a drain electrode on a substrate, which improves designability or controllability of the semiconductor device caused by occurrence of crystal defects generated by lattice mismatching with the substrate and internal field generation generated by intrinsic polarization and piezo polarization to keep the current in an off operation state when no signal is input, and can establish high withstand voltage, a large current flow, stable operation and a high reliability on the operation of the device.SOLUTION: A semiconductor device has a heterojunction structure in which a first buffer layer for reducing crystal defects and a second buffer layer for reducing internal field generation are formed between an operation active layer and a substrate, and a carrier supply layer as the operation active layer/a channel layer/a single channel for reducing stress, or a plurality of channels of the single channel are formed.

Description

  The present invention relates to a high withstand voltage / high current / stable operation technology of a semiconductor device in a field effect transistor in which a gate electrode for inputting an electric signal is provided between a source electrode and a drain electrode on a substrate, Alternatively, the present invention relates to a high output / high reliability technology of a semiconductor device.

Background technology

  This type of semiconductor device is a semiconductor device in a field effect transistor in which a gate electrode for inputting an electric signal is provided between a source electrode and a drain electrode on a substrate, and has a high withstand voltage and large current circuit control. It is the composition which carries out.

M.M. Abe, H .; Nagasawa, S .; Potastast, J. et al. Fernandez, J .; Schomann, D.M. As, and K.K. Lischka, “IEICE Trans. Electron., E89-C”, 2006, pages 1057 to 1063 S. Nakazawa, T .; Ueda, K .; Inoue, T .; Tanaka, H .; Ishikawa, and T.I. Egawa, “Solid State Physics and Applications, Japan Society of Applied Physics, 12, No. 1”, 2006, pages 15-19 N. Kobayashi, K. et al. Kumakura, T .; Nishida, N .; Maeda, T .; Makimoto, and M.M. Kasu, “OYO BUTURI, Vol. 70, No. 5”, 2001, pages 513 to 522

  In the case where the input and output signals of electrical signals are controlled and used in the semiconductor device described above, in order to increase the device withstand voltage, increase the current, stabilize the operation, and improve the reliability, It is necessary to realize few high-quality crystals.

  For this purpose, a high-quality crystal with few defects and impurities and a high withstand voltage are achieved. In large current operation, it is necessary to configure a semiconductor device that can realize stable operation by reducing parasitic effects such as unnecessary leakage current.

  Furthermore, when there is no input signal, a high-efficiency and low-loss element is required in which the current is maintained in the off-operation state. However, in normal compound semiconductors, generation of crystal defects and spontaneous polarization due to lattice mismatch with the substrate -It is difficult to improve the design or controllability of a semiconductor device due to the generation of an internal electric field due to piezo polarization.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a field effect transistor in which a gate electrode for inputting an electric signal is provided between a source electrode and a drain electrode on a substrate. In the semiconductor device, it is to provide a device capable of increasing the withstand voltage, increasing the current, stabilizing the operation, and improving the reliability of the device operation.

  In order to achieve this object, a first characteristic configuration of a semiconductor device according to the present invention is a group III nitride semiconductor on a substrate, as described in claim 1 or 2 in the claims, or A semiconductor device in a field effect transistor in which a group II-VI compound semiconductor is formed and a gate electrode for signal input is provided between a source electrode and a drain electrode, respectively, between the active active layer and the substrate It has a structure in which a buffer layer (buffer layer) for reducing crystal defects is formed.

  In the second characteristic configuration, a group III nitride semiconductor or a group II-VI compound semiconductor is formed on the substrate as described in claims 3, 4, 5, and 6 in the claims. , And having a structure formed by forming a first buffer layer and a second buffer layer.

  The third characteristic configuration is that, as described in claims 7 and 8 of the claims, the operational activity of the mixed crystal compound semiconductor composed of GaN, InN, or AlN in the group III nitride semiconductor. Heterojunction structure consisting of carrier supply layer / channel layer / stress relaxation layer as a layer forms a single channel of AlGaN / GaN / InGaN or InGaN / GaN / AlGaN or a plurality of channels of the single channel. It has the structure which becomes.

Further, the composition ratio of Al _x Ga _1-x N / GaN / In _y Ga _1-y N or In _y Ga _1-y N / GaN / Al _x Ga _1-x N is such that the composition ratio is 0 <x <0. .3 and 0 <y <0.2, or a structure formed by forming a plurality of channels of the single channel.

  As described in claim 9 in the column of claims, the fourth characteristic configuration includes, among the II-VI group compound semiconductors, ZnO, ZnS, ZnSe, CdO, MgO, MgZnO, MgS, MgSe, or Of the mixed crystal compound semiconductor composed of CdS, the heterojunction structure composed of the carrier supply layer / channel layer / stress relaxation layer as the operation active layer is a single channel of MgZnO / MgO / MgCdO or MgCdO / MgO / MgZnO. Alternatively, it has a structure in which a plurality of channels of the single channel are formed.

  According to the fifth feature of the present invention, as described in claims 10 and 11 of the claims, a gap is formed above the operation active layer in the group III nitride semiconductor or the group II-VI compound semiconductor. It has the structure which forms a layer.

The sixth feature of the present invention is that, as described in claim 12 in the column of claims, an SiO ₂ , SiON, or Si ₃ N ₄ insulating film is provided between the cap layer and the gate electrode metal film. Or a high purity film or an n-type film of the compound semiconductor or the mixed crystal compound semiconductor.

  The seventh feature of the present invention is that in a field effect transistor in which a gate electrode for signal input is provided between the source electrode and the drain electrode, respectively, as recited in claim 13 of the claims. In a semiconductor device, an electric field relaxation structure having the same potential as a source electrode or a gate electrode, or an electric field relaxation structure configured simultaneously with the electric field relaxation structure, or a gate electrode and a drain electrode. In the meantime, the p-type cap layer has a structure in which an electric field relaxation structure is formed at the same potential as the gate electrode.

  FIG. 1 shows a structure of an epitaxial crystal structure and a device structure of a semiconductor device according to the present invention.

  In the first embodiment, prior to crystal growth by the MOCVD epitaxial crystal growth method, the surface roughness of the SiC substrate was processed to 15 nm or less. As a result of epi surface morphology and structural analysis using a reciprocal lattice space map, it is known that the content ratio of hexagonal crystals to cubic crystals can be suppressed to 1% or less.

  FIG. 2 shows the substrate surface roughness dependence of the hexagonal crystal ratio according to the present invention.

In the second embodiment, an n-GaN low-temperature deposition layer (thickness: 0.1 μm, doping concentration: Si: 5E18 / cm ³ ), n− as a first buffer layer is formed on a SiC substrate by MOCVD epitaxial crystal growth. Following the Al _x Ga _1-x N buffer layer (x = 0.09, film thickness 50 nm, doping concentration Si: 5E18 / cm ³ ), as the second buffer layer, n-GaN (film thickness 0.2 μm, doping concentration) Si: 5E18 / cm ³ ), n-In _0.09 Al _0.32 Ga _0.59 N (film thickness 50 nm, doping concentration Si: 5E18 / cm ³ ), n-GaN (film thickness 0.2 μm, doping concentration) Si: 5E18 / cm ³ ) was grown sequentially.

The polarization generated when the In composition in InAlGaN is 0.08 or more (Al composition 0.37 or more) is larger than 0.052 C / m ² in the barrier layer Al _0.26 Ga _0.74 N.

In _0.09 Al _0.32 Ga _0.59 N layer is 0.05 <x <0.11 with respect to the composition ratio of In _x Al _y Ga _z N layer to Al _0.26 Ga _0.74 N layer. In the range, it is known that the generation of crystal defects due to lattice mismatch and the generation of an internal electric field due to spontaneous polarization / piezo polarization can be mitigated and the junction barrier due to the InAlGaN / AlGaN heterojunction can be lowered.

  FIG. 3 shows the In composition dependence of polarization for InAlGaN according to the present invention.

In the third embodiment, following the first buffer layer and the second buffer layer, an i-GaN channel layer (thickness: 200 nm, undoped concentration <1E16 / cm ³ ) in the operation active layer, n-Al _x Ga _1-x N carrier supply layer (x = 0.25, film thickness 30 nm, doping concentration Si: 1E18 / cm ³ ), n-GaN cap layer (film thickness 5 nm, doping concentration Si: 1E17 / cm ³ ), Grew sequentially.

  In the fourth embodiment, regarding the device structure fabrication, ohmic source and drain electrodes on the surface of the epi layer, and then a Schottky gate electrode were formed.

  In the fifth embodiment, the heterojunction structure consisting of the carrier supply layer / channel layer / stress relaxation layer as the operation active layer has a tensile strain in a single channel of AlGaN / GaN / InGaN or InGaN / GaN / AlGaN. Alternatively, the polarization electric field at the heterointerface related to spontaneous polarization and piezo polarization due to compressive strain is well known.

  FIG. 4 shows the composition ratio dependence of the electric field strength at the interface between the AlGaN / GaN and InGaN / GaN heterostructure according to the present invention.

The polarization electric field strength E at the heterostructure interface is expressed by E = E _{PE (piezo)} + E _{SP (spontaneous)} .
In _{Al x Ga 1-x N /} GaN, In _{x <0.3, E PE (piezo} ) <+ 1.4, the _{E SP (spontaneous)} <+1.8 and is E <3.2MV / cm.

In In _y Ga _1-y N / GaN, when y <0.2, E _{PE (piezo)} <-3.4, E _{SP (spontaneous)} <+0.2, and E <-3.2 MV / cm. Regarding the Al _x GaN _1-x / GaN / In _y Ga _1-y N heterostructure, it was confirmed that a normally-off operation can be realized when the composition ratio is x <0.3 and y <0.3.

  In the sixth embodiment, a source electrode and a drain electrode are formed with an ohmic Ti / Al vapor deposition film, a gate electrode is formed with a Schottky Ni / Au vapor deposition film, and subsequently, an electric field relaxation at the same potential as the gate electrode. The structure A (FIG. 5) was formed and proved to have an electric field relaxation effect and high breakdown voltage performance.

  It was also demonstrated that the electric field relaxation effect and high breakdown voltage performance can be realized by forming the electric field relaxation structure B (FIG. 6) with the p-type cap layer at the same potential as the gate electrode. 5-6 represents a device structure of an electric field relaxation structure according to the present invention.

Structure of epitaxial crystal structure and device structure of semiconductor device according to the present invention Dependence of hexagonal crystal ratio on substrate surface roughness according to the present invention In composition dependence of polarization for InAlGaN according to the present invention Composition ratio dependence of electric field strength at the interface between AlGaN / GaN and InGaN / GaN heterostructures according to the present invention Device structure of electric field relaxation structure A according to the present invention Device structure of electric field relaxation structure B according to the present invention according to the present invention

Claims (13)

  A semiconductor device in a field effect transistor in which a group III nitride semiconductor or a group II-VI compound semiconductor is formed on a substrate and a gate electrode for signal input is provided between a source electrode and a drain electrode, respectively. A semiconductor device in which a buffer layer (buffer layer) for reducing crystal defects is formed between the operation active layer and the substrate. As the substrate, various single crystal materials such as sapphire (Al ₂ O ₃ ), SiC, GaN, Ga ₂ O ₃ , ZnO, and Si are used, or the single crystal material is made up of various single crystal materials. 2. A material formed by bonding and integrating on a crystalline material is used, or a material formed by bonding and integrating the single crystal material on various amorphous materials of the single crystal material. Semiconductor device.   As the operation active layer, a mixed crystal compound semiconductor composed of GaN, InN, or AlN among the group III nitride semiconductors, or a ZnO, ZnS, ZnSe, CdO, MgO among the group II-VI compound semiconductors. A semiconductor device that operates with a mixed crystal compound semiconductor made of MgZnO, MgS, MgSe, or CdS, wherein the surface roughness of the substrate is limited to 15 nm or less. 2. The semiconductor device according to 2.   Among the group III nitride semiconductors, there is a semiconductor device that operates with a mixed crystal compound semiconductor composed of GaN, InN, or AlN. On the substrate, as a first buffer layer, a GaN low-temperature deposition layer, an AlGaN layer, Alternatively, an AlN layer, or both the GaN low-temperature deposited layer and the AlGaN layer or the AlN layer are formed, or selective lateral growth (ELOG) is formed, and a GaN containing an InAlGaN layer as a second buffer layer 4. The semiconductor device according to claim 1, wherein the semiconductor device is a / InAlGaN / AlGaN layer or a multilayer structure of the GaN / InAlGaN / AlGaN layer. Among the group III nitride semiconductors, there is a semiconductor device operating with a mixed crystal compound semiconductor made of GaN, InN, or AlN, and the In _x Al _y Ga _z N layer as the second buffer layer is set to 0. 5. The semiconductor device formed by forming a layer containing y = 4.66x and z = 1-xy in a range of 05 <x <0.11. Semiconductor device. Among the II-VI group compound semiconductors, there is provided a semiconductor device operating with a mixed crystal compound semiconductor made of ZnO, ZnS, ZnSe, CdO, MgO, MgZnO, MgS, MgSe, or CdS, wherein a buffer is formed on the substrate. 4. The semiconductor device according to claim 1, wherein the semiconductor device comprises a ZnO low-temperature deposition layer, a CaF ₂ layer, or both of the ZnO low-temperature deposition layer and the CaF ₂ layer as layers.   Of the mixed crystal compound semiconductor composed of GaN, InN, or AlN in the group III nitride semiconductor, the heterojunction structure composed of the carrier supply layer / channel layer / stress relaxation layer as the operation active layer is AlGaN / GaN / InGaN. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a single channel of InGaN / GaN / AlGaN or a plurality of channels of the single channel. Of the mixed crystal compound semiconductor composed of GaN, InN, or AlN in the group III nitride semiconductor, a heterojunction structure composed of a stress relaxation layer / carrier supply layer / channel layer serving as the operation active layer has an Al _x Ga _{1− x N / GaN / In y Ga} 1-y N, _or, with respect to _{In y Ga 1-y N /} GaN / Al x Ga 1-x N, composition ratio, 0 <x <0.3 and 0 <y < The semiconductor device according to claim 1, wherein the semiconductor device is formed by forming a single channel having 0.2 or a plurality of channels of the single channel. Among the II-VI group compound semiconductors, among the mixed crystal compound semiconductors made of ZnO, ZnS, ZnSe, CdO, MgO, MgZnO, MgS, MgSe, or CdS, the stress relaxation layer / carrier supply layer as the operation active layer A heterojunction structure comprising a / channel layer is a semiconductor device formed by forming a single channel of MgZnO / MgO / MgCdO, a single channel of MgCdO / MgO / MgZnO, or a plurality of channels of the single channel. The semiconductor device according to 1, 2, 3, or 6.   Of the mixed crystal compound semiconductor composed of GaN, InN, or AlN in the group III nitride semiconductor, a high purity GaN, InN, AlN, or n-type GaN is formed as a cap layer on the operation active layer. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a mixed crystal compound semiconductor made of InN or AlN. Among the II-VI group compound semiconductors, among the mixed crystal compound semiconductors made of ZnO, ZnS, ZnSe, CdO, MgO, MgZnO, MgS, MgSe, or CdS, high purity as a cap layer on the operation active layer A semiconductor device formed by forming a mixed crystal compound semiconductor composed of MgO, MgS, MgSe, or n-type MgO, MgS, or MgSe. The semiconductor device described. A high-purity film of SiO ₂ , SiON, or Si ₃ N ₄ insulating film, the compound semiconductor, or the mixed crystal compound semiconductor is formed between the cap layer and the gate electrode metal film. 12. The semiconductor device according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11.   A field effect transistor in which the group III nitride semiconductor or the group II-VI compound semiconductor is formed on the substrate, and a gate electrode for signal input is provided between the source electrode and the drain electrode. The electric field relaxation structure having the same potential as the source electrode or the gate electrode, or the electric field relaxation structure in which the electric field relaxation structure is formed at the same time, or the gate electrode and the drain. A semiconductor device in which an electric field relaxation structure is formed between electrodes with a p-type cap layer at the same potential as that of a gate electrode, wherein: 11. A semiconductor device according to 11, or 12.