JP2014225693A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device having a low on-resistance and a high avalanche resistance and a method of manufacturing the same are provided. A semiconductor device according to an embodiment is provided on a first surface side of a first semiconductor layer, a plurality of base regions provided in a direction parallel to the first surface, and a source selectively provided on the surface thereof A region, a first main electrode, a second main electrode electrically connected to the source region, a plurality of gate electrodes, and a second surface side of the gate electrode, and the first main electrode is interposed through the field plate insulating film A plurality of field plate electrodes provided in one semiconductor layer. The width of the field plate insulating film in the direction parallel to the first surface is larger than the width of the gate insulating film and the source region in the direction parallel to the first surface, and the width of the base region in the direction parallel to the first surface is The width is larger than the width of the adjacent field plate insulating film in the direction parallel to the first surface. [Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an upper and lower electrode structure is a semiconductor device used for power conversion of, for example, household electric appliances and automobile motors. Since this type of semiconductor device is used for electric power, it needs to have a high breakdown voltage. In addition, in order to reduce power consumption, this type of element needs to reduce the resistance during on-operation (hereinafter referred to as on-resistance).

  There is a field plate structure as means for reducing the on-resistance. In the field plate structure, a gate electrode is provided in a trench through a gate insulating film, and a field plate electrode is provided under the gate electrode through a field plate oxide film. By providing the field plate electrode, it is possible to increase the impurity concentration of the drift layer of the MOSFET, so that there is an advantage that the on-resistance is lowered. Further, in this type of MOSFET, the field plate electrode facilitates depletion of the drift layer and maintains a high breakdown voltage.

  However, with the miniaturization of the power MOSFET, the trench pitch tends to be reduced. When the pitch of the trench is reduced, the base layer sandwiched between the trenches is narrowed. This makes it increasingly difficult to form a source layer provided on the surface of the base layer and a carrier extraction layer provided in the base layer. The carrier extraction layer eliminates holes generated by avalanche breakdown, for example. Providing such a layer improves the avalanche resistance of the power MOSFET. Accordingly, there is a need for a power MOSFET that has low on-resistance and high durability even when miniaturization of the power MOSFET proceeds.

JP 2001-230414 A

  The problem to be solved by the present invention is to provide a semiconductor device having a low on-resistance and a high avalanche resistance and a method for manufacturing the same.

  The semiconductor device according to the embodiment includes a first semiconductor layer of a first conductivity type having a first surface and a second surface facing the first surface, and in the first semiconductor layer on the first surface side. A plurality of second conductivity type base regions provided in a direction parallel to the first surface; a first conductivity type source region selectively provided on each surface of the base region; A first main electrode electrically connected to one semiconductor layer; a second main electrode electrically connected to the source region; and the base interposed between the adjacent base regions through the gate insulating film A plurality of gate electrodes provided adjacent to the region, and a plurality of field plates positioned in the second surface side of the gate electrode and provided in the first semiconductor layer via a field plate insulating film An electrode. The width of the field plate insulating film in the direction parallel to the first surface is larger than the width of the gate insulating film and the source region in the direction parallel to the first surface, and is parallel to the first surface. The width of the base region is larger than the width of the field plate insulating film adjacent in the direction parallel to the first surface.

It is a schematic diagram of the semiconductor device according to the first embodiment, (a) is a schematic sectional view, (b) is a schematic plan view. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on a reference example. It is a cross-sectional schematic diagram for demonstrating the effect of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 4th Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 5th Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 6th Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 7th Embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 8th Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
1A and 1B are schematic views of a semiconductor device according to the first embodiment. FIG. 1A is a schematic cross-sectional view, and FIG. 1B is a schematic plan view. FIG. 1A shows the XX ′ cross section of FIG.
FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

A semiconductor device 100 shown in FIG. 1 is a power MOSFET element having an upper and lower electrode structure. In the semiconductor device 100, an n-type drift layer (first semiconductor layer) 11 is provided on the n ⁺ -type drain layer 10. A plurality of p-type base regions 12 are provided on the surface of the drift layer 11. An n ^{+ -type} source region 13 is selectively provided on each surface of the base region 12.

In the semiconductor device 100, a p ^{+ -type} contact region (carrier extraction region) 15 is selectively provided on the surface of the base region 12. Contact region 15 is connected to source region 13. The impurity concentration of the contact region 15 is higher than the impurity concentration of the base region 12. The distance between the lower end of the contact region 15 and the back surface of the drift layer 11 (or the surface of the drain layer 10) is the lower end of the source region 13 and the back surface of the drift layer 11 (or the surface of the drain layer 10). And shorter than the distance between.

  Further, in the semiconductor device 100, the gate electrodes 22 are provided through the gate insulating film 21 in the pair of trenches 20 that penetrate the base region 12 from the surface of the source region 13 and reach the drift layer 11. ing. The embodiment is not limited to a semiconductor device in which the trench 20 is only a pair. That is, the embodiment includes a semiconductor device provided with two or more trenches 20.

In the pair of trenches 20, field plate electrodes 24 are respectively provided below the gate electrodes 22 via field plate insulating films 23.
Since the trench-shaped field plate electrode 24 is provided in the drift layer 11, the drift layer 11 is easily depleted. For this reason, the impurity concentration of the drift layer 11 can be increased. Thereby, the specific resistance of the drift layer 11 is reduced and the on-resistance is reduced. An interlayer insulating film 30 is provided on the gate electrode 22, the gate insulating film 21, and the source region 13.

  In the semiconductor device 100, a part of the field plate insulating film 23 is thicker than the gate insulating film 21. The part of the field plate insulating film 23 is a part of the field plate insulating film 23 in contact with the side surface of the field plate electrode 24, for example. Thus, the width of the drift layer 11 between the portions of the field plate insulating film 23 provided in each of the pair of trenches 20 is set so that the gate insulating films 21 provided in each of the pair of trenches 20 are connected to each other. It is narrower than the width of the base region 12 between the two. Here, the “width” is the distance between the members of the semiconductor device 100 in the direction in which the trenches 20 are periodically arranged.

  In the semiconductor device 100, the width of the source region 13 is adjusted as appropriate. For example, in FIG. 2, the width of the source region 13 is narrower than the width of the source region 13 illustrated in FIG. That is, an embodiment in which the source region 13 is not formed immediately above the interface between the drift layer 11 and the portion of the field plate insulating film 23 in contact with the side surface of the field plate electrode 24 is also included in the embodiment. In this case, a contact region 15 is formed immediately above the interface.

  In the semiconductor device 100, the first main electrode 90 that is a drain electrode is electrically connected to the drift layer 11 via the drain layer 10. A second main electrode 91 that is a source electrode is electrically connected to the source region 13 and the contact region 15. For example, the field plate electrode 24 is electrically connected to the second main electrode 91 or the gate electrode 22.

The main component of the drain layer 10, the drift layer 11, the base region 12, the source region 13, and the contact region 15 is, for example, silicon (Si). The material of the gate insulating film 21, the field plate insulating film 23, and the interlayer insulating film 30 is, for example, silicon oxide (SiO ₂ ). The material of the gate electrode 22 and the field plate electrode 24 is polysilicon containing impurities.

  The material of the first main electrode 90 is a metal such as copper (Cu) or aluminum (Al). The material of the second main electrode 91 is a metal such as molybdenum (Mo), aluminum (Al), or copper (Cu). When the semiconductor device 100 is provided with a Schottky barrier diode (hereinafter referred to as SBD) to be described later, the material of the second main electrode 91 is preferably a metal such as molybdenum (Mo) or aluminum (Al).

In the embodiment, the first conductivity type including the n-type, n ^{+ type} , and n ^{− type} may be referred to as the second conductivity type including the p-type, p ^{+ type} , and p ^{− type} . For example, phosphorus (P), arsenic (As), or the like is used as the first conductivity type impurity, and boron (B) is used as the second conductivity type impurity.

  3 to 6 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the first embodiment.

  First, as shown in FIG. 3A, a semiconductor substrate 10s on which a drift layer 11 is formed is prepared. The semiconductor substrate 10 s includes a drain layer 10 and a drift layer 11 formed on the drain layer 10.

After preparing the semiconductor substrate 10s, a mask member 80 is selectively formed on the surface of the semiconductor substrate 10s. The material of the mask member 80 is, for example, silicon oxide (SiO ₂ ). Subsequently, the drift layer 11 exposed from the mask member 80 is etched by RIE (Reactive Ion Etching). Thereby, a pair of trenches 20 having a depth d1 is selectively formed from the surface of the drift layer 11 to the inside thereof.

Next, as shown in FIG. 3B, a mask film 81 is formed on the inner side surfaces of the pair of trenches 20 and the bottom surface of the trenches 20. The mask film 81 is, for example, a single-layer film of the material is silicon nitride _(Si 3 _{N 4)} or a film of two-layer structure of silicon nitride _{(Si 3 N} 4) / silicon oxide (SiO _2). The mask film 81 may be formed not only in the trench 20 but also on the surface and side surfaces of the mask member 80.

  Next, as shown in FIG. 3C, the mask film 81 formed on each bottom surface of the pair of trenches 20 is removed by RIE, and the drift layer 11 is exposed on each bottom surface of the pair of trenches 20. .

  Next, as shown in FIG. 4A, the drift layer 11 exposed from the bottom surface of each of the pair of trenches 20 is removed by RIE, whereby the trenches 20 having a depth d2 deeper than the depth d1. Is formed from the surface of the drift layer 11 to the inside.

  Next, as shown in FIG. 4B, the surface of the drift layer 11 exposed from the mask film 81 is oxidized in each of the pair of trenches 20. For example, the surface of the drift layer 11 is oxidized by LOCOS (Local Oxidation of Silicon) in an oxidizing atmosphere. Thereby, the field plate insulating film 23 is formed on the surface of the drift layer 11 exposed from the mask film 81.

  Next, as shown in FIG. 5A, a conductive layer 24A is embedded in each of the pair of trenches 20 by CVD (Chemical Vapor Deposition). The conductive layer 24A is, for example, a polysilicon layer. Subsequently, the conductive layer 24A is etched back until the surface of the conductive layer 24A becomes lower than the upper end of the field plate insulating film 23. Thereafter, the mask film 81 is removed. This state is shown in FIG.

  As shown in FIG. 5B, a field plate electrode 24 is formed in each of the pair of trenches 20 via a field plate insulating film 23. Thereafter, the mask member 80 is removed.

  Next, as shown in FIG. 6A, the gate insulating film 21 is formed on the inner side surface of each trench 20 and the field plate electrode 24 in each of the pair of trenches 20. For example, the gate insulating film 21 is formed by thermal oxidation in an oxidizing atmosphere. Subsequently, the conductive layer 22A is embedded in each of the pair of trenches 20 by CVD. The conductive layer 22A is, for example, a polysilicon layer. Subsequently, the conductive layer 24A is etched back so that the surface of the conductive layer 24A and the surface of the drift layer 11 are flush with each other. This state is shown in FIG.

  As shown in FIG. 6B, a gate electrode 22 is formed through a gate insulating film 21 in each of the pair of trenches 20.

  When the gate electrode 22 and the field plate electrode 24 are formed in each of the pair of trenches 20, the thickness of a part of the field plate insulating film 23 is thicker than the thickness of the gate insulating film 21. adjust. Furthermore, the width of the drift layer 11 between a part of the field plate insulating film 23 provided in the pair of trenches 20 is set so that the drift layer 11 between the gate insulating films 21 provided in the pair of trenches 20 is. Adjust to be narrower than the width of.

  The drift layer 11 between the gate insulating films 21 formed in the pair of trenches 20 is modified into the base region 12 by a process described later. In other words, in the embodiment, the width of the drift layer 11 between a part of the field plate insulating films 23 provided in the pair of trenches 20 is set between the gate insulating films 21 provided in the pair of trenches 20. The width of the base region 12 is adjusted to be narrower.

  Thereafter, the gate insulating film 21 formed on the surface of the drift layer 11 is removed. Subsequently, as shown in FIG. 1, a plurality of base regions 12 are formed on the surface of the drift layer 11 by ion implantation. Further, the source region 13 and the contact region 15 are selectively formed on the respective surfaces of the base region 12 by ion implantation. Furthermore, a first main electrode 90 electrically connected to the drift layer 11 via the drain layer 10 and a second main electrode 91 electrically connected to the source region 13 and the contact region 15 are formed. In such a manufacturing process, the semiconductor device 100 is formed.

  In the manufacturing process of the semiconductor device according to the first embodiment, the source region 13 is not formed immediately above the interface between the drift layer 11 and a part of the field plate insulating film 23 as in the semiconductor device 100 shown in FIG. As described above, the width of the source region 13 may be adjusted.

The effect of the semiconductor device 100 will be described. Before describing the effects of the semiconductor device 100, FIG. 7 shows a schematic cross-sectional view of a semiconductor device 300 according to a reference example.
In the semiconductor device 300 shown in FIG. 7, a gate electrode 220 and a field plate electrode 240 are provided in each of the pair of trenches 200. For example, the field plate electrode 240 is electrically connected to the second main electrode 91. The trench 200 has a gentle reverse taper shape (a shape in which the trench 200 becomes narrower toward the lower side).

  In the semiconductor device 300, the width of the base region 120 between the pair of trenches 200 is narrower than the width of the drift layer 11 between the pair of trenches 200. Therefore, when the pitch of the trench 20 of the semiconductor device 100 according to the first embodiment and the pitch of the trench 200 of the semiconductor device 300 according to the reference example are the same, the base region 120 between the trenches 200 of the semiconductor device 300 is The width is narrower than the width of the base region 12 between the trenches 20 of the semiconductor device 100.

  Therefore, in the semiconductor device 300, when the source region 13 and the contact region 15 are formed on the surface of the base region 120, the source region 13 and the contact region 15 are formed on the surface of the base region 120 in a narrow region. Positioning of the region 13 and the contact region 15 becomes difficult.

  Further, in the semiconductor device 300, since the trench 200 has an inversely tapered shape, the trench 200 becomes wider toward the upper side. Therefore, when forming a necessary member in the trench 200 adjacent to the base region 120, it is necessary to form the gate electrode 220 thicker or to have a structure in which the upper portion of the field plate electrode 240 is sandwiched between the gate electrodes 220.

  However, in the structure in which the field plate electrode 240 is sandwiched between the gate electrodes 220, it is necessary to provide the insulating film 211 between the field plate electrode 240 and the gate electrode 220. For this reason, the parasitic capacitance between the gate electrode 220 and the second main electrode 91 increases.

  On the other hand, FIG. 8 is a schematic cross-sectional view for explaining the effect of the semiconductor device according to the first embodiment.

  In the semiconductor device 100, the width of the trench 20 in the gate insulating film 21 portion is narrower than the width of the trench 20 in the field plate insulating film 23 portion. That is, the width of the base region 12 between the pair of trenches 20 is wider than the width of the drift layer 11 between the pair of trenches 20.

  Thereby, even if the pitch of the trench 20 becomes narrow, the base region 12 having a width wider than the width of the drift layer 11 can be secured. Accordingly, the source region 13 and the contact region 15 can be formed on the surface of the base region 12 in a wide region, and the alignment of the source region 13 and the contact region 15 becomes easy.

  In the semiconductor device 100, the upper portion of the trench 20 is narrower than the lower side. Therefore, it is sufficient to form the gate electrode 22 through the gate insulating film 21 in the trench 20 adjacent to the base region 12. Therefore, the above-described insulating film 211 becomes unnecessary. As a result, an increase in parasitic capacitance between the gate electrode 22 and the second main electrode 91 is suppressed.

  Further, in the semiconductor device 100, even if a breakdown due to, for example, avalanche breakdown occurs at the lower end portion 95 of the trench 20 and holes h (holes) are generated near the lower end portion 95 of the trench 20, the holes h are Then, it is quickly discharged to the second main electrode 91 through the contact region 15 (see arrow h in the figure). In particular, as shown in FIG. 2, when the source region 13 is not formed directly on the interface between a part of the field plate insulating film 23 and the drift layer 11 and the contact region 15 is formed, the hole h is The contact region 15 is preferentially reached over the source region 13.

  If the holes h do not reach the contact region 15 preferentially, the holes h may stay in the base region 12. For this reason, the potential of the base region 12 rises, and there is a possibility that a bipolar action due to the parasitic bipolar transistor occurs. When the bipolar action is interlocked, element destruction may occur due to so-called latch-up.

  The semiconductor device 100 has a structure in which the holes h reach the contact region 15 preferentially over the source region 13. As a result, the semiconductor device 100 has a high avalanche resistance.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the second embodiment.
The basic structure of the semiconductor device 101 according to the second embodiment is the same as that of the semiconductor device 100. However, in the semiconductor device 101, the contact region 15 penetrates the base region 12. The lower end 15 b of the contact region 15 is in contact with the drift layer 11.

  With such a structure, holes h (holes) generated near the lower end portion 95 of the trench 20 are more easily discharged to the second main electrode 91 through the contact region 15 than in the semiconductor device 100. Become. As a result, in the semiconductor device 101, low on-resistance is realized, and the semiconductor device 101 has a higher avalanche resistance than the semiconductor device 100.

(Third embodiment)
FIG. 10 is a schematic cross-sectional view of a semiconductor device according to the third embodiment.
The semiconductor device 102 according to the third embodiment is an IGBT (Insulated Gate Bipolar Transistor) element. That is, in the semiconductor device 102, in addition to the structure of the semiconductor device 100, a p ^{+ -type} semiconductor layer (second semiconductor layer) 16 is interposed between the drift layer 11 and the first main electrode 90. The p ^{+ type} semiconductor layer 16 is provided on the drain layer 10. During operation of the semiconductor device 102, holes are injected from the p-type semiconductor layer 16. As a result, the semiconductor device 102 has the same effect as the semiconductor device 100, and a larger current can flow through the semiconductor device 102 than the semiconductor device 100.

(Fourth embodiment)
FIG. 11 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment.
The semiconductor device 500 according to the fourth embodiment is an SBD. In the semiconductor device 500, the n-type drift layer 11 is provided on the n ⁺ -type drain layer 10. The drain layer 10 and the drift layer 11 may be referred to as n-type semiconductor layers since the semiconductor device 500 is an SBD.

  A pair of trenches 20 is provided from the surface of the drift layer 11 to the inside. A conductive layer 41 is provided in each trench 20. An insulating film 40 is provided between the conductive layer 41 and the drift layer 11.

  In the pair of trenches 20, field plate electrodes 24 are respectively provided below the conductive layers 41 via field plate insulating films 23. A portion of the field plate insulating film 23 is thicker than the insulating film 40. The width of the drift layer 11 between the part of the field plate insulating film 23 provided in each of the pair of trenches 20 is equal to the width of the drift layer 11 between the conductive layers 41 provided in the pair of trenches 20 respectively. It is narrower than the width.

  On the back surface side of the drift layer 11, the first main electrode which is a cathode electrode is electrically connected to the drift layer 11 via the drain layer 10. On the surface side of the drift layer 11, the second main electrode 91 that is an anode electrode is electrically connected to the drift layer 11 and the conductive layer 41. The second main electrode 91 and the drift layer 11 form a Schottky barrier junction.

  In the semiconductor device 500, the width of the drift layer 11 between some of the field plate insulating films 23 provided in the pair of trenches 20 is between the conductive layers 41 provided in the pair of trenches 20. Since the width of the drift layer 11 is narrower, the area of the Schottky barrier junction increases. Thereby, the forward drop voltage (VF) of the SBD is reduced.

  In the semiconductor device 500, the trench-shaped field plate electrode 24 is provided in the drift layer 11. For this reason, the drift layer 11 is easily depleted. As a result, the impurity concentration of the drift layer 11 can be increased. Thereby, the specific resistance of the drift layer 11 is reduced, and the forward voltage drop (VF) is further reduced.

  In the semiconductor device 500, the conductive layer 41 is provided in the trench 20 on the field plate electrode 24 via the insulating film 40. Thereby, in a state where the reverse voltage (VR) is applied to the semiconductor device 500, the depletion layer extends from the second main electrode 91 to the drift layer 11 and also extends from the insulating film 40 to the drift layer 11. As a result, in the semiconductor device 500, even when a reverse voltage is applied to the semiconductor device 500 during reverse recovery of the semiconductor device 500, the leakage current (IR) can be suppressed low.

  Further, in the semiconductor device 500, the impurity concentration of the drift layer 11 between the conductive layers 41 provided in the pair of trenches 20 is set so that a part of the field plate insulating film 23 provided in the pair of trenches 20 is part of. It may be lower than the impurity concentration of the drift layer 11 between. Thereby, it becomes easier to deplete than the portion of the drift layer 11 sandwiched between the conductive layers 41, and the leakage current can be further reduced.

  Further, each of the semiconductor device 500 and the SBD exemplified below may be provided on the same semiconductor substrate 10s as the semiconductor devices 100 to 102. For example, in the manufacturing process of the semiconductor device 500, the gate insulating film 21 shown in FIG. 6B is removed from the surface of the drift layer 11 after the steps shown in FIGS. Thus, the first main electrode 90 and the second main electrode 91 are formed. Here, the thickness of a part of the field plate insulating film 23 is adjusted to be thicker than the thickness of the insulating film 40. In addition, the width of the drift layer 11 between a part of the field plate insulating film 23 provided in each of the pair of trenches 20 is set between the insulating films 40 provided in each of the pair of trenches 20. It is adjusted to be narrower than the width of the drift layer 11.

(Fifth embodiment)
FIG. 12 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment.
The basic structure of the semiconductor device 501 according to the fifth embodiment is the same as that of the semiconductor device 500. However, in the semiconductor device 501 according to the fifth embodiment, a p-type semiconductor layer (third semiconductor layer) 50 is further provided on the surface of the drift layer 11 with the insulating film 40 interposed therebetween. The p-type semiconductor layer 50 is connected to the second main electrode 91.

  In the semiconductor device 501, since the pn junction is formed by the p-type semiconductor layer 50 and the drift layer 11, a depletion layer extends from the p-type semiconductor layer 50 to the drift layer 11. As a result, when a reverse voltage is applied to the semiconductor device 501, the drift layer 11 in the portion sandwiched between the conductive layers 41 is more easily depleted than the semiconductor device 500. As a result, in the semiconductor device 501, even when a reverse voltage is applied to the semiconductor device 501 at the time of reverse recovery of the semiconductor device 501, the leakage current (IR) can be further suppressed as compared with the semiconductor device 500.

  Note that the p-type semiconductor layer 50 is formed after the steps from FIG. 3A to FIG. 6B, and then on the surface of the drift layer 11 so as to be adjacent to the insulating film 40. Form.

The formation of the p-type semiconductor layer 50 is, for example,
(1) A mask member having a portion where the p-type semiconductor layer 50 is formed is selectively formed on the drift layer 11 by photolithography, and then ion implantation is performed on the surface of the drift layer 11 opened from the mask member. A method of injecting boron (B).
(2) After an SOG (Spin On Glass) film containing boron (B) selectively is formed on the drift layer 11, the SOG film is subjected to heat treatment to drift boron (B) contained in the SOG film. A method of diffusing into the layer 11 (the main component of the SOG film is silicon oxide (SiOx)).
(3) After selectively forming a polysilicon layer containing boron (B) on the drift layer 11, heat treatment is performed on the polysilicon layer, and boron contained in the polo silicon layer is diffused into the drift layer 11. How to make.
Made by either. The p-type semiconductor layer 50 shown below is formed in the same process.

(Sixth embodiment)
FIG. 13 is a schematic cross-sectional view of a semiconductor device according to the sixth embodiment.
In the semiconductor device 502 according to the sixth embodiment, the conductive layer 41 and the field plate electrode 24 are connected. With such a structure, it is not necessary to form the conductive layer 41 and the field plate electrode 24 separately. That is, the conductive layer 41 and the field plate electrode 24 can be formed simultaneously, and the manufacturing process is simplified. Thereby, the manufacturing cost of the semiconductor device 502 can be kept low.

(Seventh embodiment)
FIG. 14 is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment.
In the semiconductor device 503 according to the seventh embodiment, the insulating film 40 provided in the semiconductor device 500 is removed. In the semiconductor device 503, the p-type semiconductor layer 50 is provided on the surface of the drift layer 11. The p-type semiconductor layer 50 is connected to the conductive layer 41 and the second main electrode 91.

  The procedure for forming the p-type semiconductor layer 50 is as follows. For example, the conductive layer 41 is made of polysilicon containing boron (B), a semiconductor layer that is a precursor layer of the p-type semiconductor layer 50 is formed on the conductive layer 41, and boron is then added to the precursor layer from the polysilicon. The p-type semiconductor layer 50 is formed by diffusing.

  In the semiconductor device 503, the manufacturing process is simplified because the insulating film 40 is not formed. Thereby, the manufacturing cost of the semiconductor device 503 can be further reduced. Further, in the semiconductor device 503, the potential of the conductive layer 41 is directly conducted to the p-type semiconductor layer 50 because the insulating film 40 is not formed. That is, the electric potential of the conductive layer 41 can be efficiently transmitted to the p-type semiconductor layer 50 as much as no charge is charged in the insulating film 40. Therefore, even when a reverse voltage is applied to the semiconductor device 503 during reverse recovery of the semiconductor device 503, the leakage current (IR) can be further reduced as compared with the semiconductor device 501.

(Eighth embodiment)
FIG. 15 is a schematic cross-sectional view of a semiconductor device according to the eighth embodiment.
The semiconductor device 504 according to the eighth embodiment is a high efficiency diode (HED). In the semiconductor device 504, a p-type semiconductor layer (fourth semiconductor layer) 60 is further provided between the drift layer 11 and the second main electrode 91. Another p-type semiconductor layer (fifth semiconductor layer) 61 is interposed between the p-type semiconductor layer 60 and the second main electrode 91.

The impurity concentration of the p-type semiconductor layer 60 is, for example, lower than the impurity concentration of the p-type semiconductor layer 50 described above. The impurity concentration of the p-type semiconductor layer 60 is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ (atoms / cm ³ ). The impurity concentration of the p-type semiconductor layer 61 is higher than the impurity concentration of the p-type semiconductor layer 50. The impurity concentration of the p-type semiconductor layer 61 is, for example, 1 × 10 ¹⁹ (atoms / cm ³ ) or more. The p-type semiconductor layer 61 may be referred to as a high concentration p-type semiconductor layer or an ohmic layer. The p-type semiconductor layer 61 and the second main electrode 91 are in ohmic contact.

  Since the p-type semiconductor layer 61 is a high-concentration p-type semiconductor layer, there is a possibility that the amount of hole injection increases and the reverse recovery time (Trr) of the semiconductor device becomes long. Therefore, in the embodiment, the p-type semiconductor layer 61 is thinly formed in order to suppress hole injection while performing ohmic junction. Also, in order to increase the breakdown voltage of the semiconductor device, the p-type semiconductor layer 60 is formed to a thickness that allows the depletion layer to extend. The p-type semiconductor layer 60 is formed at a lower concentration than the p-type semiconductor layer 61 in order to reduce the amount of hole injection.

  Since the p-type semiconductor layer 60 is not a high-concentration p-type semiconductor layer, the amount of hole injection is reduced. As a result, it is considered that the electrical conductivity of the drift layer 11 decreases and the forward voltage drop (VF) increases. However, in the semiconductor device 504, since the field plate electrode 24 is provided, the concentration of the drift layer 11 can be increased. As a result, an increase in forward voltage drop (VF) can be suppressed.

  In addition, in the semiconductor device 504, a lifetime killer layer may be formed on at least a part of at least one of the p-type semiconductor layer 60 and the drift layer 11. For example, platinum (Pt), gold (Au), or the like is diffused into at least a part of at least one of the p-type semiconductor layer 60 and the drift layer 11, or an electron beam or a proton is diffused in the p-type semiconductor layer 60 and the drift layer 11. At least a part of at least one of them may be irradiated. By providing the lifetime killer layer, the lifetime of holes injected from the p-type semiconductor layer 61 into the drift layer 11 is further shortened. Thereby, in the semiconductor device 504, an increase in the reverse recovery time (Trr) is suppressed.

  Further, in the semiconductor device 504, in order to reduce the contact resistance between the second main electrode 91 and the p-type semiconductor 61, the material of the second main electrode 91 is an aluminum (Al) film, aluminum silicon ( An AlSi) film or the like heat-treated may be used. By the heat treatment, aluminum atoms diffuse from the second main electrode 91 into the silicon semiconductor layer. Thereby, the semiconductor layer in contact with the second main electrode 91 has an ohmic effect on the second main electrode 91 as a p-type semiconductor layer, like the semiconductor layer in which boron (B) is diffused.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 drain layer, 10s semiconductor substrate, 11 drift layer, 12, 120 base region, 13 source region, 15 contact region, 15b lower end, 16 p ^{+ type} semiconductor layer, 20, 200 trench, 21 gate insulating film, 22, 220 gate Electrode, 22A, 24A, 41 conductive layer, 23 field plate insulating film, 24, 240 field plate electrode, 30 interlayer insulating film, 40, 211 insulating film, 50, 60, 61 p-type semiconductor layer, 80 mask member, 81 mask Membrane, 90 First main electrode, 91 Second main electrode, 95 Lower end, 100, 101, 102, 300, 500, 501, 502, 503, 504 Semiconductor device, d1, d2 depth

Claims (15)

A first semiconductor layer of a first conductivity type having a first surface and a second surface facing the first surface;
A base region of a second conductivity type provided in the first semiconductor layer on the first surface side and provided in a plurality in a direction parallel to the first surface;
A source region of a first conductivity type selectively provided on each surface of the base region;
A first main electrode electrically connected to the first semiconductor layer;
A second main electrode electrically connected to the source region;
A plurality of gate electrodes located between the adjacent base regions and provided adjacent to the base region via a gate insulating film;
A plurality of field plate electrodes located in the second surface side of the gate electrode and provided in the first semiconductor layer via a field plate insulating film;
With
The width of the field plate insulating film in the direction parallel to the first surface is larger than the width of the gate insulating film and the source region in the direction parallel to the first surface,
A width of the base region in a direction parallel to the first surface is larger than a width of the field plate insulating film adjacent in the direction parallel to the first surface. A contact region of a second conductivity type is selectively provided in the base region;
The contact region is connected to the source region;
The semiconductor device according to claim 1, wherein an impurity concentration of the contact region is higher than an impurity concentration of the base region.   The distance between the end of the contact region on the second surface side and the second surface of the first semiconductor layer is the lower end of the source region, the second surface of the first semiconductor layer, and The semiconductor device according to claim 2, wherein the distance is shorter than the distance between the two.   The semiconductor device according to claim 2, wherein the contact region penetrates the base region, and the lower end of the contact region is in contact with the first semiconductor layer.   5. The semiconductor device according to claim 2, wherein a part of a boundary between the first semiconductor layer and the field plate insulating film is located immediately below the contact region.   The second semiconductor layer of the second conductivity type is interposed between the first semiconductor layer and the first main electrode, according to any one of claims 1 to 5. Semiconductor device. A first semiconductor layer of a first conductivity type having a first surface and a second surface facing the first surface;
A first main electrode electrically connected to the first semiconductor layer on the second surface side of the first semiconductor layer;
A pair of conductive layers provided from the first surface to the inside of the first semiconductor layer;
A second main electrode electrically connected to the first semiconductor layer and the conductive layer on the first surface side of the first semiconductor layer;
A field plate electrode located in the second surface side of the first semiconductor layer relative to the conductive layer and provided in the first semiconductor layer via a field plate insulating film;
With
The pair of conductive layers sandwich the first semiconductor layer below the second main electrode,
In the first semiconductor layer, a region in which a width of the first semiconductor layer sandwiched between the pair of field plate insulating films is narrower than a width of the first semiconductor layer sandwiched between the pair of conductive layers. There is
In the direction in which the pair of conductive layers are arranged, the width of the field plate electrode and the width of the field plate insulating film provided on both sides of the field plate electrode and in contact with the region of the first semiconductor layer are combined. A semiconductor device characterized in that the width is wider than the width of the conductive layer. A third semiconductor layer of a second conductivity type is further provided on the first surface of the first semiconductor layer;
The semiconductor device according to claim 7, wherein the third semiconductor layer is connected to the conductive layer and the second main electrode.   9. The semiconductor device according to claim 7, wherein a fourth semiconductor layer of a second conductivity type is further provided between the first semiconductor layer and the second main electrode.   The semiconductor device according to claim 9, wherein an impurity concentration of the fourth semiconductor layer is lower than an impurity concentration of the third semiconductor layer.   A fifth semiconductor layer of the second conductivity type is further provided between the fourth semiconductor layer and the second main electrode, and the impurity concentration of the fifth semiconductor layer is the impurity concentration of the third semiconductor layer. The semiconductor device according to claim 9, wherein the semiconductor device is higher.   The semiconductor device according to claim 7, wherein the conductive layer and the field plate electrode are connected to each other.   The impurity concentration of the first semiconductor layer sandwiched between the pair of conductive layers is lower than the impurity concentration of the first semiconductor layer sandwiched between the pair of field plate insulating films. The semiconductor device according to any one of 7 to 12. Preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type formed on a surface thereof;
Selectively forming a pair of trenches having a first depth from the surface to the inside of the first semiconductor layer;
Forming a mask film on each inner surface of the pair of trenches and on the bottom surface of the trench;
Removing the mask film formed on the bottom surface of each of the pair of trenches to expose the first semiconductor layer on the bottom surface of the trench;
The first semiconductor layer exposed from the bottom surface of each of the pair of trenches is removed, and a pair of trenches having a second depth that is deeper than the first depth are formed from the surface of the first semiconductor layer to the inner portion. A process of forming over,
A surface of the first semiconductor layer exposed from the mask film is oxidized in each of the pair of trenches, and a field plate insulating film is formed on the surface of the first semiconductor layer exposed from the mask film. Forming a step;
Forming a field plate electrode in each of the pair of trenches via the field plate insulating film;
Removing the mask film;
Forming a gate insulating film on the inner surface of the trench and the field plate electrode in each of the pair of trenches;
Forming a gate electrode through the gate insulating film in each of the pair of trenches;
Forming a plurality of second conductivity type base regions on the surface of the first semiconductor layer;
Selectively forming a source region of a first conductivity type in contact with the gate insulating film on each surface of the base region;
Forming a first main electrode electrically connected to the first semiconductor layer and a second main electrode electrically connected to the source region and the contact region;
With
In the field plate insulating film, the surface of the first semiconductor layer is oxidized so that a portion where the thickness of the field plate insulating film is thicker than the thickness of the gate insulating film is formed,
In the direction in which each of the pair of trenches is arranged, the boundary between the portion of the field plate insulating film and the first semiconductor layer is not located under the source region, but is located under the base region,
The width of the first semiconductor layer sandwiched between the portions of the field plate insulating film provided in each of the pair of trenches is sandwiched between the gate insulating films provided in each of the pair of trenches. Narrower than the width of the base region,
The source region is located closer to the gate electrode than a position immediately above a boundary between the first semiconductor layer and the portion of the field plate insulating film; and the first semiconductor layer and the portion of the field plate insulating film; A method of manufacturing a semiconductor device, comprising: adjusting a width of the source region so that the source region is not formed immediately above the boundary. Preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type formed on a surface thereof;
Selectively forming a pair of trenches having a first depth from the surface to the inside of the first semiconductor layer;
Forming a mask film on each inner surface of the pair of trenches and on the bottom surface of the trench;
Removing the mask film formed on the bottom surface of each of the pair of trenches to expose the first semiconductor layer on the bottom surface of the trench;
The first semiconductor layer exposed from the bottom surface of each of the pair of trenches is removed, and a pair of trenches having a second depth that is deeper than the first depth are formed from the surface of the first semiconductor layer to the inner portion. A process of forming over,
A surface of the first semiconductor layer exposed from the mask film is oxidized in each of the pair of trenches, and a field plate insulating film is formed on the surface of the first semiconductor layer exposed from the mask film. Forming a step;
Forming a field plate electrode in each of the pair of trenches via the field plate insulating film;
Removing the mask film;
Forming an insulating film on each of the inner surface of the trench and the field plate electrode in each of the pair of trenches;
Forming a conductive layer through the insulating film in each of the pair of trenches;
Forming a second conductivity type semiconductor layer on the surface of the first semiconductor layer so as to be adjacent to the insulating film;
With
The conductive layers provided in the pair of trenches sandwich the first semiconductor layer below the second main electrode,
In the field plate insulating film, the surface of the first semiconductor layer is oxidized so that a portion where the thickness of the field plate insulating film is thicker than the thickness of the insulating film is formed,
In the direction in which each of the pair of trenches is arranged, the total width of the field plate electrode and the width of the portion of the field plate insulating film provided on both sides of the field plate electrode is the conductive layer. Wider than the combined width of the insulating film provided on both sides of the conductive layer,
The width of the first semiconductor layer sandwiched between the portions of the field plate insulating film provided in each of the pair of trenches is the sandwiched between the insulating films provided in each of the pair of trenches. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed to be narrower than a width of the first semiconductor layer.

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