JP2014220304A - Multilayer board and electronic device using the same - Google Patents

Abstract

In a multilayer substrate in which a buildup layer made of a prepreg is laminated on an outer surface of a core layer as an insulating layer, and a plurality of inner layer wirings provided on the outer surface are sealed with a resin of the buildup layer, the inner layer wiring Suppresses the generation of voids. A plurality of inner layer wirings 511, 512, 521, 522 provided on front and back surfaces 20a, 20b of a core layer 20 are composed of a first wiring group 511, 521 and a second wiring group 512 having different wiring intervals. 522, the wiring interval d2 of the second wiring group is narrower than the wiring interval d1 of the first wiring group, and the thickness of the inner layer wiring in the second wiring group t2 is smaller than the thickness t1 of the inner layer wiring in the first wiring group. [Selection] Figure 2

Description

  The present invention relates to a multilayer substrate in which a prepreg layer is laminated on an outer surface of an insulating layer, and a plurality of inner layer wirings provided on the outer surface are sealed with a resin of the prepreg layer, and an electronic device including such a multilayer substrate About.

  Conventional: As this type of multilayer substrate, for example, a build-up substrate described in Patent Document 1 has been proposed. This comprises an electrically insulating insulating layer made of a resin having a plurality of inner layer wirings on the outer surface, and a prepreg layer made of a prepreg laminated on the insulating layer so as to cover the outer surface of the insulating layer together with the inner layer wiring. . Here, the plurality of inner layer wirings are arranged at intervals on the outer surface of the insulating layer and protrude from the outer surface.

  Moreover, the prepreg which comprises a prepreg layer seals both surfaces of a glass cloth with resin. Then, by covering the outer surface of the insulating layer with the prepreg layer, the plurality of inner layer wirings are sealed on the outer surface of the insulating layer in a state where the resin of the prepreg layer is filled between the inner layer wirings. Here, in order to ensure the thermal conductivity of the substrate, the resin of the prepreg layer usually contains a filler made of a thermally conductive ceramic such as alumina or silica.

JP 2005-175115 A

  However, in order to improve the thermal conductivity of the multilayer substrate, it is necessary to use a prepreg with a high filler filling rate as the prepreg layer. However, when the filler filling rate increases, the fluidity of the resin of the prepreg layer decreases. Resulting in.

  Therefore, when the outer surface of the insulating layer is sealed with the resin of the prepreg layer, an unfilled portion of the resin, that is, a void is generated in a portion where the fluidity of the resin is likely to be low, such as between the inner layer wirings. Is more likely to do.

  In particular, when the wiring interval between adjacent inner layer wirings becomes narrow, voids are likely to occur. When a void occurs between the inner layer wirings, a short circuit between the inner layer wirings is likely to occur due to the voids, and an insulation failure is likely to occur.

  The present invention has been made in view of the above problems, and in a multilayer substrate in which a prepreg layer is laminated on an outer surface of an insulating layer, and a plurality of inner layer wirings provided on the outer surface are sealed with a resin of the prepreg layer. An object of the present invention is to suppress the generation of voids between inner layer wirings.

In order to achieve the above object, according to the first aspect of the present invention, there are provided a plurality of insulating layers (20) that are electrically insulative and a plurality of outer surfaces (20a, 20b) that are spaced apart from each other and that protrude from the outer surfaces. The inner layer wiring (511, 512, 521, 522) and the prepreg formed by sealing both surfaces of the glass cloth (1) with the resin (2), and the insulating layer so as to cover the outer surface of the insulating layer together with the plurality of inner layer wirings Prepreg layers (30, 40) laminated to each other, and on the outer surface of the insulating layer, the resin of the prepreg layer seals the plurality of inner layer wirings while being filled between the plurality of inner layer wirings,
The plurality of inner layer wirings are classified into a first wiring group (511, 521) and a second wiring group (512, 522) having different wiring intervals, and the wiring interval ( d2) is narrower than the wiring interval (d1) of the first wiring group, and the thickness (t2) of the inner layer wiring in the second wiring group is the thickness of the inner wiring in the first wiring group. A multilayer substrate characterized in that it is thinner than (t1) is provided.

  As the wiring interval of the inner layer wiring becomes narrower, the resin of the prepreg layer becomes harder to enter between the inner layer wirings. In this regard, according to the present invention, in the second wiring group having a narrow wiring interval, the inner layer wiring is thinner than the first wiring group, so that the resin easily enters between the inner layer wirings. . Therefore, according to the present invention, generation of voids between the inner layer wirings can be suppressed.

  Here, in the invention according to claim 2, in the multilayer substrate according to claim 1, the inner layer wiring in the first wiring group is a wiring for large current through which a larger current flows than the inner layer wiring in the second wiring group. In addition, the inner layer wiring in the second wiring group is a small current wiring in which a smaller current flows than the inner layer wiring in the first wiring group. According to this, it is possible to realize an appropriate use form of wiring according to the thickness of the inner layer wiring.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of an electronic device according to a first embodiment of the present invention. (A) is the enlarged view of the A section and B section in FIG. 1, (b) is the enlarged view of the C section and D section in FIG. It is sectional drawing which shows the manufacturing process of the multilayer substrate shown by FIG. FIG. 4 is a cross-sectional view illustrating a manufacturing process of the multilayer substrate following FIG. 3. FIG. 5 is a cross-sectional view showing the manufacturing process for the multilayer substrate following FIG. 4. It is sectional drawing which shows the detail of the formation process of the inner layer wiring among the manufacturing processes of the multilayer substrate shown by FIG. FIG. 7 is a cross-sectional view showing details of an inner-layer wiring formation process following FIG. 6. It is sectional drawing which shows the detail of the formation process of the inner layer wiring in the manufacturing process of the multilayer substrate concerning 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
An electronic apparatus according to a first embodiment of the present invention will be described with reference to FIGS. The electronic device of this embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle. In FIG. 2, the mold resin 150, the solder resist 110, etc. are partially omitted.

  As shown in FIG. 1, the electronic device includes a multilayer substrate 10 having one surface 10 a and another surface 10 b, and electronic components 121 to 123 mounted on one surface 10 a of the multilayer substrate 10. And the electronic device is comprised by sealing the one surface 10a side of the multilayer substrate 10 with the mold resin 150 with the electronic components 121-123.

  The multilayer substrate 10 includes a core layer 20, a buildup layer 30 on the front surface 20a side disposed on the front surface 20a of the core layer 20, and a buildup layer 40 on the back surface 20b side disposed on the back surface 20b side of the core layer 20. Is a laminated substrate. Here, the core layer 20 is configured as an electrically insulating layer, and the front surface 20a and the back surface 20b of the core layer 20 are configured as outer surfaces of the insulating layer.

  The buildup layers 30 and 40 are configured as prepreg layers made of prepreg. As shown in FIG. 2, this prepreg is formed by sealing both surfaces of a glass cloth 1 with a resin 2 such as an epoxy resin. The resin 2 has an electrically insulating and heat conducting material such as alumina or silica. The filler 3 which consists of a ceramic which has the property and was excellent in heat dissipation is contained.

  The core layer 20 may be made of an electrically insulating material. Although details of the core layer 20 are not shown here, the core layer 20 is also composed of a single-layer or multi-layer prepreg.

  At the interface between the core layer 20 and the buildup layer 30, a plurality of patterned surface-side inner layer wirings 511 and 512 are formed on the surface 20 a of the core layer 20. Similarly, at the interface between the core layer 20 and the buildup layer 40, a plurality of patterned back surface side inner layer wirings 521 and 522 are formed on the back surface 20 b of the core layer 20.

  As shown in FIGS. 1 and 2, each buildup layer 30, 40 is laminated on the core layer 20 so as to cover the outer surfaces 20 a, 20 b of the core layer 20 together with the plurality of inner layer wirings 511, 512, 521, 522. ing.

  Then, on the outer surfaces 20 a and 20 b of the core layer 20, the resin 2 of the buildup layers 30 and 40 is sealed between the plurality of inner layer wirings 511, 512, 521, 522, and the plurality of inner layer wirings are sealed. ing.

  The plurality of front side inner layer wirings 511 and 512 are classified into a first wiring group 511 and a second wiring group 512 having different wiring intervals. On the other hand, the plurality of back side inner layer wirings 521 and 522 are also classified into a first wiring group 521 and a second wiring group 522 having different wiring intervals. In FIG. 1 and FIG. 2, reference numerals 511 and 521 are assigned to the inner layer wirings on the front and back sides that belong to the first wiring group, and reference numerals 512 and 522 are assigned to those that belong to the second wiring group.

  Here, as shown in FIG. 2, the wiring interval d2 of the inner layer wirings 512 and 522 of the second wiring group is smaller than the wiring interval d1 of the inner layer wirings 511 and 521 of the first wiring group. Has been. The thickness t2 of the inner layer wirings 512 and 522 in the second wiring group is set to be smaller than the thickness t1 of the inner layer wirings 511 and 521 in the first wiring group.

  Specifically, the inner layer wirings 511 and 521 in the thicker first wiring group are wirings for large current through which a larger current flows than the inner layer wirings 512 and 522 in the thinner second wiring group. On the other hand, the inner layer wirings 512 and 522 in the second wiring group are small current wirings through which a smaller current flows than the inner layer wirings 511 and 521 in the first wiring group.

  The inner layer wirings 511, 512, 521, and 522 having different thicknesses are formed by a method of partially etching to form a thin one or a method of partially adding a plating to form a thick one. Can be formed. Details of these forming methods will be described later.

  Further, as shown in FIG. 1, patterned surface-side surface wirings 61 to 63 are formed on the surface 30 a of the buildup layer 30. In the present embodiment, the surface-side surface layer wirings 61 to 63 are bonded electrically connected to the mounting lands 61 on which the electronic components 121 to 123 are mounted and the electronic components 121 and 122 via the bonding wires 141 and 142. Land 62 for use, and a surface pattern 63 electrically connected to an external circuit.

  Similarly, patterned back surface side wirings 71 and 72 are formed on the front surface 40 a of the buildup layer 40. In this embodiment, the back surface layer wirings 71 and 72 are a back surface pattern 71 connected to the back surface inner layer wirings 521 and 522 through filled vias, which will be described later, and a heat sink pattern 72 provided with a heat sink for heat dissipation. .

  Note that the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10. Further, the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10.

  The front and back inner layer wirings 511, 512, 521, and 522, the front side surface layer wirings 61 to 63, and the back side surface layer wirings 71 and 72 are specifically described later, but a metal foil such as copper or metal plating is appropriately laminated. Has been configured.

  Further, the front side inner layer wirings 511 and 512 and the rear side inner layer wirings 521 and 521 are electrically and thermally connected through a through via 81 provided through the core layer 20. Specifically, the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.

  Further, the front-side inner layer wirings 511 and 512 and the front-side surface layer wirings 61 to 63, and the rear-side inner layer wirings 521 and 522 and the rear-side surface wirings 71 and 72 are appropriately arranged in the thickness direction. They are electrically and thermally connected through filled vias 91 and 101 provided therethrough.

  Specifically, the filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper.

  In addition, although resin, ceramic, metal, etc. are used for the filler 81c, in this embodiment, it is set as the epoxy resin. The through electrodes 81b, 91b, and 101b are made of metal plating such as copper.

  And the solder resist 110 which covers the surface pattern 63 and the back surface pattern 71 is formed in the surface 30a, 40a of each buildup layer 30,40. The solder resist 110 that covers the surface pattern 63 is formed with an opening that exposes a portion of the surface pattern 63 that is connected to an external circuit in a cross section different from that in FIG.

  The electronic components 121 to 123 include a power element 121 such as an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, and a passive such as a chip capacitor. Element 123.

  Each electronic component 121 to 123 is mounted on the land 61 via the solder 130 and is electrically and mechanically connected to the land 61. The power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as Al and Au.

  Here, the first wiring groups 511 and 521 described above are the front and back inner layer wirings 511 and 521 connected to the power element 121 having a relatively large current, while the second wiring groups 512 and 522 described above. These are front and back inner layer wirings 512 and 522 connected to the control element 122 and the passive element 123 having a relatively small current.

  In addition, although the power element 121, the control element 122, and the passive element 123 were mentioned as an example and demonstrated here as the electronic components 121-123, the electronic components 121-123 are not limited to these.

  The mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.

  In the present embodiment, the mold resin 150 is formed only on the one surface 10 a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the heat sink pattern 72 via heat radiation grease or the like.

  The above is the configuration of the electronic device in this embodiment. Next, a method for manufacturing the electronic device will be described with reference to FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 on which the power element 121 is mounted. Further, the steps shown in FIGS. 6 and 7 are shown in the cross section of the part corresponding to FIG. 2A, but the glass cloth 1 and the filler 3 inside the build-up layer 30 are omitted. And simplified.

  First, as shown in FIG. 3A, one in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.

  Thereafter, as shown in FIG. 3C, electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81 a and the metal foils 161 and 162. As a result, a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a. In addition, when performing electroless plating and electroplating, it is preferable to carry out using catalysts, such as palladium.

  Subsequently, as illustrated in FIG. 3D, a filler 81 c is disposed in a space surrounded by the metal plating 163. Thus, the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.

  Thereafter, as shown in FIG. 4A, so-called lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.

  Thus, as shown in FIG. 4A, the metal layer M1 in which the metal foil 161, the metal plating 163, and the metal plating 164 are sequentially laminated is formed on the front surface 20a side of the core layer 20, and on the back surface 20b side, A metal layer M2 in which a metal foil 162, a metal plating 163, and a metal plating 165 are sequentially laminated is formed.

  Next, as shown in FIG. 4B, a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the surface side inner layer wirings 511 and 512, and the metal plating 165, the metal plating 163, and the metal The foil 162 is appropriately patterned to form back side inner layer wirings 521 and 522.

  That is, in the present embodiment, the front side inner layer wirings 511 and 512 are constituted by the metal layer 161 in which the metal foil 161, the metal plating 163, and the metal plating 164 are laminated, and the back side inner layer wirings 521 and 522 are formed by the metal foil 162. , And a metal layer M2 in which a metal plating 163 and a metal plating 165 are laminated.

  Here, in this embodiment, as shown in FIGS. 6 and 7, the difference in the wiring thicknesses t1 and t2 in the inner layer wirings 511, 512, 521 and 522 is realized by performing etching twice. doing. Details of the inner-layer wiring forming process shown in FIGS. 6 and 7 will be described.

  6 and 7 show a process of forming the front-side inner layer wirings 511 and 512 from the metal layer M1 on the front surface 20a side of the core layer 20, this forming process is performed on the back surface 20b side of the core layer 20. This is also performed on the metal layer M2 at the same time to form the back side inner layer wirings 521 and 522.

  Here, in FIG. 6, FIG. 7 and FIG. 4 (c) and thereafter, the metal foil 161, the metal plating 163, the metal plating 164, and the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer. .

  The state shown in FIG. 6A is the same as the state shown in FIG. 4A, and the metal layer M1 is formed on the surface 20a of the core layer 20. The metal layer M1 is formed to a thickness t1 of the thick first wiring group 511.

  Then, as shown in FIG. 6B, a resist R1 is disposed on the metal layer M1 and etching is performed, thereby patterning the metal layer M1 to form a surface as shown in FIG. 6C. A pattern of the side inner layer wirings 511 and 512 is used.

  Next, as shown in FIG. 6D, in the patterned metal layer M <b> 1, the resist R <b> 1 is left in the portion to be the first wiring group 511, and the resist is left in the portion to be the second wiring group 512. Remove R1. Then, as shown in FIG. 7A, the second etching is performed to form a thick first wiring group 511 having a thickness t1 and a thin second wiring group 512 having a thickness t2.

  Thereafter, as shown in FIG. 7B, all the resists R1 are removed. Thus, the inner wirings 511, 512, 521, and 522 having different thicknesses t1 and t2 are formed on the front surface 20a side and the back surface 20b side of the core layer 20, respectively.

  Thereafter, as shown in FIG. 4C, the build-up layer 30 and a metal plate 166 such as copper are laminated on the surface-side inner layer wirings 511 and 512 on the surface 20 a side in the core layer 20. Further, on the back surface 20 b side of the core layer 20, the buildup layer 40 and a metal plate 167 such as copper are laminated on the back surface inner layer wirings 521 and 522.

  In this way, the metal plate 166, the buildup layer 30, the front surface inner layer wirings 511 and 512, the core layer 20, the back surface inner layer wirings 521 and 522, the buildup layer 30 and the metal plate 167 are sequentially stacked from the top. The laminated body 168 is configured. In this state, the build-up layers 30 and 40 are temporarily cured and have fluidity.

  Subsequently, as illustrated in FIG. 4D, the stacked body 168 is integrated by heating while pressing from the stacking direction of the stacked body 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the surface side inner layer wirings 511 and 512, and the resin constituting the buildup layer 40 is caused to flow. Then, the space between the back side inner layer wirings 521 and 522 is embedded. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.

  Next, as shown in FIG. 5A, a through hole 91 a that penetrates the metal plate 166 and the buildup layer 30 and reaches the front-side inner layer wirings 511 and 512 is formed by a laser or the like. Similarly, in a cross section different from that shown in FIG. 5A, a through hole 101a that penetrates through the metal plate 167 and the buildup layer 40 and reaches the back surface side inner layer wirings 521 and 522 is formed.

  Then, as shown in FIG. 5B, so-called filled plating is performed by electroless plating, electroplating, or the like, and the through holes 91 a and 101 a are embedded with metal plating 169. Thus, the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layer 30. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed. In FIG. 5C and subsequent figures, the metal plate 166 and the metal plating 169 are collectively shown as one layer.

  Subsequently, as shown in FIG. 5C, a resist (not shown) is disposed on the metal plates 166 and 167. Then, the metal plates 166 and 167 are patterned by performing wet etching or the like using a resist as a mask, and the surface side surface layer wirings 61 to 63 and the back side surface layer wirings 71 and 72 are formed by appropriately forming metal plating.

  That is, in the present embodiment, the front surface side wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the back surface side wirings 71 and 72 are configured to have the metal plate 167 and the metal plating 169. ing.

  Next, as shown in FIG. 5 (d), the multilayer substrate 10 is manufactured by arranging the solder resist 110 on the surfaces 30 a and 40 a of the build-up layers 30 and 40 and patterning them appropriately. Note that, within the range shown in FIG. 5D, all the solder resist 110 on the surface 30a is removed, but the solder resist 110 remains in other regions as shown in FIG. Yes.

  Thereafter, although not particularly shown, the electronic components 121 to 123 are mounted on the land 61 via the solder 130. At this time, in this embodiment, since the land 61 has the solder wettability of the side surface 61c lower than the solder wettability of the one surface 61a, the solder 130 can be prevented from spreading to the side surface.

  Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected. Subsequently, the mold resin 150 is formed by a transfer molding method using a mold, a compression molding method, or the like so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. Thereby, the electronic device in which the mold resin 150 is in close contact with the side surface 61c of the land 61 is manufactured.

  As described above, in the present embodiment, the thickness t2 of the wiring is set to the first wiring group in the second wiring group 512, 522 having the narrow wiring interval d2 among the inner layer wirings 511, 512, 521, 522 on the front and back sides. The wirings 511 and 521 are thinner than the thickness t1.

  Therefore, even if the inner layer wirings 512 and 522 have a narrow wiring interval, the resin 2 of the buildup layers 30 and 40 easily enters between the inner layer wirings. Therefore, according to this embodiment, generation | occurrence | production of the void between inner layer wiring can be suppressed.

  In addition, according to the present embodiment, the inner layer wirings 511 and 521 in the relatively thick first wiring group are used as high current wirings, and the inner layer wirings 512 and 522 in the relatively thin second wiring group are used as small current wirings. Wiring is used. Therefore, it is possible to realize an appropriate usage pattern of the inner layer wiring according to the thickness of the wiring.

(Second Embodiment)
A process of forming the inner layer wirings 511, 512, 521, and 522 according to the second embodiment of the present invention will be described with reference to FIG.

  In the present embodiment, the difference in the thicknesses t1 and t2 due to the difference in the wiring intervals d1 and d2 in the inner layer wiring is realized by a method different from that in FIGS. 6 and 7, and this point will be described. To do.

  The state shown in FIG. 8A is the same as the state shown in FIG. 4A, and the metal layer M1 is formed on the surface 20a of the core layer 20. Here, the metal layer M1 is formed to a thickness t2 of the thin second wiring group 512.

  Then, as shown in FIG. 8B, a resist R1 is disposed on the metal layer M1 and etching is performed, whereby the metal layer M1 is patterned to form a surface as shown in FIG. 8C. A pattern of the side inner layer wirings 511 and 512 is used.

  Next, as shown in FIG. 8D, all the resists R1 on the metal layer M1 are removed. Then, as shown in FIG. 8E, a resist R1 is disposed on a portion that becomes the second wiring group 512 in the patterned metal layer M1, and a metal is formed on the portion that becomes the first wiring group 511. Perform plating.

  Thus, a thick first wiring group 511 having a thickness t1 and a thin second wiring group 512 having a thickness t2 are formed. Thereafter, all the resist R1 is removed. Thus, the inner wirings 511, 512, 521, and 522 having different thicknesses t1 and t2 are formed on the front surface 20a side and the back surface 20b side of the core layer 20, respectively.

  Thereafter, in the same manner as in the first embodiment, the electronic device shown in FIG. 1 is manufactured also in this embodiment by performing the manufacturing process after FIG. 4C.

(Other embodiments)
In each of the above embodiments, the core layer 20 is an insulating layer referred to in the present invention, and the front and back build-up layers 30 and 40 are prepreg layers referred to in the present invention. Here, as the multilayer substrate 10, a plurality of build-up layers 30 and 40 on the front and back sides of the core layer 20 may be laminated.

  In this case, of the two build-up layers to be stacked, the one having the inner layer wiring located on the core layer 20 side is used as the insulating layer, and the inner layer wiring is covered outside the multilayer substrate 10. It may be applied as a prepreg layer.

  The multilayer substrate includes an electrically insulating insulating layer having a plurality of inner layer wirings on the outer surface, and a prepreg layer laminated on the insulating layer so as to cover the outer surface of the insulating layer together with the plurality of inner layer wirings. If there is, it is not limited to the multilayer substrate 10 which consists of the core layer 20 and the buildup layers 30 and 40 of the said embodiment. For example, the insulating layer may be a layer made of ceramic or the like.

  Further, the resin 2 of the prepreg layers 30 and 40 may not contain the filler 3. However, as in the above-described embodiment, the resin 2 containing the filler 3 for improving heat dissipation tends to be less fluid than the resin 2 not containing, so that the effect of the above-described embodiment is effectively exhibited. The

  Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible, and the above embodiments are not limited to the illustrated examples. Absent.

DESCRIPTION OF SYMBOLS 1 Glass cloth 2 Resin 10 Multilayer board | substrate 20 Core layer 20a as an insulating layer The surface of the core layer as an outer surface of an insulating layer 20b The back surface of the core layer as an outer surface of an insulating layer 30 Build-up layer as a prepreg layer 40 As a prepreg layer Build-up layer 511 Front side inner layer wiring as first wiring group 512 Front side inner layer wiring as second wiring group 521 Back side inner layer wiring as first wiring group 522 Back side inner layer as second wiring group Wiring d1 Wiring interval of the first wiring group d2 Wiring interval of the second wiring group t1 Thickness of the inner layer wiring as the first wiring group t2 Thickness of the inner layer wiring as the second wiring group

Claims (4)

An electrically insulating insulating layer (20);
A plurality of inner layer wirings (511, 512, 521, 522) that are arranged at intervals on the outer surfaces (20a, 20b) of the insulating layer and project from the outer surface;
A prepreg layer (30, 30) comprising a prepreg formed by sealing both surfaces of a glass cloth (1) with a resin (2) and laminated on a pre-grease insulating layer so as to cover the outer surface of the insulating layer together with the plurality of inner layer wirings. 40), and
On the outer surface of the insulating layer, the resin of the prepreg layer seals the plurality of inner layer wirings in a state of being filled between the plurality of inner layer wirings,
The plurality of inner layer wirings are classified into a first wiring group (511, 521) and a second wiring group (512, 522) having different wiring intervals, and the second wiring group includes the first wiring group (511, 521). The wiring interval (d2) is narrower than the wiring interval (d1) of the first wiring group,
The multilayer substrate according to claim 1, wherein a thickness (t2) of the inner layer wiring in the second wiring group is thinner than a thickness (t1) of the inner layer wiring in the first wiring group. The inner layer wiring in the first wiring group is a large current wiring through which a larger current flows than the inner layer wiring in the second wiring group,
2. The multilayer substrate according to claim 1, wherein the inner layer wiring in the second wiring group is a small current wiring through which a smaller current flows than the inner layer wiring in the first wiring group.   The multilayer substrate according to claim 1 or 2, wherein the resin of the prepreg layer contains a filler (3) made of ceramic having electrical insulation and thermal conductivity. A multilayer substrate (10) according to any one of claims 1 or 2;
Electronic components (121 to 123) mounted on the outer surface side of the prepreg layer;
An electronic device comprising: a mold resin (150) for sealing the electronic component on the outer surface side of the prepreg layer.

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