JP2014212210A - Lead frame and manufacturing method of the same, and semiconductor device and manufacturing method of the same - Google Patents

Abstract

Provided is a lead frame capable of suppressing a decrease in strength of a lead portion and preventing the lead portion from being deformed even when the width of the lead portion is narrowed. A lead frame 10 includes a die pad 11 and a plurality of lead portions 12A and 12B including an internal terminal 15 and external terminals 17A and 17B. The external terminals 17A and 17B of the plurality of lead portions 12A and 12B are provided. These are alternately arranged in a staggered manner so as to be located on the inner side and the outer side between the adjacent lead portions 12A and 12B. The lead portion 12A has an inner region 51 located inside the first external terminal 17A, an outer region 52 located outside the first external terminal 17A, and an external terminal region 53 having the first external terminal 17A. ing. The inner region 51 and the outer region 52 are formed thin by half etching, respectively, and the maximum thickness of the outer region 52 is larger than the maximum thickness of the inner region 51. [Selection] Figure 2

Description

  The present invention relates to a lead frame and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.

  In recent years, it has been required to reduce the size and thickness of a semiconductor device mounted on a substrate. In order to meet such demands, conventionally, a lead frame is used, and a semiconductor element mounted on the mounting surface of the lead frame is sealed with a sealing resin, and a part of the lead is exposed on the back surface side. Various so-called QFN (Quad Flat Non-lead) type semiconductor devices have been proposed.

  With the spread of QFN, power supply ICs and analog ICs, which are general-purpose packages, are mounted on many electronic devices. In recent years, the demand for a multi-pin QFN package has increased, and the development of 100-pin to 200-pin type packages used for high-function power supplies, microcomputers, and communication / wireless basebands has been promoted. Yes.

  However, in the case of a QFN having a conventional general structure, the package becomes larger as the number of terminals increases, so that there is a problem that it is difficult to ensure mounting reliability. In addition, the increase in the size of the package increases the distance between the internal terminals and the semiconductor chip, increases the amount of gold bonding wires used, and increases the manufacturing cost of the package. Further, since the bonding wire becomes long, there is a possibility that a problem may occur when the package is assembled.

Japanese Patent No. 3732987 JP 2001-189402 A JP 2006-19767 A

  On the other hand, as a technique for realizing a multi-pin QFN, a package called DR-QFN (Dual Row QFN) in which external terminals are arranged in two rows is being developed (Patent Document 1). ~ 3). Such a DR-QFN is provided with a half-etched lead portion to support the inner terminal. However, in such a DR-QFN, since the number of lead portions increases due to the increase in the number of pins, the width of the lead portions must be designed to be narrow. For this reason, the strength of the lead part that has been half-etched is insufficient, the lead part is deformed, and the external terminal is displaced. As a result, the yield of the lead frame may be reduced.

  The present invention has been made in consideration of such points, and even when the width of the lead portion is narrowed, the strength of the lead portion is suppressed from being reduced, and deformation of the lead portion is prevented. An object of the present invention is to provide a lead frame and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.

  The present invention provides a lead frame including a die pad on which a semiconductor element is mounted and a plurality of lead portions provided around the die pad, each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are adjacent to each other. Arranged alternately in a staggered manner between the matching lead parts inside and outside, among the multiple lead parts, the lead part with the external terminal inside is located inside the external terminal and has the internal terminal A region, an outer region located outside the external terminal, and an external terminal region having an external terminal formed on the back surface, and at least the inner region and the outer region of the lead portion having the external terminal on the inside are half-etched, respectively. The lead frame is characterized in that the maximum thickness of the outer area of the lead portion is thicker than the maximum thickness of the inner area of the lead portion. That.

  The present invention is the lead frame characterized in that the inner region of the lead portion has a flat back surface and has a substantially rectangular shape in a cross section orthogonal to the longitudinal direction of the lead portion.

  The present invention is the lead frame characterized in that the outer region of the lead part has a convex part protruding downward in a cross section perpendicular to the longitudinal direction of the lead part.

  The present invention is the lead frame characterized in that the outer region of the lead part has a substantially pentagonal shape in a cross section perpendicular to the longitudinal direction of the lead part.

  The present invention is the semiconductor device characterized in that the external terminal of the lead portion is wider than the surface of the external terminal region.

  In a semiconductor device, the present invention provides a die pad, a plurality of lead portions provided around the die pad, each including an internal terminal and an external terminal, a semiconductor element mounted on the die pad, and an internal terminal of the semiconductor element and the lead portion And a bonding resin for sealing the bonding wire, a die pad, a lead portion, a semiconductor element, and a sealing resin for sealing the bonding wire. In a plurality of lead portions, the lead portion having the external terminal on the inner side is positioned inside the external terminal and has the inner terminal and the external portion. An inner region of the lead portion having an outer region located outside the terminal and an outer terminal region having an outer terminal formed on the back surface and having at least the outer terminal on the inner side And the outer region is formed on the thin by the respective half-etching, the maximum thickness of the outer region of the lead portion is a semiconductor device, characterized in that greater than the maximum thickness of the inner region of the lead portion.

  The present invention is the semiconductor device characterized in that the inner region of the lead portion has a flat back surface and has a substantially rectangular shape in a cross section orthogonal to the longitudinal direction of the lead portion.

  The present invention is the semiconductor device characterized in that the outer region of the lead part has a convex part protruding downward in a cross section orthogonal to the longitudinal direction of the lead part.

  The present invention is the semiconductor device characterized in that the outer region of the lead portion has a substantially pentagonal shape in a cross section perpendicular to the longitudinal direction of the lead portion.

  The present invention is the semiconductor device characterized in that the external terminal of the lead portion is wider than the surface of the external terminal region.

  The present invention comprises a die pad on which a semiconductor element is mounted, and a plurality of lead portions provided around the die pad, each including an internal terminal and an external terminal, and the external terminals of the plurality of lead portions are between adjacent lead portions. In a plurality of lead portions, the lead portion having the external terminal on the inner side is positioned inside the external terminal and has the inner terminal and the external portion. In a lead frame manufacturing method having an outer region located outside a terminal and an external terminal region having an external terminal formed on a back surface, a step of preparing a metal substrate and etching the metal substrate Forming a die pad and a lead portion on the substrate, and forming at least an external terminal inside when forming the die pad and the lead portion on the metal substrate. The inner region and the outer region of the lead portion are formed thin by half etching, respectively, and the inner region of the lead portion has a substantially rectangular shape having a flat back surface in a cross section perpendicular to the longitudinal direction of the lead portion, The lead frame manufacturing method is characterized in that the maximum thickness of the outer region of the lead part is larger than the maximum thickness of the inner region of the lead part.

  The present invention relates to a method of manufacturing a semiconductor device, a step of manufacturing a lead frame by a method of manufacturing a lead frame, a step of mounting a semiconductor element on a die pad of the lead frame, and bonding the semiconductor element and an internal terminal of a lead portion. A method for manufacturing a semiconductor device, comprising: a step of electrically connecting with a wire; a step of sealing a die pad, a lead portion, a semiconductor element, and a bonding wire with a sealing resin.

  According to the present invention, since the maximum thickness of the outer region of the lead part is formed to be thicker than the maximum thickness of the inner region of the lead part, the strength of the lead part is increased even when the width of the lead part is narrowed. It is possible to suppress the decrease and prevent the external terminal from being deformed.

FIG. 1 is a plan view showing a lead frame according to an embodiment of the present invention. FIG. 2 is a cross-sectional view (a cross-sectional view taken along the line II-II in FIG. 1) showing a lead frame according to an embodiment of the present invention. 3A to 3C are cross-sectional views of a lead portion having a first external terminal (cross-sectional view taken along line IIIA-IIIA, cross-sectional view taken along line IIIB-IIIB, and cross-sectional view taken along line IIIC-IIIC in FIG. 2, respectively). FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a sectional view showing a semiconductor device according to an embodiment of the present invention (a sectional view taken along line VV in FIG. 4). 6A to 6E are cross-sectional views showing a method for manufacturing a lead frame according to an embodiment of the present invention. 7A to 7B are cross-sectional views showing the inner region of the lead portion in the lead frame manufacturing process (cross-sectional views taken along the line VIIA-VIIA in FIG. 6C, respectively, and VIIB- in FIG. 6D). VIIB line cross section). 8A and 8B are cross-sectional views showing the outer region of the lead portion in the lead frame manufacturing process (cross-sectional views taken along line VIIIA-VIIIA in FIG. 6C, respectively, and VIIIB- in FIG. 6D). VIIIB line sectional view). 9A to 9E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

Construction of the lead frame initially, to FIG. 1 to FIG. 3, the outline of the lead frame according to the present embodiment. 1 to 3 are views showing a lead frame according to the present embodiment.

  As shown in FIGS. 1 and 2, the lead frame 10 is provided with a planar rectangular die pad 11 on which a semiconductor element 21 (described later) is mounted, the periphery of the die pad 11, and the semiconductor element 21 and an external circuit (not shown). Are provided with a plurality of elongated lead portions 12A and 12B.

  Of these, an outer frame 13 that supports the die pad 11 and the lead portions 12A and 12B is provided around the lead portions 12A and 12B. Further, suspension leads 14 are coupled to the four corners of the die pad 11, and the die pad 11 is coupled and supported to the outer frame 13 via the four suspension leads 14.

  Adjacent lead portions 12A, 12B are shaped to be electrically insulated from each other after manufacturing of a semiconductor device 20 (described later). Each lead portion 12A, 12B is shaped to be electrically insulated from the die pad 11 after the semiconductor device 20 is manufactured. Further, the back surfaces of the lead portions 12 </ b> A and 12 </ b> B are exposed outward from the semiconductor device 20. External terminals 17A and 17B (outer lead portions) that are electrically connected to external mounting boards (not shown) are formed on the back surfaces of the lead portions 12A and 12B, respectively.

  In this case, the external terminals 17A and 17B of the plurality of lead portions 12A and 12B are alternately arranged in a staggered manner so as to be located inside and outside between the adjacent lead portions 12A and 12B. That is, around the die pad 11, the lead portion 12A in which the external terminal 17A is located relatively inside (on the die pad 11 side), and the lead portion 12B in which the external terminal 17B is located relatively outside (on the outer frame 13 side). Are alternately arranged over the entire circumference. In the present specification, the external terminal 17A located inside is also referred to as a first external terminal 17A, and the external terminal 17B located outside is also referred to as a second external terminal 17B.

  As shown in FIG. 1, the plurality of first external terminals 17 </ b> A are all arranged along a straight line parallel to one side of the die pad 11 when viewed from the plane. Further, the plurality of second external terminals 17B are all arranged on a straight line parallel to one side of the die pad 11 when viewed from above. However, the present invention is not limited to this. For example, the plurality of first external terminals 17A and / or the plurality of second external terminals 17B may be arranged on an arc as viewed from the plane.

  Of the plurality of lead portions 12A and 12B, the lead portion 12A having the first external terminal 17A has an inner region 51, an outer region 52, and an external terminal region 53. Of these, the inner region 51 is located on the inner side (on the die pad 11 side) than the first external terminal 17A, and the inner terminal 15 (inner lead portion) is formed on the inner end surface thereof. The internal terminal 15 is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22 as will be described later. The outer region 52 is located on the outer side (outer frame 13 side) than the first external terminal 17 </ b> A, and the outer end portion thereof is connected to the outer frame 13. Further, a first external terminal 17 </ b> A is formed on the back surface of the external terminal region 53.

  In this case, each of the inner region 51 and the outer region 52 of the lead portion 12A is formed thin by half etching. On the other hand, the external terminal region 53 has the same thickness as the die pad 11 and the outer frame 13 without being half-etched. Half-etching means that the material to be etched is etched halfway in the thickness direction.

  On the other hand, among the plurality of lead portions 12A and 12B, the lead portion 12B having the second external terminal 17B has an inner region 61, an outer region 62, and an external terminal region 63. Among these, the inner region 61 is located on the inner side (on the die pad 11 side) than the second external terminal 17B, and the inner terminal 15 (inner lead portion) is formed on the inner end surface thereof. In addition, the outer region 62 is located on the outer side (outer frame 13 side) than the second external terminal 17B, and the outer end portion thereof is connected to the outer frame 13. Furthermore, a second external terminal 17 </ b> B is formed on the back surface of the external terminal region 63.

  In this case, the inner region 61 and the outer region 62 of the lead portion 12B are each formed thin by half etching. On the other hand, the external terminal region 63 has the same thickness as the die pad 11 and the outer frame 13 without being half-etched.

  Next, with reference to FIGS. 3A to 3C, the cross-sectional shape of the lead portion 12A having the first external terminal 17A among the plurality of lead portions 12A and 12B will be described. FIGS. 3A to 3C are views each showing a cross-sectional shape orthogonal to the longitudinal direction of the lead portion 12A. 3A is a cross-sectional view of the lead portion 12A in the inner region 51 (a cross-sectional view taken along the line IIIA-IIIA in FIG. 2), and FIG. 3B is a cross-sectional view of the lead portion 12A in the external terminal region 53. FIG. 3C is a cross-sectional view of the lead portion 12A in the outer region 52 (a cross-sectional view of the IIIC-IIIC line of FIG. 2).

  As shown in FIG. 3A, the inner region 51 of the lead portion 12A has a front surface 51a having an internal terminal 15, a flat back surface 51b formed by half etching, and a pair of side surfaces 51c. . The inner region 51 has a substantially square (substantially trapezoidal) cross section. Here, the substantially quadrangular shape (substantially trapezoidal shape) is not limited to a square shape (trapezoidal shape) in a strict sense, and a pair of side surfaces 51c are curved toward the inner side in the width direction as shown in FIG. Is also included.

  As described above, since the inner region 51 of the lead portion 12A has the flat back surface 51b, the back surface 51b of the inner region 51 can be stably placed on the heat block 36 as described later in the wire bonding step. Can do. As a result, the bonding wire 22 can be stably connected to the internal terminal 15, and the reliability of the wire bonding operation can be improved.

The thickness _{t a} of the inner region 51 is preferably 10% to 50% of the thickness _{t b} of the external terminal region 53 (Figure 3 (b)). Here, the thickness t _a of the inner region 51, refers to the maximum thickness in a cross section of the inner region 51.

  As shown in FIG. 3B, the external terminal region 53 of the lead portion 12A includes a front surface 53a, a first external terminal 17A formed on the back surface, and a pair of side surfaces 53c partially curved inward. have.

In this case, the width w _b2 of the first external terminal 17A (the back surface of the external terminal region 53) is wider than the width w _b1 of the surface of the external terminal region 53. Thereby, even when the interval between the lead portion 12A and the lead portion 12B adjacent to each other is narrowed, the area of the first external terminal 17A can be secured widely, and the first external terminal 17A and the external mounting board can be secured. (Not shown) can be securely connected.

  As shown in FIG. 3C, the outer region 52 of the lead portion 12A has a front surface 52a, a back surface 52b on which a convex portion 52d protruding downward by half etching is formed, and a pair of side surfaces 52c. doing. The outer region 52 has a substantially pentagonal cross section. Here, the substantially pentagonal shape is not limited to the pentagonal shape in a strict sense, but includes a case where the pair of side surfaces 52c are partially curved inward in the width direction as shown in FIG.

  In this case, in the cross section of the outer region 52, one convex portion 52d is formed at a substantially central portion in the width direction of the outer region 52 (lateral direction in FIG. 3C). However, the present invention is not limited to this. For example, the plurality of convex portions 52d may be formed in the width direction of the outer region 52 by half etching.

  Thus, by making the cross section of the outer region 52 of the lead portion 12A substantially pentagonal, the sectional moment of the outer region 52 is increased, and the strength of the outer region 52 that is the root portion of the lead portion 12A is increased. be able to. Thereby, when manufacturing the semiconductor device 20 (described later), it is possible to prevent the lead portion 12A from being deformed, and to prevent a problem that the position of the first external terminal 17A is shifted or the wire bonding operation becomes difficult. it can.

Further, the thickness t _c of the outer region 52 is thicker than the thickness t _a (FIG. 3A) of the inner region 51 (t _c > t _a ). The thickness t _c of the outer region 52 may be, for example, 50% to 90% of the thickness t _b (FIG. 3B) of the external terminal region 53. Here, the thickness t _c of the outer region 52 refers to the maximum thickness in the cross section of the outer region 52 (in this case, the thickness measured at the portion where the convex portion 52d is provided).

Thus, by that the thickness t _c of the outer region 52 of the lead portion 12A thicker than t _a of the inner region 51, can be difficult to deform the outer region 52 is a base portion of the lead portion 12A. As a result, when manufacturing the semiconductor device 20 (described later), the lead portion 12A is prevented from being deformed, and the first external terminal 17A is prevented from being displaced and the wire bonding operation becomes difficult. be able to.

  By the way, the cross-sectional shapes of the inner region 61 and the external terminal region 63 of the lead portion 12B having the second external terminal 17B are substantially the same as the cross-sectional shapes of the inner region 51 and the external terminal region 53 of the lead portion 12A described above, respectively. On the other hand, the cross-sectional shape of the outer region 62 of the lead portion 12B differs from the cross-sectional shape of the outer region 52 of the lead portion 12A, and is substantially rectangular (a shape similar to the inner region 51 shown in FIG. 3A). Yes. This is because the length of the outer region 62 of the lead portion 12B is relatively shorter than the length of the outer region 52 of the lead portion 12A, and therefore the possibility that the outer region 62 is deformed is relatively small. However, the present invention is not limited to this, and the outer region 62 of the lead portion 12B may have a substantially pentagonal cross section, similar to the outer region 52 of the lead portion 12A.

  The lead frame 10 described above is made of a metal such as copper, copper alloy, 42 alloy (Ni 42% Fe alloy) as a whole. The lead frame 10 can have a thickness of 0.10 mm to 0.30 mm, although it depends on the configuration of the semiconductor device 20 to be manufactured.

  In FIG. 1, only one die pad 11 is shown for convenience, but in actuality, a single lead frame 10 is manufactured with a plurality of die pads 11 attached thereto. In FIG. 1, a region S (virtual line) indicates a region corresponding to one semiconductor device 20 in the lead frame 10.

  In FIG. 1, a total of 36 lead portions 12A and 12B are provided. However, the present invention is not limited to this, and the total number of the lead portions 12A and 12B may be, for example, 80 to 200. Further, the pitch between the lead portions 12A and 12B adjacent to each other may be 0.15 mm to 0.40 mm. Further, in FIG. 1, the lead portions 12A and 12B are arranged along the four sides of the die pad 11, but the present invention is not limited to this. For example, the lead portions 12A and 12B are arranged along only two opposite sides of the die pad 11. May be.

Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 and 5 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.

  As shown in FIGS. 4 and 5, the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of lead portions 12 </ b> A and 12 </ b> B disposed around the die pad 11, and a semiconductor element 21 mounted on the die pad 11. And a plurality of bonding wires (connection portions) 22 for electrically connecting the lead portions 12A and 12B and the semiconductor element 21. The die pad 11, the lead portions 12 </ b> A and 12 </ b> B, the semiconductor element 21 and the bonding wire 22 are resin-sealed with a sealing resin 23.

  Among these, the die pad 11 and the lead portions 12A and 12B are manufactured from the lead frame 10 described above. The configurations of the die pad 11 and the lead portions 12A and 12B are the same as those shown in FIGS. 1 to 3 described above, and detailed description thereof is omitted here.

  Further, as the semiconductor element 21, various semiconductor elements generally used in the past can be used, and are not particularly limited. For example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like is used. it can. The semiconductor element 21 has a plurality of terminal portions 21a to which bonding wires 22 are attached. The semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.

  Each bonding wire 22 is made of a material having good conductivity such as gold. Each bonding wire 22 has one end connected to the terminal portion 21a of the semiconductor element 21 and the other end connected to the internal terminal 15 of each lead portion 12A, 12B. The internal terminal 15 is provided with a plating portion 25 that improves the adhesion with the bonding wire 22.

  As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used. The total thickness of the sealing resin 23 can be about 500 μm to 1000 μm. In FIG. 4, the display of the sealing resin 23 located on the surface side of the die pad 11 and the lead portions 12A and 12B is omitted.

Manufacturing Method of Lead Frame Next, regarding the manufacturing method of the lead frame 10 shown in FIGS. 1 to 3, FIGS. 6 (a)-(e), FIGS. 7 (a)-(b), and FIG. 8 (a)- A description will be given using (b). 6A to 6E are cross-sectional views (corresponding to FIG. 2) showing the manufacturing method of the lead frame 10. FIG. FIGS. 7A and 7B are cross-sectional views in the inner region 51 of the lead portion 12A, respectively, taken along the line VIIA-VIIA in FIG. 6C and the cross section taken along the line VIIB-VIIB in FIG. Is shown. FIGS. 8A and 8B are cross-sectional views in the outer region 52 of the lead portion 12A, respectively, taken along the line VIIIA-VIIIA in FIG. 6C and the cross section taken along the line VIIIB-VIIIB in FIG. Is shown.

  First, as shown in FIG. 6A, a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used. In addition, it is preferable to use what the metal substrate 31 performed the degreasing | defatting etc. to the both surfaces, and performed the washing process.

  Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and dried (FIG. 6B). As the photosensitive resists 32a and 33a, conventionally known resists can be used.

  Subsequently, the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 6C).

  At this time, an opening 33b is provided in a position corresponding to the inner region 51 of the lead portion 12A in the etching resist layer 33 formed on the back side of the metal substrate 31 (FIGS. 6C and 7). (A)). On the other hand, a partial resist 33c is provided along the longitudinal direction of the outer region 52 at a position corresponding to the outer region 52 of the lead portion 12A in the etching resist layer 33 (FIGS. 6C and 8A). )).

  Next, the etching resist layers 32 and 33 are used as an anticorrosion film, and the metal substrate 31 is etched with an etching solution (FIG. 6D). Thereby, the outer shape of the die pad 11 and the plurality of lead portions 12A and 12B is formed. The corrosive liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when copper is used as the metal substrate 31, an aqueous ferric chloride solution is usually used and sprayed from both surfaces of the metal substrate 31. It can be performed by etching.

  As described above, the opening 33b is provided on the back surface side of the metal substrate 31 at a position corresponding to the inner region 51 of the lead portion 12A (FIG. 7A). Thus, when the metal substrate 31 is etched with the corrosive liquid, the back surface of the metal substrate 31 is half-etched to form a flat back surface 51b (FIG. 7B). In this way, the cross-sectional shape of the inner region 51 becomes a substantially square shape (substantially trapezoidal shape).

Further, a partial resist 33c is provided on the back side of the metal substrate 31 at a position corresponding to the outer region 52 of the lead portion 12A (FIG. 8A). As a result, when the metal substrate 31 is etched with the corrosive liquid, the corrosive liquid flows from both sides of the partial resist 33c, the back surface of the metal substrate 31 is half-etched, and the back surface 52b having the convex portions 52d is formed. (FIG. 8B). The partial resist 33c is removed during the etching as the metal substrate 31 is eroded. In this way, the cross-sectional shape of the outer region 52 becomes a substantially pentagonal shape. The thickness _{t c} of the outer region 52 is thicker than the thickness _{t a} of the inner region 51.

  Although not shown, when the metal substrate 31 is etched, the lead portion 12B having the second external terminal 17B is simultaneously formed. The cross-sectional shapes of the inner region 61 and the outer region 62 of the lead portion 12B are each substantially rectangular.

  Thereafter, the etching resist layers 32 and 33 are peeled and removed to obtain the lead frame 10 shown in FIGS. 1 to 3 (FIG. 6E).

Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device 20 shown in FIGS. 4 and 5 will be described with reference to FIGS.

  First, the lead frame 10 is manufactured by the method shown in FIGS. 6A to 6E, 7A to 7B, and 8A to 8B.

  Next, in order to improve the adhesion between the bonding wire 22 and the internal terminal 15, the internal terminal 15 is subjected to a plating process to form a plated portion 25 (FIG. 9A). In this case, the type of plating selected is not limited as long as the adhesion to the bonding wire 22 can be ensured. For example, single-layer plating such as Ag or Au may be used, or Ni / Pd or Ni / Pd / Au may be used. Multi-layer plating laminated in this order may be used. Further, the plating portion 25 may be provided only on the connection portion with the bonding wire 22 in the internal terminal 15 or may be provided on the entire surface of the lead frame 10.

  Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 using, for example, an adhesive 24 such as a die bonding paste (die attaching step) (FIG. 9B).

  Next, the respective terminal portions 21a of the semiconductor element 21 and the internal terminals 15 (plating portions 25) of the respective lead portions 12A and 12B are electrically connected to each other by bonding wires 22 (wire bonding step) (FIG. 9). (C)).

  At this time, the lead frame 10 is placed on the heat block 36 of the wire bonding apparatus. Next, the surface temperature of the lead portions 12A and 12B is simultaneously heated by the heat block 36 from the back side of the inner region 51 of the lead portion 12A and the inner region 61 of the lead portion 12B, for example, to about 150 to 280 ° C. . At the same time, while applying ultrasonic waves through a capillary (not shown) of the wire bonding apparatus, the bonding wires 22 are used to connect the terminal portions 21a of the semiconductor element 21 and the internal terminals 15 of the lead portions 12A and 12B. Connect electrically.

  In this case, since the inner region 51 of the lead portion 12A and the inner region 61 of the lead portion 12B have flat back surfaces 51b and 61b, respectively, the lead portions 12A and 12B can be stably attached to the heat block 36. Can be placed. Thereby, the bonding wire 22 can be stably connected to the internal terminal 15.

  Next, the sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to the lead frame 10 (FIG. 9D). As a result, the lead frame 10, the semiconductor element 21, and the bonding wire 22 are sealed.

  Next, the lead frame 10 is separated for each semiconductor element 21 by dicing the sealing resin 23 between the semiconductor elements 21. At this time, the lead frame 10 and the sealing resin 23 between the semiconductor elements 21 may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone.

  In this way, the semiconductor device 20 shown in FIGS. 4 and 5 is obtained (FIG. 9E).

As described above, according to this embodiment, the maximum thickness t _a of the outer region 52 of the lead portion 12A is formed thicker than the maximum thickness t _c of the inner area 51 of the lead portion 12A. As a result, even when the interval between the adjacent lead portion 12A and the lead portion 12B is narrowed and the width of the lead portion 12A is narrowed, the strength of the lead portion 12A is suppressed from being lowered, and the lead portion 12A is deformed. Thus, it is possible to prevent a problem that the first external terminal 17A is displaced. As a result, the yield of the lead frame 10 can be increased.

  Further, according to the present embodiment, the inner region 51 of the lead portion 12A has a flat back surface 51b and has a substantially square shape in a cross section orthogonal to the longitudinal direction of the lead portion 12A. Thus, in the wire bonding step, the back surface 51b of the inner region 51 can be stably placed on the heat block 36, and the bonding wire 22 can be stably connected to the internal terminal 15. .

  Further, according to the present embodiment, the outer region 52 of the lead portion 12A has the convex portion 52d protruding downward in the cross section orthogonal to the longitudinal direction of the lead portion 12A. The outer region 52 has a substantially pentagonal shape in a cross section orthogonal to the longitudinal direction of the lead portion 12A. Thereby, the cross-sectional secondary moment of the outer region 52 can be increased, and the strength of the outer region 52 that is the base portion of the lead portion 12A can be increased. Thereby, the strength of the lead portion 12A can be increased, and a problem that the lead portion 12A is deformed and the first external terminal 17A is displaced can be prevented. As a result, the yield of the lead frame 10 can be increased.

  Furthermore, since the length of the lead portion 12A can be increased by increasing the strength of the lead portion 12A, the internal terminal 15 can be brought closer to the die pad 11. Thereby, the usage amount of the expensive bonding wire 22 can be reduced, and the manufacturing cost of the lead frame 10 can be reduced.

DESCRIPTION OF SYMBOLS 10 Lead frame 11 Die pad 12A, 12B Lead part 13 Outer frame 14 Hanging lead 15 Internal terminal 17A 1st external terminal 17B 2nd external terminal 20 Semiconductor device 21 Semiconductor element 22 Bonding wire 23 Sealing resin 24 Adhesive 51 Inner area 52 Outer Area 53 External terminal area 61 Inner area 62 Outer area 63 External terminal area

Claims (12)

In the lead frame,
A die pad on which a semiconductor element is mounted;
Provided around the die pad, each having a plurality of lead portions including internal terminals and external terminals,
The external terminals of the plurality of lead portions are alternately arranged in a staggered manner so as to be located inside and outside between the adjacent lead portions,
Among the plurality of lead portions, the lead portion having the external terminal on the inner side is located on the inner side of the external terminal and has the inner terminal, the outer region located on the outer side of the outer terminal, and the outer terminal on the back surface. An external terminal area, and
At least the inner region and the outer region of the lead part having the external terminal on the inside are formed thin by half etching,
The lead frame according to claim 1, wherein the maximum thickness of the outer region of the lead part is larger than the maximum thickness of the inner region of the lead part.   2. The lead frame according to claim 1, wherein the inner region of the lead portion has a flat back surface and has a substantially square shape in a cross section orthogonal to the longitudinal direction of the lead portion.   3. The lead frame according to claim 1, wherein the outer region of the lead portion has a convex portion protruding downward in a cross section perpendicular to the longitudinal direction of the lead portion.   4. The lead frame according to claim 3, wherein the outer region of the lead portion has a substantially pentagonal shape in a cross section perpendicular to the longitudinal direction of the lead portion.   The lead frame according to any one of claims 1 to 4, wherein the external terminal of the lead portion is wider than the surface of the external terminal region. In semiconductor devices,
Die pad,
A plurality of lead portions provided around the die pad, each including an internal terminal and an external terminal;
A semiconductor element mounted on a die pad;
A bonding wire for electrically connecting the semiconductor element and the internal terminal of the lead portion;
A die pad, a lead portion, a semiconductor element, and a sealing resin that seals the bonding wire,
The external terminals of the plurality of lead portions are alternately arranged in a staggered manner so as to be located inside and outside between the adjacent lead portions,
Among the plurality of lead portions, the lead portion having the external terminal on the inner side is located on the inner side of the external terminal and has the inner terminal, the outer region located on the outer side of the outer terminal, and the outer terminal on the back surface. An external terminal area, and
At least the inner region and the outer region of the lead part having the external terminal on the inside are formed thin by half etching,
The maximum thickness of the outer region of the lead part is larger than the maximum thickness of the inner region of the lead part.   The semiconductor device according to claim 6, wherein the inner region of the lead portion has a flat back surface and has a substantially quadrangular shape in a cross section orthogonal to the longitudinal direction of the lead portion.   8. The semiconductor device according to claim 6, wherein the outer region of the lead portion has a convex portion protruding downward in a cross section orthogonal to the longitudinal direction of the lead portion.   9. The semiconductor device according to claim 8, wherein the outer region of the lead portion has a substantially pentagonal shape in a cross section orthogonal to the longitudinal direction of the lead portion.   10. The semiconductor device according to claim 6, wherein the external terminal of the lead portion is wider than the surface of the external terminal region. A die pad on which a semiconductor element is mounted, and a plurality of lead portions provided around the die pad, each including an internal terminal and an external terminal, and the external terminals of the plurality of lead portions are inside and outside between adjacent lead portions Of the plurality of lead portions, the lead portion having the external terminal on the inside is located inside the external terminal and on the inside region having the internal terminal, and on the outside of the external terminal. In the lead frame manufacturing method, having an outer region located and an external terminal region having external terminals formed on the back surface,
Preparing a metal substrate;
Forming a die pad and a lead portion on the metal substrate by etching the metal substrate,
When forming the die pad and the lead portion on the metal substrate, at least the inner region and the outer region of the lead portion having the external terminal on the inside are formed thin by half etching, respectively,
The inner region of the lead portion has a substantially rectangular shape having a flat back surface in a cross section perpendicular to the longitudinal direction of the lead portion,
A method of manufacturing a lead frame, wherein the maximum thickness of the outer region of the lead part is greater than the maximum thickness of the inner region of the lead part. In a method for manufacturing a semiconductor device,
A step of producing a lead frame by the method of producing a lead frame according to claim 11;
Mounting a semiconductor element on the die pad of the lead frame;
Electrically connecting the semiconductor element and the internal terminal of the lead portion by a bonding wire;
A method of manufacturing a semiconductor device, comprising: a step of sealing a die pad, a lead portion, a semiconductor element, and a bonding wire with a sealing resin.

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