JP2014138150A - Semiconductor device inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve accuracy of a semiconductor device inspection method using a TEG (Test Element Group) formed in a chip region.SOLUTION: In a semiconductor device inspection method, a layout of semiconductor elements which compose a TEG formed in a chip region P1 is uniformed with a layout of a semiconductor chip manufactured as a product, and in addition, all of the chip regions in one shot region is made to have the same layout and each chip region is used for inspection. In addition, a wiring layer which electrically connects the semiconductor elements which compose the TEG and pads PD on the semiconductor elements is basically only a first wiring layer.

Description

  The present invention relates to a method for inspecting a semiconductor device, and more particularly to a technique effective when applied to a method for inspecting a semiconductor device having a TEG.

  When manufacturing a semiconductor device, a TEG (Test Elemental Group), which is an evaluation device including a semiconductor element for inspection, is used to inspect the characteristics or lifetime of the semiconductor elements, wirings, or insulating films constituting the semiconductor device. ) Is known.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2003-273186) and Patent Document 2 (Japanese Patent Laid-Open No. 2001-203247), only a few wafers extracted from a lot are subjected to accuracy measurement in an inspection process. It is described that a sampling inspection is performed.

JP 2003-273186 A JP 2001-203247 A

  For example, a plurality of chip areas are laid out in a shot area that exposes a chip pattern on a semiconductor wafer, and various TEGs are formed in the plurality of chip areas to inspect the characteristics of different semiconductor elements. May have been. At this time, it is conceivable that the TEG for inspecting the characteristics of the specific semiconductor element is formed only in a part of the one chip region in the shot region, for example. The TEG may have a structure in which a plurality of semiconductor elements having the same shape are repeatedly formed.

  In this case, the region where the TEG for inspecting the characteristics of the specific semiconductor element is limited on the semiconductor wafer, and the scale of the TEG is small. Therefore, in order to collect inspection results when inspecting the characteristics of the specific semiconductor element, it is necessary to prepare a large number of semiconductor wafers containing the TEG. For this reason, there is a problem that the time and cost for the inspection increase.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to an inspection method of a semiconductor device according to an embodiment, the layout of a semiconductor element constituting a TEG formed in a chip region is the same as that of a semiconductor chip manufactured as a product, and the semiconductor element constituting the TEG The wiring layer that electrically connects the semiconductor element and the pad on the semiconductor element is basically only the first wiring layer.

  According to one embodiment disclosed in the present application, it is possible to improve the accuracy of a semiconductor device inspection method.

It is a top view of the semiconductor wafer containing TEG used for the test | inspection method of the semiconductor device which is one embodiment of this invention. It is a top view which expands and shows a part of FIG. It is a top view which expands and shows a part of FIG. It is sectional drawing which shows a part of FIG. It is a flow which shows the inspection method of the semiconductor device which is one embodiment of the present invention. It is a top view which shows a part of semiconductor device used for the test | inspection method of the semiconductor device which is a comparative example. It is a top view which expands and shows a part of FIG. It is sectional drawing which shows a part of FIG. It is a top view of the semiconductor device used for the inspection method of the semiconductor device which is a comparative example. It is a flow which shows the inspection method of the semiconductor device which is a comparative example.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
In the semiconductor device inspection method of the present embodiment, a semiconductor including a TEG including a semiconductor element formed on the semiconductor substrate in the same layout as the product layout, one layer of wiring on the TEG, and a pad. An inspection method using the apparatus will be described.

  First, FIG. 1 to FIG. 5 show the structure of the TEG used in the semiconductor device inspection method of the present embodiment. FIG. 1 is a plan view of a semiconductor wafer including a TEG used in the inspection method of the present embodiment. FIG. 2 is an enlarged plan view showing a part of FIG. FIG. 3 is an enlarged plan view showing a part of FIG. 4 is a partial cross-sectional view of FIG. FIG. 5 is a flow showing the inspection method of the present embodiment.

  As shown in FIG. 1, a TEG (not shown) used in the inspection process of the semiconductor device of the present embodiment is formed on a semiconductor wafer WF. A semiconductor wafer WF shown in FIG. 1 includes, for example, a semiconductor substrate made of single crystal silicon, and semiconductor elements, wiring layers, and pads sequentially formed thereon. On the main surface of the semiconductor wafer WF, a plurality of chip regions CR are arranged in a matrix. That is, the plurality of chip regions CR are arranged side by side in each of a first direction along the upper surface of the semiconductor wafer WF and a second direction perpendicular to the first direction and along the upper surface of the semiconductor wafer WF. Yes.

  The chip regions CR are separated from each other via a scribe region SL extending in the first direction and a scribe region SL extending in the second direction. That is, the plurality of scribe regions SL define a plurality of chip regions CR and are arranged in a lattice pattern on the main surface of the semiconductor wafer WF. The scribe region SL is a region that is cut in a dicing process that is performed to separate the semiconductor wafer WF. However, since the semiconductor wafer WF described here is used only for inspection, the dicing process may not be performed after the inspection process.

  As described above, the semiconductor wafer WF is used only for inspection. That is, all of the plurality of chip regions CR on the semiconductor wafer WF are used for inspection, and do not become semiconductor chips that are products. As will be described later, semiconductor elements such as transistors are formed on a semiconductor substrate constituting the semiconductor wafer WF, and have the same layout as the product. However, unlike a semiconductor device manufactured as a product, a large number of wiring layers are not formed on the semiconductor element of this embodiment, and one wiring layer and a pad are formed.

  Next, FIG. 2 shows an enlarged plan view of a part of FIG. FIG. 2 is a plan view showing a range that can be exposed in one shot by the exposure apparatus among the plurality of chip regions CR shown in FIG. 1, that is, the chip region CR included in the shot region SH. Here, 15 chip areas are included in one shot area SH. One shot region SH has a rectangular shape, in which five chip regions P1 to P15 are arranged vertically and three horizontally. The chip areas P1 to P15 shown in FIG. 2 correspond to 15 chip areas CR in one shot area SH formed in a part of the area shown in FIG.

  Each of the chip regions CR shown in FIG. 1 constitutes a plurality of shot regions SH arranged in a matrix on the semiconductor wafer WF. A rectangular area surrounded by a thick line shown in FIG. 1 shows the outline of one shot area SH shown as an example. All the chip regions CR on the semiconductor wafer WF are regions in the shot region SH arranged in a matrix, but here, only one shot region SH of the plurality of shot regions SH is shown in outline.

  The shot region SH is a range in which an image of a reticle can be transferred to a photoresist film on a semiconductor wafer using an exposure apparatus when performing an exposure process in the photolithography technique. As shown in FIG. 2, here, a range including 15 chip regions P1 to P15 can be exposed at a time. In the manufacturing process of the semiconductor device, when performing exposure of the photoresist film, after exposing a part of the region on the semiconductor wafer WF in the range of the shot region SH, the semiconductor wafer WF is scanned to perform the above exposure. The exposure is also performed on the area adjacent to the area where the process has been performed, and this process is repeated to expose the entire surface of the semiconductor wafer. That is, on the semiconductor wafer WF, the shot area SH, which is a unit area including 15 chip areas CR, is repeatedly arranged, and all the chip areas CR on the semiconductor wafer WF are arranged in a plurality of shot areas SH. Contained within.

  The layouts of the shot areas SH arranged in a matrix are the same. In other words, the arrangement of the plurality of chip regions CR constituting each of the specific shot region SH and the other one shot region SH is the same. Note that the layout of the elements in the chip areas P1 to P15 in the shot area shown in FIG. 2 may be different from each other. In the present embodiment, the layout of the elements in the chip areas P1 to P15 is considered. Are the same. As shown in FIG. 2, the chip regions P1 to P15 are arranged in a matrix of 5 vertically and 3 horizontally. A scribe region SL extending in the first direction or the second direction is formed between each of the chip regions P1 to P15.

  Next, FIG. 3 shows an enlarged plan view of a part of FIG. FIG. 3 is an enlarged plan view showing the chip region P1 shown in FIG. Note that the chip regions P2 to P15 shown in FIG. 2 all have the same layout as P1 shown in FIG. Also, FIG. 3 does not show the scribe area SL (see FIG. 2). The chip area P1 shown in FIG. 3 is an area surrounded by the four scribe areas SL shown in FIG. As shown in FIG. 3, the chip region P1 has a rectangular shape in plan view.

  A plurality of pads PD are formed in the peripheral region R1 of the chip region P1. On the chip region P1, regions R2, R3, R4, and R5 are formed in a range surrounded by the region R1. In the regions R2 and R3, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory having a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure is formed. The nonvolatile memory formed in the region R3 is, for example, a data storage flash memory. In the region R4, an SRAM (Static Random Access Memory) is formed, and in the region R5, a low breakdown voltage MOSFET of a core portion used for driving the nonvolatile memory is formed.

  In the region R1, when a semiconductor device is manufactured as a product, a high withstand voltage element that supplies a potential to the semiconductor elements formed in the regions R1 to R5 and outputs information from the semiconductor elements. That is, a high breakdown voltage MOSFET used for I / O is formed. Further, in the regions R1 and R5, for example, a capacitive element is also formed. The pad PD formed in the region R1 is used for supplying a predetermined potential to the semiconductor elements formed in the regions R1 to R5 and evaluating each semiconductor element, wiring, insulating film, or the like in probe inspection or the like. Electrode. A plurality of pads PD are arranged side by side along each of the four sides on a region R1 formed in an annular shape along each of the four sides of the peripheral edge of the chip region P1 having a rectangular shape in plan view.

  In the case of a semiconductor chip manufactured as a product, the low breakdown voltage semiconductor element formed in the regions R2 to R5 is connected to the pad PD via a high breakdown voltage MOSFET formed for I / O. In this case, a part of the elements formed in the regions R2 to R5 are directly connected to the pad PD. This is because the semiconductor device used in this embodiment is not used for a product but only for an inspection process. That is, in a semiconductor chip used in a product, it is necessary to convert an external input voltage to a low value in the semiconductor chip and then supply it to a low breakdown voltage semiconductor element. This is because a lower voltage can be supplied to each semiconductor element for a low breakdown voltage semiconductor element.

  Further, in the inspection process using the semiconductor device for inspection, it is sufficient that the output current can be detected by the inspection device. Therefore, it is not necessary to amplify the current that is the information to be output through the high-breakdown-voltage semiconductor element.

  Further, the wiring connecting the semiconductor element formed in the chip region P1 and the pad PD may be formed over a plurality of layers in a semiconductor chip manufactured as a product. Here, a single-layer wiring, The semiconductor element on the semiconductor substrate and the pad PD are connected by the upper and lower vias and the contact plug.

  That is, unlike the semiconductor chip manufactured as a product, the chip region P1 on the semiconductor wafer used for inspection in the present embodiment has only one wiring layer. Also, unlike a semiconductor chip manufactured as a product, even a low breakdown voltage semiconductor element is directly connected to the pad PD via the one wiring layer without passing through a high breakdown voltage semiconductor element. Yes.

  Next, FIG. 4 shows a cross-sectional view of a part of the chip region shown in FIG. In FIG. 4, in order to make the drawing easy to understand, elements formed on the semiconductor substrate in one chip region P1 (see FIG. 3), the memory cells formed in the region R2 shown in FIG. The formed high breakdown voltage MOSFET, the low breakdown voltage MOSFET formed in the region R4, and the capacitive element formed in the region R1 are shown side by side. Note that a memory cell similar to the memory cell shown in FIG. 4 is also formed in the region R3 shown in FIG. Also in the region R5 shown in FIG. 3, a low breakdown voltage MOSFET similar to the low breakdown voltage MOSFET shown in FIG. 4 is formed.

  In FIG. 4, in order from the left side of the drawing, a pair of memory cells Q1, a high breakdown voltage MOSFET Q2, a low breakdown voltage MOSFET Q3, and a capacitive element CP are formed side by side. As shown in FIG. 4, a plurality of element isolation regions IE having a structure such as STI (Shallow Trench Isolation) or LOCOS (Local Oxidization of Silicon) are formed on a semiconductor substrate SB made of a single crystal silicon substrate. The semiconductor elements are separated by the element isolation regions IE. Although it is conceivable that a p-type or n-type well is formed on the upper surface of the semiconductor substrate SB below each semiconductor element, the illustration thereof is omitted here.

  First, the memory cell Q1 which is a MONOS type nonvolatile memory will be described. The memory cell Q1 is formed on a p-type well (not shown) on the main surface of the semiconductor substrate SB. The memory cell Q1 includes a control transistor and a memory transistor. A control gate electrode CG which is a selection gate electrode of the control transistor is made of a polysilicon film, and is formed on the gate insulating film GF1 made of a silicon oxide film. Further, the memory gate electrode MG which is a memory gate electrode of the memory transistor is made of a polysilicon film and is formed adjacent to one side wall of the control gate electrode CG.

  The memory gate electrode MG is electrically separated from the control gate electrode CG and the semiconductor substrate SB via an ONO (Oxide Nitride Oxide) film OX having an L-shaped cross section. A part of the ONO film OX is formed between the control gate electrode CG and the memory gate electrode MG, and the other part of the ONO film OX is formed between the semiconductor substrate SB and the memory gate electrode MG. That is, the memory gate electrode MG is adjacent to the side wall of the control gate electrode CG and the main surface of the semiconductor substrate SB via the ONO film OX.

  The ONO film OX includes a two-layer silicon oxide film and a silicon nitride film formed between them. Here, the laminated structure of the silicon oxide film and the silicon nitride film constituting the ONO film OX is not shown. At the time of writing data, hot electrons generated in the channel region of the main surface of the semiconductor substrate SB immediately below the control gate electrode CG and the memory gate electrode MG are injected into the ONO film OX, which is a charge storage film constituting the ONO film OX. It is captured by a trap in the silicon nitride film.

On the semiconductor substrate SB in the vicinity of the control gate electrode CG, an n ⁺ type semiconductor region D1d that is a diffusion layer functioning as a drain region of the memory cell Q1 is formed. In addition, an n ⁺ type semiconductor region D1s that is a diffusion layer functioning as a source region of the memory cell Q1 is formed in the semiconductor substrate SB in the vicinity of the memory gate electrode MG.

The semiconductor substrate SB in a region adjacent to the n ⁺ -type semiconductor region D1d, n ⁺ -type semiconductor region impurity concentration than D1d lower n ^- -type semiconductor regions (not shown) is formed. That is, the n ⁻ type semiconductor region of the low concentration diffusion layer and the n ⁺ type semiconductor region D1d of the high concentration diffusion layer are formed. The n ⁻ type semiconductor region is an extension region for relaxing the high electric field at the end of the n ⁺ type semiconductor region D1d and making the control transistor have an LDD (Lightly Doped Drain) structure.

Further, in the semiconductor substrate SB in a region adjacent to the n ⁺ -type semiconductor region D1s, n ⁺ -type semiconductor region impurity concentration than D1s lower n ^- -type semiconductor regions (not shown) is formed. That is, the n ⁻ type semiconductor region of the low concentration diffusion layer and the n ⁺ type semiconductor region D1s of the high concentration diffusion layer are formed. The n ⁻ type semiconductor region is an extension region for relaxing the high electric field at the end of the n ⁺ type semiconductor region D1s and making the memory transistor have an LDD structure.

A sidewall SW made of, for example, a silicon oxide film is formed on the other sidewall of the control gate electrode CG and one sidewall of the memory gate electrode MG. The sidewall SW is used to form the n ⁺ type semiconductor region D1d and the n ⁺ type semiconductor region D1s. The memory cell Q1 is a split gate type MONOS memory having a control gate electrode CG and a memory gate electrode MG which are adjacent to each other via the ONO film OX.

The pair of memory cells Q1 have a line-symmetric structure with the n ⁺ type semiconductor region D1d between each other. That is, each of the pair of memory cells Q1 shares an n ⁺ type semiconductor region D1d, that is, a drain region.

Here, each operation of writing, erasing and reading when the memory cell Q1 is a selected memory cell will be described. However, since the semiconductor device of the present embodiment is used only for inspection, some of the plurality of memory cells Q1 formed on the semiconductor wafer may be used for information writing or the like as described below. It does not have to be connected so as to be possible. Here, injecting electrons into the ONO film OX is defined as “writing”, and injecting holes is defined as “erasing”. Hereinafter, the n ⁺ type semiconductor region D1s is referred to as a source region, and the n ⁺ type semiconductor region D1d is referred to as a drain region.

  For the writing, a hot electron writing method called a so-called source side injection method is adopted. At the time of writing, for example, 0.7V is applied to the control gate electrode CG, 10V to the memory gate electrode MG, 6V to the source region, 0V to the drain region, and 0V to the semiconductor substrate SB. As a result, hot electrons are generated in a region near the middle between the control gate electrode CG and the memory gate electrode MG in the channel region formed between the source region and the drain region, and this is injected into the ONO film OX. . The injected electrons are captured by traps in the silicon nitride film constituting the ONO film OX, and the threshold voltage of the memory transistor constituting the memory cell Q1 rises.

  For erasing, a hot hole injection erasing method using a channel current is adopted. At the time of erasing, for example, 0.7V is applied to the control gate electrode CG, −8V to the memory gate electrode MG, 7V to the source region, 0V to the drain region, and 0V to the semiconductor substrate SB. Thereby, a channel region is formed in the semiconductor substrate SB below the control gate electrode CG.

  Further, since a high voltage (7 V) is applied to the source region, the depletion layer extending from the source region approaches the channel region of the control transistor. As a result, the electrons flowing through the channel region are accelerated by a high electric field between the end of the channel region and the source region, and impact ionization occurs, generating a pair of electrons and holes. This hole is accelerated by a negative voltage (−8V) applied to the memory gate electrode MG to become a hot hole and injected into the ONO film OX. The injected holes are captured by traps in the silicon nitride film constituting the ONO film OX, and the threshold voltage of the memory transistor is lowered.

  At the time of reading, for example, 1.5V is applied to the control gate electrode CG, 1.5V to the memory gate electrode MG, 0V to the source region, 1.5V to the drain region, and 0V to the semiconductor substrate SB. That is, the voltage applied to the memory gate electrode MG is set between the threshold voltage of the memory transistor in the write state and the threshold voltage of the memory transistor in the erase state, and the write state and the erase state are discriminated. .

  Next, the high voltage MOSFET Q2 used for I / O and the like will be described. The high breakdown voltage MOSFET Q2 is a semiconductor element used to input and output current between the semiconductor device and an external device. For this reason, a high breakdown voltage is required as compared with the low breakdown voltage MOSFET Q3 formed in the core portion or the like. Therefore, the gate length of the gate electrode G2 of the high voltage MOSFET Q2 is formed longer than the gate length of the gate electrode G3 of the low voltage MOSFET Q3. Further, the thickness of the gate insulating film GF2 of the high voltage MOSFET Q2 is formed larger than the thickness of the gate insulating film GF3 of the low voltage MOSFET Q3.

The high breakdown voltage MOSFET Q2 has a gate electrode G2 formed on the semiconductor substrate SB via a gate insulating film GF2, and has a source / drain region formed on the upper surface of the semiconductor substrate SB next to the gate electrode G2. doing. Each of the source / drain regions includes an n ⁺ type semiconductor region D2 formed on the upper surface of the semiconductor substrate SB, and the main surface of the semiconductor substrate SB is adjacent to each n ⁺ type semiconductor region D2, An n ⁻ type semiconductor region (not shown) having an impurity concentration lower than that of the n ⁺ type semiconductor region D2 is formed. Each of the pair of n ⁻ type semiconductor regions is formed in a region closer to the gate electrode G2 than the adjacent n ⁺ type semiconductor region D2.

  Here, a p-type well formed on the upper surface of the semiconductor substrate SB immediately below the high breakdown voltage MOSFET Q2 is not shown. On the side walls on both sides of the gate electrode G2, sidewalls SW made of, for example, a silicon oxide film are formed in a self-aligning manner.

  Next, the low breakdown voltage MOSFET Q3 used in the SRAM or the logic circuit of the core portion will be described. The low breakdown voltage MOSFET Q3 is a field effect transistor that requires a high processing speed.

The low breakdown voltage MOSFET Q3 has a point that the gate length of the gate electrode G3 is smaller than the gate length of the gate electrode G2 of the high breakdown voltage MOSFET Q2, and the thickness of the gate insulating film GF3 is smaller than the thickness of the gate insulating film GF2 of the high breakdown voltage MOSFET Q2. Except for this, the structure is the same as that of the high voltage MOSFET Q2. That is, the low breakdown voltage MOSFET Q3 has the gate electrode G3 on the semiconductor substrate SB via the gate insulating film GF3, and a pair of source / drain regions constituting the source / drain region is formed on the main surface of the semiconductor substrate SB next to the gate electrode G3. It has an n ⁺ type semiconductor region D3. An n ⁻ type semiconductor region (not shown) is formed on the upper surface of the semiconductor substrate SB adjacent to the n ⁺ type semiconductor region D3.

  Next, the capacitive element CP will be described. The capacitive element CP is an element that is formed on the semiconductor substrate SB and used by generating a capacitance between the polysilicon films PS1 and PS2 that are insulated from each other. The polysilicon film PS1 is formed on the semiconductor substrate SB via the insulating film IF1, and the polysilicon film PS2 is formed on the polysilicon film PS1 via the insulating film IF2.

  A part of the upper surface of the polysilicon film PS1 is exposed from the polysilicon film PS2 and the insulating film IF2. The insulating film IF1 is made of, for example, a silicon oxide film, and the insulating film IF2 is made of, for example, a laminated film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed in the same manner as the ONO film OX. However, the insulating film IF2 is not limited to the ONO film, and may be formed of a silicon oxide film. On the sidewalls on both sides of each of the polysilicon films PS1 and PS2, sidewalls SW made of, for example, a silicon oxide film are formed in a self-aligning manner.

  Here, since the capacitive element CP and the memory cell Q1 are formed on the same semiconductor substrate SB, the insulating film formed on the semiconductor substrate when the ONO film OX is formed is formed between the conductor films of the capacitive element CP. It is used as an insulating film for insulating. Therefore, the ONO film OX constituting the memory cell Q1 and the insulating film IF2 are the same layer. Here, illustration of a laminated structure such as a silicon oxide film and a silicon nitride film constituting the insulating film IF2 is omitted.

  Further, although description and illustration are omitted in the present embodiment, it is conceivable that, for example, a bipolar transistor, a diode, or a resistance element is formed in addition to the above-described various semiconductor elements shown in FIG. As described above, the case where the n-channel type high breakdown voltage MOSFET Q2 and the low breakdown voltage MOSFET Q3 are formed has been described with reference to FIG. 4, but the MOSFET formed on the semiconductor substrate SB may be a p channel type. Also, both n-channel and p-channel MOSFETs may be formed on the semiconductor substrate SB.

The upper surfaces of the n ⁺ type semiconductor regions D1d, D1s, D2, D3, the control gate electrode CG, the memory gate electrode MG, the gate electrodes G2, G3, and the polysilicon films PS1 and PS2 are made of, for example, nickel silicide (NiSi). A silicide layer S1 is formed. The material of the silicide layer S1 may be cobalt silicide or nickel platinum silicide. The silicide layer S1 is a conductor layer provided to reduce contact resistance between the underlying conductor layer and the contact plug C1 on the silicide layer S1.

  A stopper insulating film ES made of, for example, a silicon nitride film is formed so as to cover each of the memory cell Q1, the high voltage MOSFET Q2, the low voltage MOSFET Q3, and the capacitive element CP. On the stopper insulating film ES, an interlayer insulating film ILF made of, for example, a P-TEOS (Tetraethoxysilane) film formed by, for example, a plasma CVD (Chemical Vapor Deposition) method is formed as a silicon oxide film. A contact hole, which is a plurality of through holes, is formed in the laminated film including the stopper insulating film ES and the interlayer insulating film ILF, and a contact plug C1 is embedded inside each of the plurality of contact holes. The contact plug C1 is mainly made of a W (tungsten) film.

The plurality of contact plugs C1 include silicide layers on the upper surfaces of the n ⁺ type semiconductor regions D1d, D1s, D2, and D3, the control gate electrode CG, the memory gate electrode MG, the gate electrodes G2 and G3, and the polysilicon films PS1 and PS2. It is connected to the upper surface of S1. In FIG. 4, the control gate electrode CG, the memory gate electrode MG, the gate electrodes G2, G3, and the contact plug C1 connected to the upper surface of the polysilicon film PS2 via the silicide layer S1 are not shown. . The upper surface of the interlayer insulating film ILF and the upper surface of the contact plug C1 are planarized, and the height of each upper surface is made uniform.

  On the interlayer insulating film ILF and the contact plug C1, an interlayer insulating film L1 made of, for example, a SiOC film is formed. In the interlayer insulating film L1, a plurality of wiring grooves extending in a specific direction along the upper surface of the semiconductor substrate SB and exposing the upper surface of the contact plug C1 are formed. The first layer wiring M1 is embedded. The upper surface of the first layer wiring M1 and the upper surface of the interlayer insulating film L1 are flattened, and the heights of the upper surfaces are aligned with each other. That is, the first layer wiring M1 is connected to the upper surface of the contact plug C1, and extends in a specific direction along the upper surface of the semiconductor substrate SB. Here, a layer including the interlayer insulating film L1 and the first layer wiring M1 embedded in the wiring trench penetrating the interlayer insulating film L1 is referred to as a first wiring layer.

  A barrier insulating film BF and an interlayer insulating film L2 are sequentially stacked on the first wiring layer, that is, on the interlayer insulating film L1 and the first layer wiring M1. The barrier insulating film BF is made of, for example, a SiCN film, and the interlayer insulating film L2 is made of, for example, a SiOC film. In the laminated film composed of the interlayer insulating film L2 and the barrier insulating film BF, a plurality of via holes penetrating from the upper surface to the back surface are formed, and vias V1 are buried in the plurality of via holes. That is, the via V1 passes through the interlayer insulating film L2 and the barrier insulating film BF, and the bottom surface of the via V1 is connected to the upper surface of the first layer wiring M1. The upper surfaces of the via V1 and the interlayer insulating film L2 are flattened and aligned at the same height.

  The via V1 is a conductor film provided not for connecting the wirings but for connecting the lower-layer first-layer wiring M1 and the upper-layer pad PD, and has, for example, a cylindrical shape. . The via V1 is mainly made of Cu (copper), for example. The pad PD is a pattern of a conductor film made of, for example, Al (aluminum) formed on the interlayer insulating film L2 and the via V1. The pad PD is an electrode used for contacting an inspection needle, for example, when performing a probe inspection in the semiconductor device inspection method of the present embodiment.

  Therefore, the pad PD pattern has a larger area in plan view than the via V1. Further, the shortest width of the pad PD in plan view is larger than the shortest width of the first layer wiring M1 in plan view. The pad PD is electrically connected to each semiconductor element on the semiconductor substrate SB through the via V1, the first layer wiring M1, and the contact plug C1.

  In FIG. 4, for easy understanding of the structure of the semiconductor device according to the present embodiment, the pad PD is shown immediately above the memory cell Q1 or the low breakdown voltage MOSFET Q3. However, the pad PD is actually described with reference to FIG. As described above, the regions R2 to R5 in which the core portion, the SRAM or the nonvolatile memory are formed and the region R1 in which the pad PD is formed do not overlap in plan view. That is, it is considered that the pad PD is not formed immediately above the memory cell Q1 or the low breakdown voltage MOSFET Q3. The memory cell Q1 or the low breakdown voltage MOSFET Q3 is connected to the pad PD on the region R1 via a first layer wiring M1 (see FIG. 4) which is a lead wiring extending to the region R1.

  Although not shown in FIG. 4, a passivation film exposing the upper surface of the pad PD is formed on the interlayer insulating film L2. The passivation film is made of, for example, a polyimide film.

  4 shows a structure in which some of the first layer wirings M1 such as the first layer wirings M1 connected to the high breakdown voltage MOSFET Q2 are not connected to the pads PD. The first layer wiring M1 connected to the high breakdown voltage MOSFET Q2, the low breakdown voltage MOSFET Q3, and the capacitive element CP are all connected to the pad PD in a region not shown.

  However, the wiring that connects the pads PD and a plurality of semiconductor elements arranged in the same layout as the product formed in the chip region P1 shown in FIG. 3 is a first layer wiring M1 (see FIG. 4). Only. Some of the plurality of semiconductor elements formed on the chip region P1 may not be able to be connected to the pad unless the upper layer wiring intersects in plan view. This is because a plurality of semiconductor elements are densely formed in the product layout on the chip region P1, and only one layer of the first layer wiring is used to connect all the semiconductor elements to the pad PD. This is because it is difficult. Therefore, some semiconductor elements may be in an electrically floating state. In other words, not all semiconductor elements on the semiconductor substrate need be connected to the pad PD.

  As will be described later, the wiring for connecting the semiconductor element and the pad PD may be formed in two layers. Further, a part of the metal film in the same layer as the metal film constituting the pad PD may be formed in a shape extending in one direction and used as a wiring. That is, when two wiring layers are formed between the semiconductor element and the pad PD, and further a wiring is formed in the same layer as the pad PD, there are three layers that can be used as wiring. Further, if a wiring made of a conductor film is formed in the same layer as the semiconductor element on the semiconductor substrate, there are four layers that can be used as the wiring. If there are at least two layers that can be used as wirings in this way, a plurality of wirings can be crossed in a plan view, and the degree of freedom of wiring layout can be increased.

  As described above, the semiconductor device used in the semiconductor device inspection method of the present embodiment is used only for inspection, but semiconductor elements are formed in the same layout as the product in each chip region. Yes. Therefore, as shown in FIG. 4, on the semiconductor substrate SB in one chip region, the memory cell Q1 constituting the nonvolatile memory, the high breakdown voltage MOSFET Q2 used for the I / O, the core portion or the SRAM constituting the SRAM is formed. A breakdown voltage MOSFET Q3, and a capacitive element CP that constitutes a core portion and the like are formed.

  In addition, a conductor extending in a specific direction along the main surface of the semiconductor substrate SB formed in a region above the semiconductor elements such as the memory cell Q1, the high breakdown voltage MOSFET Q2, the low breakdown voltage MOSFET Q3, and the capacitive element CP. A certain wiring is only the first layer wiring M1. That is, there is only one wiring layer that electrically connects the plurality of semiconductor elements formed on the upper surface of the semiconductor substrate SB and the pad PD exposed on the upper surface of the semiconductor wafer WF (see FIG. 1). is there.

  Next, a process of manufacturing the above-described semiconductor device and performing an inspection using the semiconductor device will be described with reference to FIG. FIG. 5 is a flowchart showing a manufacturing process of a semiconductor device including a TEG used in the semiconductor device inspection method of the present embodiment and an inspection process performed using the manufacturing process.

  First, a semiconductor wafer, that is, the semiconductor substrate SB shown in FIG. 4 is prepared (step ST1 in FIG. 5).

  Next, the element isolation region IE is formed in the groove formed on the upper surface of the semiconductor substrate SB (step ST2 in FIG. 5).

  Next, a well (not shown) is formed on the main surface of the semiconductor substrate SB. The well is formed by implanting a p-type impurity (for example, B (boron)) or an n-type impurity (for example, As (arsenic) or P (phosphorous)) into the main surface of the semiconductor substrate SB by an ion implantation method ( Step ST3 in FIG. 5).

  Next, the memory cell Q1 of the split gate type MONOS memory which is a nonvolatile memory is formed (step ST4 in FIG. 5).

  Next, peripheral MOSFETs are formed (step ST5 in FIG. 5). The peripheral MOSFET referred to here includes a low breakdown voltage MOSFET Q3 that constitutes a core portion or SRAM, and a high breakdown voltage MOSFET Q2 used for I / O. In step ST5, other semiconductor elements such as a capacitive element CP, a diode, a bipolar transistor, or a resistance element are also formed.

  Next, a silicide layer S1 is formed using a known salicide technique (step ST6 in FIG. 5). Steps ST1 to ST6 in FIG. 5 are the same as the manufacturing steps performed when a semiconductor device is manufactured as a product.

  Next, after forming the interlayer insulating film ILF, the contact plug C1 is formed (step ST7 in FIG. 5). The process performed in step ST7 of FIG. 5 may be the same as the manufacturing process performed when a semiconductor device is manufactured as a product.

  Next, a first wiring layer including the first layer wiring M1 is formed (step ST8 in FIG. 5). The processes performed after step ST8 in FIG. 5 are different from the manufacturing processes performed when a semiconductor device is manufactured as a product. For example, when forming a semiconductor chip of a product, a contact plug is formed in a process corresponding to step ST7 in FIG. 5, and then a first wiring layer is formed on the contact plug. In step ST8 of the present embodiment, the first wiring layer is formed. The first layer wiring M1 to be formed has a different layout from the first layer wiring in the first wiring layer of the semiconductor chip of the product.

  Next, a via V1 for connecting the first layer wiring M1 and the pad PD is formed on the first wiring layer (step ST9 in FIG. 5). Here, the via provided for connecting the pad and the underlying wiring is called a pad via.

  Next, the pad PD is formed (step ST10 in FIG. 5). By performing the above steps ST1 to ST10, a semiconductor wafer having a TEG formed on the main surface is prepared. Although the illustration of the steps is omitted here, in the step of preparing the semiconductor wafer on which the TEG is formed, after the pad PD is formed, the upper surface of the pad PD is exposed on the wiring layer on the semiconductor substrate. Forming a passivation film. The following probe inspection is performed after the passivation film is formed.

  Next, the semiconductor device is inspected by performing a probe inspection (step ST11 in FIG. 5). In the inspection process using the semiconductor device described above, the characteristics or lifetime of the semiconductor elements, wirings, or insulating films formed on the semiconductor wafer are evaluated by probe inspection. That is, the evaluation is performed by bringing the inspection needle into contact with the upper surface of the pad PD (see FIGS. 3 and 4), supplying a potential to a semiconductor element or wiring constituting the TEG, and measuring the current.

  For example, in the probe inspection, the performance of the SRAM that changes depending on the size such as the gate length and the gate width of the low breakdown voltage MOSFET that forms the SRAM formed in the region R4 shown in FIG. 3 is inspected. In the probe inspection, the breakdown voltage of the element isolation region IE formed on the upper surface of the semiconductor substrate SB shown in FIG. 4 can be inspected. In the probe inspection, the characteristics that change depending on the size of the high breakdown voltage MOSFET Q2 or the low breakdown voltage MOSFET Q3, the junction between the p-type semiconductor region and the n-type semiconductor region, and the like can be evaluated.

  In the probe inspection, parasitic capacitance generated in a semiconductor element or wiring can be evaluated. In the probe inspection, by changing the width of the element isolation region IE in the direction along the main surface of the semiconductor substrate SB, the stress generated in the element isolation region IE is changed to a semiconductor element near the element isolation region IE. The presence or absence of the influence on the characteristics of can be investigated.

  In addition, in the memory cell Q1, the high breakdown voltage MOSFET Q2, the low breakdown voltage MOSFET Q3, and the capacitor element CP, when the applied voltage is increased stepwise, a voltage that causes dielectric breakdown in the gate insulating films GF1 to GF3 or the insulating films IF1 and IF2 is generated. Can be inspected. That is, the TZDB (Time Zero Dielectric Breakdown) characteristic of the insulating film can be evaluated.

  In the memory cell Q1, the high breakdown voltage MOSFET Q2, the low breakdown voltage MOSFET Q3, and the capacitive element CP, when the gate insulating films GF1 to GF3 or the insulating films IF1 and IF2 cause dielectric breakdown when a constant applied voltage is continuously applied. The time required can be inspected. That is, the TDDB (Time Dependent Dielectric Breakdown) characteristic of the insulating film can be evaluated.

  In the probe inspection, when current flows through the first layer wiring M1, the presence or absence of EM (Electromigration), which is a phenomenon that the first layer wiring M1 is disconnected, or the first layer wiring M1 is heated. Thus, it is possible to inspect whether or not SM (Stress migration), which is a phenomenon in which the first layer wiring M1 is disconnected, is generated. In addition, by generating a potential difference between the adjacent first layer wirings M1 through the interlayer insulating film L1, whether or not dielectric breakdown occurs due to deterioration with time of the interlayer insulating film L1 between the first layer wirings M1 is determined. It is also possible to inspect.

  As described above, various characteristics and the like can be evaluated using the TEG of the present embodiment shown in FIGS. The result obtained by performing the probe inspection in step ST11 of FIG. 5 is fed back to the subsequent manufacturing process of the semiconductor device (step ST12 of FIG. 5). Thereby, the reliability of the semiconductor device can be improved and the performance of the semiconductor device can be improved by changing the manufacturing conditions of the semiconductor device. In addition, the inspection result obtained by the above inspection can be used to determine the size or impurity concentration of a semiconductor element manufactured as a product, the layout of wiring, or the like.

  Next, the effect of the inspection method of the semiconductor device of this embodiment will be described using a comparative example. FIG. 6 shows one shot region SHa formed on a semiconductor wafer used in the semiconductor device inspection method of the comparative example. On the semiconductor wafer, as in the semiconductor wafer WF shown in FIG. 1, a plurality of pads in one shot region SHa are taken as one unit, and a plurality of pads are arranged so that a plurality of pads of this unit are arranged. .

  As shown in FIG. 6, fifteen chip regions P1a to P15a are arranged in a matrix in one shot region SHa. However, unlike the semiconductor device of the present embodiment shown in FIG. 2, all of the chip regions P1a to P15a shown in FIG. 6 have different layouts. This is because the uses of the chip regions P1a to P15a are different. That is, the chip regions P1a to P15a have different types of semiconductor elements formed in these regions, semiconductor element sizes, wiring layouts, and the like.

  The chip regions P1a to P6a, P10a, and P12a to P15a are regions used only for the inspection of the semiconductor device, but the chip regions P7a to P9a and P11a are processed through the dicing process of separating the semiconductor wafer into products. It is an area used as. That is, in the chip areas P1a to P15a in the shot area SHa, an area used for inspection and an area used as a product are mixed.

  In the semiconductor device of the comparative example shown in FIG. 6, in each chip region P1a to P15a in the shot region SH, semiconductor elements or wirings are formed with different layouts for inspection and for products. Moreover, even if it is a chip | tip area | region for a test | inspection, chip area | region P1a-P6a, P10a, and P12a-P15a are formed by the separate structure by the object evaluated by a test | inspection. That is, in the shot area SHa, chip areas P1a to P6a, P10a and P12a to P15a having various layouts are formed according to the inspection item.

  Here, FIG. 7 shows a plan view in which a part of FIG. 6 is enlarged. FIG. 7 is an enlarged plan view showing the inspection chip region P6a of FIG. As shown in FIG. 7, the chip region P6a has a plurality of regions R6 to R11 on the semiconductor substrate. The layout of the chip area P1 shown in FIG. 3 is the same as that of the product, but the layout of the chip area P6a shown in FIG. 7 is formed exclusively for inspection and is different from the layout used for the product. Although not shown, pads connected to the TEGs formed in the regions R6 to R11 are formed immediately above the regions R6 to R11. However, the pad may be formed on the peripheral edge of the chip region P6a as in FIG.

  In the regions R6 to R11 shown in FIG. 7, semiconductor elements or wirings used for the respective inspections are formed. For example, the region R6 is a region for evaluating deterioration with time of the insulating film between the wirings. In the region R6, for example, a plurality of wirings embedded in the insulating film are formed adjacent to each other. In addition, the region R7 and the region R11 are regions used for evaluating the presence or absence of the occurrence of EM in the wiring. For example, a plurality of wirings are formed in the region R7 and the region R11.

  The region R8 is a region where a TEG for evaluating TZDB characteristics is formed. In the region R8, for example, a plurality of MOSFETs including a gate insulating film are formed. The region R9 is a region used for evaluating whether or not SM has occurred, and a plurality of wirings are formed in the region R9, for example. The region R10 is a region where a TEG for evaluating TDDB characteristics is formed. In the region R10, for example, a plurality of MOSFETs including a gate insulating film are formed.

  As described above, TEGs corresponding to the inspection purpose are formed in the regions R6 to R11, respectively. However, these TEGs have a layout in which a semiconductor element having a specific shape or a wiring pattern having a specific layout is repeatedly formed, unlike a semiconductor element or wiring used in a product. In other words, the MOSFETs that make up a semiconductor chip manufactured as a product form different types of MOSFETs in one region, such as the size of the gate electrode, the thickness of the gate insulating film, or the impurity concentration in the semiconductor region. On the other hand, in the above comparative example, a plurality of MOSFETs having the same shape and uniform characteristics are arranged in an array in one region.

  The reason why each region in the chip region P6a of the comparative example mainly has a repetitive pattern as described above is as follows. That is, the area occupied by each region in one chip region P6a is small, and semiconductor elements and the like are formed in regions R6 to R11 having shapes different from the chip region to be a product. This is because it is difficult to form various semiconductor elements having various sizes or characteristics.

  Further, in the semiconductor device of the comparative example, semiconductor elements or wirings necessary for performing a specific inspection are formed in one chip region, but other types of semiconductor elements are not formed. That is, as in the comparative example shown in FIG. 7, when a low breakdown voltage MOSFET used for SRAM is formed in the region R8, other semiconductor elements such as a high breakdown voltage MOSFET, non-volatile in the chip region P6a. It is conceivable that a memory cell or a capacitor element of the volatile memory is not formed.

  This is because the region R8 of the chip region P6a is used only for the evaluation of TZDB characteristics, and the other regions R6, R7, R9 to R11 are used for specific inspections such as evaluation of TDDB, SM or EM. is there. That is, unlike the semiconductor chip used as a product, the semiconductor device of the comparative example has only a structure used for inspection. Therefore, the type of semiconductor element formed in one chip region P6a is the semiconductor of the product. Less than a chip. The specific inspection referred to here refers to inspection of any one of inspections such as TZDB characteristics, TDDB characteristics, parasitic capacitance, resistance abnormality, EM or SM.

  Next, FIG. 8 shows a cross-sectional view of the semiconductor device of the comparative example. FIG. 8 shows a cross-sectional view of each of the four chip regions for inspection in the shot region SHa shown in FIG. That is, in FIG. 8, four regions are shown side by side, but each region exists in a different chip region. Specifically, for example, four regions shown in FIG. 8 are partial cross sections of the chip regions P4a, P5a, P6a, and P10a shown in FIG. 6 in order from the left. Therefore, the four regions of the semiconductor substrate SB shown in FIG. 8 indicate the same substrate. However, unlike the semiconductor device of the present embodiment shown in FIG. 4, each of a plurality of types of semiconductor elements is formed on different chip regions.

  As shown in FIG. 8, a memory cell Q1, a high breakdown voltage MOSFET Q2, a low breakdown voltage MOSFET Q3, and a capacitor element CP are formed on the semiconductor substrate SB, as in FIG. The first layer wiring M1a in the layer is electrically connected by a contact plug C1 penetrating the interlayer insulating film ILF. However, unlike the present embodiment, the semiconductor device of the comparative example shown in FIG. 8 further has a second wiring layer, a third wiring layer, a fourth wiring layer, a fifth wiring layer, a first wiring layer on the first wiring layer. 6 wiring layers, 7th wiring layer, 8th wiring layer, and pad PD are laminated in order.

  8 shows a simplified cross-sectional view of the memory cell Q1, the high voltage MOSFET Q2, the low voltage MOSFET Q3, and the capacitor CP having the same structure as the four types of semiconductor elements shown in FIG. In FIG. 8, the illustration of the silicide layer is omitted.

  The semiconductor device of the comparative example shown in FIG. 8 has a memory cell Q1, a high breakdown voltage MOSFET Q2, a low breakdown voltage MOSFET Q3, and a capacitor element CP on a semiconductor substrate SB, and these semiconductor elements are covered with an interlayer insulating film ILF. ing. A plurality of contact plugs C1 penetrating the interlayer insulating film ILF are connected to each of the plurality of semiconductor elements, and a first wiring layer including the first layer wiring M1a and the interlayer insulating film L1 is formed on the contact plug C1. Is formed. A laminated film in which the barrier insulating film B1 and the interlayer insulating film L2a are sequentially laminated is formed on the first wiring layer, and the second layer wiring M2 is formed in the wiring groove on the upper surface of the laminated film. ing. The lower surface of the second layer wiring M2 and the upper surface of the first layer wiring M1a are electrically connected through a via V1a integrated with the second layer wiring M2.

  The barrier insulating film B1 is made of, for example, a SiCN film, and the interlayer insulating film L2a is made of, for example, a SiOC film. The second layer wiring M2 and the via V1a are formed by a dual damascene method, and are mainly made of a Cu (copper) film. Here, a layer including the barrier insulating film B1, the interlayer insulating film L2a, the second layer wiring M2, and the via V1a is referred to as a second wiring layer. A third wiring layer having the same structure as the second wiring layer is formed on the second wiring layer. The third wiring layer includes a barrier insulating film B2, an interlayer insulating film L3, a third layer wiring M3, and a via V2. The third layer wiring M3 includes the via V2, the second layer wiring M2, the via V1a, and the first layer. Each semiconductor element is electrically connected through the layer wiring M1a and the contact plug C1.

  On the third wiring layer, a fourth wiring layer, a fifth wiring layer, a sixth wiring layer, and a seventh wiring layer having the same structure as the third wiring layer are formed in this order. That is, the fourth wiring layer includes the barrier insulating film B3, the interlayer insulating film L4, the fourth layer wiring M4, and the via V3. The fifth wiring layer includes a barrier insulating film B4, an interlayer insulating film L5, a fifth layer wiring M5, and a via V4. The sixth wiring layer includes a barrier insulating film B5, an interlayer insulating film L6, a sixth layer wiring M6, and a via V5. The seventh wiring layer includes a barrier insulating film B6, an interlayer insulating film L7, a seventh layer wiring M7, and a via V6.

  On the seventh wiring layer, a barrier insulating film B7, an interlayer insulating film L8a, a barrier insulating film B8a, and an interlayer insulating film L8b are sequentially stacked, and pass through the stacked film including the barrier insulating film B8a and the interlayer insulating film L8b. An eighth layer wiring M8 mainly made of copper is formed in the wiring trench. The eighth layer wiring M8 and the seventh layer wiring M7 are electrically connected through a via V7 penetrating a laminated film composed of the barrier insulating film B7 and the interlayer insulating film L8a. Here, the layer including the barrier insulating film B7, the interlayer insulating film L8a, the barrier insulating film B8a, the interlayer insulating film L8b, the via V7, and the eighth layer wiring M8 is referred to as an eighth wiring layer.

  A barrier insulating film B8b and an interlayer insulating film L9 are sequentially stacked on the eighth wiring layer, and a pad PD mainly made of an Al (aluminum) film is formed on the interlayer insulating film L9. The pad PD and the eighth layer wiring M8 are electrically connected through a via V8 penetrating the laminated film composed of the barrier insulating film B8b and the interlayer insulating film L9. The pad PD includes a via V8, an eighth layer wiring M8, a via V7, a seventh layer wiring M7, a via V6, a sixth layer wiring M6, a via V5, a fifth layer wiring M5, a via V4, a fourth layer wiring M4, and a via. It is electrically connected to each semiconductor element on the semiconductor substrate SB via V3, the third layer wiring M3, the via V2, the second layer wiring M2, the via V1a, the first layer wiring M1a, and the contact plug C1.

  Although not shown in FIG. 8, a passivation film that exposes the upper surface of the pad PD is formed on the interlayer insulating film L8b. The passivation film is made of, for example, a polyimide film.

  As described above with reference to FIG. 8, the semiconductor device of the comparative example is different from the semiconductor device of this embodiment in which only one wiring layer is provided (see FIG. 4), with a plurality of wiring layers on the semiconductor element. It has a structure in which a pad PD is provided thereon.

  Since the layout in each inspection chip region constituting the semiconductor device of the comparative example shown in FIG. 6 has many repeated patterns, the wiring connected to the pad for supplying the potential to the TEG is a semiconductor manufactured as a product. It may be simpler than a chip. In other words, as long as it is within the inspection chip region used in the semiconductor device inspection method of the comparative example, it is not necessary to provide a large number of wiring layers as shown in FIG. 4, and the number of wiring layers can be reduced. However, as shown in FIG. 6, since the shot regions SH have chip regions P7a to P9a and P11a used as products, chip regions P1a to P6a, P10a formed on the same semiconductor substrate and In P12a to P15a, it is necessary to provide a multilayer wiring structure similar to the product.

  Further, in one chip region P6a, for example, the area of the region R8 used for inspecting the TZDB characteristic is smaller than the chip region P1 (see FIG. 3) of the present embodiment. Further, the chip regions P1a to P6a, P10a, and P12a to P15a shown in FIG. 6 have different layouts for performing different inspections. For this reason, in one shot region SHa, for example, the region that can be used for inspecting the TZDB characteristic is only the region R8 in the chip region P6a. That is, in the comparative example, areas used for inspection of a plurality of items are separately provided in the shot area SHa, but the scale of each area that can be used for inspection of individual items is small.

  Here, FIG. 9 shows a semiconductor wafer WFa of a comparative example. On the semiconductor wafer WFa, a plurality of chip regions CR are arranged by arranging a plurality of layouts of the shot regions SHa. In FIG. 9, the outline of one shot area SHa is shown by a thick line as an example. The chip regions CR on the semiconductor wafer WFa are all regions within the shot region SHa arranged in a matrix, but here, only one shot region SHa is shown out of the plurality of shot regions SHa arranged.

  In FIG. 9, the chip region CR at the position corresponding to the chip region P6a (see FIG. 6) is shown in black. The plurality of chip areas CR correspond to the chip areas P1a to P15a shown in FIG.

  Each shot area SHa has the same layout. Therefore, the arrangement of the plurality of chip areas CR in each shot area SHa is the same. For this reason, as shown in FIG. 9, chip regions P6a that are regions that can be used to inspect TZDB characteristics are arranged in a matrix at equal intervals on the semiconductor wafer WFa. In such a case, the range in which the TZDB characteristic can be inspected on the semiconductor wafer WFa is limited to the range surrounded by the broken line in FIG.

  The reason why the range surrounded by the broken line in FIG. 9 does not surround all the chip regions CR is that the portion where the TZDB characteristic can be inspected in the shot region SHa is the region R8 in the chip region P6a (see FIG. 7). ) Only. That is, since the TZDB characteristic can be inspected only in a part of the shot area SHa, there is an area where the TZDB characteristic cannot be inspected at the end of the semiconductor wafer WFa.

  Next, a process for manufacturing the semiconductor device of the above-described comparative example and performing an inspection using the semiconductor device will be described with reference to FIG. FIG. 10 is a flowchart showing a manufacturing process of a semiconductor device including a TEG used in the semiconductor device inspection method of the comparative example and an inspection process performed using the manufacturing process.

  Steps ST1 to ST8 shown in FIG. 10 are performed in the same manner as steps ST1 to ST8 shown in FIG. However, the layout of semiconductor elements and wirings formed on the semiconductor substrate differs between this embodiment and the comparative example. Further, as described with reference to FIG. 7 and the like, the semiconductor elements formed in the inspection chip region by steps ST1 to ST5 in FIG. 10 are formed in a layout different from the layout used in the product.

  As described above, steps ST5 to ST8 shown in FIG. 10 are first performed, and then a second wiring layer is formed on the first wiring layer (step ST8a in FIG. 10). Step ST8a includes a step of forming an upper second layer wiring M2 in the second wiring layer shown in FIG. 8, and a step of forming a via V1a connecting the second layer wiring M2 and the first layer wiring M1a. It is out. In the case of using the dual damascene method, the via V1a and the second layer wiring M2 are collectively formed by the same process.

  Next, the third wiring layer is formed on the second wiring layer by performing the wiring layer forming process in the same manner as in step ST8a (step ST8b in FIG. 10). Thereafter, the same wiring layer forming process is repeated. Here, the first wiring layer to the eighth wiring layer are formed. FIG. 10 shows a step ST8 for forming the first wiring layer, a step ST8a for forming the second wiring layer, a step ST8b for forming the third wiring layer, and a step ST8b for forming the wiring layer laminated on the semiconductor substrate. Although step ST8g for forming the eight wiring layers is shown, the steps for forming the fourth to seventh wiring layers between steps ST8b and ST8g are omitted.

  The subsequent steps are performed in the same manner as steps ST9 to ST12 in FIG.

  That is, after step ST8g, a via V9 for connecting the eighth-layer wiring M8 and the pad PD shown in FIG. 8 is formed (step ST9 in FIG. 10).

  Next, the pad PD is formed (step ST10 in FIG. 10). By performing the above steps ST1 to ST8, ST8a to ST8g, steps ST9 and ST10, a semiconductor wafer having a TEG formed on the main surface is prepared. Although not described here, a passivation film that covers the wiring layer on the semiconductor substrate and exposes the upper surface of the pad PD is formed after the pad PD is formed and before performing the following probe inspection. Forming.

  Next, the semiconductor device is inspected by performing a probe inspection (step ST11 in FIG. 10).

  The result obtained by performing the probe inspection in step ST11 in FIG. 10 is fed back to the subsequent manufacturing process of the semiconductor device (step ST12 in FIG. 10).

  Hereinafter, problems of the semiconductor device inspection method of the comparative example described with reference to FIGS. 6 to 10 and effects of the semiconductor device inspection method of the present embodiment will be described.

  First, the semiconductor device of the comparative example described above has a problem that the TEG that can be used in a specific inspection is small on the semiconductor wafer WFa (see FIG. 9). For example, the TEG used for the inspection of the TZDB characteristic is limited in one chip region P6a among a plurality of chip regions P1a to P15a (see FIG. 6) in one region divided by the shot region SHa. It is formed only in the region. Therefore, when inspecting the TZDB characteristic using the TEG, if an attempt is made to obtain a large number of inspection results in order to improve the inspection accuracy, the number of semiconductor wafers WFa (see FIG. 9) having the TEG is, for example, several tens to Thousands of sheets are required. This is not limited to the TZDB characteristics, and the same applies to the evaluation of other characteristics of the semiconductor device, wirings, insulating films, and the like, and the scale of TEGs that can be used for inspection of each characteristic is small.

  In the semiconductor device of the comparative example, in order to perform various inspections within one chip region, the chip region is divided into a plurality of regions, and TEGs for performing specific inspections are formed in the respective regions. Yes. For this reason, the scale of each TEG becomes small. Further, since the layout of the chip regions P1a to P15a (see FIG. 6) in one shot region SHa (see FIG. 6) is different, it can be used for a specific inspection on the semiconductor wafer WFa (see FIG. 9). The scale of TEG is smaller. If the scale of the TEG in one semiconductor wafer WFa is small, it is necessary to inspect a large number of semiconductor wafers WFa in the inspection of a semiconductor device in order to collect a large number of inspection data in order to increase the inspection accuracy. For this reason, the cost required for the test | inspection of a semiconductor device increases by the increase in the process of manufacturing and inspecting the semiconductor wafer WFa containing TEG.

  Further, the semiconductor device of the comparative example described above has a problem that the accuracy of inspection of the semiconductor device is lowered because elements or wirings constituting the TEG have a repeated pattern. That is, for example, there are cases where the semiconductor elements constituting a part of the TEG formed in the chip region have only a configuration in which a plurality of single-shaped semiconductor elements are arranged. In this way, when the TEG is composed of a monotonous repeating pattern such as an element, even if an inspection is performed using the TEG, the obtained inspection result shows that the characteristic or defect of the element having a specific shape is unique. Only will be emphasized.

  That is, when a TEG having a monotonous pattern is used instead of a TEG having a semiconductor element or a wiring pattern formed under various conditions according to various purposes like a semiconductor device manufactured as a product, In the process, abnormalities that are likely to occur in products cannot be found. This causes a problem that the accuracy of the inspection of the semiconductor device is lowered. That is, when the TEG is composed of repeated patterns, it is difficult to detect product-specific characteristics and abnormalities.

  Further, as shown in FIG. 8, the semiconductor device of the comparative example described above has a large number of wiring layers on the semiconductor substrate SB. Therefore, these wiring layers are formed before performing the inspection process of the semiconductor device. There is a problem that a process is required, and it takes time to complete the inspection process, resulting in an increase in cost. In the semiconductor device of the comparative example, as shown in FIG. 6, chip regions P7a to P9a and P11a used as products and chip regions P1a to P6a, P10a and P12a to P15a used only for inspection are mixedly mounted on the same semiconductor wafer WFa. Therefore, it is necessary to form a plurality of wiring layers also on the inspection chip region, and the structure of the apparatus is complicated. Even if there is no chip region used as a product on the semiconductor wafer WFa, if a plurality of wiring layers are formed as shown in FIG. 8, as shown in steps ST8a, ST8b and ST8g in FIG. Since the number of processes increases and the time required for inspection increases, the manufacturing cost of the semiconductor device increases.

  Further, as shown in FIG. 9, in the semiconductor device of the comparative example described above, since there is a region where a specific inspection cannot be performed on the semiconductor wafer WFa, the accuracy is improved with respect to all the chip regions on the semiconductor wafer WFa. There is a problem that high inspection cannot be performed. This is because a region where a TEG that can be used for a specific inspection is formed is limited to a part of one shot region SHa (see FIGS. 6 and 9). In a region away from the TEG, for example, a chip region in the vicinity of the peripheral edge of the semiconductor wafer WFa, or a chip region between a plurality of the TEGs, characteristics to be evaluated by the inspection cannot be accurately grasped.

  For this reason, in the inspection using the semiconductor device of the comparative example, there is a problem that it becomes easy to overlook defects and the like that are likely to occur in the vicinity of the peripheral portion of the semiconductor wafer WFa, and the accuracy of the inspection of the semiconductor device is lowered.

  Here, as a solution to the above problems caused by the small layout of the TEG in the chip area and the repetition pattern as described above, the same mask is used as the product. It is conceivable to form a semiconductor element and a wiring layer for inspection with the same layout. However, if the wiring layer is formed in the same layout as the product and a plurality of wiring layers are formed in the same manner as the product, it is difficult to perform probe inspection by directly applying a potential to a specific semiconductor element. Further, when a plurality of wiring layers are formed, there arises a problem that the manufacturing cost increases as described above.

  Furthermore, when a plurality of wiring layers are formed in the same layout as the product, the chip area for inspection is separated into pieces by a dicing process to form a semiconductor chip, and the semiconductor chip is mounted on a die pad and incorporated in a package. It may be necessary to perform an inspection. In this case, the cost required for performing the inspection process further increases.

  In addition, if a plurality of wiring layers are formed as in the case as described above, it may be necessary to repeatedly perform an extra stress test, which increases the time required for inspecting the semiconductor device. For example, when the memory gate electrode MG (see FIG. 4) constituting the memory cell Q1 of the nonvolatile memory as shown in FIG. 8 is formed in a self-aligned manner by anisotropic etching, if the etching time is increased, the memory The breakdown voltage between the gate electrode MG and the semiconductor substrate SB (see FIG. 8) is improved. When inspecting characteristics of a semiconductor element or the like that changes due to a change in manufacturing conditions such as etching time, that is, a change in the manufacturing process of a semiconductor device, a plurality of wiring layers are formed on the semiconductor substrate SB as described above. In the case of being formed, as described below, it is conceivable to collect inspection data by repeatedly performing a process of applying stress to the element and the probe inspection.

  That is, when examining the breakdown voltage of a semiconductor element when a large number of wiring layers are stacked in the same manner as a product, first, a semiconductor element (for example, a memory cell Q1 or a high breakdown voltage MOSFET Q2) constituting the TEG is placed on the wiring layer. For example, a voltage is applied through the pad for about 20 seconds to apply stress to the semiconductor element. Next, probe inspection is performed to inspect whether or not the semiconductor element operates. When the semiconductor element operates, a voltage is applied to the semiconductor element for a longer time to apply a greater stress, and then a probe test is performed again to check whether the semiconductor element operates.

  Thus, in a semiconductor device in which a plurality of wiring layers are stacked on a semiconductor substrate, when examining the breakdown voltage of a semiconductor element constituting the TEG, it is possible to repeatedly apply a long-time stress and perform a probe test. Determine the stress conditions that cause the device to short circuit. The voltage application for applying stress to the semiconductor element takes about 100 seconds at a time if it is long. As described above, in a semiconductor device in which a plurality of wiring layers are formed and the wiring layers and the pads on the wiring layers are formed in the same manner as the product, it is possible to directly apply a voltage to the semiconductor element and inspect the current flowing through the semiconductor element. Since it is difficult, it is necessary to repeat the application of stress and the probe inspection as described above. Therefore, there arises a problem that the process and time required for the inspection increase.

  In contrast, the TEG used in the semiconductor device inspection method of the present embodiment forms the layout of the chip region CR (see FIG. 1) on the semiconductor wafer WF (see FIG. 1) with the same layout as the product. . In addition, the plurality of chip regions CR on the semiconductor wafer WF are all formed in the same layout. That is, as shown in FIG. 3, the layout in one chip region P1 is the same as that of a semiconductor chip manufactured as a product. Therefore, all TEGs used in the present embodiment are formed using the same mask as that used in the manufacturing process of the product semiconductor device. Thereby, a TEG used for a specific inspection can be formed on a large scale on one semiconductor wafer WF.

  For this reason, for example, a MOSFET that can be used for evaluation of the TZDB characteristic is formed not over a limited region in the chip region P1, but over a wide range. That is, in the chip region P6a of the comparative example shown in FIG. 7, since the region is divided for each inspection object and the TEG is separately created, the region including the TEG for evaluating specific characteristics is, for example, one. It was limited.

  However, in this embodiment, the layout of the chip area is not divided according to the inspection object. Therefore, in the chip region P1 shown in FIG. 3, for example, MOSFETs that can be used for evaluating TZDB characteristics are formed in a wide range in the chip region P1. Therefore, since the scale of the TEG in one chip region is larger than that of the comparative example, the number of semiconductor wafers used for the inspection can be reduced without reducing the inspection accuracy. That is, more sensitive evaluation can be performed with fewer steps compared to the comparative example.

  In the present embodiment, since all the chip areas P1 to P15 in the shot area SH shown in FIG. 2 are inspection areas having the same layout, all the chip areas of the semiconductor wafer WF shown in FIG. CR can be used for the same inspection. For example, the inspection of the TZDB characteristic can be performed on all the chip regions CR on the semiconductor wafer WF. That is, the TEG is made larger in this embodiment than the comparative example in which the chip area that can be used for a specific inspection exists only in a part of the shot area.

  In the inspection performed using the semiconductor device of the comparative example, several tens to several thousand semiconductor wafers must be used in order to collect the number of inspection results necessary to increase the inspection accuracy to a certain level. On the other hand, in this embodiment, even if the number of semiconductor wafers used for inspection is about several, it is possible to obtain the number of inspection results necessary to realize the above-described certain level of inspection system. As a result, the number and time of semiconductor wafers required for the inspection process of the semiconductor device can be reduced, and the cost required for the inspection can be reduced without reducing the accuracy of the inspection.

  In the present embodiment, since the layout in each chip region is the same as that of a semiconductor chip manufactured as a product, the TEG configuration is not a monotonous repetitive pattern, but includes TEGs having various sizes or characteristics. It is out. Since the layout of the semiconductor elements constituting the TEG used for the inspection is the same as that of the product, it is possible to easily detect an abnormality that easily occurs in the product and to inspect the characteristics of the semiconductor element used in the product. For this reason, the accuracy of the inspection of the semiconductor device can be increased.

  When a TEG in which semiconductor elements having the same size and characteristics are arranged as in the comparative example is used, the semiconductor element can be inspected, but semiconductor elements having different sizes cannot be evaluated. On the other hand, in the semiconductor device for inspection according to the present embodiment, since the elements in the chip region are formed with a layout according to the product, various semiconductor elements are included in the chip region. For example, in a MOSFET, a large number of elements having different parameters such as gate length, gate width, impurity concentration of source / drain regions, or gate insulating film thickness exist in one chip region. Therefore, test results can be obtained not only for elements having specific shapes and characteristics but also for various elements.

  In addition, in order to inspect elements having various shapes and characteristics, it is not necessary to prepare a plurality of types of semiconductor wafers. Furthermore, since the TEG is formed using the same mask as the product, it is not necessary to prepare a new TEG mask. For this reason, the manufacturing cost of the semiconductor device used for inspection can be reduced.

  In the present embodiment, as shown in FIG. 4, there is only one wiring layer on the interlayer insulating film ILF covering the semiconductor elements on the semiconductor substrate SB. That is, the semiconductor element constituting the TEG is electrically connected to the probe PD pad using only the contact plug C1, the via V1, and the first layer wiring M1. Therefore, as compared with the case where a plurality of wiring layers are formed on the semiconductor substrate SB as shown in FIG. 8, the cost for forming the semiconductor device for inspection is reduced, and the time required for manufacturing the semiconductor device for inspection is reduced. It is possible to shorten the time required to complete the inspection including

  One of the reasons why the number of wiring layers can be omitted as described above is that there is no chip area used for manufacturing products on the semiconductor wafer WF (see FIG. 1), and all chip areas on the semiconductor wafer WF are present. Is used for inspection, it is not necessary to form a plurality of wiring layers on the TEG. When only one wiring layer is used, it is difficult to connect all the elements to the pad PD as compared with the case where a plurality of wiring layers are formed. However, this problem is caused by bundling the same kind of semiconductor elements. It can be resolved by connecting the wires.

  In this embodiment, the pad and the TEG are connected using only one wiring layer, and power can be directly supplied to the TEG. For example, when the layout in the chip area is a TEG similar to a product and a plurality of wiring layers are formed in the same manner as the product, in order to supply a potential to the semiconductor element in the core portion, I / O It is necessary to pass through the element used. On the other hand, in the present embodiment, there is only one wiring layer, and the layout of the wiring layer and the pad is not the same as the product, so even if it is a semiconductor element such as a low breakdown voltage MOSFET in the core part, It is possible to directly supply a potential and measure a current.

  In addition, since it does not have a plurality of wiring layers like a product, there is no need to inspect after a process of forming a semiconductor chip by dicing the chip region into pieces by dicing and further incorporating the semiconductor chip into a package. Does not occur. For this reason, the time required for the inspection process can be shortened, and the manufacturing cost of the semiconductor device used for the inspection can be reduced.

  In the present embodiment, the case where only one wiring layer is used is exemplified, but a TEG formed by adding one more wiring layer may be used. That is, in this embodiment, only one or two wiring layers are formed. When two wiring layers are formed, the manufacturing cost for one layer is generated as compared with the case where only one wiring layer is formed, but it is necessary to form a large number of wiring layers of three or more layers as in the comparative example. The inspection can be performed at a minimum cost. Note that the use of two wiring layers in this manner can increase the degree of freedom in layout for wiring connection.

  In the present embodiment, since all the chip regions CR on the semiconductor wafer WF shown in FIG. 1 have the same layout, an inspection performed for a specific purpose is performed on all the chip regions CR on the semiconductor wafer WF. Can be implemented. In the semiconductor wafer WFa of the comparative example shown in FIG. 9, the chip region CR that can be an inspection target in a specific inspection item is limited to a part of the shot region SHa. For this reason, it is difficult to inspect all the chip regions on the semiconductor wafer WFa. On the other hand, in the present embodiment, an inspection can be performed without overlooking an abnormality even in the chip region CR near the peripheral edge of the semiconductor wafer WF.

  Thereby, in this Embodiment, it can test | inspect, without overlooking a characteristic which changes with places, such as a center part or a peripheral part, among the upper surfaces of a semiconductor wafer. In addition, the inspection can be performed without overlooking an abnormality or the like having a different occurrence frequency depending on the location on the upper surface of the semiconductor wafer. For this reason, the accuracy of the inspection of the semiconductor device can be improved.

  Further, in the present embodiment, it is possible to supply power to the TEG more directly than in the case of forming a plurality of wiring layers, so that it is not necessary to repeatedly perform unnecessary stress tests. For example, when inspecting the breakdown voltage characteristic depending on the etching time for the memory gate electrode MG shown in FIG. 4, a potential is directly supplied to the memory gate electrode MG via the pad PD and the first wiring layer M1, and the memory gate electrode MG and By inspecting the value of the current between the semiconductor substrates SB, it is possible to inspect the withstand voltage between the memory gate electrode MG and the semiconductor substrate SB.

  In this case, if a voltage is applied to the memory gate electrode MG, the voltage is gradually increased, and the value of the voltage at the time when the current value suddenly increases is detected, between the memory gate electrode MG and the semiconductor substrate SB. It is possible to check the withstand voltage. As described above, the step of applying a voltage to raise it and checking the withstand voltage is performed by probe inspection. The time required for this inspection is several seconds.

  When a TEG is formed with the same layout as the product and a plurality of wiring layers are formed with the same layout as the product, the potential is directly supplied to the elements constituting the TEG, and the current of the TEG is supplied. It may not be possible to measure. In such a case, in the inspection process for examining the breakdown voltage of the element, it is necessary to repeat the process of applying stress to the element and the probe inspection as described above.

  On the other hand, in the semiconductor device used for the inspection of the present embodiment, the layout of the TEG including the semiconductor elements on the semiconductor substrate SB (see FIG. 4) is the same as that of the product, and the wiring layer on the TEG is inspected. Since there is only one wiring layer for the device, each element constituting the TEG can be directly electrically accessed. Therefore, it is possible to inspect the characteristics of the semiconductor element only by performing a simple probe inspection without performing an extra stress test for the inspection. Therefore, since the inspection is simple, the time required for the inspection can be shortened.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

B1 to B7, B8a, B8b, BF Barrier insulating film C1 Contact plug CG Control gate electrode (selection gate electrode)
CP capacitive element CR Chip region D1d, D1s, D2, D3 n ⁺ type semiconductor region ES Stopper insulating film G2, G3 Gate electrodes GF1 to GF3 Gate insulating film IE Element isolation region IF1, IF2 Insulating film ILF Interlayer insulating film ES Stopper insulating film L1, L2, L2a, L3 to L7, L8a, L8b, L9 Interlayer insulating film M1, M1a First layer wiring M2 Second layer wiring M3 Third layer wiring M4 Fourth layer wiring M5 Fifth layer wiring M6 Sixth layer wiring M7 7th layer wiring M8 8th layer wiring MG Memory gate electrode (memory gate electrode)
OX ONO films P1 to P15, P1a to P15a Chip area PD Pad PS1, PS2 Polysilicon film Q1 Memory cell Q2 High voltage MOSFET
Q3 Low voltage MOSFET
R1-R11 Region S1 Silicide layer SB Semiconductor substrate SH, SH Shot region SL Scribe region SW Side walls V1, V1a, V2-V8 Via WF, WFa Semiconductor wafer

Claims (6)

(A) A wiring layer having a chip region including a TEG formed in the same layout as a semiconductor chip for a product, and electrically connecting the TEG and a pad on the TEG is provided between the TEG and the pad. Preparing a semiconductor device in which only one layer or only two layers are formed;
(B) supplying a potential to the TEG via the pad and evaluating the TEG;
A method for inspecting a semiconductor device. The method for inspecting a semiconductor device according to claim 1,
The TEG includes a memory element, a first field effect transistor, a second field effect transistor having a lower withstand voltage than the first field effect transistor, and a capacitor element in one chip region. The method for inspecting a semiconductor device according to claim 1,
The TEG is a method for inspecting a semiconductor device, which is formed using a mask used when manufacturing a semiconductor chip for the product. The method for inspecting a semiconductor device according to claim 1,
A method for inspecting a semiconductor device, wherein a plurality of the chip regions are provided side by side. The semiconductor device inspection method according to claim 4,
A method for inspecting a semiconductor device, wherein each of the plurality of chip regions in a shot region exposed at a time has the same layout. The method for inspecting a semiconductor device according to claim 1,
The method for inspecting a semiconductor device, in which only one layer of the wiring layer is formed between the TEG and the pad.

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