JP2014120530A - Stack lsi chip - Google Patents

Abstract

Provided is a multilayer LSI chip that can reduce parasitic impedance generated between communication driver circuits and can more easily grasp the parasitic impedance.
Each LSI chip of a laminated LSI chip has a bidirectional communication driver circuit for communicating between the LSI chips through each through electrode. The communication driver circuit 51 is disposed in the chip central region P and in the vicinity of the corresponding through electrode 20.
[Selection] Figure 2

Description

  The present invention relates to a stacked LSI chip having a plurality of through electrodes in a chip central region and configured by stacking a plurality of LSI chips.

  In order to achieve high integration of semiconductor devices, a three-dimensional mounting technique has been developed in which a plurality of LSI chips are stacked to form a stacked LSI chip. As one of the three-dimensional mounting techniques, a plurality of through-electrodes that function as a communication bus by penetrating each layer of LSI chips in a stacked LSI chip in the vertical direction (that is, in the chip thickness direction) are arranged in parallel in the central region of the chip plane Has already been proposed (see Patent Document 1). According to this, the through-electrodes collected in the chip central region can constitute, for example, a massively parallel system bus, and a low power consumption system can be realized.

  In addition, in order to perform communication between LSI chips of each layer through the through electrode, communication driver circuits are provided in the LSI chips of a plurality of layers.

JP 2010-1556569 A

  By the way, in the multilayer LSI chip as described above, a unique communication load is imposed between a plurality of communication driver circuits by vias constituting through electrodes of each layer, bumps connecting upper and lower layer vias, or the like. Parasitic impedance is generated.

  The parasitic impedance described above greatly affects the power consumption, circuit delay time, etc. of the laminated LSI chip, and its reduction is required. However, in recent years when low-power consumption and high-speed communication of a laminated LSI chip are promoted, the reduction has not been sufficiently achieved. Further, in designing a circuit in consideration of parasitic impedance, it is necessary to grasp the parasitic impedance, but the calculation is complicated and difficult to grasp.

  The present invention has been made in view of the above points, and provides a multilayer LSI chip that can reduce the parasitic impedance between the communication driver circuits as described above and can more easily grasp the parasitic impedance between the communication driver circuits. That is the purpose.

  In order to achieve the above object, the present invention provides a stacked LSI chip having a plurality of through electrodes in a chip central region and formed by stacking a plurality of LSI chips, each LSI chip being connected to an LSI through the through electrodes. A multilayer communication driver circuit for performing communication between chips for each through electrode, and the communication driver circuit is disposed in the center region of the chip and in the vicinity of the corresponding through electrode. LSI chip.

  The through electrodes are arranged in a matrix that is vertically and horizontally as viewed from above, and each of the communication driver circuits is on a straight line along the array of the through electrodes and in the vicinity of the same side with respect to the corresponding through electrode. It may be arranged.

  The communication driver circuit disposed between adjacent through electrodes on the array may be located at the center of the adjacent through electrodes.

  The communication driver circuits may be arranged on a straight line connecting the arranged through electrodes in an oblique direction and in the vicinity of the same side with respect to the corresponding through electrodes.

  Furthermore, each of the communication driver circuits may be located at the center between four adjacent through electrodes.

  In addition, the through electrodes are arranged in a matrix that is vertically and horizontally as viewed from above, and the communication driver circuits of the four adjacent through electrodes may be collectively located at the center between the four through electrodes. Good.

  An insulating film made of an organic resin may be formed between the vias constituting the through electrodes in the LSI chips and the side wall surfaces of the via holes.

It is a schematic diagram which shows the structure of the semiconductor device which has a lamination LSI chip. It is a schematic diagram which shows the structure of a laminated LSI chip and the structure of a parasitic impedance. It is explanatory drawing which shows the example of arrangement | positioning of a communication driver circuit and a penetration electrode. It is explanatory drawing which shows the distance of a communication driver circuit and a penetration electrode. It is explanatory drawing which shows the other example of arrangement | positioning of a communication driver circuit and a penetration electrode. It is explanatory drawing which shows the distance of a communication driver circuit and a penetration electrode. It is explanatory drawing which shows the other example of arrangement | positioning of a communication driver circuit and a penetration electrode.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram showing an example of a configuration of a semiconductor device 1 on which a laminated LSI chip is mounted.

  As shown in FIG. 1, the semiconductor device 1 includes a stacked LSI chip 11 formed by stacking a plurality of LSI chips 10 and a package substrate 13 that supports the stacked LSI chip 11 via an interposer 12.

  The stacked LSI chip 11 has a plurality of, preferably several tens, hundreds, and thousands units of communication buses penetrating the LSI chip 10 of each layer in the chip central region (TSV placement region) P in the vertical direction. A through electrode 20 is provided. In the through electrode 20, vias 30 such as TSVs (Through silicon vias) penetrating vertically in each LSI chip 10 are aligned with each other in a vertical straight line, and the vias 30 are joined by bumps 31 between the upper and lower LSI chips 10. It is configured. The lower end of the through electrode 20, that is, the lowermost via 30 is electrically connected to the electrode of the interposer 12 via the lowermost bump 31. A large number of through-electrodes 20 formed in parallel in the central region of the chip constitute, for example, a massively parallel system bus to realize a low power consumption system.

  The interposer 12 and the package substrate 13 are electrically connected to each other by bumps 31. The gap between the LSI chips 10 and the gap between the lowermost LSI chip 10 and the interposer 12 are shielded from outside air for reliability. In order to improve the above, a filler such as an underfill resin having an insulating property and a low thermal conductivity is filled.

  In each LSI chip 10, for example, as shown in FIG. 2, a conductor via 30 is embedded in a via hole 41 formed in the chip substrate 40, and an insulating film 42 is formed between the via 30 and the side wall surface of the via hole 41. Is formed. Pad electrodes 43 that cover the vias 30 are formed on the upper and lower end surfaces of the vias 30, and the pad electrodes 43 of the LSI chips 10 that are vertically adjacent to each other are joined by bumps 31. As the insulating film 42, an inorganic insulating film such as silicon oxide or silicon nitride and an organic resin film such as parylene, polyimide, silicon resin, or BCB are used. The organic resin film is more desirable from the viewpoint of reducing internal stress.

  As shown in FIG. 1, a communication interface chip 50 is provided in a chip central region P where each LSI chip 10 has a via 30. The communication interface chip 50 is provided with a bidirectional communication driver circuit 51 for performing communication between the LSI chips 10 through the through electrodes 20 as shown in FIG. The communication driver circuit 51 is provided for each through electrode 20 (via 30). The communication driver circuit 51 is disposed in the vicinity of the corresponding through electrode 20, for example, within 2 times, more preferably within 1 time, of the arrangement pitch interval from the through electrode 20 to the through electrode 20.

  As illustrated in FIG. 3, the through electrodes 20 (vias 30) and the pad electrodes 43 are arranged in a matrix arranged vertically and horizontally as viewed from the plane. The communication driver circuit 51 is arranged on a straight line along the vertical and horizontal arrangement of the through electrodes 20 and in the vicinity of the corresponding through electrode 20 on the same side (the lower side in the drawing in FIG. 3). A wiring region T <b> 1 that communicates with the outside of the communication interface chip 50 is formed between the columns of the through electrodes 20 and the communication driver circuit 51.

  Further, the distance D1 between the communication driver circuit 51 shown in FIG. 4 and the corresponding through electrode 20 is set to be the same. For example, the communication driver circuit 51 is located at the center of the through electrode 20 adjacent to both sides thereof.

  In the laminated LSI chip 11 configured as described above, when communication is performed between arbitrary LSI chips 10, for example, a signal is transmitted from the communication driver circuit 51 of the nth LSI chip 10 as shown in FIG. When the signal is output, the signal is sequentially transmitted from the pad electrode 43 of the nth LSI chip 10 to the via 30 and the bump 31 of the through electrode 20, the via 30 and the bump 31 of the n−1th LSI chip 10 in order, for example. As described above, the signal is sent to the communication driver circuit 51 from the pad electrode 43 of the LSI chip 10 of the k-th layer as the communication destination.

  At this time, between the communication driver circuit 51 of the transmission source and the transmission destination, for example, the resistance R1 of the via 30 of each LSI chip 10 on the communication bus, the resistance R2 of the bump 31 between the LSI chips 10, and the insulating film 42 Although the parasitic impedance I as a load including the capacitance C1 and the like is generated, since the communication driver circuit 51 is disposed in the vicinity of the through electrode 20, the impedance between the communication driver circuit 51 and the via 30 is extremely small. It becomes negligible.

  Therefore, according to the present embodiment, the parasitic impedance I generated between the transmission source and transmission destination communication driver circuits 51 can be reduced. In addition, since it is not necessary to consider the parasitic impedance between the communication driver circuit 51 and the through electrode 20, the calculation of the parasitic impedance I is simplified and the parasitic impedance I can be grasped more easily.

  That is, according to the present invention, the parasitic impedance I generated between the communication driver circuits 51 can be reduced, so that low power consumption and high speed communication of the multilayer LSI chip 11 can be achieved. Further, since the parasitic impedance I can be grasped more easily, the circuit design of the laminated LSI chip 11 can be easily performed.

  In addition, for example, the communication driver circuit 51 is arranged on a straight line along the arrangement of the through electrodes 20 and in the vicinity of the corresponding through electrode 20 on the same side. A wiring region T1 for wiring from the via 30 or the pad electrode 43 to the outside of the communication interface chip 50 can be secured. In the example of FIG. 3, each communication driver circuit 51 is arranged below the through electrode 20 in a plan view. However, of course, the communication driver circuit 51 is not limited to this position, and one set including the through electrode 20, the pad electrode 43, and the communication driver 51. In the vicinity of the array provided on a plurality of straight lines (in the example of FIG. 3, the column in the vertical direction in plan view), it is only necessary to secure a plurality of wiring regions T1 for each set.

  Further, for example, as shown in FIG. 4, the distance D1 between the communication driver circuit 51 and the corresponding through electrode 20 can be set to be the same. It is possible to further simplify the circuit design in consideration of the load impedance of the communication driver circuit 51 and to minimize power consumption by setting the distance to the through electrode 20 to be the shortest and constant. Note that the communication driver circuit 51 is generally arranged outside the TSV arrangement region. In that case, the distance between the communication driver circuit 51 and the through electrode 20 is in a separated state, and it is necessary to design the communication driver circuit 51 by assuming the value of the longest wiring for the wiring capacitance serving as the load of the communication driver circuit 51. There is. Since it is necessary to employ the communication driver circuit 51 having a large driving capability, the power consumption is unnecessarily designed.

  Furthermore, the communication driver circuit 51 arranged between the adjacent through electrodes 20 on the array is arranged at the center position between the adjacent through electrodes 20, so that an empty area between the adjacent through electrodes 20 is effective. This makes it easy to secure the wiring area from the circuit outside the TSV arrangement area to each through electrode 20 (via 30).

  Unlike the arrangement example of FIG. 3, the communication driver circuit 51 takes a straight line connecting the through electrodes 20 arranged in a matrix in an oblique direction as shown in FIG. 20 may be arranged in the vicinity of the same side (in FIG. 5, it is the lower right side in plan view, but of course not limited to this). Also in this case, for example, the distance D2 (shown in FIG. 6) between the communication driver circuit 51 and the corresponding through electrode 20 can all be set to the same distance, and also seen from the four adjacent through electrodes 20 The communication driver circuit 51 can be disposed at the center position of the four through electrodes 20.

  According to this example, for example, as shown in FIG. 5, an oblique wiring region T <b> 2 for wiring from each via 30 or pad electrode 43 to the outside of the communication interface chip 50 can be secured. In addition, the distance between the communication driver circuit 51 and the through electrode 20 in each layer can be made constant so that the design of the communication driver circuit in consideration of the load impedance can be further simplified. Accordingly, the communication driver circuit 51 can be arranged and wired more easily at the center position of 20.

  When the through electrodes 20 are arranged in a matrix as viewed from above as described above, the communication driver circuits 51 of the four adjacent through electrodes 20 are arranged between the four through electrodes 20 as shown in FIG. You may be located in the center of. Even in such a case, it is easy to secure a wiring region connecting each through electrode 20 to the outside of the interface chip 50.

  In addition to the various arrangements of the communication driver circuit 51 described above, for example, by using a flexible organic resin for the insulating film 42 provided between the conductor via 30 and the side wall surface of the via hole 41, internal stress of the through electrode 20 can be obtained. Accordingly, the communication driver circuit 51 can be appropriately provided in the vicinity of the through electrode 20. When the internal stress of the through electrode 20 is large, the characteristics of the transistors arranged around the through electrode 20 fluctuate. Therefore, a region in which a transistor is prohibited from being disposed within a certain distance from the through electrode 20 (Deep Out Zone) is generally used. On the other hand, if the internal stress of the through electrode 20 is small, the transistor can be disposed in the vicinity of the through electrode 20 without affecting the characteristics of the transistor.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood.

  For example, the present invention can be applied even if the semiconductor device 1, the stacked LSI chip 11, the LSI chip 10 and the like in the present embodiment have other configurations.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 LSI chip 11 Stacked LSI chip 20 Through-electrode 30 Via 31 Bump 40 Chip substrate 41 Via hole 42 Insulating film 43 Pad electrode 50 Communication interface chip 51 Communication driver circuit P Chip center area

Claims (7)

A laminated LSI chip having a plurality of through-electrodes in a chip central region and configured by laminating a plurality of LSI chips,
Each LSI chip has a bidirectional communication driver circuit for performing communication between LSI chips through the through electrodes for each through electrode,
The stacked LSI chip, wherein the communication driver circuit is disposed in the chip central region and in the vicinity of a corresponding through electrode. The through electrodes are arranged in a matrix shape vertically and horizontally as viewed from above.
2. The multilayer LSI chip according to claim 1, wherein each of the communication driver circuits is arranged on a straight line along the arrangement of the through electrodes and in the vicinity of the same side with respect to the corresponding through electrode.   The multilayer LSI chip according to claim 2, wherein the communication driver circuit disposed between adjacent through electrodes on the array is located at the center of the adjacent through electrodes. The through electrodes are arranged in a matrix shape vertically and horizontally as viewed from above.
2. The multilayer LSI chip according to claim 1, wherein each of the communication driver circuits is arranged on a straight line connecting the arranged through electrodes in an oblique direction and in the vicinity of the same side with respect to the corresponding through electrode.   The multilayer LSI chip according to claim 4, wherein each of the communication driver circuits is located at a center between four adjacent through electrodes. The through electrodes are arranged in a matrix shape vertically and horizontally as viewed from above.
2. The multilayer LSI chip according to claim 1, wherein the communication driver circuits of the four adjacent through electrodes are collectively located at a center between the four through electrodes.   The multilayer LSI chip according to any one of claims 1 to 6, wherein an insulating film made of an organic resin is formed between a via constituting the through electrode in each LSI chip and a side wall surface of the via hole.