JP2014115412A - Light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply a data signal to a gate of a driving transistor, hold it in a gate-source capacitor, and supply a current from a source to a light emitting element, and the voltage held in the capacitor is a data signal. It does not match.
A driving transistor (DT) having a drain disposed on a power supply (Voled) side and a source disposed on a reference potential (Vcom) side, and a light emitting element disposed between the source of the driving transistor and a reference potential EL) and a storage capacitor (CS) disposed between the gate and source of the drive transistor, and a light emitting device that emits light by supplying a current corresponding to the voltage of the storage capacitor from the drive transistor to the light emitting element. And
A light emitting device, wherein a switch (SW) is provided in series in a current path from a source of a driving transistor to a storage capacitor.
[Selection] Figure 1

Description

  The present invention relates to a light emitting device such as a display device and a lighting device, and more particularly to a light emitting device in which a plurality of pixels including light emitting elements are arranged.

  A light-emitting device including a plurality of light-emitting elements has a configuration in which a plurality of pixels including light-emitting elements are arranged in a line shape or a matrix shape, and a drive circuit is connected to the light-emitting elements of each pixel. In order to cause the light emitting element of each pixel to emit light with luminance according to image data, the amount of current flowing from the drive circuit to the light emitting element must be accurately controlled. However, there is a problem in that the luminance of the light emitting element varies because the characteristics of the transistors constituting the driver circuit are not uniform. On the other hand, Patent Document 1 discloses a drive circuit that makes the current flowing through the light emitting element uniform regardless of non-uniform characteristics.

  FIG. 17 is a circuit diagram of a typical drive circuit in Patent Document 1. In FIG.

  An organic electroluminescence element (hereinafter referred to as an organic EL element) EL driving circuit includes a driving transistor DT, a storage capacitor CS connecting the gate G and the source S of the driving transistor DT, and connecting the gate G and the data line Data. The transistor M is a selection switch.

  The organic EL element EL has a structure in which an organic material layer is sandwiched between an anode and a cathode, and itself forms one capacitor CL.

  As an initial state, a voltage exceeding the threshold voltage of the drive transistor DT is given to the storage capacitor CS. When the selection switch M is turned on and the gate and the data line Data are connected, a transient current flows from the source S of the drive transistor DT to the data line Data via the storage capacitor CS, and the voltage of the source S of the drive transistor DT increases. This current stops when the gate-source voltage becomes equal to the threshold voltage. The potential across the storage capacitor CS after stopping the current is equal to the threshold voltage of the drive transistor DT.

  Next, when the voltage of the data line Data is changed by the amount corresponding to the data voltage, the gate voltage changes accordingly. However, since the capacity CL of the organic EL element is sufficiently larger than the storage capacity CS, the source potential hardly rises. As a result, the voltage across the storage capacitor CS exceeds the threshold value of the drive transistor DT, turning on the drive transistor. The voltage across the holding capacitor CS is held even after the selection switch M is turned off, and the drive transistor DT supplies a current corresponding to this voltage to the organic EL element EL.

  When a current flows through the organic EL element EL, the capacitor CL of the organic EL element EL is charged, and the anode voltage increases. Since the selection switch M is off, the gate voltage also increases accordingly, and the voltage across the storage capacitor CS does not change. Accordingly, the drive transistor DT continues to supply a constant current to the organic EL element EL.

  In the drive circuit of FIG. 17, when a data voltage is applied to the data line while the selection switch M is on, a current flows through the drive transistor because the gate-source voltage of the drive transistor DT exceeds the threshold voltage. Since part of this current also flows through the storage capacitor CS, the voltage held in the storage capacitor CS changes.

  In Patent Document 2, as in FIG. 17, in a drive circuit having an organic EL element on the source side of the drive transistor and having a storage capacitor between the gate and the source, a current cutoff switch between the drain of the drive transistor and the power supply An invention providing the above is disclosed. When the selection switch M is on, this switch is turned off so that no current flows through the drive transistor DT. Thereby, the voltage change of the storage capacitor CS is prevented.

JP 2003-271095 A JP 2004-280059 A

  In the circuit of FIG. 17, when the selection switch M is turned on and a data voltage is applied to the gate of the drive transistor DT, the gate-source voltage of the drive transistor DT exceeds the threshold voltage, and the drive transistor DT becomes conductive. While the selection switch M is on, the current flowing through the drive transistor DT flows to the capacitor of the organic EL element and charges the capacitor, and part of the current flows to the data line through the holding capacitor CS and the selection switch M. As a result, the voltage of the storage capacitor changes and deviates from a predetermined value given from the data line.

  In the invention of Patent Document 2, a switch is provided on the drain side of the drive transistor DT so that no current flows through the drive transistor DT while the selection switch M is on. However, also in this case, when the gate voltage of the driving transistor DT changes, a transient current flows from the gate to the source via the parasitic capacitance between the gate and the source of the driving transistor DT. Although this current is transient, it still flows through the storage capacitor and changes the voltage of the storage capacitor.

  In the driving circuit in which the source of the driving transistor is connected to the light emitting element and the storage capacitor is connected between the gate and the source, the driving transistor flows when a signal voltage is applied to the gate. The voltage between the terminals of the storage capacitor changes due to the current, and deviates from the voltage corresponding to the signal voltage.

  The size of the parasitic capacitance CL is determined by the area of the organic EL element. Although a method of suppressing the change in the voltage between the terminals by increasing the value of the storage capacitor CS is also conceivable, a large area is required to form a large storage capacitor, and in a light emitting device in which the pixel size is limited, It is difficult to secure the area.

  An object of the present invention is to provide a drive circuit that can program an accurate voltage by eliminating a voltage change of a storage capacitor while a selection switch is on.

According to a first aspect of the present invention, a drive transistor having a drain disposed on a power supply side and a source disposed on a reference potential side, a light emitting element disposed between the source of the drive transistor and the reference potential, and the drive transistor A light-emitting device that emits light from the drive transistor by supplying a current corresponding to the voltage of the storage capacitor from the drive transistor to the light-emitting element,
A first switch in series is provided in a current path from the source of the driving transistor to the storage capacitor.

According to a second aspect of the present invention, there is provided a drive transistor having a drain disposed on the power supply side and a source disposed on the reference potential side, a storage capacitor disposed between the gate and the source of the drive transistor, and the drive transistor. A driving method for driving a light emitting element arranged between a source of the driving transistor and the reference potential using a driving circuit having a switch arranged in series in a current path leading to the storage capacitor,
A first step of applying a voltage to both ends of the storage capacitor; and applying the same voltage to the terminal of the storage capacitor disposed on the gate side of the drive transistor as in the first step, causing the switch to conduct, A second step of passing a current from the source of the driving transistor to the storage capacitor; a third step of cutting off the switch and applying a data voltage to the gate of the driving transistor; and a power source for supplying the data voltage to the driving transistor. It has the 4th step which isolate | separates from a gate and makes the said switch conductive.

  According to the present invention, even if the drive circuit is turned on during programming, no current flows into the storage capacitor, so that an accurate voltage can be held.

1 is a drive circuit for an organic EL element according to an embodiment of the present invention. 2 is a timing chart showing the operation of the drive circuit of FIG. 1. It is a drive circuit of an organic EL element when a drive transistor is P type. 1 is a circuit diagram showing a pixel configuration of a first example of the present invention. FIG. 1 is an overall block diagram of a display device according to a first embodiment. It is a timing chart which shows the circuit operation | movement of a 1st Example. It is a circuit diagram which shows the pixel structure of the 2nd Example of this invention. It is a timing chart which shows the circuit operation of the 2nd example. It is a circuit diagram which shows the pixel structure of the 3rd Example of this invention. It is a timing chart which shows operation | movement of a 3rd Example. It is a circuit diagram which shows the pixel structure of the 4th Example of this invention. It is a timing chart which shows operation | movement of a 4th Example. It is a circuit diagram which shows the pixel structure of the 5th Example of this invention. It is a timing chart which shows operation | movement of a 5th Example. It is a block diagram which shows the structure of the digital still camera system which is an application example of this invention. It is a block diagram showing a configuration of an exposure head of an electrophotographic printer which is an application example of the present invention. It is the drive circuit of the conventional light emitting element.

  In a drive circuit in which the drain of the drive transistor is connected to the power source, the source is connected to the light emitting element, and a storage capacitor is provided between the gate and the source, a selection transistor is provided between the gate of the drive transistor and the data line, and it is turned on. Apply a data voltage to the gate. Although the drive transistor is in a conductive state, a series switch is provided in the middle of the current path from the source of the drive transistor to the storage capacitor, and the switch transistor is turned off while the selection transistor is on, so that current is supplied to the drive transistor. Even if it flows, it can be prevented from flowing into the holding capacity. As a result, the voltage across the storage capacitor can be maintained.

  FIG. 1 is a circuit diagram showing a configuration of a light emitting device according to an embodiment of the present invention.

  In the light emitting device, a drive transistor DT and an organic EL element EL are arranged in series between a power supply Voled and a reference potential Vcom (ground potential). The drive transistor DT has a drain D on the power supply side and a source S on the power supply side. The organic EL element EL is disposed on the reference voltage side, and the storage capacitor CS and the first switch SW are disposed in series between the gate and the source.

  The gate side terminal and the source side terminal of the storage capacitor CS are connected to the voltage supply source via the second and third switches, respectively, so that a voltage can be applied independently. These switches are controlled on and off independently or together. When turned off, the voltage at each terminal can change according to the operation of this circuit. The voltage supplied via the second switch and the voltage supplied via the third switch can be set independently.

  FIG. 2 is a timing chart showing the operation of this circuit. In order from the top, the state of the switch SW, the voltage at the node A, that is, the gate G of the driving transistor, the voltage at the terminal (node B) opposite to the node A of the storage capacitor, and the voltage at the source S (node C) of the driving transistor are shown. . The operation of this circuit is described in the following four steps.

  The first step of time t1-t2 is precharge of the storage capacitor CS. Precharging is an operation in which the switch SW is turned on and a constant voltage is applied to both ends of the storage capacitor CS from the external circuit. By this operation, the gate-source voltage of the drive transistor DT exceeds the threshold voltage Vth, and the drive transistor DT becomes conductive. Furthermore, in this circuit, it is preferable to set the anode voltage of the organic EL element EL to be equal to or lower than the light emission threshold value so that the organic EL element EL does not emit light when the switch SW is turned on. In general, an organic EL element has a light emission threshold value. Below that voltage, the parasitic capacitance of the organic EL element only charges and does not emit light. Accordingly, the precharge applies different voltages to the terminals so that both ends of the storage capacitor CS are voltages that cause the drive transistor to conduct and the source-side terminal is equal to or lower than the light emission threshold of the organic EL. Here, the reference voltage Vref is applied to the gate side terminal A of the storage capacitor, and the precharge voltage Vpre is applied to the source side terminal B. These differences are equal to or higher than the threshold voltage of the driving transistor, and Vpre is equal to or lower than the light emission threshold of the organic EL element.

  The next time t2-t3 is a step of holding the threshold voltage Vth of the drive transistor DT in the holding capacitor CS. The gate side terminal A of the storage capacitor CS is fixed to a constant reference potential Vref, and the switch SW is turned on. Since the drive transistor DT is in a conductive state, a current enters the drain D from the power supply Voled, exits from the source S, and further flows to the storage capacitor CS through the switch SW. Depending on this current, the potential (C) of the source gradually increases, and finally the voltage across the storage capacitor CS becomes equal to the threshold voltage Vth, and the current stops. At this time, the storage capacitor CS holds the threshold voltage Vth of the drive transistor DT. The step of maintaining this threshold voltage is called auto-zero.

  The next time t3-t4 is a programming step for writing the data voltage Vdata to the storage capacitor CS. The switch SW is turned off to switch the voltage of the gate G of the drive transistor DT from the reference voltage Vref to the data voltage Vdata. At this time, the source side terminal of the storage capacitor CS is connected to the anode of the organic EL element EL or an auxiliary capacitor CA (not shown) instead of the anode.

  Since the parasitic capacitance CP or the auxiliary capacitance CA of the organic EL element EL is sufficiently larger than the holding capacitance CS, the source side (B) hardly changes even when the voltage of the gate side terminal (A) is switched. Thus, the data voltage Vdata is written to the storage capacitor CS. Since the threshold voltage Vth of the driving transistor DT was originally held in the storage capacitor CS, the sum of the data voltage and the threshold voltage is held in the storage capacitor CS by writing data.

  The last time t4-t5 is a light emission step in which a current is passed through the organic EL element EL to emit light. The connection from the outside that determines the voltage of the gate G is disconnected, and the switch SW is turned on. A current corresponding to the voltage of the storage capacitor CS flows through the drive transistor DT. However, since the voltage of the storage capacitor is the sum of the data voltage Vdata and the threshold voltage Vth, the current flowing through the drive transistor DT does not depend on the threshold voltage. As the current flows, the anode voltage of the organic EL element EL, that is, the source voltage (C) of the driving transistor DT rises, but the gate voltage also rises accordingly, so that the current is kept constant. Eventually, a steady state is reached and the voltages of the source S and the gate G become constant.

  Since the switch is turned off in the data writing step, even if a current flows through the driving transistor, it does not flow into the storage capacitor. The voltage of the holding capacitor does not change as it is immediately after the data voltage is applied, and an accurate voltage is held.

  When the light-emitting device of FIG. 1 is integrally formed on one substrate, the switch is also formed of a transistor having the same structure as the driving transistor. These transistors may be thin film transistors or single crystal silicon transistors formed on a silicon substrate. When formed on a single crystal substrate, the transistor constituting the switch preferably has the same polarity as the driving transistor in order to increase the degree of integration.

  FIG. 3 is obtained by replacing the N-type field effect transistor of FIG. 1 with a P-type field effect transistor. When the driving transistor is a P-type, the power supply Voled is set to a voltage lower than the reference potential Vcom, and the anode and the cathode of the organic EL element are reversed so that a current flows from the bottom to the top in the figure. In this case, the drain of the driving transistor is disposed on the power supply side, and the source is disposed on the reference potential side where the organic EL element is present.

  The invention will now be described by means of several examples. The following description will be made on a light emitting device using an organic EL element. However, the light emitting element may be a light emitting element such as an inorganic EL element, a light emitting diode, or a field emission element. The light-emitting device may be any device that functions when a light-emitting element included therein emits light, such as a display device or a lighting device.

  FIG. 4 is a circuit diagram of a pixel of the light emitting device according to the first embodiment of the present invention and its periphery.

  The pixel 1 has an organic EL element EL, a drive transistor DT, and a storage capacitor CS, and these circuit elements function in the same manner as the drive circuit shown in FIG. In addition to this, the pixel 1 includes a transistor M1, which is a first switch for connecting a terminal opposite to the gate of the storage capacitor CS to the source of the drive transistor DT, and a first switch for connecting the gate of the drive transistor to the data line 5. A transistor M2 that is a two-switch and a transistor M3 that is a third switch that connects the same terminal of the storage capacitor to the precharge line 4 are included.

  Around the pixel 1, a data line 5 and a precharge line 4 are provided in parallel to the data line 5. Similarly to the data line 5, the precharge line 4 is common to the pixels in the column direction, and a transistor M0 as a fourth switch is connected between the precharge voltage Vpre and the constant voltage source 40 that is generated by switching the reference voltage Vref. Has been. The gate of the transistor M0 is connected to a control line common to the precharge lines in other columns, and is turned on / off by a control signal P0.

  The pixel 1 includes a first control line 2 for turning on / off the first switch M1 by the control signal P1, and a second control line 3 for turning on / off the second switch M2 and the third switch M3 by the control signal P2. Is provided. These control lines are provided in common for the pixels 1 arranged in the row direction, and the control signals P1 and P2 select the pixels 1 in units of rows and perform a write operation.

  Further, the pixel 1 is provided with a power supply line 41 for supplying a power supply voltage Voled and a reference voltage line 42 for supplying a reference voltage Vcom. The reference voltage Vcom is supplied to the cathode of the organic EL element EL, and the power supply voltage Voled is supplied to the drain of the driving transistor DT.

  A parasitic capacitance CP is generated in the precharge line 4 due to the intersection with the first and second control lines 2 and 3 and the wiring interval between the adjacent data lines 5. The parasitic capacitance CP can be designed to have a value sufficiently larger than the storage capacitor CS of the pixel by designing the intersection with the first and second control lines and the wiring interval between the adjacent data lines 5. As will be described below, the parasitic capacitance CP of this embodiment serves as an auxiliary capacitance that keeps the source-side terminal voltage of the holding capacitor CS constant during a period in which the first switch M1 is off.

  FIG. 5 is a block diagram showing a configuration of a display device using the light emitting device of this embodiment.

  In the display area 20, the pixels 1 are arranged in a matrix, and the first control lines 2 and the second control lines 3 are arranged in the row direction, and the data lines 5 and the precharge lines 4 are arranged in the column direction. Although not shown in FIG. 5, the power supply voltage Voled is delivered to each pixel through the power supply wiring 41. The power supply wiring 42 for delivering the reference voltage Vcom to the cathode of the organic EL element is a planar electrode provided over the entire display region 20.

  The first control line 2 coming out of the control line control circuit 22 supplies the first control signal P1 (P1 (1), P1 (2)... P1 (n)) to each row. The second control line 3 coming out from the second line supplies a second control signal P2 (P2 (1), P2 (2)... P2 (n)) (n is the number of rows) to each row. The data line 5 supplies a video signal (Video) input from the outside of the display device to each column via the data signal circuit 21. The precharge line 4 supplies a precharge voltage (Vpre) or a reference voltage (Vref) input to the wiring 7 from an external constant voltage source 40 (FIG. 4) to each column. The fourth switch M0 of the precharge line 4 is controlled by the control signal P0.

  The video signal Video, the control signal P0, the precharge voltage Vpre, and the reference voltage Vref can be output from a controller mounted on the same substrate by the COG method.

  FIG. 6 is a timing chart showing the operation of the circuit of FIG. In order from the top, the control signal P0 of the fourth switch M0, the first control signal P1 (1) for controlling the first switch M1 of the pixels in the first row, and the second switch M2 and the third switch of the pixels in the first row as well. The second control signal P2 (1) for controlling M3, the same first control signal P1 (2) and second control signal P2 (2) of the pixels in the second row, the voltage Vd of the data line 5, the precharge line 4 Voltage Va, source voltage VS (1) of the driving transistor DT of the pixel 1 in the first row, voltage VC (1) at the connection point between the storage capacitor CS and the third switch M3, and the same voltage VS ( 2) and VC (2) are shown.

  Hereinafter, the operation will be described in the order of time.

(Reset operation)
In this embodiment, prior to the four operations described with reference to FIGS. 1 and 2, a reset operation for introducing the storage capacitor voltage to zero is introduced between times t0 and t1. This is an operation provided for performing the light-off operation described below in another row, and is not necessarily required.

  During time t0-t1, the control signal P0 is at the H level, and the fourth switch M0 is turned on. The precharge line 4 is connected to a constant voltage source 40. The constant voltage source generates a reference voltage Vref and a precharge voltage Vpre by switching, and outputs the reference voltage Vref to the precharge line 4 during this period.

  The first control signal P1 (1) and the second control signal P2 (1) in the first row are at the H level, and the pixels in the first row are selected. The first switch M1, the second switch M2, and the third switch M3 are turned on. A reference voltage Vref is applied to the data line 5, and both the gate voltage and the source voltage of the drive transistor DT become the reference voltage Vref. As a result, the voltage held in the storage capacitor CS is reset so that the voltage across the capacitor becomes zero.

  Next, the four steps described above are executed from time t1.

(Precharge operation)
During the precharge period of time t1-t2, the output of the constant voltage source 40 of the precharge line 4 is switched to the precharge voltage Vpre. The precharge voltage Vpre is set to a potential lower than the reference voltage Vref. The gate-source voltage of the driving transistor DT becomes Vgs = Vref−Vpre, which is larger than the threshold voltage (Vgs> Vth). The drive transistor DT is in a conductive state where current can flow, but since the precharge voltage Vpre is low, the voltage between the anode and the cathode of the organic EL element is small, and no current flows through the organic EL element.

(Auto zero operation)
At time t2-t3, the control signal P0 changes from H (high) level to L (low) level, and the fourth switch M0 is turned off. From time t2 to time t3, the driving transistor DT is in a floating state in which the voltage is not set anywhere from the source while the gate voltage is held at Vref. The storage capacitor CS connected to the source of the drive transistor DT and the parasitic capacitance CP of the precharge line 4 are charged by the current flowing through the drive transistor DT, and the source voltage rises. As the gate-source voltage approaches the threshold voltage Vth, the current flowing through the drive transistor DT decreases, and when the threshold voltage Vth is reached, the current becomes zero and the increase in the source voltage VS (1) stops. At this time, the source potential is lower than the gate voltage by the threshold voltage, and VS (1) = Vref−Vth. The source side terminal voltage VC (1) of the storage capacitor CS and the voltage of the parasitic capacitor CP are also the same as VS (1).

  In this way, the threshold voltage Vth of the drive transistor DT is held at both ends of the storage capacitor CS, and the drive transistor DT is in a conductive state just below the threshold.

(Programming operation)
At time t3, the first control signal P1 (1) is switched from the H level to the L level, and the first switch M1 is turned off. At the same time, the voltage Vd of the data line 5 is switched from the reference voltage Vref so far to the data voltage Vdata corresponding to the gradation data. Due to the voltage change of the data line, the voltage across the storage capacitor CS is obtained by multiplying the voltage change amount (Vdata−Vref) of the data line by the capacity division ratio of CS and CP. ΔV = (CP / (CS + CP)) × (Vdata -VREF) Formula (1)
Increases to Vth + ΔV. In this way, the signal voltage of the gradation data is written into the storage capacitor CS.

  By making the parasitic capacitance CP larger than the holding capacitance CS of the pixel, the capacitance division ratio of the equation (1) becomes close to 1, and ΔV in the programming operation can be increased. On the contrary, the change in the source voltage of the driving transistor is suppressed to a small level. The parasitic capacitance CP functions as an auxiliary capacitance that holds the source-side terminal voltage VC of the holding capacitor CS while the first switch M1 is off.

  Since the gate-source voltage immediately after the voltage of the data line is switched to Vdata exceeds the threshold voltage and is Vth + ΔV, the driving transistor DT becomes conductive and current flows. Due to this current, the source voltage VS (1) of the drive transistor DT rises during the period of time t2-t3. However, since the first switch M1 is off, the current flowing through the drive transistor DT does not flow into the storage capacitor CS.

  When the voltage of the data line is switched from Vref to Vdata, a current flows transiently from the gate to the source via the gate-source parasitic capacitance of the driving transistor DT, but this current flows to the storage capacitor CS. It is blocked by one switch M1. Therefore, no current flows into the storage capacitor CS, and the both-end voltage is held at the voltage set at time t2.

(Light emission operation)
The light emission step is after time t4. The first control signal P1 (1) becomes H (high) level, and the first switch M1 is turned on. On the other hand, the second control signal P2 (1) becomes L (low) level, and the second switch M2 and the third switch M3 are turned off. A voltage (Vth + ΔV) held in the holding capacitor CS is applied between the gate and source of the drive transistor DT, and a current corresponding thereto is supplied from the drive transistor DT to the organic EL element. The organic EL element emits light with a luminance corresponding to the current.

  Each step in the second row starts from time t4.

  In the reset step at time t4-t5, the control signal P0 becomes H level, and the first control signal P1 (2) and the second control signal P2 (2) in the second row also become H level. Precharge is executed at time t5-t6, auto-zero is executed at time t6-t7, and programming steps are executed at time t7-t8. These operations are performed in the same manner as in the first row.

  Thereafter, the third row and the fourth row are sequentially selected and the same operation is repeated.

(Lights off)
If necessary, the light emission period ends in the middle of one frame period. In this embodiment, the pixels in the first row that started to emit light at time t4 stop emitting light at time t9, and thereafter, the erasing operation is performed so as to stop emitting light sequentially for each row.

  During the period from time t9 to t10, the control signal P0, the first control signal P1 (1) and the second control signal P2 (2) in the first row are at the H level, the fourth switch M0 and the pixel in the first row 1 first to third switches M1-M3 are turned on. A reference voltage Vref is set for the data line 5, and the reset operation of the pixels in the first row is executed. The gate-source voltage of the drive transistor DT becomes zero, the current supply from the drive transistor DT is stopped, and the organic EL element is turned off. Thereafter, the same turn-off operation from the second line is performed, and the entire screen is turned off.

  The start time and end time of the light emission period are different for each row, but the length of the light emission period is the same for all the rows. In order to adjust the display brightness as a whole, the start timing t9 of the turn-off operation may be changed.

  By setting the light emission period to one field period or less, the moving image performance can be improved. It is also possible to write the next image data by returning to the selection period of the first row after the writing scan is completed without performing the light-off operation.

  The timing of the erasing operation may overlap with the reset operation of other pixels. At the time of reset, the data line becomes Vref, so that two rows can be referred to jointly.

  Since the data line 5 and the precharge line 4 are provided in common for the pixels in the column direction, the parasitic capacitance CP of the precharge line 4 is the reset operation, precharge operation, auto zero operation, and programming operation of each row. Used in common. The parasitic capacitance CP is used in a time-sharing manner by the second switch M2 and the third switch M3.

  Since the parasitic capacitance CP is commonly used by the pixels in the column direction, it is possible to use only one storage capacitor CS in the pixel. A capacitor requires a larger layout area than a transistor, but by using a common parasitic capacitor, the pixel size can be reduced and the pixel can be made high definition.

  FIG. 7 is a diagram showing a circuit configuration of a pixel in the light emitting device according to the second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

  The difference from the first embodiment is that the second switch M2 and the third switch M3 are controlled by the second control line 3 and the third control line 8 with different control signals P2 and P3, respectively, This is that an auxiliary capacitor CP ′ in series with the holding capacitor CS is provided. The auxiliary capacitor CP ′ is used to hold the voltage of VC during the program period, as in the first embodiment.

  In this embodiment, the parasitic capacitance of the precharge line has no role. There is no fourth switch M0, and Vref or Vpre is always supplied to the precharge line 4 from the constant voltage source 40. The precharge lines 4 are arranged in the row direction, but may be arranged in the column direction as in the first embodiment.

  The configuration of the light emitting device is the same as that in FIG.

  FIG. 8 is a timing chart showing the circuit operation of the pixel of this embodiment. There are three control lines P1-P3 from the control line control circuit 22. The third control signal P3 is transmitted to the pixels in the row direction by the third control line 8. Similar to the first control signal P1 and the second control signal P2, the third control signal P3 is also supplied to each row separately.

  Compared to the first embodiment (FIG. 6), there is no control signal P0, and a third control signal P3 is added to each row instead.

  Since the reset operation at time t0-t1 and the precharge operation at time t1-t2 are the same as those in the first embodiment, description thereof is omitted.

  During the auto-zero operation period from time t2 to t3, the third control signal P3 (1) becomes L level, and the third switch M3 is turned off. The current flowing through the drive transistor DT flows through the storage capacitor CS and the auxiliary capacitor CP ′, and stops when the voltage across the storage capacitor CS becomes equal to the threshold voltage Vth of the drive transistor DT.

At time t3, the voltage of the data line is switched from the reference voltage Vref to the data voltage Vdata, and the voltage across the storage capacitor CS is changed from Vth to ΔV ′ = (CP ′ / (CS + CP ′)) * (Vdata−Vref) Expression ( 2)
Only increase. Thereafter, since the first switch M1 is turned off, a voltage of Vth + ΔV is held across the holding capacitor CS during the programming period from time t3 to t4.

  The subsequent light emitting operation and erasing operation are performed in the same manner as in the first embodiment.

  In this embodiment, the auxiliary capacitor CP ′ is provided in the pixel. Since the auxiliary capacitance CP ′ cannot be increased as much as the parasitic capacitance CP of the precharge line 4, ΔV ′ in the equation (2) is smaller than ΔV in the equation (1), but the amplitude of the signal voltage Vdata is increased accordingly. For example, Vdata−Vref becomes large, and ΔV ′ can be made equal to ΔV.

  FIG. 9 is a diagram showing a circuit configuration of a pixel in the light emitting device according to the third embodiment of the present invention. The same parts as those in the second embodiment are denoted by the same reference numerals and the description thereof is omitted.

  The difference from the second embodiment is that the variable voltage source 50 is attached to the power supply line 41, the fixed voltage Vpre is applied to the precharge line 4, and the third switch M3 and the third control for controlling it. The line 8 is lost. The variable voltage source 50 can switch the voltage between Voled and Vpre at different timings in each row.

  FIG. 10 is a timing chart showing the circuit operation of the pixel of this embodiment.

  Compared to the second embodiment (FIG. 6), there is no third control signal P3, and voltages Voled (1) and Voled (2) of the power supply lines 41 in each row are applied instead. The voltage Va of the precharge line 4 is fixed at Vpre.

  In this embodiment, there is no reset period from t0 to t1 in the second embodiment, and the erase operation is performed by changing the voltage of the power supply line 41 in the middle of light emission (the first row is time t9).

  Time t1-t2 is a period during which precharging is performed. The first switch M1 and the second switch M2 are turned on, the output of the variable voltage source 50 is switched, and the voltage of the power supply line 41 is lowered to Vpre. The voltage at the source of the drive transistor DT and one end of the storage capacitor CS connected to the source drops to Vpre. Since the data line 5 is at the reference voltage Vref, the voltage across the storage capacitor is Vref−Vpre. Since this voltage is higher than the threshold voltage of the driving transistor, the driving transistor DT becomes conductive.

  During the auto-zero operation period from time t2 to t3, the first switch M1 and the second switch M2 remain on and the output of the variable voltage source 50 returns to Voled. The current flowing through the drive transistor DT flows through the storage capacitor CS and the auxiliary capacitor CP ′, and stops when the voltage across the storage capacitor CS becomes equal to the threshold voltage Vth of the drive transistor DT.

At time t3, the voltage of the data line is switched from the reference voltage Vref to the data voltage Vdata, and the voltage across the storage capacitor CS is changed from Vth to ΔV ′ = (CP ′ / (CS + CP ′)) * (Vdata−Vref).
Only increase. Thereafter, since the first switch M1 is turned off, a voltage of Vth + ΔV is held across the holding capacitor CS during the programming period from time t3 to t4.

  The subsequent light emission operation is performed in the same manner as in the second embodiment.

  At time t9, the output of the variable voltage source 50 in the first row is switched to Vpre and the power supply voltage Voled (1) is lowered, so that the source voltage of the drive transistor DT is lowered and the light emission of the organic EL element EL is stopped. Thereafter, the same erasing operation is executed for each row while shifting the time.

  In this embodiment, since the precharge operation is performed by changing the voltage of the power supply line 41, a simple drive circuit without the third switch can be realized.

  FIG. 11 is a circuit diagram of a pixel in the light emitting device according to the fourth embodiment of the present invention. The auxiliary capacitor CP ′ of Example 3 was substituted with a parasitic capacitor CL associated with the organic EL element EL. The parasitic capacitance CL of the organic EL element is formed using an organic layer such as a light emitting layer between the anode and the cathode of the organic EL element as a dielectric and a dielectric.

  Since the parasitic capacitance CL is inseparable from the organic EL element EL, it cannot be separated from the organic EL element like the auxiliary capacitance CP ′ of the third embodiment. In this embodiment, a transistor M5 serving as a first switch in series with the current path is provided in the middle of the current path from the source of the drive transistor DT to the organic EL element.

  One terminal of the storage capacitor CS is connected to a connection point between the first switch M1 and the anode of the organic EL element EL. The other terminal is connected to the gate of the drive transistor DT. The gate of the first switch M5 is connected to the first control line 2. The first switch M5 is controlled to be turned on / off by the first control signal P1.

  FIG. 12 is a timing chart showing the operation of the pixel of this embodiment.

The precharge at time t1-t2 and the auto zero at time t2-t3 are the same operations as in the second embodiment. In the programming period t3-t4, the first switch M5 is turned off at time t3, and at the same time, the voltage of the data line is switched from Vref to Vdata. As a result, the voltage across the storage capacitor is ΔV = (CL / (CS + CL)) * (Vdata−Vref) (3)
Only changes. As is clear from the comparison of Equation (3) with Equation (1) or Equation (2), the parasitic capacitance CL of the organic EL element functions as an auxiliary capacitance.

  Since the first switch M5 is off, no current flows through the drive transistor DT during the period of time t3-t4. Further, when the voltage of the data line is switched from Vref to Vdata, a current flows from the gate to the source via the gate-source parasitic capacitance of the driving transistor DT, but this is also blocked by the first switch M5. The Therefore, no current flows into the storage capacitor CS, and the voltage across the both ends is maintained.

  At time t4, the first switch M5 is turned on and the second switch M2 is turned off, so that the voltage across the storage capacitor CS is held, and a current corresponding thereto flows from the drive transistor DT to the organic EL element EL. With this current, the voltage between the terminals of the organic EL element EL increases, and the source voltage VS (1) of the drive transistor DT and the terminal voltage VC (1) of the storage capacitor CS connected thereto increase accordingly, but the storage capacitor CS Since the voltage between the terminals of the driving transistor DT does not change, the voltage between the gate and the source of the driving transistor DT does not change and a constant current continues to flow.

  When the first control voltage P1 (1) in the first row falls to the L level at time t9, the first switch M5 is turned off, and the current supply to the organic EL element is stopped. Since the first switch M5 is provided in the middle of the current path from the source of the drive transistor DT to the anode of the organic EL element EL, the erase operation is executed by turning off the first switch M5. Therefore, the reset operation performed at t0-t1 in the second embodiment is not necessary, and the timing of the erase operation can be performed regardless of the operation of other rows.

  The above operation is repeated in order from the second line.

  In this embodiment, since the parasitic capacitance CL of the organic EL element is used, it is not necessary to provide an auxiliary capacitance in the pixel. Therefore, the area occupied by the pixels can be reduced and the definition of the display device can be increased.

  FIG. 13 shows a circuit configuration of a pixel according to the fifth embodiment of the present invention. From Example 4 (FIG. 11), the third switch M3, the third control line, and the precharge line 4 are eliminated, and Voled (1), Voled (2),... (N) is supplied.

  FIG. 14 shows a timing chart. During the precharge period from time t1 to t2, the first switch M5 and the second switch M2 are turned on, and at the same time, the second power supply voltage Voled (1) in the first row becomes Vpre. As a result, the reference voltage Vref is applied to the gate of the drive transistor DT, and the source voltage VS (1) of the drive transistor DT and the terminal VC (1) on the organic EL element side of the storage capacitor CS become Vpre. The value of Vpre is the same as that used in Example 3.

  Operations other than precharge are the same as those in the fourth embodiment.

  The transistors constituting the pixels of Examples 1 to 5 may be thin film transistors formed of amorphous silicon, polysilicon, or an oxide semiconductor, or transistors formed on a single crystal silicon substrate. In the transistor formed on the silicon substrate, the substrate or body voltage is set in addition to the gate, source, and drain terminals. The body is a region electrically isolated from the substrate by the well.

  When the drive transistor and the other transistors serving as switches are all MOS transistors having the same polarity, the body is common to all the transistors and a constant voltage is applied. At this time, the substrate may be a body. When all the transistors are N-channel type, the body or the substrate is P-type and is set to the lowest potential in the circuit.

  By making the polarity of the transistors constituting the pixels the same, the body can be shared by at least the display region 20 (FIG. 5). When peripheral circuits such as the data signal circuit 21 and the control line control circuit 22 are composed of transistors having polarities different from those of the pixels, the entire display region 20 is formed using an N-type substrate (the pixel transistors are N-channel type). A P-well is formed on the substrate and separated from the peripheral region.

  Although the body is electrically separated for each well, a space of about 1 to 3 μm is required for the well separation. Therefore, it is not a good idea to provide a well in the pixel. It is preferable to have the same potential.

  Further, by fixing the body to a constant voltage, the current flowing through the body can be made almost zero. In order to reduce power consumption, it is preferable to fix the body to a constant voltage.

  The light emitting device of the present invention is applied to a display device and an image forming apparatus.

  The display device is a light emitting device in which pixels are arranged in a matrix as described in FIG. Matrix display devices are used in electronic devices such as mobile phones, mobile computers, digital still cameras, and video cameras.

  FIG. 15 is a block diagram of an example of a digital still camera system. Reference numeral 108 denotes a digital still camera system, 109 denotes a photographing unit, 110 denotes a video signal processing circuit, 111 denotes a light emitting device of the present invention as a display panel, 112 denotes a memory, 113 denotes a CPU, and 114 denotes an operation unit. A video image captured by the imaging unit 109 or a video image recorded in the memory 112 can be signal-processed by the video signal processing circuit 110 and viewed on the display panel 111. The CPU 113 controls the photographing unit 109, the memory 112, the video signal processing circuit 110, and the like according to the input from the operation unit 114, and performs photographing, recording, reproduction, and display suitable for the situation. In addition, the display panel 111 can be used as a display unit of various electronic devices.

  An example of applying the light emitting device of the present invention to an image forming apparatus is an exposure head of an electrophotographic printer in which light emitting elements are arranged in a line.

  FIG. 16 is an overall view of an exposure head that forms a latent image by irradiating the photosensitive drum with light.

  On the glass substrate, organic EL elements EL are arranged in a line shape, and a drive circuit 10 is connected to each organic EL element. Although the driving circuit 10 is the same as that of the second embodiment (FIG. 7), driving circuits of other embodiments can be used. The power supply line 60, the constant voltage line 63 for applying the precharge voltage Va, and the reference voltage line 64 for setting the cathode of the organic EL element to the reference potential Vcom are provided in common to all the organic EL elements and the drive circuit along the line. Yes.

  The drive circuit 10 is divided into N blocks with M drive circuits as one block, and the M drive circuits in the same block are controlled by common control lines 71, 72, 73. There are N control lines 71, 72, and 73, respectively, and the drive circuit can be controlled for each block. N control lines select each block individually and give a control signal. N and M may be integers of 2 or more, but typically, the total number is 4800 when N = 64 and M = 75.

  On the other hand, one signal line 61 for supplying the luminance signal Vdata to each drive circuit is selected one by one for each drive circuit and connected to all the blocks in common.

  The control lines 71, 72, 73 supply control signals P1 (n), P2 (n), P3 (n) (n is a block number, n = 1, 2,..., N) for each block. ing. A scanning circuit SCN for generating these control signals is provided on the outside thereof. The scanning circuit SCN receives a clock signal CK, an inverted signal CKB, and a scanning start signal ST from the outside.

  The control signals P1, P2, and P3 select blocks in order from the first block to the Nth block, and write the signal voltage Vdata from the signal line 61 to the drive circuit 10 of the selected block.

  The pixel organic EL elements and the drive circuit in FIG. 16 are arranged in a line, but the circuit connection is equivalent to the matrix arrangement shown in FIG. The pixels in the block correspond to the pixels in each row in the matrix display device, and are simultaneously selected and written simultaneously. Pixels having different blocks and sharing control lines correspond to the pixels in each column in the matrix display device. Reference numerals such as (1, 1) attached to the drive circuit 10 in FIG. 16 indicate a block number and a position in the block, and correspond to the rows and columns of the display device of the first embodiment.

1 pixel 2, 3, 8 control line 4 precharge line 5 data line EL organic EL element DT drive transistor M1, M2, M3 switch transistor CS holding capacitor Voled power supply voltage Vcom reference voltage Vd data signal P1, P2, P3 control signal

Claims (16)

A drive transistor having a drain disposed on the power supply side and a source disposed on the reference potential side, a light emitting element disposed between the source of the drive transistor and the reference potential, and between the gate and the source of the drive transistor A light-emitting device that emits light from the light-emitting element by supplying a current corresponding to the voltage of the storage capacitor from the drive transistor to the light-emitting element.
A light emitting device, wherein a first switch in series is provided in a current path from a source of the driving transistor to the storage capacitor.   2. The light emitting device according to claim 1, wherein a voltage source for applying a voltage is connected to a terminal of the storage capacitor on the gate side of the driving transistor via a second switch.   The first switch is disposed in a current path from the middle of the current path from the source of the drive transistor to the light emitting element to the storage capacitor, and the terminal of the storage capacitor disposed on the source side of the drive transistor An auxiliary capacitor is connected to the light emitting device according to claim 2.   The light emitting device according to claim 3, wherein the auxiliary capacitor is connected via a third switch.   A voltage source that applies a voltage independent of the voltage applied via the second switch is connected to the terminal of the storage capacitor on the source side of the driving transistor via the third switch. The light-emitting device according to claim 4. An operation of making all of the first to third switches conductive;
Conducting the first switch and the second switch and shutting off the third switch;
Shutting off the first switch and the third switch and making the second switch conductive;
The light emitting device according to claim 5, wherein the first switch is turned on, and the second switch and the third switch are shut off.   4. The light emitting device according to claim 3, wherein the power source to which the drain of the driving transistor is connected is a variable voltage source that switches and outputs different voltages.   The first switch is disposed in a current path from the source of the driving transistor to the light emitting element, and one terminal of the storage capacitor is connected to a connection point between the first switch and the light emitting element. The light emitting device according to claim 2.   9. The light emitting device according to claim 8, wherein the power source to which the drain of the driving transistor is connected is a variable voltage source that switches and outputs different voltages.   A voltage source that applies a voltage independent of a voltage applied via the second switch is connected to a terminal of the storage capacitor connected to a connection point of the first switch and the light emitting element. The light emitting device according to claim 8.   The light emitting device according to claim 1, wherein the driving transistor and the first switch are composed of transistors having the same polarity.   2. The light emitting device according to claim 1, wherein the driving transistor and the first switch are transistors formed on a silicon substrate and having a common body.   The light emitting device according to claim 1, wherein the light emitting element is an organic electroluminescent element. A drive transistor having a drain disposed on the power supply side and a source disposed on the reference potential side, a storage capacitor disposed between the gate and the source of the drive transistor, and a current path extending from the drive transistor to the storage capacitor Using a driving circuit having a switch disposed on the light emitting element, the light emitting element disposed between the source of the driving transistor and the reference potential,
A first step of applying a voltage to both ends of the storage capacitor; and applying the same voltage to the terminal of the storage capacitor disposed on the gate side of the drive transistor as in the first step, causing the switch to conduct, A second step of passing a current from the source of the driving transistor to the storage capacitor; a third step of cutting off the switch and applying a data voltage to the gate of the driving transistor; and a power source for supplying the data voltage to the driving transistor. A driving method characterized by comprising a fourth step of separating the gate and conducting the switch.   15. The switch is disposed in a current path from a source of the driving transistor to the light emitting element, and one terminal of the storage capacitor is connected to a connection point between the switch and the light emitting element. The driving method described in 1. The switch is arranged in the current path from the middle of the current path from the source of the driving transistor to the light emitting element to the storage capacitor,
The driving method according to claim 14, wherein in the third step, a terminal of the storage capacitor disposed on a source side of the driving transistor is connected to an auxiliary capacitor.

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