JP2014182218A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of reducing power consumption.SOLUTION: In a liquid crystal display device 1, shift registers connected to a scanning signal line X are divided into plural groups 6; and plural clock signal lines 61 are wired from a driver IC 21 to the respective groups 6 being separated from each other. The driver IC 21 supplies a clock signal selectively to the plural groups 6.

Description

  The present invention relates to a liquid crystal display device, and more particularly to driving a shift register.

  2. Description of the Related Art Conventionally, a liquid crystal display device including a plurality of shift registers connected to a plurality of scanning signal lines wired in an image display region and sequentially outputting pulse signals is known.

JP-A-8-160387

  In a conventional liquid crystal display device, a clock signal is supplied to all shift registers during a scanning period in which scanning signal lines are scanned. That is, each shift register is always supplied with a clock signal even though it does not operate for most of the scanning period. For this reason, there is a problem that wasteful power consumption is large. In particular, when the shift register transistor includes amorphous silicon, since a relatively high voltage is required for driving, the power consumption is likely to be excessive, and the life is likely to be shortened.

  FIG. 8 of Patent Document 1 discloses a configuration in which a shift register block 803 is connected to a path branched from one plus-side power supply line 801 via a P-channel TFT 802. However, this configuration has a problem that the waveform of the power supply signal tends to be dull because the on-resistance of the P-channel TFT 802 is high.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a liquid crystal display device capable of suppressing power consumption.

  In order to solve the above problems, a liquid crystal display device of the present invention is connected to an image display region including a plurality of pixels partitioned by a plurality of scanning signal lines and a plurality of video signal lines, and the plurality of scanning signal lines. A plurality of shift registers that sequentially output pulse signals, wherein the plurality of shift registers are divided into a plurality of groups including one or a plurality of shift registers, a clock signal supply circuit, And a plurality of clock signal lines wired independently from each other from the clock signal supply circuit to the respective groups. The clock signal supply circuit includes an amplifier at an output stage connected to each of the clock signal lines, and selectively supplies a clock signal to the plurality of groups according to the order in which the pulse signals are output.

  In one aspect of the present invention, the clock signal supply circuit supplies the clock signal to a group corresponding to an order of outputting the pulse signal among the plurality of groups.

  In one aspect of the present invention, the clock signal supply circuit does not supply the clock signal to a group that does not correspond to the order in which the pulse signals are output among the plurality of groups.

  In one embodiment of the present invention, the clock signal supply circuit supplies the clock signal to the group before data is input to the first shift register of the group.

  In one aspect of the present invention, the clock signal supply circuit makes the clock signal supply start timing in a certain group of the plurality of groups earlier than the clock signal supply end timing in the previous group.

  In one embodiment of the present invention, the shift register includes at least one thin film transistor including amorphous silicon as a semiconductor layer.

  In one aspect of the present invention, the plurality of shift registers are provided on at least one side of the image display area parallel to the video signal line, and the clock signal supply circuit is configured to scan the image display area. Provided on at least one side of the side parallel to the signal line.

  In one aspect of the present invention, the clock signal supply circuit is included in an integrated circuit package.

  According to the present invention, since clock signals are selectively supplied to a plurality of groups in accordance with the order in which pulse signals are output, power consumption can be suppressed. In addition, since the clock signal supply circuit includes an amplifier in the output stage, it is possible to suppress a dull waveform of the clock signal.

1 is an external perspective view of a liquid crystal display device according to an embodiment of the present invention. It is a figure which shows the structural example of the circuit formed on an array board | substrate. It is a figure which shows one of the pixels formed in an image display area with a circuit diagram. It is a figure which shows schematically the example of a relationship between a shift register and a clock signal line. It is a figure which shows the structural example of a shift register. It is a timing chart which shows the example of supply of a clock signal. It is a figure which shows the structural example of a clock signal supply circuit. It is a timing chart which shows the example of a state of a clock signal supply circuit.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an external perspective view of a liquid crystal display device 1 according to an embodiment of the present invention. The liquid crystal display device 1 has a structure in which a liquid crystal material having a thickness of about several micrometers is sandwiched between the array substrate 2 and the color filter substrate 3, and the array substrate is sealed by a sealing material provided along the outer periphery of the color filter substrate 3. 2 and the color filter substrate 3 are bonded together and sealed so that the liquid crystal material does not leak.

  The array substrate 2 is a glass substrate in which a large number of switching elements and pixel electrodes are formed in a lattice shape on the front surface thereof. When a TFT is used as the switching element, the array substrate 2 is also called a TFT substrate. The array substrate 2 has an outer shape larger than that of the color filter substrate 3 as shown in the figure, and at least one side thereof protrudes from the color filter substrate 3 so that the front surface is exposed. A driver IC 21, which is an integrated circuit package including a control circuit for controlling on / off of a large number of switching elements and a video signal applied to each pixel electrode, is mounted on the exposed portion of the front surface of the array substrate 2. In addition, a connection terminal 22 for electrically connecting the liquid crystal display device 1 to an external device by, for example, FPC (Flexible Printed Circuits) is formed.

  The color filter substrate 3 is a glass substrate in which a colored thin film that is colored red, green, and blue is formed for each pixel that is a unit when the liquid crystal display device 1 forms an image. The colored thin film is an array substrate. 2 is provided at a position corresponding to the pixel electrode formed in 2.

  A polarizing film 4 is attached to the back surface of the array substrate 2 and the front surface of the color filter substrate 3.

  In the embodiment described above, the liquid crystal display device 1 is a so-called transmission type, and the array substrate 2 and the color filter substrate 3 are transparent substrates such as glass. However, in the case of a reflection type, the liquid crystal display device 1 is not necessarily transparent. There is no need to be, and the material is not limited to glass. In the embodiment shown here, since the liquid crystal display device 1 is capable of full color display, the color filter substrate 3 is provided with red, green and blue colored thin films. The liquid crystal display device 1 may be a monochrome display and the colored thin film may be a single color or may be omitted.

  FIG. 2 is a diagram showing a configuration example of a circuit formed on the array substrate 2 of the liquid crystal display device 1 according to the embodiment of the present invention.

  On the array substrate 2, a rectangular image display region 5 in which a large number of pixels are arranged in a grid is formed. The resolution of the image display area 5 and the lengths in the horizontal direction and the vertical direction are determined according to the application of the liquid crystal display device 1. The liquid crystal display device 1 exemplified in this embodiment has a vertically long shape (the length in the left-right direction is shorter than the length in the vertical direction). This is because the liquid crystal display device 1 is a display for a portable information terminal such as a so-called smart phone. This is because the device is assumed to be used as an apparatus, and depending on the application, even if the image display area 5 has a horizontally long shape (the length in the left-right direction is longer than the length in the up-down direction), May be equal.

  A plurality of scanning signal lines X and a plurality of video signal lines Y are formed on the array substrate 2 so as to penetrate the image display area 5. The scanning signal lines X and the video signal lines Y are orthogonal to each other, and divide the image display area 5 in a lattice shape. A region surrounded by two adjacent scanning signal lines X and two adjacent video signal lines Y is one pixel.

  FIG. 3 is a circuit diagram showing one of the pixels formed in the image display area 5. The area surrounded by the scanning signal lines Xn and Xn + 1 and the video signal lines Yn and Yn + 1 shown in the drawing is one pixel. Here, it is assumed that the pixel of interest is driven by the video signal line Yn and the scanning signal line Xn. Each pixel is provided with a TFT 51. The TFT 51 is turned on by a scanning signal input from the scanning signal line Xn. The video signal line Yn applies a voltage (a signal representing the gradation value of each pixel) to the pixel electrode 52 of the pixel via the TFT 51 in the on state.

  A common electrode 53 is formed corresponding to the pixel electrode 52 so as to form a capacitor through a liquid crystal layer sandwiched and sealed between the array substrate 2 and the color filter substrate 3. The common electrode 53 is electrically connected to a common potential. For this reason, the electric field between the pixel electrode 52 and the common electrode 53 changes according to the voltage applied to the pixel electrode 52, thereby changing the alignment state of the liquid crystal in the liquid crystal layer and transmitting the image display region 5. Controls the polarization state of the light beam. The transmittance of light transmitted through the liquid crystal display device 1 is determined by the relationship between the polarization direction controlled by the liquid crystal layer and the polarization direction of the polarizing film 4 attached to the array substrate 2 and the color filter substrate 3. The pixel functions as an element that controls light transmittance. An image is displayed by controlling the light transmittance of each pixel according to the input image data. Therefore, in the liquid crystal display device 1, the area where the pixels are formed is the image display area 5 where the image is displayed.

  The substrate on which the common electrode 53 is formed differs depending on the liquid crystal driving method. For example, a method called IPS (In Plane Switching) is applied to the array substrate 2 and, for example, VA (Vertical alignment), TN ( In the case of a method called “Twisted Nematic”, a common electrode is formed on the color filter substrate 3. In the present invention, the liquid crystal driving method is not particularly limited, but in the present embodiment, the IPS method is used.

  Returning to FIG. 2, a driver including a scanning signal driving circuit 211 and a video signal driving circuit 212 is provided on at least one side of the image display area 5 parallel to the scanning signal line X, in the illustrated example, on the upper side of the image display area. IC21 is provided. Various signals such as a power supply voltage, a ground voltage, a timing signal, and a video signal are input to the driver IC 21 from an external device. In the present embodiment, the common potential is the ground potential, but is not necessarily limited to this.

  A plurality of shift registers 65 (FIG. 4) connected to the respective scanning signal lines X are provided on at least one side of the side parallel to the video signal line Y of the image display area 5, on the left and right sides of the image display area in the illustrated example. And FIG. 5). The shift register 65 outputs a pulse signal to the scanning signal line X in the connected order, in the illustrated example, in order from the side closer to the driver IC 21. As a result, a voltage for turning on the TFT 51 (see FIG. 3) (hereinafter referred to as an on-voltage) is sequentially applied to the scanning signal line X.

  The plurality of shift registers 65 are divided into a plurality of groups 6, and a clock signal line 61 is connected to each group 6. The plurality of clock signal lines 61 are wired independently from each other from the scanning signal drive circuit 211 of the driver IC 21 to each group 6. The scanning signal driving circuit 211 includes a clock signal supply circuit 75 (see FIG. 7), and selects a clock signal for a plurality of groups 6 by switching the clock signal line 61 that supplies the clock signal at a predetermined timing. To supply.

  The clock signal line 61 is provided on at least one of the sides (left and right sides in the illustrated example) parallel to the video signal line Y of the image display area 5, and on both sides in this embodiment. Here, the clock signal line 61 extends from the scanning signal driving circuit 211 to an area outside the image display area 5 in the left-right direction, and then passes outside the left and right sides of the image display area 5 in parallel with the video signal line Y. , And arranged to be connected to each group 6.

  The start group 6 is connected to a start signal line 62 for supplying a start signal to the start shift register 65 included in the group 6. The start signal line 62 is wired from the scanning signal drive circuit 211 of the driver IC 21 to the first group 6. When the scanning signal driving circuit 211 outputs a start signal to the leading shift register 65, a series of output of pulse signals by the plurality of shift registers 65 is started. Here, the head indicates the beginning in the order of outputting the pulse signals.

  The video signal drive circuit 212 is connected to the video signal line Y. In accordance with the selection of the scanning signal line X by the shift register 65, the video signal driving circuit 212 responds to each of the TFTs 51 connected to the selected scanning signal line X in accordance with the video signal representing the gradation value of each pixel. Apply the correct voltage.

  FIG. 4 is a diagram schematically showing an example of the relationship between the shift register 65 and the clock signal line 61. In the present embodiment, the shift register 65 is distributed to both sides of the side parallel to the video signal line Y of the image display area 5, that is, to the left and right sides in the illustrated example. For example, the shift register 65 connected to the odd-numbered scanning signal line X is arranged on one side of the side parallel to the video signal line Y of the image display area 5, on the left side in the illustrated example. On the other hand, the shift register 65 connected to the even-numbered scanning signal line X is arranged on the other side of the side parallel to the video signal line Y of the image display region 5, that is, on the right side in the illustrated example. However, the present invention is not limited to this, and the shift register 65 may be provided only on one side of the side parallel to the video signal line Y of the image display area 5.

  The number of scanning signal lines X and video signal lines Y depends on the resolution of the image display area 5. In this embodiment, the number of scanning signal lines X is 1920 and the number of video signal lines Y is 1080. The division number m of the shift register 65 is 10, and the number of scanning signal lines X connected to each group 6 is 192. In this case, the shift register 65 connected to the scanning signal lines X1 to X192 constitutes the first group 6 (G1), and the shift register 65 connected to the scanning signal lines X193 to X384 is the second group 6 (G2). ), And so on. In the present embodiment, since the shift registers 65 are distributed to the left and right sides of the image display area 5, each group 6 is also divided into the left and right sides.

  Each clock signal line 61 includes a pair of signal lines CK and CKB that transmit clock signals having opposite phases to each other. The pair of signal lines CK and CKB are connected to each shift register 65 included in the group 6 to be connected. Specifically, the first clock signal 61 (CK1, CKB1) is connected to all the shift registers 65 included in the first group 6 (G1), and the second clock signal 61 (CK2, CKB2). Are connected to all shift registers 65 included in the second group 6 (G2), and so on. In the present embodiment, since the shift register 65 is distributed to the left and right sides of the image display area 5, each clock signal line 61 is also provided on both the left and right sides.

  FIG. 5 is a diagram illustrating a configuration example of the shift register 65. The shift register 65 includes a pair of clock terminals CK and CKB, a ground terminal VSS, an input terminal SET, and an output terminal OUT. Clock signal lines 61 (CK, CKB) are connected to the clock terminals CK, CKB, and clock signals having phases opposite to each other are supplied. An off signal line 69 is connected to the ground terminal VSS, and an off voltage Vgoff is supplied. The potential of the off voltage Vgoff is, for example, a common potential (that is, a ground potential).

  The pulse signal output from the upstream shift register 65 is input to the input terminal SET as input data. When the clock signal is supplied to the clock terminals CK and CKB and the pulse signal is input to the input terminal SET, the shift register 65 scans the pulse signal having the same length as one pulse of the clock signal from the output terminal OUT. The signal is output to the signal line X and the downstream shift register 65.

  A plurality of transistors 71 are provided in the shift register 65. In the present embodiment, the transistor 71 is a TFT and is formed together with the TFT 51 (see FIG. 3) in the image display region 5 in the manufacturing process of the array substrate 2. Therefore, the semiconductor layer of the transistor 71 is made of amorphous silicon like the TFT 51.

  Returning to FIG. 4, the operation of the shift register 65 will be described. The start signal Vst output from the scanning signal drive circuit 211 is input to the first shift register 65 through the start signal line 62. When the start signal Vst is input, the first shift register 65 outputs a pulse signal to the first scanning signal line X1. The pulse signal output from the first shift register 65 is input to the second shift register 65 through the first scanning signal line X1. When the pulse signal is input, the second shift register 65 outputs the pulse signal to the second scanning signal line X2. The pulse signal output from the second shift register 65 is input to the third shift register 65 through the second scanning signal line X2. Repeat in the same manner.

  Further, the description will be made focusing on the nth shift register 65. The pulse signal output from the (n-1) th shift register 65 is transferred to the nth shift register 65 through the (n-1) th scanning signal line Xn-1. Entered. When the pulse signal is input, the nth shift register 65 outputs the pulse signal to the nth scanning signal line Xn. The pulse signal output from the nth shift register 65 is input to the (n + 1) th shift register 65 through the nth scanning signal line Xn.

  A clock signal supply circuit 75 included in the scanning signal drive circuit 211 selectively supplies a clock signal to the plurality of groups 6 according to the order in which the pulse signals are output. Specifically, the clock signal supply circuit 75 supplies the clock signal to the group 6 including the shift register 65 in the order of outputting the pulse signal among the plurality of groups 6, and supplies the clock signal to the other groups 6. Do not supply.

  For example, during a period in which the shift register 65 included in the first group 6 (G1) scans the scanning signal lines X1 to X192, the clock signal supply circuit 75 transmits the first through the first clock signal 61 (CK1, CKB1). The clock signal is supplied to the shift register 65 included in the group 6 (G1), and the clock signal is not supplied to the other groups 6 (G2 to G10). In the period in which the shift register 65 included in the second group 6 (G2) scans the scanning signal lines X193 to X384, the clock signal supply circuit 75 transmits the second signal through the second clock signal 61 (CK2, CKB2). A clock signal is supplied to the shift register 65 included in the group 6 (G2), and no clock signal is supplied to the other groups 6 (G1, G3 to G10). Repeat in the same manner.

  Note that the clock signal supply circuit 75 makes the clock signal supply start timing in a certain group 6 earlier than the clock signal supply end timing in the previous group 6. Specifically, the clock signal supply circuit 75 starts the group 6 before the pulse signal output from the last shift register 65 of the previous group 6 is input to the first shift register 65 of the next group 6. Clock signal. Thereby, the leading shift register 65 can be set in an operable state in advance.

  As shown in FIG. 6, the supply start timing of the period T2 for supplying the clock signal to the second group 6 (G2) is the supply end timing of the period T1 for supplying the clock signal to the first group 6 (G1). It is faster than. Further, the supply start timing in the period T3 for supplying the clock signal to the third group 6 (G3) is also earlier than the supply end timing in the period T2 for supplying the clock signal to the second group 6 (G2). . Repeat in the same manner. The overlap of periods for supplying the clock signal is, for example, one to several clocks of the clock signal.

  FIG. 7 is a diagram illustrating a configuration example of the clock signal supply circuit 75, and FIG. 8 is a timing chart illustrating a state example of the clock signal supply circuit 75. Although only one clock signal CK1 to CK10 is shown in the figure, the same applies to the other clock signal CKB1 to CKB10. The clock signal supply circuit 75 includes a clock generation circuit CG1 that generates a clock signal. The clock signal output from the clock generation circuit CG1 is sent to a plurality of clock signal lines CK1 to CK10 via the buffer circuit BF. Distributed.

  Level shift circuits LS1 to LS10 are provided at the output stage of the clock signal supply circuit 75 connected to the clock signal lines CK1 to CK10. The level shift circuits LS1 to LS10 boost the clock signal from the buffer circuit BF to a necessary voltage level and output it. Thus, by providing the level shift circuits LS1 to LS10 as amplifiers in the output stage, the waveform of the clock signal supplied to the shift register 65 is less likely to be dull.

  In each path from the buffer circuit BF to the level shift circuits LS1 to LS10, switches SW1 to SW10 for turning on / off the passage of the clock signal are provided. These switches SW1 to SW10 are controlled according to exclusive OR outputs (XOR outputs) x1 to x10 of the pair of counter circuits CU. The counter circuit CU counts clock pulses, and outputs 1 when a predetermined count number is reached. By appropriately setting the count number at which the counter circuit CU outputs 1, a clock signal is selectively supplied to the plurality of groups 6 as described above.

  Specifically, when the reset signal RST is input, the output y1 becomes 0, the XOR output x1 between the output y1 and the always output 1 y0 from the power supply voltage Vdd becomes 1, and the switch S1 is turned on. . When the predetermined count is reached after the switch S1 is turned on, the output y1 becomes 1, the XOR output x1 of the outputs y0 and y1 becomes 0, and the switch S1 is turned off. When the predetermined count is reached after the switch S1 is turned on, the output y2 becomes 1, the XOR output x2 of the outputs y2 and y3 becomes 1, and the switch S2 is turned on. Here, if the timing at which the output y2 becomes 1 is made earlier than the timing at which the output y1 becomes 1, the start timing of the on period of the switch S2 becomes earlier than the end timing of the on period of the switch S1. When the predetermined count number is reached after the switch S2 is turned on, the output y3 becomes 1, the XOR output x2 between the output y2 and the output y3 becomes 0, and the switch S2 is turned off. Repeat in the same manner.

  In addition, the specific structure embodied in each embodiment demonstrated above was illustrated when describing this invention, and does not limit the technical scope of this invention to this specific structure. Absent. Those skilled in the art can appropriately modify or optimize the contents disclosed in the above-described embodiments. For example, the arrangement position, number, shape, and the like of each member may be arbitrarily changed as necessary.

  DESCRIPTION OF SYMBOLS 1 Liquid crystal display device, 2 Array substrate, 3 Color filter substrate, 4 Polarizing film, 5 Image formation area, 6 Selection circuit, 7 Selection cancellation circuit, 8 Liquid crystal layer, 9 Sealing material, 21 Driver IC, 22 Connection terminal, 23 Function Film, 31 functional film, 51 TFT, 52 pixel electrode, 53 common electrode, 6 groups, 61 clock signal line, 62 start signal line, 65 shift register, 69 off signal line, 71 transistor, 75 clock signal supply circuit.

Claims (8)

An image display area comprising a plurality of pixels partitioned by a plurality of scanning signal lines and a plurality of video signal lines;
A plurality of shift registers connected to the plurality of scanning signal lines and sequentially outputting pulse signals, wherein the plurality of shift registers are divided into a plurality of groups including one or a plurality of shift registers. Registers,
A clock signal supply circuit;
A plurality of clock signal lines wired independently from each other from the clock signal supply circuit to the respective groups;
With
The clock signal supply circuit includes:
An output stage connected to each of the clock signal lines includes an amplifier,
Selectively supplying a clock signal to the plurality of groups according to an order of outputting the pulse signals;
A liquid crystal display device characterized by the above. The clock signal supply circuit supplies the clock signal to a group corresponding to an order of outputting the pulse signal among the plurality of groups.
The liquid crystal display device according to claim 1. The clock signal supply circuit does not supply the clock signal to a group that does not correspond to the order of outputting the pulse signal among the plurality of groups.
The liquid crystal display device according to claim 1. The clock signal supply circuit supplies the clock signal to the group before data is input to the first shift register of the group of the plurality of groups.
The liquid crystal display device according to claim 1. The clock signal supply circuit makes the supply start timing of the clock signal in a certain group of the plurality of groups earlier than the supply end timing of the clock signal in the previous group.
The liquid crystal display device according to claim 1. The shift register includes at least one thin film transistor having amorphous silicon as a semiconductor layer,
The liquid crystal display device according to claim 1. The plurality of shift registers are provided on at least one side of the side parallel to the video signal line of the image display area,
The clock signal supply circuit is provided on at least one side of the image display region that is parallel to the scanning signal line.
The liquid crystal display device according to claim 1. The clock signal supply circuit is included in an integrated circuit package.
The liquid crystal display device according to claim 1.

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