JP2014179484A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device capable of efficiently dissipating heat generated by a controller.
A semiconductor memory device according to an embodiment of the present invention includes a semiconductor memory and a controller that is disposed on the semiconductor memory and controls the semiconductor memory.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  Some semiconductor memory devices have a plurality of semiconductor memory chips and a controller chip for controlling the memory chips stacked and sealed in one package in order to realize miniaturization and high-density mounting. In recent years, so-called POP (Package on Package) has been proposed in which a package in which semiconductor memory chips are stacked and a package in which controller chips are sealed is stacked for the purpose of further miniaturization and high-density mounting. Has been.

  In such a semiconductor memory device, a controller is usually arranged on a wiring board for communication with a host. A semiconductor memory chip is stacked on the controller. However, as the performance of the controller is improved (particularly, the operating frequency is increased), the power consumption of the controller is also increasing. As a result, heat generated by the controller cannot be ignored. Therefore, there is a demand for a semiconductor memory device that can efficiently dissipate the heat generated by the controller.

US Pat. No. 8,310,855 U.S. Pat. No. 7,868,441 US Pat. No. 7,564,126 U.S. Pat. No. 7,464,225 US Published Patent No. 2012/238725

  An object of an embodiment of the present invention is to provide a semiconductor memory device that can efficiently dissipate heat generated by a controller.

  A semiconductor memory device according to an embodiment of the present invention includes a semiconductor memory and a controller that is disposed on the semiconductor memory and controls the semiconductor memory.

1 is a configuration diagram of a semiconductor memory device according to an embodiment. 1 is a cross-sectional view of a semiconductor memory device according to an embodiment. 1 is a schematic diagram illustrating a connection relationship of a semiconductor memory device according to an embodiment. 1 is a schematic diagram illustrating a connection relationship of a semiconductor memory device according to an embodiment. It is a block diagram of the semiconductor memory device which concerns on the modification of embodiment. It is sectional drawing of the semiconductor memory device which concerns on the modification of embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

(Embodiment)
FIG. 1 is a configuration diagram (overhead view) of a semiconductor memory device 100 according to the embodiment. As shown in FIG. 1, the semiconductor memory device 100 includes a wiring substrate 110, semiconductor packages 120A to 120E, a heat sink 130, a heat pipe 140, a temperature sensor 150, a power supply element 160, and a passive element 170.

  The wiring board 110 is, for example, a mother boat or a daughter board. The wiring board 110 is, for example, a wiring board in which wiring is formed on glass epoxy obtained by impregnating glass fiber with an epoxy resin. The semiconductor packages 120 </ b> A to 120 </ b> E are stacked on the wiring substrate 110 in the same order. As shown in FIG. 1, a high thermal conductive resin E (for example, silicone thermal conductive grease) or a film is applied and pasted on the upper surfaces of the semiconductor packages 120A to 120D. One or a plurality of semiconductor memory chips are sealed in the semiconductor packages 120A to 120D. The semiconductor memory chip is, for example, a NAND flash memory.

  The semiconductor package 120E is stacked on the semiconductor package 120D. A controller chip that controls the semiconductor packages 120A to 120D is sealed in the semiconductor package 120E. That is, the semiconductor memory device 100 has a structure in which a controller chip is stacked on a semiconductor memory chip. The stacked structure of the semiconductor packages 120A to 120E will be described later with reference to FIG.

  The controller chip in the semiconductor package 120E performs data writing, reading, erasing, and the like on the semiconductor memory chips in the semiconductor packages 120A to 120D based on a control signal from a host (not shown). The semiconductor package 120E controls the operation according to a temperature output from a temperature sensor 150 described later. Specifically, when the temperature output from the temperature sensor 150 exceeds a predetermined value (threshold), the operation speed is reduced or the operation is stopped.

  The heat sink 130 is a heat spreader. The heat radiating plate 130 uses a metal having excellent thermal conductivity (for example, copper (Cu), aluminum (Al), nickel (Ni), etc.). The heat sink 130 is disposed on the semiconductor package 120E. Further, a high thermal conductive resin (for example, silicone thermal conductive grease) or a film may be applied and pasted between the heat threader and the semiconductor package 120E. Note that the size of the heat sink 130 may be equal to or slightly larger than the controller chip, and the temperature sensor 150, the power supply element 160, and the passive element 170 can be disposed on the upper surface of the semiconductor package 120E other than the heat sink 130.

  The heat pipe 140 is disposed on the heat sink 130 in a state of being in thermal contact with the heat sink 130. The heat pipe 140 is connected to a heat exchanger such as a heat sink or a fin (not shown). For this reason, the heat generated in the semiconductor packages 120 </ b> A to 120 </ b> E is radiated to the outside of the electronic device via the heat sink 130 and the heat pipe 140.

  The temperature sensor 150 is disposed on the semiconductor package 120E. The temperature sensor 150 detects the temperature of the semiconductor package 120E. The temperature sensor 150 outputs the detected temperature to the controller chip in the semiconductor package 120E.

  The power supply element 160 is a regulator. The power supply element 160 steps down and / or boosts electric power input from the outside through the wiring board 110 and through package vias (10 and 11 in FIG. 2) and converts the electric power into a desired voltage. The power supply element 160 supplies the converted voltage to the semiconductor package 120E. The voltage stepped down and / or stepped up by the power supply element 160 may be supplied to the other semiconductor packages 120A to 120D.

  The passive element 170 is, for example, a capacitor, an inductor, a resistor, a crystal unit, or the like. The passive element 170 is placed on the wiring board 110 or the semiconductor package 120E.

  The semiconductor packages 120A to 120E are electrically connected through through-package vias (TPVs) described later with reference to FIG. The temperature sensor 150, the power supply element 160, and the passive element 170 are also electrically connected to the wiring substrate 110 and the semiconductor packages 120A to 120E. A mounting pad 11A for mounting the temperature sensor 150, the power supply element 160, and the passive element 170 is formed on the upper surface of the semiconductor package 120E. Further, a wiring for electrically connecting the through electrode and the mounting pad 11A is formed as necessary.

  FIG. 2 is a cross-sectional view of the stacked semiconductor packages 120A to 120E. In FIG. 2, illustrations other than the semiconductor packages 120 </ b> A to 120 </ b> E are omitted. Hereinafter, a stacked structure of the semiconductor packages 120A to 120E will be described with reference to FIG.

  Each of the semiconductor packages 120 </ b> A to 120 </ b> E has a configuration in which a plurality of semiconductor chips 6 stacked on the wiring substrate 2 are sealed with a sealing resin 12. Each wiring board 2 has a first wiring layer 3 on the front surface 2a and a second wiring layer 4 on the back surface 2b. The surface 2 a of each wiring board 2 of the semiconductor packages 120 </ b> A to 120 </ b> D has a semiconductor chip 6 mounting area near the center.

  The first wiring layer 3 and the second wiring layer 4 are electrically connected through a via 5. The first wiring layer 3 includes a first connection pad (not shown) arranged around the chip mounting area, and a second connection pad (not shown) arranged on the outer peripheral side from the first connection pad. have. The second wiring layer 4 has third connection pads (not shown) arranged so as to correspond to the second connection pads.

  The first connection pad functions as a connection portion with the semiconductor chip 6 mounted on the wiring board 2. The second and third connection pads function as projecting electrode forming portions to be described later, and are provided in the outer peripheral region excluding the mounting region of the semiconductor chip 6 and the corresponding region.

  A semiconductor chip 6 is mounted in the mounting area of the wiring board 2. Each semiconductor chip 6 has an electrode pad (not shown) arranged along one outer side. In FIG. 2, five semiconductor chips 6 are stacked. However, the number of stacked semiconductor chips 6 is not particularly limited (for example, one may be used). In the semiconductor packages 120A to 120D, semiconductor memory chips such as NAND flash memories are stacked as the semiconductor chip 6. In the semiconductor package 120E, one or more semiconductor chips 7 are mounted as controller chips for controlling the semiconductor memory chips.

  The semiconductor chips 6 are stacked stepwise so that the electrode pads are exposed. The electrode pads of the conductor chip 6 of each semiconductor chip 6 are electrically connected to a first connection pad located in the vicinity thereof via a metal wire (Au wire or the like) 9. Note that the electrode pads of the semiconductor chip 6 and the first connection pads may be connected by a wiring layer (conductor layer) formed by inkjet printing or the like, or may be connected by fine solder bumps.

  A first protruding electrode 10 is formed on the second connection pad of the first wiring layer 3. A second protruding electrode 11 is formed on the third connection pad of the second wiring layer 4. The first and second protruding electrodes 10 and 11 are, for example, solder balls. First and second protruding electrodes 10 and 11 using solder balls (solder bumps) can be formed by mounting and reflowing solder balls on the second and third connection pads, respectively. Note that the first and second protruding electrodes 10 and 11 constitute a through-package via (TPV).

  A resin sealing layer 12 that seals the semiconductor chip 6 together with the metal wires 9 and the first protruding electrodes 10 is formed on the first surface 2 a of the wiring board 2. The resin sealing layer 12 has a recess 13 that exposes a part of the first protruding electrode 10. That is, the semiconductor chip 6 and the metal wire 9 are sealed with the resin sealing layer 12. However, since the first protruding electrode 10 functions as an external connection terminal, a part of the first protruding electrode 10 is exposed from the recess 13 of the resin sealing layer 12.

  The concave portion 13 is formed by cutting or melting a portion corresponding to the first protruding electrode 10 of the resin sealing layer 12 or by providing a convex portion corresponding to the concave portion 13 in a resin sealing mold. The Further, the height of the first and second protruding electrodes 10 and 11 is set to a height at which the upper and lower semiconductor packages can be electrically connected when the semiconductor packages 120A to 120D are stacked. Yes.

  That is, the semiconductor packages 120A to 120E are electrically connected between the upper and lower semiconductor packages by connecting the first protruding electrode 10 of the lower semiconductor package and the second protruding electrode 11 of the upper semiconductor package. It is connected.

  3 and 4 are schematic diagrams showing connections in the semiconductor memory device 100. FIG. As shown in FIG. 3, the semiconductor package 120E in which the controller chip is sealed is connected to an external host (Host) via an external connection terminal ET of the wiring board 110. For connection with the host, Serial ATA, PCI Express, or the like is used. The semiconductor package 120E is connected to the host via the wiring substrate 110 by the through electrode constituted by the first and second protruding electrodes 10 and 11 described with reference to FIG.

  In addition, a crystal oscillator, which is one of the passive elements 170, and a temperature sensor 150 are connected to the semiconductor package 120E. From the passive element 170 (crystal oscillator) and the temperature sensor 150, the clock signal and the detected temperature are respectively penetrated by the first and second protruding electrodes 10 and 11 described with reference to FIG. Input via electrodes.

  Further, the semiconductor packages 120A to 120E and the power supply element 160 are connected to an external power supply through the wiring substrate 110 by the through electrode constituted by the first and second protruding electrodes 10 and 11 described with reference to FIG. ing. The power supply element 160 steps down and / or steps up the electric power supplied through the wiring substrate 110 and the through electrode, converts it to a desired voltage, and supplies it to the semiconductor packages 120A to 120E.

  As described above, in the semiconductor memory device 100 according to the present embodiment, the semiconductor package 120E in which the controller chip with a large amount of heat generation is sealed is arranged on the upper stage of the semiconductor packages 120A to 120D in which the semiconductor memory chip is sealed. . That is, the semiconductor package 120E that generates a large amount of heat is disposed at the top. For this reason, the heat generated in the semiconductor package 120E can be efficiently radiated.

  Moreover, since the heat sink 130 is provided on the semiconductor package 120E, the heat generated in the semiconductor package 120E can be radiated more efficiently. Similarly to the controller chip, the power supply element 160 that generates a large amount of heat is disposed on the semiconductor package 120E. For this reason, the heat generated in the power supply element 160 can be radiated efficiently.

  Furthermore, a temperature sensor 150 that detects the temperature of the semiconductor package 120E is provided. Therefore, the operation can be stopped when the temperature of the semiconductor package 120E exceeds a predetermined value (threshold value). As a result, it is possible to suppress the so-called thermal runaway of the semiconductor memory device 100. In addition, since the temperature sensor 150 is provided on the semiconductor package 120E having the heat generation amount disposed on the semiconductor package 120E in which the controller chip having a large amount of heat generation is sealed, thermal runaway with higher accuracy is provided. Can be suppressed.

(Modification of the embodiment)
In the semiconductor memory device 100 described with reference to FIGS. 1 to 4, the power supply element 160 is disposed on the semiconductor package 120 </ b> E in which the controller chip is sealed. However, when the size of the semiconductor package 120E is smaller than that of the semiconductor package 120D, the power supply element 160 may be disposed on the semiconductor package 120D as shown in FIG. In FIG. 5, the same components as those of the semiconductor memory device 100 described with reference to FIGS.

  In the semiconductor memory device 100 described with reference to FIGS. 1 to 4, the POP structure semiconductor memory device in which the semiconductor packages 120 </ b> A to 120 </ b> E are stacked has been described. However, a semiconductor memory device may be configured by stacking bare chips. FIG. 6 is a cross-sectional view of a semiconductor memory device 200 configured by stacking bare chips. In the following description, the same components as those of the semiconductor memory device 100 described with reference to FIGS.

  The semiconductor memory device 200 includes a wiring substrate 210, semiconductor chips 220A to 220E, a sealing resin 230, a heat sink 130, a temperature sensor 150, and a power supply element 160. Although not shown in FIG. 6, passive elements such as capacitors, inductors, resistors, and crystal oscillators are arranged on the wiring board 210.

  The wiring board 210 is, for example, a wiring board in which wiring is formed on glass epoxy obtained by impregnating glass fiber with an epoxy resin. The wiring board 210 has a first wiring layer 211 on the front surface 210a and a second wiring layer 212 on the back surface 210b. In addition, the wiring substrate 210 includes a through via 213 that electrically connects the first wiring layer 211 and the second wiring layer 212. On the surface 210a of the wiring substrate 210, the vicinity of the center is a mounting area for the semiconductor chips 220A to 220E.

  The semiconductor chips 220A to 220D are memory chips such as a flash memory, for example. The semiconductor chip 220E is a controller chip that controls the semiconductor chips 220A to 220D that are memory chips. The semiconductor chips 220A to 220D are formed with through electrodes 220b and bumps 220a penetrating the inside vertically. A rewiring 220c is formed on the semiconductor chip 220D.

  The sealing resin 230 seals the semiconductor chips 220A to 220E. In addition, the sealing resin 230 is filled with metal (for example, Cu, Au, Ag, Ni, Pd, Sn) in a through hole formed by a laser or the like, and a via conductor 230a is formed. Further, a mounting pad 230 b for mounting the temperature sensor 150, the power supply element 160 and the passive element 170 is formed on the upper surface of the sealing resin 230. Further, a wiring for electrically connecting the through electrode and the mounting pad 230b is formed as necessary.

  The semiconductor chips 220A to 220E are electrically connected to each other through each through electrode 220a, the bump 220b, and the rewiring layer 220c. Further, the temperature sensor 150, the power supply element 160, and the passive element 170 are connected to the semiconductor chips 220 </ b> A to 220 </ b> E and the wiring substrate 210 through via conductors 230 a and mounting pads 230 b formed in the sealing resin 230.

  The sealing resin 230 seals the semiconductor chips 220A to 220E. Similar to the semiconductor memory device 100 described with reference to FIGS. 1 to 4, a metal thin film is provided between the heat sink 130 and the sealing resin 230 or conductive grease is applied in order to lower the thermal resistance. May be.

  In the semiconductor memory device 100 described with reference to FIGS. 1 to 5, the semiconductor chips sealed in the respective semiconductor packages 120 </ b> A to 120 </ b> E are electrically connected by the metal wires 9. However, the semiconductor chips sealed in the respective semiconductor packages 120A to 120E of the semiconductor memory device 100 may be electrically connected to each other through the through electrodes 220a and the bumps 220b as shown in FIG. .

(Other embodiments)
As mentioned above, although several embodiment of this invention was described, the said embodiment is shown as an example and is not intending limiting the range of invention. The above embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications are included in the invention described in the claims and the equivalents thereof as well as included in the scope and gist of the invention.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor memory device, 110 ... Wiring board, 120A-120E ... Semiconductor package, 130 ... Heat sink, 140 ... Heat pipe, 150 ... Temperature sensor, 160 ... Power supply element, 170 ... Passive element, 200 ... Semiconductor memory device, 210 ... wiring board, 220A-220E ... semiconductor chip, 230 ... sealing resin.

Claims (5)

Semiconductor memory,
A controller disposed on the semiconductor memory and controlling the semiconductor memory;
A power supply element disposed on the semiconductor memory or the controller and supplying power to at least one of the semiconductor memory and the controller;
A temperature sensor disposed on the controller for detecting the temperature of the controller;
A heat dissipating means disposed on the controller;
With
The semiconductor memory includes a semiconductor memory chip, a sealing resin for sealing the semiconductor memory chip, and a first external connection terminal,
The controller includes a controller chip, a sealing resin that seals the controller chip, and a second external connection terminal.
A semiconductor device in which the first external connection terminal and the second connection terminal are electrically connected. Semiconductor memory,
A controller disposed on the semiconductor memory and controlling the semiconductor memory;
A semiconductor memory device.   The semiconductor memory device according to claim 2, further comprising: a power supply element that is disposed on the semiconductor memory or the controller and supplies power to at least one of the semiconductor memory and the controller.   The semiconductor memory device according to claim 2, further comprising a temperature sensor that is disposed on the controller and detects a temperature of the controller.   The semiconductor memory device according to claim 2, further comprising a heat dissipating unit disposed on the controller.

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