JP2014167842A - Semiconductor memory and controller thereof - Google Patents

Abstract

To improve the use efficiency of a storage area.
A semiconductor memory device includes a memory cell array and a control circuit that controls data access to the memory cell array. The memory cell array 111 includes a plurality of blocks, each of the plurality of blocks being stacked on the semiconductor substrate and connected in series, and a plurality of blocks connected respectively to the gates of the plurality of memory cell transistors. A word line. When a word line short defect occurs in the block, the word line in the block is divided into a plurality of areas for management.
[Selection] FIG.

Description

  Embodiments described herein relate generally to a semiconductor memory device and a controller thereof.

  A NAND flash memory in which memory cells are arranged three-dimensionally is known.

JP 2009-176384 A

  Embodiments provide a semiconductor storage device and a controller thereof that can improve the use efficiency of a storage area.

  The semiconductor memory device according to the embodiment includes a plurality of blocks, and each of the plurality of blocks is stacked on a semiconductor substrate and connected in series to the gates of the plurality of memory cell transistors. A memory cell array including a plurality of word lines connected to each other, and a control circuit for performing data access control on the memory cell array, and when a short defect of the word line occurs in the block, The word line is divided into a plurality of areas for management.

1 is a block diagram of a memory system according to a first embodiment. 1 is a block diagram of a semiconductor memory device according to a first embodiment. The circuit diagram of a memory cell array. The perspective view of a memory cell array. FIG. 3 is a cross-sectional view of a memory cell array. FIG. 3 is a cross-sectional view of a memory cell array. The perspective view of a memory cell array. The block diagram of a row decoder and a driver circuit. FIG. 9 is a diagram illustrating a voltage relationship in a write operation. The figure explaining the channel boost system at the time of write-in prohibition. The figure explaining the voltage relationship of the channel boost system in another example. 10A and 10B illustrate voltage relationships in a read operation. The figure explaining an example of the unit which divides a block into a plurality of fields. The figure explaining an example of the unit which divides a block into a plurality of fields. The flowchart of a test method. Sectional drawing which shows an example of a short defect. The figure explaining the relationship between a defect area | region and an available area | region. Sectional drawing which shows an example of a short defect. The figure explaining the relationship between a defect area | region and an available area | region. The schematic diagram of the block which has ROM fuse area | region. Flow chart of overall test method. The figure explaining the applied voltage in a short test. The circuit diagram explaining leak current detection operation. The circuit diagram explaining leak current detection operation. FIG. 6 is a schematic diagram illustrating a writing operation. The flowchart which shows the control operation of the controller 200 which concerns on 2nd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

1. First embodiment
The semiconductor memory device and its controller according to the first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cells are stacked on a semiconductor substrate will be described as an example.

1.1 Configuration
1.1.1 Memory system configuration
First, the configuration of a memory system including the semiconductor memory device according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram of a memory system according to this embodiment.

  As illustrated, the memory system includes a NAND flash memory 100, a controller 200, and a host device 300.

  The NAND flash memory 100 includes a plurality of memory cells and stores data in a nonvolatile manner. Details of the configuration of the NAND flash memory will be described later.

In response to a command from the host device 300, the controller 200 commands the NAND flash memory 100 to read, write, erase, and the like. The memory space of the NAND flash memory 100 is managed. The controller 200 and the NAND flash memory 100 may constitute the same semiconductor device, for example, and examples thereof include a memory card such as an SD ^TM card, an SSD (solid state drive), and the like.

  The controller 200 includes a host interface circuit 210, a built-in memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, and a NAND interface circuit 250.

  The host interface circuit 210 is connected to the host device 300 via the controller bus and manages communication with the host device 300. Then, the command and data received from the host device 300 are transferred to the CPU 230 and the buffer memory 240, respectively. The host interface circuit 210 transfers data in the buffer memory 240 to the host device 300 in response to a command from the CPU 230.

  The NAND interface circuit 250 is connected to the NAND flash memory 100 via the NAND bus and manages communication with the NAND flash memory 100. Then, the command received from the CPU 230 is transferred to the NAND flash memory 100, and the write data in the buffer memory 240 is transferred to the NAND flash memory 100 at the time of writing. Further, at the time of reading, the data read from the NAND flash memory 100 is transferred to the buffer memory 240.

  The CPU 230 controls the operation of the entire controller 200. For example, when a read command is received from the host device 300, a read command based on the NAND interface is issued in response thereto. The same applies to writing and erasing. The CPU 230 executes various processes for managing the NAND flash memory 1 such as wear leveling. Further, the CPU 230 executes various calculations. For example, data encryption processing, randomization processing, error checking (ECC) processing, and the like are executed.

  The built-in memory 220 is a semiconductor memory such as a DRAM, and is used as a work area for the CPU 230. The built-in memory 220 holds firmware for managing the NAND flash memory 100, various management tables, and the like.

1.1.2 Configuration of semiconductor memory device
Next, the configuration of the semiconductor memory device 100 will be described.

1.1.2.1 Overall configuration of semiconductor memory device
FIG. 2 is a block diagram of the NAND flash memory 100 according to the present embodiment. As shown in the figure, a NAND flash memory 100 includes a memory cell array 111, a row decoder (R / D) 112, a sense amplifier 113, a page buffer 120, a column decoder 121, a latch circuit 122, an input / output circuit 130, and a control circuit (sequencer). 141, a voltage generation circuit (charge pump) 142, an address / command register 143, and a driver 144.

  The memory cell array 111 includes a plurality of (four in the example of FIG. 2) blocks BLK (BLK0 to BLK3) that are a set of nonvolatile memory cells. The block BLK serves as a data erasing unit, and data in the same block BLK is erased collectively. Each of the blocks BLK includes a plurality (four in this example) of string groups GP (GP0 to GP3) that are sets of NAND strings 114 in which memory cells are connected in series. Of course, the number of blocks in the memory cell array 111 and the number of string groups in one block BLK are arbitrary.

  The row decoder 112 receives a block address signal and the like from the address / command register 143 and receives a word line control signal and a selection gate control signal from the driver 144. The row decoder 112 selects a specific block or word line WL based on the received block address signal, word line control signal, and selection gate control signal. The row decoder 112 may be provided on both sides of the memory cell array 111.

  The sense amplifier 113 senses and amplifies data read from the memory cell when reading data. When data is written, the write data is transferred to the memory cell. Data reading and writing to the memory cell array 111 are performed in units of a plurality of memory cells, and this unit becomes a page. The definition of page details will be described later.

  The page buffer 120 holds data in units of pages. When reading data, the page buffer 120 temporarily holds the data transferred from the sense amplifier 113 in units of pages, and transfers the data serially to the input / output unit 130. On the other hand, when data is written, the data transferred serially from the input / output unit 130 is temporarily held and transferred to the sense amplifier 113 in units of pages.

  The input / output circuit 130 controls transmission / reception of various commands and data to / from the controller 200 via the NAND bus. The address / command register 143 receives commands and addresses from the input / output circuit 130 and holds them.

  The driver 144 supplies voltages necessary for writing, reading, and erasing data to the row decoder 112, the sense amplifier 113, and a source line driver (not shown). This voltage is applied to memory cells (a word line, a select gate line, a back gate line, a bit line, and a source line, which will be described later) by the row decoder 112, the sense amplifier 113, and the source line driver.

  The voltage generation circuit 142 boosts a power supply voltage supplied from the outside and supplies a necessary voltage to the driver 144.

  The latch circuit 122 temporarily holds the management data read from the ROM fuse of the memory cell array 111 at the time of power-on, for example. The management data includes information regarding the defective area in the block. The management data will be described later. The latch circuit 122 is composed of, for example, an SRAM.

  The control circuit 141 controls the operation of the entire NAND flash memory 100.

1.1.2.2 Memory cell array 111
Next, details of the configuration of the memory cell array 111 will be described. FIG. 3 is a circuit diagram of the block BLK0. The blocks BLK1 to BLK3 have the same configuration.

  As illustrated, the block BLK0 includes, for example, four string groups GP. Each string group GP includes n (n is a natural number) NAND strings 114.

  Each of the NAND strings 114 includes, for example, eight memory cell transistors MT (MT0 to MT7), select transistors ST1 and ST2, and a back gate transistor BT. The memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and holds data in a nonvolatile manner. The number of memory cell transistors MT is not limited to 8, and may be 16, 32, 64, 128, etc., and the number is not limited. Similar to the memory cell transistor MT, the back gate transistor BT also includes a stacked gate including a control gate and a charge storage layer. However, the back gate transistor BT is not for holding data but functions as a simple current path at the time of writing, reading and erasing data. Memory cell transistor MT and back gate transistor BT are arranged between select transistors ST1 and ST2 such that their current paths are connected in series. Note that the back gate transistor BT is provided between the memory cell transistors MT3 and MT4. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2. ing.

  The gates of the select transistors ST1 of the string groups GP0 to GP3 are commonly connected to select gate lines SGD0 to SGD3, respectively, and the gates of the select transistors ST2 are commonly connected to select gate lines SGS0 to SGS3, respectively. In contrast, the control gates of the memory cell transistors MT0 to MT7 in the same block BLK0 are commonly connected to the word lines WL0 to WL7, respectively, and the control gate of the back gate transistor BT is the back gate line BG (in the blocks BLK0 to BLK3). BG0 to BG3), respectively.

  That is, the word lines WL0 to WL7 and the back gate line BG are commonly connected between the plurality of string groups GP0 to GP3 in the same block BLK0, while the select gate lines SGD and SGS are connected to the same block BLK0. Even if it exists, it is independent for every string group GP0-GP3.

  In addition, among the NAND strings 114 arranged in a matrix in the memory cell array 111, the other end of the current path of the select transistor ST1 of the NAND string 114 in the same row is connected to any one of the bit lines BL (BL0 to BLn, n Are commonly connected to natural numbers). That is, the bit line BL commonly connects the NAND strings 114 between the plurality of blocks BLK. Further, the other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. For example, the source line SL connects the NAND strings 114 in common between a plurality of blocks.

  As described above, the data of the memory cell transistors MT in the same block BLK are erased collectively. On the other hand, data reading and writing are performed collectively for a plurality of memory cell transistors MT connected in common to any word line WL in any string group GP in any block BLK. . This unit is called “page”.

  Next, a three-dimensional stacked structure of the memory cell array 111 will be described with reference to FIGS. 4 and 5 are a perspective view and a cross-sectional view of the memory cell array 111. FIG.

  As illustrated, the memory cell array 111 is provided on the semiconductor substrate 20. The memory cell array 111 includes a back gate transistor layer L1, a memory cell transistor layer L2, a selection transistor layer L3, and a wiring layer L4 that are sequentially formed on the semiconductor substrate 20.

  The back gate transistor layer L1 functions as the back gate transistor BT. The memory cell transistor layer L2 functions as the memory cell transistors MT0 to MT7 (NAND string 114). The selection transistor layer L3 functions as selection transistors ST1 and ST2. The wiring layer L4 functions as the source line SL and the bit line BL.

  The back gate transistor layer L1 includes a back gate conductive layer 21. The back gate conductive layer 21 is formed to expand two-dimensionally in a first direction D1 and a second direction D2 parallel to the semiconductor substrate 20 (that is, in the first direction and the second direction, memory cells are stacked). Is orthogonal to the third direction D3). The back gate conductive layer 21 is divided for each block BLK. The back gate conductive layer 21 is formed of, for example, polycrystalline silicon. The back gate conductive layer 21 functions as a back gate line BG.

  The back gate conductive layer 21 has a back gate hole 22 as shown in FIG. The back gate hole 22 is formed so as to dig the back gate conductive layer 21. The back gate hole 22 is formed in a substantially rectangular shape with the first direction as the longitudinal direction when viewed from the top.

  The memory cell transistor layer L2 is formed in the upper layer of the back gate conductive layer L1. The memory cell transistor layer L2 includes word line conductive layers 23a to 23d. The word line conductive layers 23a to 23d are stacked with an interlayer insulating layer (not shown) interposed therebetween. The word line conductive layers 23a to 23d are formed in stripes extending in the second direction with a predetermined pitch in the first direction. The word line conductive layers 23a to 23d are made of, for example, polycrystalline silicon. The word line conductive layer 23a functions as a control gate (word lines WL3, WL4) of the memory cell transistors MT3, MT4, and the word line conductive layer 23b functions as a control gate (word lines WL2, WL5) of the memory cell transistors MT2, MT5. The word line conductive layer 23c functions as control gates (word lines WL1, WL6) for the memory cell transistors MT1 and MT6, and the word line conductive layer 23d functions as control gates (word lines WL0, WL7) for the memory cell transistors MT0 and MT7. Function as.

  Further, the memory cell transistor layer L2 has a memory hole 24 as shown in FIG. The memory hole 24 is formed so as to penetrate the word line conductive layers 23a to 23d. The memory hole 24 is formed so as to align with the vicinity of the end portion of the back gate hole 22 in the first direction.

  Further, the back gate transistor layer L1 and the memory cell transistor layer L2 include a block insulating layer 25a, a charge storage layer 25b, a tunnel insulating layer 25c, and a semiconductor layer 26, as shown in FIG. The semiconductor layer 26 functions as the body of the NAND string 114 (back gate of each transistor).

  As shown in FIG. 5, the block insulating layer 25 a is formed with a predetermined thickness on the side wall facing the back gate hole 22 and the memory hole 25. The charge storage layer 25b is formed with a predetermined thickness on the side surface of the block insulating layer 25a. The tunnel insulating layer 25c is formed with a predetermined thickness on the side surface of the charge storage layer 25b. The semiconductor layer 26 is formed in contact with the side surface of the tunnel insulating layer 25c. The semiconductor layer 26 is formed so as to fill the back gate hole 22 and the memory hole 24.

  The semiconductor layer 26 is formed in a U shape when viewed from the second direction. That is, the semiconductor layer 26 includes a pair of columnar portions 26 a extending in a direction perpendicular to the surface of the semiconductor substrate 20, and a connecting portion 26 b connecting the lower ends of the pair of columnar portions 26 a.

The block insulating layer 25a and the tunnel insulating layer 25c are made of, for example, silicon oxide (SiO ₂ ). The charge storage layer 25b is made of, for example, silicon nitride (SiN). The semiconductor layer 26 is made of polycrystalline silicon. The block insulating layer 25a, the charge storage layer 25b, the tunnel insulating layer 25c, and the semiconductor layer 26 form a MONOS transistor that functions as the memory transistor MT.

  In other words, the configuration of the back gate transistor layer L1 is such that the tunnel insulating layer 25c is formed so as to surround the connecting portion 26b. The back gate conductive layer 21 is formed so as to surround the connecting portion 26b.

  In other words, the configuration of the memory transistor layer L2 is such that the tunnel insulating layer 25c is formed so as to surround the columnar portion 26a. The charge storage layer 25b is formed so as to surround the tunnel insulating layer 25c. The block insulating layer 25a is formed so as to surround the charge storage layer 25b. The word line conductive layers 23a-23d are formed so as to surround the block insulating layers 25a-25c and the columnar portion 26a.

  The select transistor layer L3 includes conductive layers 27a and 27b as shown in FIGS. The conductive layers 27a and 27b are formed in a stripe shape extending in the second direction so as to have a predetermined pitch in the first direction. The pair of conductive layers 27a and the pair of conductive layers 27b are alternately arranged in the first direction. The conductive layer 27a is formed in an upper layer of one columnar portion 26a, and the conductive layer 27b is formed in an upper layer of the other columnar portion 26a.

  Conductive layers 27a and 27b are formed of polycrystalline silicon. The conductive layer 27a functions as the gate (select gate line SGS) of the select transistor ST2, and the conductive layer 27b functions as the gate (select gate line SGD) of the select transistor ST1.

  As shown in FIG. 5, the select transistor layer L3 has holes 28a and 28b. The holes 28a and 28b penetrate through the conductive layers 27a and 27b, respectively. The holes 28a and 28b are aligned with the memory hole 24, respectively.

  As shown in FIG. 5, the select transistor layer L3 includes gate insulating layers 29a and 29b and semiconductor layers 30a and 30b. The gate insulating layers 29a and 29b are formed on the side walls facing the holes 28a and 28b, respectively. The semiconductor layers 30a and 30b are formed in a column shape extending in a direction perpendicular to the surface of the semiconductor substrate 20 so as to be in contact with the gate insulating layers 29a and 29b, respectively.

The gate insulating layers 29a and 29b are made of, for example, silicon oxide (SiO ₂ ). The semiconductor layers 30a and 30b are made of, for example, polycrystalline silicon.

  In other words, the configuration of the selection transistor layer L3 is such that the gate insulating layer 29a surrounds the columnar semiconductor layer 30a. The conductive layer 27a is formed so as to surround the gate insulating layer 29a and the semiconductor layer 30a. The gate insulating layer 29b is formed so as to surround the columnar semiconductor layer 30b. The conductive layer 27b is formed so as to surround the gate insulating layer 29b and the semiconductor layer 30b.

  As shown in FIGS. 4 and 5, the wiring layer L4 is formed in an upper layer of the selection transistor layer L3. The wiring layer L4 includes a source line layer 31, a plug layer 32, and a bit line layer 33.

  The source line layer 31 is formed in a plate shape extending in the second direction. The source line layer 31 is formed so as to be in contact with the upper surfaces of a pair of semiconductor layers 27a adjacent in the first direction. The plug layer 32 is formed so as to be in contact with the upper surface of the semiconductor layer 27 b and to extend in a direction perpendicular to the surface of the semiconductor substrate 20. The bit line layer 33 is formed in a stripe shape extending in the first direction with a predetermined pitch in the second direction. The bit line layer 33 is formed in contact with the upper surface of the plug layer 32. The source line layer 31, the plug layer 32, and the bit line layer 33 are formed of a metal such as tungsten (W), for example. The source line layer 31 functions as the source line SL described in FIG. 3, and the bit line layer 33 functions as the bit line BL.

  6 and 7 show another example of the memory cell array 111. FIG. 6 is a cross-sectional view along the bit line direction, and FIG. 7 is a perspective view.

  As shown in the drawing, the semiconductor layer 26 may have a single columnar shape instead of the U-shape as shown in FIGS. In this case, as shown in FIGS. 6 and 7, a source line layer 31 is formed above the semiconductor substrate, and a plurality of columnar semiconductor layers 30 are formed on the source line layer 31. Then, around the semiconductor layer 30, a selection transistor ST2, memory cell transistors MT0 to MT7, and a selection transistor ST1 are formed in order from the bottom, and a bit line layer 33 is further formed. In the case of this configuration, the back gate transistor BT is not necessary.

1.1.2.3 Row Decoder 112 Next, the configuration of the row decoder 112 will be described with reference to FIG. FIG. 8 is a block diagram of the row decoder 112 and the driver 144, and the row decoder 112 shows only the configuration associated with one of the blocks BLK. That is, the row decoder 112 shown in FIG. 8 is provided for each block BLK. The row decoder 112 selects or deselects the associated block BLK.

  As shown, the row decoder 112 includes a block decoder 41 and high breakdown voltage n-channel enhancement type (E type) MOS transistors 42 to 46 (42-0 to 42-7, 43-0 to 43-3, 44-0 to 44). -3, 45-0 to 45-3, 46-0 to 46-3), 47.

<About Block Decoder 41>
First, the block decoder 41 will be described. The block decoder 41 decodes the block address BA and outputs signals TG and / RDECA when data is written, read and erased. When the block address BA matches the corresponding block BLK, the signal TG is set to the “H” level. The voltage of the signal TG set to the “H” level is VPGMH at the time of writing, VREADH at the time of reading, and Vdda at the time of erasing. Further, the signal / RDECA is set to the “L” level (for example, 0 V).

  On the other hand, when the block address BA does not coincide with the block BLK, the signal TG is set to “L” level (eg, 0 V), and the signal / RDECA is set to “H” level.

  Note that VPGMH is a voltage for transferring the high voltage VPGM applied to the selected word line at the time of data writing, and VPGMH> VPGM. VREADH is a voltage for transferring the voltage VREAD applied to the non-selected word line at the time of reading data, and VREADH> VREAD. Vdda is a voltage for transferring a voltage Vdd (for example, 0 V) applied to the word line when erasing data, and Vdda> Vdd.

<Regarding Transistor 42>
Next, the transistor 42 will be described. The transistor 42 is for transferring a voltage to the word line WL of the selected block BLK. In each of the transistors 42-0 to 42-7, one end of the current path is connected to the word lines WL0 to WL7 of the corresponding block BLK, the other end is connected to the signal lines CG0 to CG7, and the gate is connected to the signal line TG. Connected in common.

  Therefore, for example, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 42-0 to 42-7 are turned on, and the word lines WL0 to WL7 are connected to the signal lines CG0 to CG7. On the other hand, in the row decoders 112-1 to 11-3 corresponding to the non-selected blocks BLK1 to BLK3, the transistors 42-0 to 42-7 are turned off, and the word lines WL0 to WL7 are separated from the signal lines CG0 to CG7. The

  The transistor 42 is commonly used for all string groups GP in the same block BLK.

<Regarding the transistors 43 and 44>
Next, the transistors 43 and 44 will be described. The transistors 43 and 44 are for transferring a voltage to the select gate line SGD. In each of the transistors 43-0 to 43-3, one end of the current path is connected to the select gate lines SGD0 to SGD3 of the corresponding block BLK, the other end is connected to the signal lines SGDD0 to SGDD3, and the gate is connected to the signal line TG. Connected in common. Each of the transistors 44-1 to 44-3 has one end of the current path connected to the select gate lines SGD0 to SGD3 of the corresponding block BLK0, the other end connected to the node SGD_COM, and a signal / RDECA applied to the gate. . The node SGD_COM is a voltage for turning off the selection transistor ST1, such as 0V or a negative voltage VBB.

  Therefore, for example, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 43-0 to 43-3 are turned on, and the transistors 44-0 to 44-3 are turned off. Therefore, the select gate lines SGD0 to SGD3 of the selected block BLK0 are connected to the signal lines SGDD0 to SGDD3.

  On the other hand, in the row decoders 112-1 to 11-3 corresponding to the non-selected blocks BLK1 to BLK3, the transistors 43-0 to 43-3 are turned off and the transistors 44-0 to 44-3 are turned on. The Therefore, the select gate lines SGD0 to SGD3 of the non-selected blocks BLK1 to BLK3 are connected to the node SGD_COM.

<Regarding the transistors 45 and 46>
The transistors 45 and 46 are for transferring a voltage to the select gate line SGS, and their connection and operation are equivalent to the transistors 43 and 44 in which the select gate line SGD is replaced with the select gate line SGS.

  That is, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 45-0 to 45-3 are turned on and the transistors 46-0 to 44-4 are turned off. On the other hand, in the row decoders 112-1 to 11-3 corresponding to the unselected blocks BLK1 to BLK3, the transistors 43-0 to 43-3 are turned off and the transistors 44-1 to 44-3 are turned on. The

<Regarding Transistor 47>
Next, the transistor 47 will be described. The transistor 47 is for transferring a voltage to the back gate line BG. The transistor 47 has one end of the current path connected to the back gate line BG of the corresponding block BLK, the other end connected to the signal line BGD, and the gate connected to the signal line TG in common.

  Accordingly, in the row decoder 112 corresponding to the selected block BLK0, the transistor 47 is turned on, and in the row decoders 112-1 to 11-3 corresponding to the non-selected blocks BLK1 to BLK3, the transistor 47 is turned off.

  Of course, when the memory cell array 111 has the configuration of FIGS. 6 and 7, the transistor 47 is unnecessary.

1.1.2.4 About the driver 144
Next, the configuration of the driver 144, particularly the configuration for transferring the voltage to the row decoder 112, will be described with reference to FIG. The driver 144 transfers a voltage necessary for data writing, reading, and erasing to each of the signal lines CG0 to CG7, SGDD0 to SGDD3, SGSD0 to SGSD3, and BGD.

  As shown in FIG. 8, the driver 144 includes a CG driver 51 (51-0 to 51-7), an SGD driver 52 (52-0 to 52-3), an SGS driver 53 (53-0 to 53-3), and a BG. A driver 54 and a voltage driver 55 are provided.

  The voltage driver 55 receives the voltage from the charge pump 142 and transfers necessary voltages to the block decoder 41 and the CG driver 51 as voltages VRDEC and VCGSEL. The CG drivers 51-0 to 51-7 respectively transfer necessary voltages to the signal lines CG0 to CG7 (word lines WL0 to WL7) according to the page address. The SGD drivers 52-0 to 52-3 transfer necessary voltages to the signal lines SGDD0 to SGDD3 (select gate lines SGD0 to SGD3), respectively. The SGS drivers 53-0 to 53-3 transfer necessary voltages to the signal lines SGSD0 to SGSD3 (select gate lines SGS0 to SGS3), respectively. The BG driver 54 transfers a necessary voltage to the signal line BGD.

1.2 Write operation
Next, the write operation will be described. FIG. 9 is a diagram for explaining the voltage relationship in the write operation. In FIG. 9, the back gate transistor BT is not shown. The back gate transistor BT is turned on at the time of writing. For example, word lines WL0 to WL23 are provided in the block, and data is written to the word line WL10.

  A power supply voltage VDD or a ground voltage VSS (0 V) is applied to the bit line BL according to write data. A column for writing data (injecting charge into the charge storage layer to increase the threshold voltage) is given 0V, and writing is prohibited (to maintain the threshold voltage without injecting charge into the charge storage layer). Is supplied with a power supply voltage VDD. A write voltage VPGM (for example, 20 V) is applied to the selected word line WL10. The write voltage VPGM is a high voltage for injecting charges into the charge storage layer.

  A cut-off voltage VISO (for example, 0 V) for isolating (cutting off) the channel is applied to the unselected word line WL7. Intermediate voltage VGP is applied to unselected word line WL8. A write pass voltage VPASS (for example, 10 V) is applied to the other non-selected word lines WL0 to WL6, WL9, and WL11 to WL23. The write pass voltage VPASS is a high voltage that turns on the memory cell transistor regardless of the retained data. The intermediate voltage VGP is a voltage that alleviates an abrupt potential difference between the cutoff voltage VISO and the write pass voltage VPASS, and is “VISO <VGP <VPASS”.

  The voltage VSGD is applied to the select gate line SGD. The voltage VSGD is a voltage that turns on the selection transistor ST1 to which 0 V is applied to the bit line BL (that is, the drain) and cuts off the selection transistor ST1 to which the power supply voltage VDD is applied. 0V is applied to the select gate line SGS, and the select transistor ST2 is turned off. 0 V is applied to the source line SL.

  As a result, in the selected string group GP, in the NAND string in which 0 V is applied to the bit line BL, the selection transistor ST1 is turned on. Therefore, 0V is transferred to the channel of the memory cell transistor MT10, and charges are injected into the charge storage layer. On the other hand, in the NAND string in which the power supply voltage VDD is applied to the bit line BL, the selection transistor ST1 is cut off. Therefore, the channel of this NAND string is in a floating state, and the channel potential rises due to coupling with the word line WL. In particular, since the memory cell transistor MT7 cuts off the channel, the channel voltages of the memory cell transistors MT8 to MT23 are efficiently boosted. As a result, no charge is injected into the charge storage layer of the memory cell transistor MT10, and no data is written (a write inhibit state is realized).

  On the other hand, in the non-selected string group GP, the selection transistors ST1 and ST2 are turned off. Therefore, no data is written in the non-selected string group GP.

  FIG. 10 is a diagram for explaining a channel boost method when writing is prohibited. The horizontal axis in FIG. 10 indicates the number of the selected word line, and the vertical axis in FIG. 10 indicates the voltage applied to the word line.

  The selected word line WLi is used. A write voltage VPGM is applied to the selected word line WLi. Cut-off voltage VISO is applied to unselected word line WLi-3. When writing is performed in ascending order from the word line WL0, the boosted channel portion decreases as the word line number increases. Therefore, boost efficiency improves as the writing in the block proceeds.

  The channel boost method for realizing write inhibition is not limited to the voltage relationship described above. For example, the voltage VGP may be omitted, and WL10 = VPGM, WL9 = VPASS, and WL8 = VISO may be set. That is, when the selected word line WLi is used, the cut-off voltage VISO is applied to the unselected word line WLi-2.

  FIG. 11 is a diagram illustrating the voltage relationship of the channel boost method in another example. A cut-off voltage VISO is further applied to the non-selected word line WL12 on the bit line side from the selected word line WL10. Thereby, the channel can be cut off on both sides of the selected word line WL10. In the example of FIG. 11, since the channel region to be boosted is further reduced, boost efficiency can be further improved.

1.3 Read operation
Next, the reading operation will be described. FIG. 12 is a diagram illustrating the voltage relationship in the read operation. In FIG. 12, the back gate transistor BT is not shown. The back gate transistor BT is turned on at the time of reading. For example, word lines WL0 to WL23 are provided in the block, and data is read from the word line WL9.

  First, the bit line BL is precharged to the voltage VPRE by the sense amplifier 113. A read voltage VCGR is applied to the selected word line WL9. The read voltage VCGR is a voltage corresponding to the level to be read. The voltage VREAD is applied to the unselected word lines WL0 to WL8 and WL10 to WL23. VREAD is a voltage that turns on the memory cell transistor MT regardless of the retained data.

  A voltage VSG (for example, 5 V) is applied to the select gate line SGD. VSG is a voltage that turns on the select transistors ST1 and ST2. 0V is applied to the select gate line SGS, and 0V is applied to the source line SL.

  As a result, in the selected string group GP, the selection transistors ST1 and ST2 are turned on. Therefore, when the memory cell transistor MT of the read target page is turned on, a current flows from the bit line BL to the source line SL. On the other hand, no current flows in the off state.

  On the other hand, in the non-selected string group GP, the selection transistors ST1 and ST2 are turned off. Therefore, data is not read from the non-selected string group GP.

  Note that FIG. 12 is merely an example, and for example, a positive voltage VSRC (for example, 2.5 V) may be applied to the source line SL. In this case, the potentials of the bit line BL, the word line WL, the back gate line BG, and the select gate lines SGD, SGS are set to values obtained by adding VSRC to the voltage described above.

1.4 Test method of NAND flash memory 100
1.4.1 Word line short test
Next, a test method for the NAND flash memory 100 configured as described above will be described. In this embodiment, one block is managed by dividing it into a plurality of regions in the vertical direction (stacking direction). FIG. 13 is a diagram illustrating an example of a unit for dividing a block into a plurality of regions. In FIG. 13, two NAND strings in one block are extracted and shown.

  In the example of FIG. 13, one block is managed by being divided into four areas AR0 to AR3. When one or more short defects occur in a word line in a certain area AR, the area AR is managed as a defective area.

  FIG. 14 is a diagram illustrating an example of a unit for dividing a block having a columnar (I-shaped) semiconductor layer into a plurality of regions. In the example of FIG. 14, one block is managed by being divided into four areas AR0 to AR3. The present invention is not limited to dividing one block into four areas, and may be divided into, for example, 8 areas, 16 areas, and the like. When one or more short defects occur in a word line in a certain area AR, the area AR is managed as a defective area.

  FIG. 15 is a flowchart of a test method performed on the NAND flash memory 100 before shipment. The test of this embodiment is a test (short test) for checking a short circuit between word lines. In the short test, for example, a tester is used to check whether or not the test target word lines are short-circuited.

  The following short tests are sequentially performed in units of blocks. First, in the block to be tested, a short test between all the word line layers is performed simultaneously (collectively) (step S200). Specifically, a short test between word lines adjacent in the horizontal direction and a short test between word lines adjacent in the vertical direction are performed. As a result of the short test (1) in step S200, if there is no short between all the word line layers, the block has no short defect, and therefore the tester registers the block BLK as a good block (step S201).

  If it is determined as a result of the short test (1) that a word line short has occurred, the four areas AR0 to AR3 in the block are individually subjected to a short test (step S202). As a result of the short test (2) in step S202, an area AR in which a short defect of the word line has occurred is specified. A specific example of the short test will be described later.

  Subsequently, a short test of two adjacent areas AR is performed simultaneously (step S203). The short test (3) in step S203 is a test for determining a short defect in a word line which is arranged at the boundary between two adjacent areas AR and which is adjacent in the vertical direction. The short test (3) in step S203 includes a step of simultaneously performing a short test of the regions AR0 and AR1, a step of simultaneously performing a short test of the regions AR1 and AR2, and a step of simultaneously performing a short test of the regions AR2 and AR3. One process is included. According to the short test (3) in step S203, no short defect has occurred as an individual area AR, that is, an area in which the short test (2) has been passed but a short defect has occurred between two adjacent areas AR. AR can be detected. When a short defect occurs between two adjacent areas AR, the two areas AR are determined to be defective areas.

  Subsequently, based on the results of the short tests (2) and (3), the defective area and the unused area in the block are specified (step S204), and the defective area and the unused area are registered in the tester. The defective area corresponds to an area AR in which a word line short defect has occurred as a result of the short test (2), and two adjacent areas AR in which a word line short defect has occurred as a result of the short test (3). However, this defective area is not used as a data storage area.

  The unused area is a buffer area for boost voltage control at the time of writing, and corresponds to the area AR on both sides of the defective area. That is, a region in which boost voltage control cannot be performed because a short circuit failure has not occurred but is adjacent to the defective region is defined as a non-use region. The unused area is not used as a data storage area like the defective area. The defective area and the unused area are collectively referred to as a sub-bad block area.

  FIG. 16 is a cross-sectional view showing an example of a short circuit defect. In FIG. 16, a short defect of the word line has occurred in the area AR2. Therefore, the area AR2 is a defective area. The areas AR1 and AR3 on both sides of the area AR2 are unused areas. For example, assuming that data is written to the word line WL9, the voltage for performing channel boost control cannot be applied to the word lines WL6 to WL8, so the area AR3 becomes an unused area. Similarly, for example, assuming that data is written to the word line WL18, since the voltage for performing the channel boost control cannot be applied to the word lines WL15 to WL17, the area AR1 becomes an unused area. The remaining area excluding the defective area where the short defect has occurred and the non-use area among the non-defective areas other than the defective area from all the areas AR0 to AR3 in the block is the usable area used as the data storage area. .

  FIG. 17 is a diagram for explaining the relationship between a defective area where a short-circuit defect has occurred and a usable area. A punishment point (cross) in FIG. 17 represents a defective area in which a short defect has occurred, and a circle in FIG. 17 represents a non-defective area other than the defective area.

  As can be understood from FIG. 17, of all the areas AR0 to AR3, an area excluding the defective area and the unused areas adjacent to both sides thereof becomes the usable area. For example, when the area AR4 is a defective area, the area A3 adjacent to the area A4 becomes a non-use area, so the usable areas are the area A1 and the area A2. A block having a defective area other than the pattern shown in FIG. 17 is a bad block. For example, in a block in which the areas AR0 and AR2 are defective areas, the areas AR1 and AR3 adjacent to the areas AR0 and AR2, respectively, are unused areas, so that the block is a bad block.

  FIG. 18 is a cross-sectional view showing an example of a short circuit defect in a block having an I-shaped semiconductor layer. In FIG. 18, a short defect of the word line has occurred in the area AR2. Therefore, the area AR2 is a defective area. In the example of FIG. 18, writing is performed upward from the lowermost layer (WL0) of the word line. In this case, a region adjacent to the upper side of the defective region is a non-use region where boost voltage control cannot be performed. Therefore, in FIG. 18, the area AR1 adjacent to the upper side of the area AR2 is an unused area. The remaining areas AR0 and AR3 excluding the defective area AR2 in which the short defect has occurred and the unused area AR1 from all the areas AR0 to AR3 in the block are usable areas used as data storage areas.

  FIG. 19 is a diagram for explaining the relationship between a defective area and a usable area in a block having an I-shaped semiconductor layer. As can be understood from FIG. 18, of all the areas AR <b> 0 to AR <b> 3, the area excluding the defective area and the unused area adjacent to the upper side is the usable area. A block having a defective area other than the pattern shown in FIG. 19 is a bad block. Note that when the channel boost method of FIG. 11 is used, both sides of the defective area are set as buffer areas (non-use areas).

  Returning to FIG. 15, the tester writes management data to the memory cell array 111 (step S205). The management data here includes information on the good block, bad block, and sub-bad block areas (defective area and unused area) obtained by the short test. This management data is written in the ROM fuse of the memory cell array 111.

  For example, it is assumed that the block BLKm of the memory cell array 111 is designated as a block having a ROM fuse area. FIG. 20 is a schematic diagram of a block BLKm having a ROM fuse area. As shown in the figure, two pages PG1 and PG2 in the block BLKm are used as ROM fuse areas. The same management data is stored in the two pages PG1 and PG2. The management data described above is stored in this ROM fuse area.

1.4.2 Test Status Registration Method Next, a test status registration method will be described. FIG. 21 is a flowchart for explaining a short circuit between word lines and other tests.

  First, a test other than a short circuit between word lines is performed (step S300). The test in step S300 includes a bit line and sense amplifier test and a wiring short test other than the word line. The test in step S300 is performed on all blocks.

Subsequently, the inter-word line short test shown in FIG. 15 is performed on the test target block (step S301).
Subsequently, the test status is registered. An example of status [2: 0] is as follows.
“000”: Good block “001”: Partial good block (usable area AR0)
“010”: Partial good block (usable area AR3)
“011”: Partial good block (usable area AR0, 1)
“100”: partial good block (usable area AR2, 3)
“111”: True Bad Block When the block to be tested is not a good block (step S302), a bad block flag is registered in the tester (step S302). Subsequently, when the block to be tested is not an authentic bad block (that is, includes an available area) (step S304), the status of the partial good block is registered in the tester (step S305).

  Subsequently, when the short test between word lines and the status registration of all the blocks are completed (step S306), the process proceeds to a test process other than steps S300 and S301 (step S307).

1.4.3
Next, a specific example of the short test will be described. In the short test, two word lines adjacent in the horizontal direction are charged to different voltages, and further, two word lines adjacent in the vertical direction are charged to different voltages. FIG. 22 is a diagram illustrating the applied voltage in the short test.

  For example, it is assumed that a short test of the area AR0 is performed, and the two types of voltages are the voltage VPGM and the voltage VPASS. For example, the word lines WL1, 2, 23 are charged to the write voltage VPGM, and the word lines WL0, 2, 22 are charged to the write pass voltage VPASS. As a result, adjacent word lines are charged to different voltages in each of the horizontal and vertical directions. Then, it is detected whether or not a leakage current is generated in a plurality of selected word lines charged to one voltage.

  FIG. 23 is a circuit diagram illustrating a leakage current detection operation. Driver 144 includes N-channel MOS transistors DR1 to DR4. One end of the current path of the MOS transistor DR1 is connected to the terminal 73, and the other end is connected to the node VCGSEL. The voltage VPGM is applied to one end of the current path of the MOS transistor DR2, and the other end is connected to the node VCGSEL. The read voltage VCGR is applied to one end of the current path of the MOS transistor DR3, and the other end is connected to the node VCGSEL. A non-select voltage VUSEL (VPASS or VREAD) is applied to one end of the current path of the MOS transistor DR4, and the other end is connected to a non-selected word line. Node VCGSEL is connected to the selected word line. Switching between the selected word line and the non-selected word line is performed using, for example, a command from a tester.

  A leak detection circuit 70 is connected to the terminal 73. The leak detection circuit 70 includes a voltage generation circuit 71 and an ammeter 72. The leak detection circuit 70 may be included in the tester or may be incorporated in the NAND flash memory 100. A leak current due to a short between the word lines has a very small current value. In order to detect this very small current value, it is practical to incorporate the leak detection circuit 70 in the NAND flash memory 100.

  In the leakage current detection operation, first, the selected word line (WL0, WL2, WL4 in the example of FIG. 23) is charged to the voltage VPGM via the MOS transistor DR2, and the unselected word line (through the MOS transistor DR4). In the example of FIG. 23, WL1, WL3) is charged to the voltage VUSEL (= VPASS).

  Subsequently, as shown in FIG. 24, after the MOS transistors DR2 and DR4 are turned off, the MOS transistor DR1 is turned on. In this state, when no short failure has occurred between the word lines, no leakage current flows through the MOS transistor DR1, and therefore the leakage current is not detected by the leakage detection circuit 70. On the other hand, when a short failure occurs between the word lines, a leak current Ileak flows through the MOS transistor DR1, and this leak current Ileak is detected by the leak detection circuit 70.

  As described above, leakage current detection, that is, a short test can be realized. The case where the area of the short test is increased can be implemented as in the case of the area AR0.

1.5 Operation of NAND flash memory 100
Next, the operation of the NAND flash memory 100 will be described. First, the controller 200 supplies power to the NAND flash memory S10. Then, the control circuit 141 reads management data from the ROM fuse of the memory cell array 111 and stores the read management data in the latch circuit 122. Thereafter, the control circuit 141 treats the defective area and the unused area as non-selected areas (non-write areas) based on the management data of the latch circuit 122.

  In a write operation on a block having a defective area, the control circuit 141 controls to write data only in the usable area of the block. That is, the control circuit 141 does not write data in the defective area and the unused area. At this time, the write pass voltage VPASS is applied to all the word lines in the defective area. Other voltage control is the same as the write operation described in FIG. For example, as shown in FIG. 25, it is assumed that the area AR0 is a defective area, the area AR1 is an unused area, and the areas AR2 and AR3 are usable areas. In this example, in the write operation, the write pass voltage VPASS is applied to all the word lines in the area AR0, and voltage control in the normal write operation is performed on the areas AR1 to AR3.

  In a read operation for a block having a defective area, the control circuit 141 controls to read data only from the usable area of the block. That is, the control circuit 141 does not read data from the defective area and the unused area. At this time, the voltage VREAD is applied to all the word lines in the defective area. Other voltage control is the same as the read operation described in FIG.

  In the case of a writing method in which the cut-off voltage VISO is not used at the time of writing, that is, the channel is not cut off halfway, control is performed so that only the defective area is set as a non-selected area. In this case, data can be written in the entire non-defective area other than the defective area.

1.6 Effect While the memory capacity can be increased by stacking memory cells, if the peripheral circuit such as a row decoder remains in a planar structure, the peripheral circuit becomes larger than the memory cell array. However, the chip size cannot be reduced. Although the chip size can be reduced by sharing the word line with a plurality of NAND strings, the block size increases as the word line is shared. As the block size increases, the performance decreases due to the increase in the erase unit, and the yield decreases due to the increase in the defective replacement unit. For example, when a short defect occurs in a word line in a block, the block is conventionally defective, that is, a bad block.

  On the other hand, in the present embodiment, the word lines in the block are managed by being divided into a plurality of regions in the stacking direction. In addition, by managing the area where the word line short-circuit defect has occurred as a defective area and the other areas as non-defective areas, it is possible to avoid treating the entire block as defective and minimize the reduction in the storage area available to the user. Can be suppressed. As a result, the use efficiency of the storage area can be improved.

  In addition, an area where voltage control required for the channel boost method cannot be performed is managed as an unused area where data is not written. As a result, data can be written accurately even when various write methods are applied to a block in which a word line short defect has occurred.

  Note that if a short defect of a word line occurs in a block after product shipment, a write error occurs during writing. If this write error can be relieved by error correction (ECC), the block is used as it is. On the other hand, if the error is the number of bits that cannot be remedied by ECC, the status becomes Status Fail and the block is converted into a bad block.

  As for erasure, if an erasure error occurs due to a short defect in the word line, the status becomes Status Fail and the block is made into a bad block. If an erase error does not occur even if a word line short defect occurs, the block is used as it is.

2. Second Embodiment In the first embodiment, the control circuit 141 in the NAND flash memory 100 restricts access to a block including a defective area in which a short defect of a word line has occurred. In the second embodiment, the controller 200 that controls the NAND flash memory 100 restricts access to a block including a defective area.

FIG. 26 is a flowchart showing the control operation of the controller 200.
First, the controller 200 turns on the NAND flash memory 100 (step S400). Subsequently, the controller 200 reads information (management data) in the ROM fuse from the NAND flash memory 100 (step S401). The information received by the controller 200 in step S401 is management data stored in the pages PG1 and PG2 in FIG. 20, and includes information regarding good blocks, bad blocks, and sub-bad block areas (defective areas and unused areas). . Note that step S401 may be performed by a request from the controller 200 or may be performed spontaneously by the NAND flash memory 100 without receiving a request from the controller 200 (POR: Power on Read). .

  The controller 200 stores the management data received from the NAND flash memory 100, for example, in the RAM 220. Then, the NAND flash memory 100 is accessed in response to a request from the host device 300 (step S402). At this time, the controller 200 accesses only the usable area among the blocks including the good block and the defective area based on the management data in the RAM 220, and does not access the bad block and the sub-bad block area.

  As described above in detail, in the second embodiment, the controller 200 can be configured not to access the sub-bad block area. As a result, the processing load of the NAND flash memory 100 can be reduced, and specification changes can be minimized.

  In each of the above embodiments, a plurality of regions are divided into one block along the stacking direction. This is because in the stacked memory, the frequency of occurrence of word line short-circuit defects tends to vary along the stacking direction. That is, in the stacked memory, since a plurality of wirings are stacked in the trench, the probability that a word line short-circuit defect occurs in the lower part is higher than that in the upper part. However, the criteria for dividing the blocks are not limited to the stacking direction, and can be set as appropriate according to the status of the word line short circuit failure.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 41 ... Block decoder, 51 ... CG driver, 52 ... SGD driver, 53 ... SGS driver, 54 ... BG driver, 55 ... Voltage driver, 70 ... Leak detection circuit, 100 ... Semiconductor memory device, 111 ... Memory cell array, 112 ... Row Decoder, 113 ... Sense amplifier, 114 ... NAND string, 120 ... Page buffer, 121 ... Column decoder, 122 ... Latch circuit, 130 ... I / O circuit, 141 ... Control circuit, 142 ... Voltage generation circuit, 143 ... Address command register DESCRIPTION OF SYMBOLS 144 ... Driver, 200 ... Controller, 210 ... Host interface circuit, 220 ... RAM, 230 ... CPU, 240 ... Buffer memory, 250 ... NAND interface circuit, 300 ... Host apparatus.

Claims (6)

Each of the plurality of blocks includes a plurality of memory cell transistors stacked on a semiconductor substrate and connected in series, and a plurality of word lines respectively connected to gates of the plurality of memory cell transistors. A memory cell array comprising:
A control circuit for performing data access control on the memory cell array;
Comprising
2. A semiconductor memory device according to claim 1, wherein when a short defect of a word line occurs in the block, the word line in the block is divided into a plurality of areas for management. The plurality of regions are divided along a stacking direction,
2. The semiconductor memory device according to claim 1, wherein an area that does not include a word line in which a short defect has occurred is managed as a non-defective area, and an area that includes a word line in which a short defect has occurred is managed as a defective area.   The semiconductor memory device according to claim 2, wherein the control circuit performs data access to the non-defective region and does not perform data access to the defective region. A ROM fuse for storing information on the defective area in a nonvolatile manner;
4. The semiconductor memory device according to claim 3, wherein the control circuit controls the voltage of the word line so that the defective area is in a non-selected state using information stored in the ROM fuse. A controller for controlling the semiconductor memory device according to claim 2,
A controller that reads information on the defective area from the semiconductor memory device and controls the information so as not to access the defective area.   The controller according to claim 5, further comprising a storage unit that stores information on the defective area.

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