JP2014165642A - Amplifier and amplification method - Google Patents

Abstract

An image signal suppressing effect can be remarkably exhibited even when characteristics are varied among a plurality of DPAs, and an apparatus can be manufactured at a low cost.
When phase adjustment signals having different phases are input to at least two or more DPAs 11 _{1 to} 11 _N that perform amplification control of an input signal in synchronization with a clock signal based on discrete amplitude information, The phase controller 16 adjusts the phase of the clock signal input to each of the DPAs 11 _{1 to} 11 _N so that the amplitude of the image signal included in the synthesized signal obtained by synthesizing the signals output from the DPAs 11 _{1 to} 11 _N is maximized. The change amount is determined, and the phase variable unit 14 adjusts the phase of the clock signal input to each of the DPAs 11 _{1 to} 11 _N according to the change amount of the phase of the clock signal after the change amount is determined.
[Selection] Figure 3

Description

  The present invention relates to an amplification device and an amplification method for amplifying an input signal.

  In the field of digital communications such as mobile communications, in order to increase the frequency utilization efficiency, modulation schemes in which the envelope becomes a non-constant envelope, such as QPSK (Quadrature Phase Shift Keying), QAM (Quadrature Amplitude Modulation), OFDM (Orthogonal) Frequency Division Multiplexing) has been used. In these modulation schemes, the power amplifier operates at a back-off level that is somewhat below the saturation output.

  In general, a high-frequency power amplifier has good power efficiency in the saturation region, and the power efficiency decreases as the linear region is reached. Therefore, in order to prevent a reduction in power efficiency during the back-off operation, it is necessary to operate the power amplifier as close to the saturation region as possible.

  There is a digital power amplifier that enables such an operation. In a digital power amplifier, output switching control is performed by a circuit such as an inverter, and operation in a saturation region is realized. The amplitude of the output signal is controlled by a discrete value (digital value) given separately. In this respect, the digital power amplifier can be said to be a digital-analog converter (hereinafter referred to as DAC).

  The amplitude control of the output signal is performed every sampling period. As is well known, in the DAC, so-called image signals such as spurious and aliasing noise are generated in the vicinity of the sampling frequency which is the reciprocal of the sampling period.

  For example, in mobile communication and wireless LAN, a signal having a frequency of 1 GHz to several GHz is used as an RF (Radio Frequency) signal. Since the sampling frequency is several MHz to several hundred MHz, the image signal is an RF signal. It often occurs in the vicinity.

  To remove this, a very complicated and expensive filter must be used. Therefore, as a method for suppressing an image signal without using a filter, there is a method in which a plurality of DACs are prepared and each DAC is interleaved (see, for example, Patent Document 1 and Non-Patent Document 1).

FIG. 1 is a schematic diagram illustrating a configuration of a conventional amplifying apparatus 1 that suppresses an image signal by the above method, and FIG. 2 is a conceptual diagram illustrating the above method. As shown in FIG. 1, the amplifying apparatus 1 includes four DPAs (Digital Power Amplifiers) 2 ₁ to 2 ₄ and a 90-degree phase shifter 3.

DPA2 ₁ to 2 ₄ receives a sampling clock signal, and an input of the discrete amplitude information values, according to the amplitude information values, in synchronization with the sampling clock signal for amplifying the input signal. 90-degree phase shifter 3, and generates a sampling clock signal having different phases by 90 degrees, and supplies the sampling clock signals of different phases to each DPA2 ₁ to 2 _4.

  FIG. 2 shows the timing of the sampling clock whose frequency fs is 500 kHz. In FIG. 2, the frequency f0 of the desired signal to be output is 50 kHz. That is, sampling is performed on a signal having a frequency of 50 kHz at a clock timing having a frequency of 500 kHz. In this case, an image signal having a frequency of 450 kHz (= fs−f0) appears. 2A to 2D show an image signal having a frequency of 450 kHz.

  Here, the sampling clock whose timing is shown in FIGS. 2B to 2D is the same as the sampling clock whose timing is shown in FIG. 270 degrees off. In this case, the phase of the image signal having a frequency of 450 kHz is also shifted by 90 degrees, 180 degrees, and 270 degrees, respectively.

Therefore, when combining the output signals of the DPA2 ₁ to 2 _4, small whereas larger summed amplitude of the frequency component of the frequency 50 kHz, amplitude of the frequency component of the frequency 450kHz is canceled out. The conventional amplifying apparatus 1 shown in FIG. 1 uses this phenomenon to suppress the image signal.

US Pat. No. 7,164,328

Amirpouya Kavousian, David K. Su, Mohammad Hekmat, Alireza Shirvani, Bruce A. Wooley, "A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

However, in the prior art described above, due to variations in characteristics that exist between the respective DPA2 ₁ to 2 _4, the capability of suppressing the image signal is lowered. Such variation in characteristics occurs because it is difficult to uniformly manufacture elements constituting each DPA.

  In order to reduce this variation, it is conceivable to increase the size of the element. In this case, however, the chip area increases and the power consumption also increases. In order to avoid such an adverse effect, it is conceivable to provide a mechanism for detecting an image signal and adjusting it so as to minimize it.

  However, such a mechanism complicates the configuration of the apparatus and increases the manufacturing cost. Further, as the image signal is suppressed, it becomes difficult to detect the image signal, so that it is difficult to further enhance the suppression effect of the image signal.

  The present invention provides an amplifying apparatus and an amplifying method capable of remarkably exhibiting the effect of suppressing an image signal even when characteristics are varied among a plurality of DPAs, and enabling manufacturing of the apparatus at a low cost. The purpose is to do.

  According to the amplification device of the present invention, at least two or more amplifiers that perform amplification control of an input signal in synchronization with a clock signal based on discrete amplitude information, and phase adjustment signals having different phases are input to the respective amplifiers. A phase control unit that determines a change amount of the phase of the clock signal input to each amplifier so that the amplitude of the image signal included in the combined signal obtained by combining the signals output from the amplifiers is maximized, After the change amount is determined, a configuration is provided that includes a phase variable unit that adjusts the phase of the clock signal input to each amplifier in accordance with the change amount of the phase of the clock signal.

  In the amplification method of the present invention, when phase adjustment signals having different phases are input to at least two or more amplifiers that perform amplification control of an input signal in synchronization with a clock signal based on discrete amplitude information, A control step for determining the amount of change in the phase of the clock signal input to each amplifier so that the amplitude of the image signal included in the combined signal obtained by combining the signals output from each amplifier is maximized, and determination of the amount of change And adjusting the phase of the clock signal input to each amplifier in accordance with the amount of change in the phase of the clock signal.

  According to the present invention, even when there are variations in characteristics among a plurality of DPAs, the effect of suppressing an image signal can be remarkably exhibited, and an apparatus can be manufactured at low cost.

Schematic showing the configuration of a conventional amplifying device that suppresses image signals Conceptual diagram explaining how to perform interleave operation The block diagram which shows an example of a structure of the amplifier which concerns on embodiment of this invention The figure explaining an example of the image signal suppression process which concerns on embodiment of this invention Diagram explaining the binary search method The figure explaining the synthesis | combination of the output signal of DPA The figure which shows an example of a structure of the radio | wireless communication apparatus which detects a synthesized signal using a receiving circuit The figure which shows the spectrum of the signal which is output with the variable gain amplifier

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a block diagram showing an example of the configuration of the amplifying apparatus 10 according to the embodiment of the present invention. The amplification device 10 is mounted on, for example, a wireless communication device that performs communication using wireless radio waves.

The amplifying apparatus 10 includes a DPA (Digital Power Amplifier) 11 _{1 to} 11 _N (N is an integer of 2 or more; the same applies hereinafter), an N-phase signal generator 12, a 360 / N-degree phase shifter 13, and a phase variable unit 14. , An amplitude detection unit 15, a phase control unit 16, and an input switching unit 17.

The DPAs 11 _{1 to} 11 _N receive the sampling clock signal and the input of the discrete amplitude information value, and amplify the input signal in synchronization with the sampling clock signal according to the amplitude information value.

  The N-phase signal generator 12 generates N types of sine wave signals for phase adjustment (hereinafter referred to as phase adjustment signals) whose phases are different by (360 / N) degrees. For example, the N-phase signal generator 12 generates a sine wave signal using sine wave data stored in advance in a memory (not shown) or the like.

  The 360 / N degree phase shifter 13 generates N kinds of sampling clock signals whose phases are different by (360 / N) degrees. The 360 / N degree phase shifter 13 can be easily configured using a frequency divider or the like. The phase variable unit 14 changes the phase of the sampling clock signal output from the 360 / N-degree phase shifter 13 based on a control signal from the phase control unit 16 described later. The phase variable unit 14 can be configured by preparing a plurality of inverter elements and switching their outputs or using a frequency divider or the like.

The amplitude detection unit 15 detects the amplitude of the image signal included in the combined signal obtained by combining the signals output from the DPAs 11 _{1 to} 11 _N. For example, the amplitude detector 15 may be provided in a semiconductor chip in which the DPAs 11 _{1 to} 11 _N are constructed. Thereby, the circuit area can be reduced and the cost can be reduced.

  Then, the phase control unit 16 determines the amount of change in the phase of the sampling clock signal so that the amplitude is maximized. This change amount is stored in a memory (not shown) or the like. A specific determination method will be described later.

The phase control unit 16 may also be provided in the semiconductor chip on which the DPAs 11 _{1 to} 11 _N are constructed. Alternatively, the phase control unit 16 may be configured using a control microcomputer or a processor provided in the wireless communication device. Thereby, the circuit area can be reduced and the cost can be reduced.

The input switching unit 17 switches a signal input to the DPAs 11 _{1 to} 11 _N between a phase adjustment signal generated by the N-phase signal generator 12 and an amplitude information value used for amplification of the input signal.

Specifically, the input switching unit 17 inputs a phase adjustment signal to the DPAs 11 _{1 to} 11 _N when adjusting the phase of the sampling clock signal, and amplitude information to the DPAs 11 _{1 to} 11 _N when performing normal communication. Enter a value. The adjustment of the amplifying apparatus 10 is performed, for example, when the power is supplied to the amplifying apparatus 10 or when the amplifier apparatus 10 returns from the sleep mode in intermittent communication. Alternatively, the adjustment of the amplification device 10 may be performed periodically.

  Next, an example of the image signal suppression process according to the embodiment of the present invention will be described. FIG. 4 is a diagram for explaining an example of image signal suppression processing according to the embodiment of the present invention. In FIG. 4, an example in which N is 4 will be described. However, if N is 2 or more, the image signal suppression process can be executed as in the case where N is 4.

  FIG. 4 shows the timing of the sampling clock whose frequency fs is 500 kHz. In FIG. 4, the frequency f0 of the desired signal to be output is 50 kHz. That is, sampling is performed on a signal having a frequency of 50 kHz at a clock timing having a frequency of 500 kHz. In this case, an image signal appears at a frequency of 450 kHz (= fs−f0). 4A to 4D show an image signal having a frequency of 450 kHz.

  Here, the sampling clock whose timing is shown in FIGS. 4B to 4D is the same as the sampling clock whose timing is shown in FIG. 270 degrees off. In this case, the phase of the image signal having a frequency of 450 kHz is also shifted by 90 degrees, 180 degrees, and 270 degrees, respectively.

As described above, when the amplification device 10 is adjusted, the DPAs 11 _{1 to} 11 ₄ are each input with a phase adjustment signal whose phase is shifted by 90 degrees. Therefore, as shown in FIG. 4 (A) ~ FIG _{4 (D), DPA11 1 ~11} 4 image signals of frequency 450kHz outputted from phase matching substantially, the desired signal frequency 50kHz phase approximately 90 degrees It will shift one by one.

Therefore, when combining the output signals of the DPA11 ₁ ~11 _4, whereas the amplitude of the image signal is summed increases included in the output signals, the amplitude of the desired signal becomes smaller cancel.

Here, the phase of the image signal is not aligned perfectly, also not be the that the phase of the desired signal is shifted by fully 90 degrees, there is a variation in the characteristics of the DPA11 ₁ ~11 _4, each DPA11 ₁ ~11 _This is because a phase shift occurs between the _four output signals.

For this reason, when adjusting the amplifier 10, the phase control unit 16, the amplitude of the image signal in the composite signal (signal image signals are synthesized in the output signal of each DPA11 ₁ ~11 ₄₎ is maximum The amount of change in the phase of the sampling clock signal is determined so that

At the time of normal communication, the phase variable unit 14 changes the phase of the sampling clock signal input by the change amount each DPA11 ₁ ~11 _4. Then, input switching unit 17 receives the amplitude information values DPA11 ₁ ~11 _4, to perform the amplification of RF signals using the amplitude information value to each DPA11 ₁ ~11 _4. By performing such processing, it is possible to suppress the primary to tertiary image signals without increasing the circuit scale.

In this case, for example, the phase control unit 16 performs other three sampling clock signals (DPA11 _{2 to} 11 ₄ ) with respect to the phase of a certain sampling clock signal (for example, the sampling clock signal input to the DPA11 ₁ ). The amplitude of the image signal can be maximized by sequentially changing the phase of the sampling clock signal input to.

  When N is an even number equal to or greater than 2, the phase control unit 16 can also change the phase of the sampling clock signal as follows. In the following, the case of FIG. 4, that is, the case where N is 4 will be described as an example.

First, the N-phase signal generator 12 generates two types of phase adjustment signals (for example, signals having phases of 0 degrees and 180 degrees) that are 180 degrees different in phase. Then, the input switching unit 17 inputs the respective phase adjustment signals to the different DPAs 11 ₁ and 11 ₃ .

Thereafter, the phase control unit 16 changes the phase of the sampling clock signal input to _one of the DPAs 11 ₁ and 11 ₃ , and in the synthesized signal obtained by synthesizing the signals output from the DPAs 11 ₁ and 11 ₃ , the amplitude of the image signal The amount of phase change is determined so that becomes maximum. This change amount is stored in a memory (not shown) or the like.

Next, the N-phase signal generator 12 has two types of phase adjustment signals (for example, signals having phases of 90 degrees and 270 degrees) having phases different from the phase adjustment signal generated last time but having a phase difference of 180 degrees. ) And the respective phase adjustment signals are input to different DPAs 11 ₂ and 11 ₄ .

Then, the phase control unit 16 changes the phase of one of DPA11 _2, 11 ₄ sampling clock signal input, in DPA11 _2, 11 synthesized composite signal a signal output from the _4, the image signal amplitude The amount of phase change is determined so that becomes maximum. This change amount is stored in a memory (not shown) or the like.

Then, N-phase signal generator 12, all phases (0 °, 90 °, 180 °, 270 °) to generate a phase adjustment signal, and inputs the phase adjustment signals to the respective DPA11 ₁ ~11 ₄ .

Here, the phase variable unit 14 adjusts the phase of the sampling clock signal based on the change amount. Thus, DPA11 _1, 11 ₃ aligned phase image signal in signals output from, also would DPA11 _2, 11 ₄ of the image signal in the signals output from the phase aligned.

Then, the phase control unit 16, DPA11 _1, 11 ₃ of the set, or, DPA11 _1, to change the 11 _third set of phase one of the sampling clock signal input to the set, the output from DPA11 ₁ ~11 ₄ The amount of phase change is determined so that the amplitude of the image signal is maximized in the synthesized signal obtained by synthesizing the signals to be processed. This change amount is stored in a memory (not shown) or the like.

  By performing such processing, it is possible to determine an optimal phase change amount in a shorter time than in the case where the phases of the four sampling clock signals are sequentially adjusted.

  Further, when determining the optimum amount of change in the phase of the sampling clock signal, for example, a binary search method is used. FIG. 5 is a diagram for explaining the binary search method. The vertical axis in FIG. 5 indicates the amplitude of the image signal in the composite signal described above. The horizontal axis indicates the amount of phase change. The change amount p0 indicates the optimum change amount that maximizes the amplitude.

  First, the phase control unit 16 sets the amount of phase change to p1. Then, the amplitude detector 15 detects the amplitude corresponding to the change amount p1. Next, the phase control unit 16 sets the amount of phase change to p2. Then, the amplitude detector 15 detects the amplitude corresponding to the change amount p2.

  Here, the change amounts p1 and p2 define both ends of the search range of the optimum change amount p0. This search range is set sufficiently wide in advance so that the change amount p0 is included in the range from p1 to p2.

  Subsequently, the phase control unit 16 sets the phase change amount to p3 (= (p1 + p2) / 2) which is an intermediate between p1 and p2. Then, the amplitude detector 15 detects the amplitude corresponding to the change amount p3.

  Then, the phase control unit 16 changes the change amount (p2 in the example of FIG. 5) corresponding to the amplitude having a large value among the two change amounts p1 and p2 that are both ends of the search range, and the change amount that is an intermediate point. A range having both ends of p3 is set as the next search range. By repeating such processing, the phase control unit 16 can efficiently detect the phase change amount p0 at which the amplitude is maximized in a short time.

  Here, although the phase control unit 16 uses the binary search method, the phase change amount is sequentially increased from the end point p1 toward the end point p2, and the change amount that maximizes the amplitude is detected. It is good. In this case, the phase control unit 16 determines that the change amount immediately before the amplitude starts to decrease is the change amount p0. Alternatively, the change amount p0 may be searched using a three-part search method, a golden section search method, or other algorithms for obtaining extreme values.

Next, the synthesis of output signals of DPAs 11 _{1 to} 11 _N will be described. FIG. 6 is a diagram illustrating the synthesis of output signals of DPAs 11 _{1 to} 11 _N. 6A shows a spectrum of output signals of the DPAs 11 _{1 to} 11 _N during normal communication, and FIG. 6B shows output signals of the DPAs 11 _{1 to} 11 _N during adjustment of the amplifying device 10. This is the spectrum of the synthesized signal.

Here, fRF is the frequency of the RF signal input to the DPAs 11 _{1 to} 11 _N , fs is the frequency of the sampling clock signal, and f0 is the frequency of the sine wave signal input by the N-phase signal generator 12 at f0. is there.

As shown in FIG. 6A, the output signal spectrum of DPAs 11 _{1 to} 11 _N includes a side lobe (modulation signal) having a frequency of fRF ± f0 and a frequency of fimg (= fRF ± (fs−f0). )) Image signal appears.

Then, by inputting sine waves whose phases are different by (360 / N) degrees from the N-phase signal generator 12 to the DPAs 11 _{1 to} 11 _N , respectively, as shown in FIG. 6B, the frequency becomes fRF ± f0. The side lobe is suppressed, and the image signal whose frequency is fimg is enhanced.

The phase control unit 16 sets the change amount of the phase of the sampling clock signal so that the degree of enhancement of the image signal is maximized. Thus, it is possible to align the phase of the image signal included in the signals output from the respective DPA11 ₁ ~11 _N.

When performing normal communication, the input switching unit 17 inputs amplitude information values to the DPAs 11 _{1 to} 11 _N , and the phase variable unit 14 applies the change amount to the phase of the sampling clock signal.

Thereby, even when there is a variation in characteristics among the plurality of DPAs 11 _{1 to} 11 _N , the effect of suppressing the image signal can be remarkably exhibited. Further, since the image signals are added when the output signals of the DPAs 11 _{1 to} 11 _N are combined, a detection circuit having a dynamic range that is not so large and a resolution that is not so high can be used for detecting the image signal.

  For example, when suppressing an image signal by 70 dB, a detector having the same dynamic range and an AD converter equivalent to 12 bits are required, which complicates the circuit. However, according to the above method, complication of the circuit is avoided. can do.

  Next, a case where the amplitude of the image signal described above is detected using a receiving circuit that processes a signal received by the receiving antenna will be described. FIG. 7 is a diagram illustrating an example of a configuration of the wireless communication device 20 that detects the amplitude of an image signal using a receiving circuit.

The wireless communication device 20 includes DPAs 21 _{1 to} 21 ₄ , a four-phase signal generator 22, a 90-degree phase shifter 23, a phase variable unit 24, an attenuator 25, a phase control unit 26, an input switching unit 27, and a receiving circuit 30. .

Here, the DPAs 21 _{1 to} 21 ₄ , the four-phase signal generator 22, the 90-degree phase shifter 23, the phase variable unit 24, the phase control unit 26, and the input switching unit 27 are respectively the DPAs 11 _{1 to} 11 _N shown in FIG. , N phase signal generator 12, 360 / N degree phase shifter 13, phase variable unit 14, phase control unit 16, and input switching unit 17. Here, for simplification, FIG. 7 shows a case where the number of DPAs is four, but the number of DPAs may be any number equal to or greater than two as in the case of FIG.

The attenuator 25 attenuates the signal input to the receiving circuit 30. This amplitude of a signal output from DPA21 ₁ ~21 ₄ is a receiving circuit 30 is larger than the amplitude of the processable signal.

  The reception circuit 30 is a circuit that performs reception processing on a signal received by the reception antenna. Although FIG. 7 shows a general Low-IF receiver circuit, the present invention is not limited to this, and a heterodyne receiver circuit or a direct conversion receiver circuit may be used for detection of the composite signal.

The reception circuit 30 includes a low noise amplifier 31, a PLL (Phase Locked Loop) circuit 32, mixers 33 ₁ and 33 ₂ , variable gain amplifiers 34 ₁ , 34 ₂ and 36, a complex filter 35, an A / D converter 37, and a reception signal. A processing unit 38 is provided.

The low noise amplifier 31 amplifies a signal in a desired RF band. Here, the output signal from the attenuator 25 is input to the low noise amplifier 31. If the amplitude of the output signal is within a predetermined range, the output signal from the attenuator 25 is input to the mixers 33 ₁ and 33 ₂ . It may be input directly.

The PLL circuit 32 inputs signals of a predetermined frequency to the mixers 33 ₁ and 33 ₂ . The mixers 33 ₁ and 33 ₂ convert the frequency of the received signal into an intermediate frequency. The variable gain amplifiers 34 ₁ , 34 ₂ , 36 amplify the signal to a predetermined level.

  The complex filter 35 extracts a desired signal from the signal converted to the intermediate frequency. The A / D converter 37 converts the analog signal extracted by the complex filter 35 into a digital signal. The received signal processing unit 38 performs predetermined processing according to the digital signal obtained as a result of the conversion.

Here, it is assumed that the combined signal whose spectrum is shown in FIG. 6B is input to the receiving circuit 30 via the attenuator 25. Further, it is assumed that the PLL circuit 312 inputs a signal having a frequency fRF to the mixers 33 ₁ and 33 ₂ .

  FIG. 8 is a diagram showing a spectrum of a signal output from the variable gain amplifier 36 in this case. As shown in FIG. 8, the variable gain amplifier 36 outputs a sine wave signal with a frequency f0 and an image signal with a frequency fimg (= fs−f0) generated by the four-phase signal generator 22.

  The image signal is converted into a digital signal by the A / D converter 37, and the digital signal is input to the phase control unit 26. The phase control unit 26 refers to the digital signal and determines the amount of change in the phase of the sampling clock signal so that the amplitude of the image signal is maximized by the method described above.

  In the above embodiment, the amplitude value of the image signal in the composite signal is detected, and the amount of change in the phase of the sampling clock signal is determined based on the amplitude value. The phase change amount at which the amplitude of the image signal is maximized may be determined by detecting the power and determining the phase change amount at which the power is maximized.

  The amplifying apparatus and the amplifying method according to the present invention are suitable for use in an apparatus that suppresses an image signal using a plurality of DPAs.

_{1, 10,} 20 Amplifying device 2 _{1 to} 2 ₄ , 11 _{1 to} 11 _N , 21 _{1 to} 21 ₄ DPA
3 90-degree phase shifter 12 N-phase signal generator 13 360 / N-degree phase shifter 14, 24 Phase variable section 15 Amplitude detection section 16, 26 Phase control section 17, 27 Input switching section 22 4-phase signal generator 23 90 Phase shifter 25 Attenuator 30 Receiving circuit 31 Low noise amplifier 32 PLL (Phase Locked Loop) circuit 33 ₁ , 33 ₂ Mixer 34 ₁ , 34 ₂ , 36 Variable gain amplifier 35 Complex filter 37 A / D converter 38 Received signal Processing part

Claims (9)

Based on discrete amplitude information, at least two or more amplifiers that perform amplification control of the input signal in synchronization with the clock signal;
When a phase adjustment signal having a different phase is input to each amplifier, the amplitude of the image signal included in the combined signal obtained by combining the signals output from the amplifiers is maximized. A phase control unit for determining the amount of change in the phase of the clock signal, and
After the determination of the amount of change, a phase variable unit that adjusts the phase of the clock signal input to each amplifier according to the amount of change in the phase of the clock signal,
An amplification device comprising: The phase control unit determines a change amount of the phase between two phase adjustment signals belonging to each set in a plurality of sets each including two phase adjustment signals whose phases are shifted by 180 degrees, and the change amount The amplification device according to claim 1, wherein the phase change amount is determined between phase adjustment signals that do not belong to the same group. The amplification device according to claim 1, wherein the phase control unit detects the combined signal using a reception circuit that processes a signal received by a reception antenna. The amplification device according to claim 1, wherein the phase control unit determines a change amount of the phase by a bisection method. The amplifying apparatus according to claim 1, wherein the phase control unit determines the amount of phase change by sequentially changing the phase of each clock signal. The amplifying apparatus according to claim 1, further comprising an input switching unit that switches whether or not to input the phase adjustment signal to the amplifier. The amplifying apparatus according to claim 1, further comprising a signal generator that generates the phase adjustment signal.   A wireless communication device comprising the amplifying device according to claim 1. A signal output from each amplifier when a phase adjustment signal having a different phase is input to at least two or more amplifiers that perform amplification control of an input signal in synchronization with a clock signal based on discrete amplitude information A control step for determining a change amount of the phase of the clock signal input to each amplifier so that the amplitude of the image signal included in the synthesized signal obtained by synthesizing is maximized;
After the determination of the change amount, an adjustment step of adjusting the phase of the clock signal input to each amplifier according to the change amount of the phase of the clock signal,
An amplification method comprising:

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