JP2014160721A - Field effect transistor - Google Patents

Abstract

A field effect transistor capable of protecting a collapse suppression film under a gate electrode against a hole current generated when a high voltage is applied and capable of realizing higher reliability is provided.
In a normally-on type field effect transistor 1 in which a source electrode 9, a drain electrode 10 and a gate electrode 11 disposed between these electrodes are formed on the surface side of a stack of a plurality of nitride semiconductors, The physical semiconductor has at least an Al _x Ga _1-x N breakdown voltage layer 4, a GaN channel layer 5, and an Al _y Ga _1-y N (0 <x <y <0.5) barrier layer 6. A collapse suppression film 7 was formed on a portion between the surfaces of the plurality of nitride semiconductors and the gate electrode 11.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor.

  A field effect transistor (FET) based on a nitride semiconductor, GaN, has a wide bandgap and generates a two-dimensional electron gas generated at the AlGaN / GaN interface in the laminated structure of the GaN layer and the AlGaN layer. It can be used as an electronic channel. As a result, it is expected that a high breakdown voltage characteristic and a low Ron characteristic can be realized as compared with a field effect transistor using conventional Si.

  In such a field effect transistor, there is a concern about the phenomenon of current collapse. Current collapse is a phenomenon in which the on-resistance value during high-voltage operation is higher than the on-resistance value during low-voltage operation, and a high output cannot be obtained when the drain current decreases. Known causes of current collapse include the influence of trap levels in the semiconductor and the presence of traps at the interface between the semiconductor and its protective film. A conventional technique for suppressing this current collapse is disclosed in Patent Document 1.

In the conventional field effect transistor described in Patent Document 1, the surface of the laminated semiconductor is covered with a laminated film composed of a first insulating film (SiN) and a second insulating film (SiO ₂ ), and the gate electrode is a drain electrode. A field plate portion is formed on the insulating film so as to project on the side. The balance between the current collapse and the gate breakdown voltage is improved by the synergistic effect of the laminated film composed of the two insulating films and the field plate portion.

JP 2004-200248 A

  However, when the inventors of the present application operate by applying a high voltage exceeding 600 V to a conventional field effect transistor made of a nitride semiconductor, there is a problem that the gate electrode is destroyed in the reliability test. The investigation of the cause of this destruction led to the following mechanism.

  At the time of high voltage operation of a conventional field effect transistor, impact ionization occurs due to hot electrons, or holes (current) are generated directly from the drain electrode. The holes flow in the direction of the gate electrode to which a negative bias (−10 V) is applied. At that time, holes accumulate in the collapse suppression film under the gate insulating film. By continuing such hole accumulation, the electric field generated in the collapse suppression film under the gate electrode is infinitely increased, and it is considered that the gate electrode was eventually destroyed.

  FIG. 7 shows the drain current when an off voltage of −10 V is applied to the gate electrode of a conventional field effect transistor made of a nitride semiconductor, and a voltage of up to 1000 V is sequentially applied to the drain electrode. 4 is an experimental data graph showing the relationship between the gate current and substrate current and the drain voltage. According to FIG. 7, the drain current, the gate current, and the substrate current are maintained at low values until the drain voltage is up to 600 V, and good off characteristics are exhibited.

  However, each current starts to increase when the drain voltage exceeds 600V. In particular, the substrate current generated around 600 V is considered to be a hole current because its polarity is positive. This indicates that a hole current is generated around a drain voltage exceeding 600V.

  In addition, a phenomenon in which the drain current and the gate current are separated from the vicinity where the drain voltage reaches 900V appears. This shows that the positive charge accumulation in the collapse suppression film under the gate insulating film is remarkable, the negative bias applied to the gate electrode is canceled, and the gate is about to turn on. Yes.

  Thus, in order to obtain high reliability in the operation of the transistor even at a high voltage exceeding 600 V, it is necessary to protect the collapse suppression film below the gate electrode from the hole current.

  The present invention has been made in view of the above points, and can protect the collapse suppression film below the gate electrode against a hole current generated when a high voltage is applied, thereby realizing higher reliability. An object of the present invention is to provide a field effect transistor capable of satisfying the requirements.

In order to solve the above-described problems, the present invention provides a normally-on field effect transistor in which a source electrode, a drain electrode, and a gate electrode disposed between the electrodes are formed on the surface side where a plurality of nitride semiconductors are stacked. The plurality of nitride semiconductors are composed of at least a breakdown voltage layer made of Al _x Ga _1-x N, a channel layer made of GaN, and Al _y Ga _1-y N (0 <x <y <0.5). A collapse suppression film is formed on a portion between the surface of the plurality of stacked nitride semiconductors and the gate electrode.

According to this configuration, a hole path that is an interface where holes are likely to exist is formed between the pressure-resistant layer made of Al _x Ga ₁ -xN and the channel layer made of GaN. The hole current generated by the high voltage flows preferentially through this hole path. Therefore, the hole current moves away from the collapse suppression film under the gate electrode.

In the field effect transistor having the above structure, the channel layer has an intermediate layer made of Al _x Ga _1-x N inside.

  In the field effect transistor having the above structure, the sum of the thicknesses of the barrier layer and the channel layer is 50 to 500 nm.

  According to the configuration of the present invention, a field effect transistor capable of protecting the collapse suppression film below the gate electrode against a hole current generated when a high voltage is applied and realizing higher reliability. Can be provided.

It is sectional drawing of the field effect transistor of 1st Embodiment of this invention. It is a band calculation figure of the field effect transistor of 1st Embodiment of this invention. It is sectional drawing of the field effect transistor of a comparative example. It is a band calculation figure of the field effect transistor of a comparative example. It is sectional drawing of the field effect transistor of 2nd Embodiment of this invention. It is a band calculation figure of the field effect transistor of 2nd Embodiment of this invention. It is a graph which shows the relationship between the drain current of a conventional field effect transistor, a gate current, and a substrate current, and drain voltage.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

<First Embodiment>
First, the structure of the field effect transistor according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a field effect transistor.

As shown in FIG. 1, the field effect transistor 1 has a plurality of nitride semiconductors stacked on the surface of a substrate 2. The plurality of nitride semiconductors include a buffer layer 3, a withstand voltage layer 4 made of Al _x Ga _1-x N, a channel layer 5 made of GaN, and a barrier layer 6 made of Al _y Ga _1-y N. It is formed by laminating in order. A collapse suppression film 7, a gate insulating film 8, a source electrode 9, a drain electrode 10, and a gate electrode 11 are formed on the surface side where a plurality of nitride semiconductors are stacked.

A two-dimensional electron gas 12 is distributed at a high concentration at the interface between the GaN channel layer 5 and the Al _y Ga _1-y N barrier layer 6 and serves as an electron channel between the drain and the source. A hole path 13 is generated at the interface between the Al _x Ga _1-x N breakdown voltage layer 4 and the GaN channel layer 5 and serves as a path for releasing hole current.

  Next, a detailed configuration and a manufacturing method of the field effect transistor 1 will be described.

  As the substrate 2, for example, a Si substrate (111) surface can be used. As a material other than Si, a substrate made of a material such as SiC, sapphire, or GaN can also be used.

The buffer layer 3 is formed to improve the crystallinity of the nitride semiconductor layer formed on the surface of the buffer layer 3. The Al _x Ga _1-x N breakdown voltage layer 4, the GaN channel layer 5, and the Al _y Ga _1-y N barrier layer 6 are each epitaxially grown by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Can be sequentially formed on the surface of the buffer layer 3. The buffer layer 3 is formed by forming an AlN film and / or an AlGaN / AlN superlattice structure.

The Al _x Ga _1-x N breakdown voltage layer 4 is formed immediately above the buffer layer 3. As the composition x, if the value of x is too low, the effect of the hole path 13 is reduced. On the other hand, if the value of x is too high, the concentration of holes in the hole path 13 becomes too high, hole gas is generated, and drain leakage increases. Therefore, a preferable value of x is, for example, x = 0.05, and an appropriate performance of the hole path 13 can be maintained as long as 0 <x <0.1. In order to obtain a withstand voltage of 600 V or more, the sum of the Al _x Ga _1-x N withstand voltage layer 4 and the buffer layer 3 is preferably 1 to 3 μm or more.

Next, the GaN channel layer 5 is formed on the surface of the Al _x Ga _1-x N breakdown voltage layer 4. If the layer thickness of the GaN channel layer 5 is too thin, the closest distance between the hole path 13 and the gate electrode 11 becomes too short, which is not suitable for moving the hole current away from the gate electrode 11. On the other hand, if it is too thick, it is not suitable for efficiently collecting holes generated by a high voltage. Therefore, it is appropriate that the layer thickness of the GaN channel layer 5 is in the range of 50 to 500 nm in total with the layer thickness of the Al _y Ga _1-y N barrier layer 6 on which crystal growth is performed next.

Next, an Al _y Ga _1-y N barrier layer 6 is formed on the surface of the GaN channel layer 5. Since the two-dimensional electron gas 12 needs to be appropriately generated at the interface between the GaN channel layer 5 and the Al _y Ga _1-y N barrier layer 6, the composition y has a thin GaN channel layer 5 with a thin layer thickness. When not relaxed, for example, y = 0.20 is appropriate, and usually 0.1 <y <0.5 can be used. When the GaN channel layer 5 is thick and lattice-relaxed, a value obtained by adding y is appropriate. For example, when y = 0.05, 0.15 <y <0.55.

If the thickness of the Al _y Ga _1-y N barrier layer 6 is too thin, the concentration of the two-dimensional electron gas 12 becomes low, and if it is too thick, cracks occur. Therefore, the layer thickness of the Al _y Ga _1-y N barrier layer 6 is appropriately 5 to 50 nm, and can be changed according to the required concentration of the two-dimensional electron gas 12.

Next, a collapse suppression film 7 is formed on the surface of the Al _y Ga _1-y N barrier layer 6. In the current collapse phenomenon, electrons accumulate on the surface of the nitride semiconductor, thereby increasing the resistance when the transistor is on. In order to suppress this, the collapse suppression film 7 made of SiN is preferably used.

As the collapse suppression film 7, a Si-rich SiN film containing more Si than a normal SiN film (Si ₃ N ₄ ) was formed by CVD (Chemical Vapor Deposition). The gas flow rate ratio during CVD film formation was N ₂ / NH ₃ / SiH ₄ = 300 sccm / 40 sccm / 35 sccm, and the substrate temperature was 200 ° C. Thereby, a SiN film having a high Si ratio with a composition ratio of Si: N = 1.3 to 1.5: 1 can be formed. It is known that this SiN film can suppress current collapse more than a stoichiometric SiN film (Si ₃ N ₄ ). Thereafter, in order to further improve the collapse suppression characteristic and the leakage characteristic, for example, heat treatment is performed at 500 ° C. for 30 minutes.

  Next, the gate electrode 11 is formed. In forming the gate electrode 11, it is necessary to perform dry etching in the formation place of the gate electrode 11 on the surface of the collapse suppression film 7 and remove the collapse suppression film 7 in that portion. At that time, as shown in FIG. 1, a part of the collapse suppression film 7 on the drain electrode 10 side and having a length D is left.

  The reason is as follows. The portion of the gate electrode 11 where the electric field is most concentrated is a portion having a length D corresponding to the drain electrode 10 side end portion below the gate electrode 11. The region into which the hole current flows is mainly that portion. When the breakdown voltage (insulating property) of the portion is too low, the gate leak increases, and when the breakdown voltage (insulating property) is too high, the portion easily breaks due to hole accumulation. Therefore, it is necessary to form a film having an appropriate breakdown voltage (insulating property) comparable to that of the collapse suppression film 7.

Thereafter, a gate insulating film 8, which is a SiN film that is further Si-rich than the collapse suppression film 7, is formed in a portion from which the collapse suppression film 7 is removed. At that time, the SiH _4, the flow ratio _{NH 3 (SiH 4 / NH 3} ) the use of the film forming condition for increasing the 0.92. Thereby, gate leakage can be reduced.

  In this manner, the gate insulating film 8 is formed on the surface of the nitride semiconductor corresponding to the main portion of the gate electrode 11, and the length is formed on the surface of the nitride semiconductor corresponding to the end of the gate electrode 11 on the drain electrode 10 side. By forming the collapse suppression film 7 in the range of D, it is possible to obtain favorable characteristics in terms of both gate breakdown voltage and leakage characteristics. Here, if the length D of the collapse suppression film 7 formed on the lower side of the gate electrode 11 is too short, the leak characteristics deteriorate, and if it is too long, the breakdown voltage and reliability characteristics deteriorate. Therefore, the length D of the collapse suppression film 7 is suitably 0.1 to 0.5 μm, and preferably 0.2 μm, for example.

  As a material of the gate electrode 11, for example, a WN layer, WN / W in which W layers are sequentially stacked, or TiN is appropriate. The gate electrode 11 is formed by sputtering these.

Next, the source electrode 9 and the drain electrode 10 are formed. In forming the source electrode 9 and the drain electrode 10, dry etching is performed at the positions where the source electrode 9 and the drain electrode 10 are formed on the surface of the nitride semiconductor to form a recess structure. The depth of the recess of the source electrode 9 is set to a thickness corresponding to the GaN channel layer 5 (which reaches the hole path 13). The depth of the recess of the drain electrode 10 is set to a thickness corresponding to the Al _y Ga _1-y N barrier layer 6 (which reaches the two-dimensional electron gas 12). As a result, the source electrode 9 can come into contact with the two-dimensional electron gas 12 and the hole path 13, and the drain electrode 10 can come into contact with the two-dimensional electron gas 12.

  As a material for the source electrode 9 and the drain electrode 10, an alloy in which a Ti layer and an Al layer are sequentially laminated is used. The source electrode 9 and the drain electrode 10 are formed by sputtering these. Thereafter, for example, by performing a heat treatment at 500 ° C. for 30 minutes, the two-dimensional electron gas 12 and the hole path 13 can be brought into ohmic contact.

  Finally, although not shown, a gate field plate structure, a source field plate structure, a drain field plate structure, and various electrodes are appropriately formed by a general method, and the field effect transistor 1 is completed.

  Next, the operation of the field effect transistor 1 of the first embodiment will be described with reference to FIG. FIG. 2 is a band calculation diagram of the field effect transistor 1.

The vertical axis in FIG. 2 indicates electron energy (eV), and the horizontal axis indicates the distance (nm) from the surface of the nitride semiconductor. Further, in the upper side of FIG. 2, the ranges occupied by the Al _x Ga _1-x N breakdown voltage layer 4, the GaN channel layer 5, and the Al _y Ga _1-y N barrier layer 6 with respect to the distance from the surface of the nitride semiconductor. Is indicated by an arrow.

Regarding the configuration of the field effect transistor 1, the layer thickness of the Al _y Ga _1-y N barrier layer 6 is 25 nm, the layer thickness of the GaN channel layer 5 is 100 nm, and the composition is x = 0.05, y = 0.25. Was used. As a result, in FIG. 2, a conduction band band (Ec) is drawn on the upper side of the Fermi level (Ef), and a valence band band line (Ev) is drawn on the lower side. Yes.

According to FIG. 2, the valence band (Ev) is maximized at the interface between the GaN channel layer 5 and the Al _x Ga _1-x N breakdown voltage layer 4. As a result, holes generated by the drain high voltage are easily collected at the interface, and become a hole path 13 that is a path of holes. Even when a transistor is operated at a high drain voltage of 600 V or higher and holes are generated, most of the holes are collected in the hole path 13 and flow to the source electrode 9 as they are. Therefore, damage to the gate electrode 11 can be reduced, and the reliability and operation of the field effect transistor 1 can be improved and improved.

  Subsequently, as a comparative example, the structure and operation of a conventional field effect transistor will be described with reference to FIGS. FIG. 3 is a cross-sectional view of a field effect transistor of a comparative example, and FIG. 4 is a band calculation diagram of the field effect transistor of the comparative example. Since the basic configuration of this comparative example is the same as that of the first embodiment described with reference to FIGS. 1 and 2, the description of the same components as those of the first embodiment will be omitted. .

  A conventional field effect transistor 101 as a comparative example has a plurality of nitride semiconductors stacked on the surface of a substrate 102 as shown in FIG. As the plurality of nitride semiconductors, a buffer layer 103, a breakdown voltage layer 104 made of GaN, and a barrier layer 106 made of AlGaN are stacked in this order. A collapse suppression film 107, a source electrode 109, a drain electrode 110, and a gate electrode 111 are formed on the surface side where a plurality of nitride semiconductors are stacked. A two-dimensional electron gas 112 is distributed at a high concentration at the interface between the GaN breakdown voltage layer 104 and the AlGaN barrier layer 106, and serves as an electron channel between the drain and the source.

  The collapse suppression film 107 is formed over the entire surface of the nitride semiconductor. The gate electrode 111 is formed on the surface of the collapse suppression film 107. Therefore, the collapse suppression film 107 exists in the range over the entire lower surface of the gate electrode 111.

  The depths of the recesses in the source electrode 9 and the drain electrode 10 are each set to a thickness corresponding to the AlGaN barrier layer 106 (which reaches the two-dimensional electron gas 112). Thereby, the source electrode 109 and the drain electrode 110 can contact the two-dimensional electron gas 112.

  Next, the operation of the field effect transistor 101 of the comparative example will be described with reference to FIG. The vertical axis in FIG. 4 indicates electron energy (eV), and the horizontal axis indicates the distance (nm) from the surface of the nitride semiconductor. Further, on the upper side of FIG. 4, the range occupied by each of the GaN breakdown voltage layer 104 and the AlGaN barrier layer 106 is indicated by an arrow with respect to the distance from the surface of the nitride semiconductor.

  According to FIG. 4, there is no local maximum of the valence band (Ev) as in the field effect transistor 1 of the first embodiment described with reference to FIG. is there. As a result, when holes are generated, the holes can move freely inside the nitride semiconductor, and therefore go to the gate electrode 111 having the lowest potential. Therefore, when the field effect transistor 101 is operated at a high voltage exceeding 600 V, holes generated by the high voltage move to the gate electrode 111 as a hole current. As a result, the collapse suppression film 107 on the lower side of the gate electrode 111 is finally destroyed, and reliability cannot be obtained.

Second Embodiment
Next, the field effect transistor of 2nd Embodiment of this invention is demonstrated using FIG.5 and FIG.6. FIG. 5 is a sectional view of the field effect transistor, and FIG. 6 is a band calculation diagram of the field effect transistor. Since the basic configuration of this embodiment is the same as that of the first embodiment described with reference to FIGS. 1 and 2, the same reference numerals are assigned to the same components as those of the first embodiment. The description of the drawings and the description thereof will be omitted.

In the field effect transistor 1 of the second embodiment, as shown in FIG. 5, the GaN channel layer 5 has an intermediate layer 14 made of Al _x Ga _1-x N therein. The GaN channel layer 5 includes an upper GaN channel layer 5U and a lower GaN channel layer 5L.

Next, the operation of the field effect transistor 1 of the second embodiment will be described with reference to FIG. The vertical axis in FIG. 6 represents electron energy (eV), and the horizontal axis represents the distance (nm) from the surface of the nitride semiconductor. Further, on the upper side of FIG. 6, regarding the distance from the surface of the nitride semiconductor, the Al _x Ga _1-x N breakdown voltage layer 4, the GaN channel layer 5, the Al _x Ga _1-x N intermediate layer 14, and the Al _y Ga _{1 -y The} range occupied by each of the N barrier layers 6 is indicated by arrows.

The structure of the field effect transistor 1, the thickness of the Al _y Ga _1-y N barrier layer 6 and 25 nm, the thickness of the upper GaN channel layer 5U and 170 nm, a layer of Al _x Ga _1-x N intermediate layer 14 The thickness was 20 nm, the layer thickness of the lower GaN channel layer 5L was 10 nm, and the composition was x = 0.05 and y = 0.2. That is, an Al _x Ga _1-x N intermediate layer 14 having a thickness of 20 nm is inserted into the GaN channel layer 5 having a thickness of 200 nm. As a result, in FIG. 6, a conduction band band (Ec) is drawn on the upper side of the Fermi level (Ef), and a valence band band line (Ev) is drawn on the lower side. Yes.

According to FIG. 6, the valence band (Ev) is maximized in the vicinity of the Al _x Ga ₁ -xN intermediate layer 14. As a result, holes generated by the drain high voltage are easily collected in the vicinity of the Al _x Ga ₁ -xN intermediate layer 14, thereby forming a hole path 13 that is a path for holes.

  In the structure of the second embodiment, the lower GaN channel layer 5L is not lattice-relaxed even if the GaN channel layer 5 has a relatively thick layer thickness of 100 nm or more. Thereby, the piezoelectric polarization effect is maintained, and a sufficient hole path 13 can be generated. Even when the transistor operation is performed with a high drain voltage of 600 V or more, holes are generated, most of the holes are collected in the hole path 13 and flow to the source electrode 9 as they are. Therefore, damage to the gate electrode 11 can be reduced, and the reliability and operation of the field effect transistor 1 can be improved and improved.

As described above, in the normally-on field effect transistor 1 in which the source electrode 9, the drain electrode 10, and the gate electrode 11 disposed between the electrodes are formed on the surface side where a plurality of nitride semiconductors are stacked, The nitride semiconductor has at least an Al _x Ga _1-x N breakdown voltage layer 4, a GaN channel layer 5, and an Al _y Ga _1-y N (0 <x <y <0.5) barrier layer 6. A collapse suppression film 7 was formed in a portion between the surface of the plurality of nitride semiconductors and the gate electrode 11. As a result, a hole path 13, which is an interface where holes are likely to exist, is formed between the Al _x Ga _1-x N breakdown voltage layer 4 and the GaN channel layer 5. This is caused by the spontaneous polarization and the piezo polarization due to the influence of the Al _x Ga _1-x N breakdown voltage layer 4 which is the layer immediately below the GaN channel layer 5. The hole current generated by the high voltage flows preferentially through the hole path 13. Therefore, it is possible to keep the hole current away from the collapse suppression film 7 below the gate electrode 11.

In the field effect transistor 1, the GaN channel layer 5 has an Al _x Ga ₁ -xN intermediate layer 14 therein. For example, even if the GaN channel layer 5 has a relatively thick layer thickness of 100 nm or more, the GaN channel layer 5 is lattice-relaxed, so that the piezoelectric polarization effect is greatly weakened. This also weakens the hole path 13 at the same time, making it difficult to effectively induce the hole current. In such a case, for example, the lower GaN channel layer 5L is formed to a thickness of 10 to 100 nm, which is a layer thickness that does not relax the lattice, and then the Al _x Ga _1-x N intermediate layer 14 is inserted, and the upper GaN channel layer 5U is further formed as an upper layer. Form. Since the lower GaN channel layer 5L does not undergo lattice relaxation, the piezoelectric effect is high and the hole path 13 is not weakened. Therefore, even when the GaN channel layer 5 is thick, a hole current can be effectively induced to the source electrode 9 and damage to the gate electrode 11 can be reduced.

In the field effect transistor 1, the sum of the layer thicknesses of the Al _y Ga _1-y N barrier layer 6 and the GaN channel layer 5 is 50 to 500 nm. As described above, the distance between the hole path 13 and the gate electrode 11 corresponds to the sum of the layer thicknesses of the Al _y Ga _1-y N barrier layer 6 and the GaN channel layer 5. If the sum of these layer thicknesses is too thin, the closest distance between the hole path 13 and the gate electrode 11 becomes too short, which is not suitable for moving the hole current away from the gate electrode 11. Further, if the sum of the layer thicknesses is too thick, it is not suitable for efficiently collecting holes generated by a high voltage. Therefore, the distance between the gate electrode 11 and the hole path 13 is preferably 50 to 500 nm. Here, due to restrictions on the concentration of the two-dimensional electron gas 12 and the occurrence of cracks, the thickness of the Al _y Ga _1-y N barrier layer 6 can be adjusted only within a relatively narrow range of 5 to 50 nm. Thereby, the sum of the layer thicknesses of the Al _y Ga _1-y N barrier layer 6 and the GaN channel layer 5 is adjusted as the distance between the gate electrode 11 and the hole path 13 by adjusting the layer thickness of the GaN channel layer 5. 50 to 500 nm can be secured.

  In this way, according to the configuration of the above embodiment of the present invention, the collapse suppression film 7 below the gate electrode 11 can be protected against the hole current generated when a high voltage is applied, and higher reliability is achieved. Thus, it is possible to provide the field effect transistor 1 capable of realizing the characteristics.

  Although the embodiments and examples of the present invention have been described above, the scope of the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the invention.

  The present invention can be used in a field effect transistor.

1 FET 2 substrate 3 buffer layer 4 Al _x Ga _1-x N voltage withstanding layer (withstand voltage layer)
5 GaN channel layer (channel layer)
6 Al _y Ga _1-y N barrier layer (barrier layer)
7 Collapse Suppression Film 8 Gate Insulating Film 9 Source Electrode 10 Drain Electrode 11 Gate Electrode 14 Al _x Ga _1-x N Intermediate Layer (Intermediate Layer)

Claims (3)

In a normally-on type field effect transistor in which a source electrode, a drain electrode, and a gate electrode disposed between the electrodes are formed on the surface side of a plurality of nitride semiconductors stacked,
The plurality of nitride semiconductors include at least a breakdown voltage layer made of Al _x Ga _1-x N, a channel layer made of GaN, and a barrier made of Al _y Ga _1-y N (0 <x <y <0.5). A field-effect transistor, wherein a collapse suppression film is formed between a portion of the surface of the plurality of nitride semiconductors stacked and the gate electrode. 2. The field effect transistor according to claim 1, wherein the channel layer has an intermediate layer made of Al _x Ga _1-x N therein.   The field effect transistor according to claim 1 or 2, wherein a sum of thicknesses of the barrier layer and the channel layer is 50 to 500 nm.

Images