JP2014158195A - Wireless communication system and semiconductor device for wireless communication - Google Patents

Abstract

A highly reliable demodulation operation is realized in a wireless communication system and a wireless communication semiconductor device.
For example, an antenna ANT that receives an RF signal RFi1 in which amplitude modulation based on a modulation signal is added to a carrier signal of a specific frequency, I-side and Q-side sampling mixer circuits MIXi, MIXq, and a processing circuit PBK are provided. MIXi detects RFi1 by sampling at a specific frequency and a phase of X °, and MIXq detects by sampling RFi1 at a specific frequency and a phase of Y °. X ° and Y ° are 90 ° <X ° <180 ° and 180 ° <Y ° <270 ° and (180 ° −X °) ≈ (Y ° −180), where the zero cross point of the carrier signal is 0 °. The PBK calculates the difference value between the detection signals IOUT and QOUT from MIXi and MIXq.
[Selection] Figure 1

Description

  The present invention relates to a wireless communication system and a wireless communication semiconductor device, for example, a technology effective when applied to a wireless communication semiconductor device that realizes an NFC (Near Field Communication) function, a mobile phone system including the wireless communication semiconductor device, and the like. .

  For example, Patent Document 1 discloses a technique that enables reliable clock reproduction and correct data reproduction even when the duty ratio changes from 50% with the carrier signal frequency varying. Specifically, the I arm and the Q arm are respectively compared in phase with the binarized signal obtained by binarizing the detection signal, and the I arm and the binarized signal are phase-synchronized using the phase comparison result as appropriate. . Japanese Patent Application Laid-Open No. 2004-228561 shows a configuration that includes sampling mixer circuits on the I side and Q side and a signal generator that supplies a local signal to the sampling mixer circuit, and does not use a PLL circuit for the signal generator. . Non-Patent Document 1 describes a communication hall.

Japanese Patent Laid-Open No. 2007-6060 JP 2012-109647 A

Hiroshi Isobe, “Introduction to non-contact IC card design”, Nikkan Kogyo Shimbun, October 2005, p. 46-50

  In recent years, NFC (Near Field Communication) functions have been increasingly installed on behalf of mobile devices such as mobile phone systems and digital cameras. NFC is a non-contact short-range communication standard via a magnetic field by magnetic coupling. The carrier signal (carrier wave) is 13.56 MHz, the modulation method is basically ASK (Amplitude Shift Keying), and the modulation frequency is about 1 MHz at maximum. In NFC, there are a card mode in which a mobile device operates as an IC card and a reader / writer mode (hereinafter referred to as RW mode) in which the mobile device operates as a reader / writer (RW). The wireless communication operation in the card mode and the RW mode is realized mainly by a wireless communication semiconductor chip (referred to as an NFC chip) mounted in the mobile device.

  Here, operations in the card mode and the RW mode will be briefly described with reference to FIGS. 2 (a) and 2 (b). As shown in FIG. 2A, the NFC chip set to the card mode CDMD receives a high-frequency signal (hereinafter also referred to as an RF signal) RFi1 to which ASK modulation (in other words, amplitude modulation) is applied from the reader / writer RW. Then, the modulated signal is demodulated. On the other hand, as shown in FIG. 2B, the NFC chip set in the RW mode RWMD first transmits the carrier signal CR2 toward the IC card CD. At this time, the CD applies ASK modulation to the CR 2 using a method called load modulation, for example, and the NFC chip demodulates the modulation signal.

  One of the causes of the characteristic deterioration in such an NFC chip is noise in the reception system. The noise is mainly caused by temporal noise (so-called jitter) riding on the clock signal or carrier signal. Jitter is presumed to be caused by, for example, peripheral CPUs or noise caused by logic. FIG. 17A and FIG. 17B are explanatory diagrams showing an example of problems associated with noise in the wireless communication system studied as a premise of the present invention.

  As shown in FIG. 17A, the RF signal RFi received by the antenna is obtained by superimposing a modulation signal (for example, an ASK modulation signal) of about 1 MHz at the maximum on a 13.56 MHz carrier signal. Here, for example, a detection method using a sampling mixer circuit is used, and the sampling mixer circuit samples the RFi at a sampling point SP corresponding to the 13.56 MHz sampling clock signal SCK. When the SCK has no jitter (ie, the period Ts is constant) and the SP is stable, a desired detection signal OUT is obtained as shown in FIG. It can be demodulated correctly.

  On the other hand, in FIG. 17B, the sampling clock signal SCK ′ has jitter (that is, the cycle Ts fluctuates), and accordingly, the sampling point SP ′ varies. As a result, the temporal variation is converted into a variation in the voltage direction in the detection signal OUT ′, and it becomes difficult to correctly demodulate the modulation signal. Such a problem may occur in both the card mode and the RW mode, but becomes particularly serious in the card mode. For example, in the RW mode, as can be seen from FIG. 2B, normally, both the carrier signal and the sampling clock signal are generated by themselves, and therefore, such a problem can be suppressed to some extent by increasing the accuracy thereof. On the other hand, in the card mode, as can be seen from FIG. 2A, the sampling clock signal is generated by itself and the carrier signal is generated by the external reader / writer RW. For this reason, there may be a limit to keeping the phase relationship between the carrier signal and the sampling clock signal uniform.

  Furthermore, as another problem, in the RW mode, as shown in Non-Patent Document 1, there is a problem called a communication hole (or null). As shown in FIG. 2 (b), the communication hole refers to the relative positional relationship between the reader / writer (RW) and the IC card, although the IC card has applied ASK modulation. This is a phenomenon in which the modulation component appears not in the amplitude direction but in the phase direction. In this case, the reader / writer (RW) substantially receives an RF signal to which PSK (Phase Shift Keying) modulation is applied.

  In order to solve this communication hole problem, for example, as suggested in Non-Patent Document 1 or Patent Document 2, an orthogonal (IQ) demodulation method may be used. That is, detection is performed using the I-side clock and the Q-side clock whose phase is shifted by 90 ° from the I-side clock. By using two clocks on the I side and the Q side, when one of the I side and the Q side has high detection sensitivity for ASK modulation and low detection sensitivity for PSK modulation, the other of the I side and Q side The detection sensitivity for ASK modulation is low, and the detection sensitivity for PSK modulation is high. Therefore, by complementing each other with the detection results of the two systems, the modulated signal can be correctly demodulated even when there is a communication hole.

  However, when the sampling mixer circuit as described with reference to FIGS. 17A and 17B is used, the detection and demodulation with higher reliability (in other words, lower error rate) are performed by the inventors. In order to do this, it has been found that the sampling point must be optimized with the I-side clock and the Q-side clock.

  Embodiments to be described later have been made in view of the above, and other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  A wireless communication system according to an embodiment includes an antenna that receives an RF signal in which amplitude modulation based on a modulation signal is added to a carrier signal of a specific frequency, first and second sampling mixer circuits, and a processing circuit. The first sampling mixer circuit detects the RF signal by sampling it at a specific frequency and a phase of X °, and the second sampling mixer circuit detects the RF signal by sampling it at a specific frequency and a phase of Y °. The processing circuit performs operations upon receiving the first and second detection signals from the first and second sampling mixer circuits. Here, X ° and Y ° are 90 ° <X ° <180 °, 180 ° <Y ° <270 °, and (180 ° −X °) ≈ (Y, where the zero cross point of the carrier signal is 0 °. The processing circuit calculates a difference value between the level of the first detection signal and the level of the second detection signal.

  According to the embodiment, a highly reliable demodulation operation can be realized in the wireless communication system and the wireless communication semiconductor device.

In the radio | wireless communications system by one embodiment of this invention, it is a block diagram which shows the schematic structural example of the principal part. (A) is a schematic diagram which shows the schematic operation example at the time of card mode in the radio | wireless communications system of FIG. 1, (b) is a schematic diagram which shows the schematic operation example at the time of RW mode in the radio | wireless communications system of FIG. is there. (A) And (b) is a figure which shows an example of the sampling point in the sampling mixer circuit of FIG. 1, (a) is a figure which shows at the time of card mode, (b) is a figure which shows at the time of RW mode. is there. (A) is a figure which shows an example of the sampling point including Fig.3 (a), (b) is a figure which shows an example of the effect of (a). It is a supplementary figure of Drawing 4 (a) and Drawing 4 (b). FIG. 4 is a schematic diagram illustrating an operation example when the sampling point of FIG. 3A is used in the wireless communication system of FIG. 1. (A) And (b) is the schematic which shows the operation example at the time of using the sampling point of FIG.3 (b) in the radio | wireless communications system of FIG. FIG. 2 is a circuit diagram showing a more detailed configuration example of the mixer circuit unit in the wireless communication system of FIG. 1. It is a wave form diagram which shows the operation example of the sampling mixer circuit of FIG. FIG. 2 is a circuit diagram showing a more detailed configuration example of the clock generation circuit in the wireless communication system of FIG. 1. It is a wave form diagram which shows the operation example of FIG. FIG. 12 is a circuit diagram illustrating a detailed configuration example of a clock generation circuit different from FIG. 11. (A), (b) and (c) are circuit block diagrams showing different configuration examples of the processing circuit in the wireless communication system of FIG. It is a block diagram which shows the example of schematic structure of the mobile telephone system provided with the radio | wireless communications system of FIG. FIG. 15 is a block diagram showing a more detailed configuration example around the NFC chip (wireless communication semiconductor device) in FIG. 14. FIG. 16 is a block diagram illustrating a more detailed configuration example of the NFC chip (semiconductor device for wireless communication) in FIG. 15. (A) And (b) is explanatory drawing which shows an example of the problem accompanying the noise in the radio | wireless communications system examined as a premise of this invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<< Schematic configuration of wireless communication system (main part) >>
FIG. 1 is a block diagram showing a schematic configuration example of a main part of a radio communication system according to an embodiment of the present invention. FIG. 1 shows a configuration example around a reception system circuit unit in a wireless communication system that realizes an NFC (Near Field Communication) function. 1 includes an antenna ANT, a mixer circuit unit MIXBK, filters FLTi and FLTq, an amplifier circuit unit AMPBK, an analog / digital conversion circuit unit ADCBK, a logic circuit unit LGBK, a clock extraction circuit CKEXT, an oscillation circuit OSC, and a clock generator. A circuit CKGEN and a mode setting unit MDSET are provided.

  As described above, the mode setting unit MDSET sets a card mode that operates as an IC card or an RW mode that operates as a reader / writer (RW), and notifies the set mode to the clock generation circuit CKGEN using a mode signal MD. The antenna ANT receives high-frequency signals (RF signals) RFi1 and RFi2 obtained by adding ASK modulation (amplitude modulation) based on a modulation signal (for example, a baseband signal of about 1 MHz at the maximum) to a carrier signal of a specific frequency (for example, 13.56 MHz). To do. RFi1 is an RF signal received when operating in the card mode, and RFi2 is an RF signal received when operating in the RW mode.

  The mixer circuit unit MIXBK includes an I-side sampling mixer circuit (first sampling mixer circuit) MIXi and a Q-side sampling mixer circuit (second sampling mixer circuit) MIXq. MIXi detects the RF signal RFi1 (or RFi2) by sampling it at a specific frequency (for example, 13.56 MHz) and a phase of X ° (details will be described later). In other words, MIXi directly converts RFi1 (or RFi2). Specifically, MIXi is an I-side sampling switch (first switch) SWi that is controlled to be turned on / off by an I-side local signal LOi, and an I-side coupled between the output terminal of SWi and the ground power supply voltage GND. A sampling capacitor (first capacitor) Csi, and performs sampling based on LOi.

  Further, here, the I-side sampling mixer circuit MIXi further includes an output switch SWoi having an input end coupled to the output end of the I-side sampling switch SWi, and an output capacitor Coi coupled between the output end of the SWoi and GND. With. SWoi is controlled to be turned on / off by an inverted signal (/ LOi) of the I-side local signal LOi. The electric charge stored in the I-side sampling capacitor Csi is distributed to Coi according to the inversion signal (/ LOi), and MIXi is an I-side detection signal (first detection signal) IOUT at one end of Coi (the output end of SWoi). Is output.

  Similarly, the Q-side sampling mixer circuit (second sampling mixer circuit) MIXq detects the RF signal RFi1 (or RFi2) by sampling it at a specific frequency (for example, 13.56 MHz) and a phase of Y ° (details will be described later). (In other words, direct conversion). More specifically, MIXq includes a Q-side sampling switch (second switch) SWq that is controlled to be turned on / off by a Q-side local signal LOq, and a Q-side sampling capacitor coupled between the output terminal of SWq and GND ( A second capacitor) Csq, and performs sampling based on LOq. MIXq further includes an output switch SWoq having an input terminal coupled to the output terminal of SWq, and an output capacitor Coq coupled between the output terminal of SWoq and GND. SWoq is controlled to be turned on / off by an inverted signal (/ LOq) of LOq, and MIXq outputs a Q-side detection signal (second detection signal) QOUT at one end of Coq (the output end of SWoq).

  Note that the sampling mixer circuits MIXi and MIXq in FIG. 1 conceptually indicate that they are sampling mixer circuits, and the actual configuration is not limited to FIG. 1. For example, FIG. Various configurations such as a configuration example can be applied as a representative. However, in general, the sampling mixer circuit includes sampling switches SWi and SWq and sampling capacitors Csi and Csq, and often has various circuit configurations at the subsequent stage.

  The filters FLTi and FLTq are, for example, bandpass filters and lowpass filters, and pass only the necessary signal bands for the detection signals IOUT and QOUT, respectively. The amplifier circuit unit AMPBK amplifies the output signals of FLTi and FLTq with a predetermined gain, and the analog / digital conversion circuit unit ADCBK converts the output signal from the AMPBK into a digital signal. The logic circuit unit LGBK determines the “H” level and the “L” level based on the digital signal from the ADCBK, and demodulates the modulation signal included in the RF signals RFi1 and RFi2. Here, FLTi, FLTq, AMPBK, ADCBK, and LGBK function as a processing circuit PBK. The PBK mainly calculates a difference value between the level of IOUT and the level of QOUT, which will be described in detail later. By doing so, the modulated signal is demodulated.

  The clock extraction circuit CKEXT receives an RF signal (for example, RFi1), extracts a carrier signal included therein, and generates an extracted clock signal CKext. Although not particularly limited, CKEXT is configured by a circuit that detects the center level of the RF signal and compares the center level with the RF signal by a comparator circuit. Although not particularly limited, the oscillation circuit OSC is a crystal oscillation circuit, and generates a reference clock signal CCosc having a specific frequency (for example, 13.56 MHz). The clock generation circuit CKGEN selects CKext or CKosc based on the mode signal MD from the mode setting unit MDSET, and generates the I-side local signal LOi and the Q-side local signal LOq using the selected clock signal.

  2A is a schematic diagram showing a schematic operation example in the card mode in the wireless communication system of FIG. 1, and FIG. 2B is a schematic operation example in the RW mode in the wireless communication system of FIG. It is a schematic diagram shown. As shown in FIG. 2A, the wireless communication system operating in the card mode CDMD receives the RF signal RFi1 generated by the external reader / writer RW. The RFi1 is a signal obtained by adding ASK modulation (amplitude modulation) based on a first modulation signal (for example, about 1 MHz at the maximum) to a first carrier signal having a specific frequency (for example, 13.56 MHz).

  The wireless communication system receives the RF signal RFi1, and first generates an extracted clock signal CKext corresponding to the first carrier signal from RFi1 using the clock extraction circuit CKEXT. The clock generation circuit CKGEN generates the I-side local signal (first local signal) LOi and the Q-side local signal LOq (second local signal) using the CKext (in other words, the first carrier signal). Then, the wireless communication system demodulates the first modulation signal included in RFi1 through various processes in the mixer circuit unit MIXBK and the subsequent processing circuit PBK.

  As shown in FIG. 2B, the wireless communication system operating in the RW mode RWMD first transmits a second carrier signal CR2 having a specific frequency (for example, 13.56 MHz) to the external IC card CD. . The CD performs ASK modulation on the CR2 using load modulation using the second modulation signal. The wireless communication system receives an RF signal RFi2 that is a signal obtained by adding ASK modulation (amplitude modulation) based on a second modulated signal (for example, about 1 MHz at the maximum) to the CR2. In other words, the radio communication system drives the load of the antenna ANT of the own antenna and the load of the antenna ANT of the CD whose size varies with CR2, and as a result, RFi2 corresponding to the load fluctuation of the CD ANT is obtained. Receive.

  Here, when transmitting the second carrier signal CR2 toward the IC card CD, the wireless communication system passes through an antenna drive circuit (not shown) based on the reference clock signal CCosc generated by the oscillation circuit OSC. The antenna ANT is driven. Further, the clock generation circuit CKGEN generates the I-side local signal (third local signal) LOi and the Q-side local signal (fourth local signal) LOq using the CCosc (in other words, the second carrier signal). Then, the radio communication system demodulates the second modulation signal included in RFi2 through various processes in the mixer circuit unit MIXBK and the subsequent processing circuit PBK.

<Sampling points of sampling mixer circuit>
3A and 3B are diagrams showing an example of sampling points in the sampling mixer circuit of FIG. 1, FIG. 3A is a diagram showing the card mode, and FIG. These are figures which show the time of RW mode. As shown in FIG. 3A, in the card mode, the zero-cross point of the RF signal RFi1 is set to 0 °, and the sampling point SPi is set to a phase of 135 ° in the I-side sampling mixer circuit MIXi, and the Q-side In the sampling mixer circuit MIXq, the sampling point SPq is set at a phase of 225 °. That is, as described in FIG. 1, MIXi samples RFi1 at a specific frequency (for example, 13.56 MHz) and a phase of X ° = 135 °, and MIXq calculates RFi1 as a specific frequency and a phase of Y ° = 225 °. To sample.

  Here, as can be seen from FIG. 3A, the zero-cross point of the RF signal RFi1 corresponds to the position corresponding to the rising edge of RFi1 (the position of 0 ° shown in FIG. 3A) and the position corresponding to the falling edge ( There is a 180 ° portion shown in FIG. In this embodiment, any one of these locations may be set to 0 °. For example, when the position corresponding to the falling is set to 0 °, the sampling point SPi of 135 ° corresponds to the position of 315 ° when fitted to FIG. 3A, and the sampling point SPq of 225 ° is equal to FIG. When applied to (a), it corresponds to a position of 405 °.

  On the other hand, as shown in FIG. 3B, in the RW mode, the zero cross point of the RF signal RFi2 is set to 0 °, and the sampling point SPi is set to a phase of 90 ° in the I-side sampling mixer circuit MIXi. In the Q side sampling mixer circuit MIXq, the sampling point SPq is set to a phase of 180 °. That is, as described in FIG. 1, MIXi samples RFi2 at a specific frequency (for example, 13.56 MHz) and a phase of X ° = 90 °, and MIXq calculates RFi2 at a specific frequency and a phase of Y ° = 180 °. To sample. Similarly to the case of FIG. 3A, the zero-crossing point may be any of the rising and falling positions. When the position corresponding to the falling is set to 0 °, the SPi of 90 ° is as shown in FIG. When applied to (b), it corresponds to a 270 ° position, and 180 ° SPq corresponds to a 360 ° position when applied to FIG. 3 (b).

<Details of sampling points in card mode>
FIG. 4A is a diagram showing an example of sampling points including FIG. 3A, and FIG. 4B is a diagram showing an example of the effect of FIG. 4A. FIG. 5 is a supplementary diagram of FIG. 4 (a) and FIG. 4 (b). In FIG. 3A, X ° = 135 ° is set as the sampling point SPi and Y ° = 225 ° is set as the sampling point SPq in the card mode CDMD, but this is not necessarily limited thereto. That is, as shown in FIG. 4A, the zero cross point of the RF signal RFi1 is set to 0 °, SPi may be set in the range of 90 ° <X ° <180 °, and SPq is set to 180 ° <Y ° <270. Set in the range of °. In this case, however, it is desirable to satisfy ΔPi (= 180 ° −X °) ≈ΔPq (= Y ° −180 °). As in the case of FIG. 3A, the zero cross point is not limited to the rising position of RFi1, and may be a falling position.

  FIG. 4B shows an RF signal RFi1 and an RF signal RFi1 'when jitter or the like occurs in RFi1. Further, detection signals IOUT and QOUT when RFi1 is detected at the sampling points SPi and SPq, and detection signals IOUT 'and QOUT' when RFi1 'is detected at the SPi and SPq, respectively, are shown. By setting SPi and SPq within the range shown in FIG. 4A, as can be seen from FIG. 4B, even when jitter occurs in RFi1, the I-side detection signal and the Q-side detection signal By calculating the difference value between them, the influence of jitter or the like can be reduced, and a highly reliable demodulation operation can be realized.

  That is, in the I-side detection signal and the Q-side detection signal, there is a high possibility that a deviation in the voltage direction due to the jitter of the RF signal or the like will occur in the same phase. Therefore, by calculating the difference value, ΔIQ (= IOUT−QOUT) ≈ΔIQ ′ (= IOUT′−QOUT ′) can be easily realized. However, as shown in FIG. 5, in the RF signal RFi1, the voltage fluctuation with respect to a predetermined time fluctuation Δt is large near the zero cross point (ΔV2) and small near the apex (ΔV1). Therefore, in order to make the amount of deviation in the voltage direction accompanying the jitter of the RF signal the same between the I-side detection signal and the Q-side detection signal, as shown in FIG. 4A, ΔPi (= 180 ° −X °) ≈ΔPq (= Y ° −180 °).

  Further, among them, as shown in FIG. 3A, it is desirable that X ° = 135 ° and Y ° = 225 °. One reason for this is that the closer the X ° and Y ° are to the vicinity of the apexes (90 ° and 270 ° in FIG. 3A), the more likely that the deviation in the voltage direction due to jitter or the like will occur in reverse phase. Conversely, the difference value between the I-side detection signal and the Q-side detection signal becomes smaller as X ° and Y ° approach the zero cross point (180 ° in FIG. 3A). . Further, as another reason, as shown in FIG. 3B, in the RW mode, sampling points SPi and SPq whose phases are different by 90 ° are used. Therefore, SPi and SPi whose phases are different by 90 ° are also used in the card mode. The use of SPq can simplify the circuit for generating SPi and SPq (clock generation circuit CKGEN in FIG. 1).

  FIG. 6 is a schematic diagram illustrating an operation example when the sampling point of FIG. 3A is used in the wireless communication system of FIG. As shown in FIG. 6, when there is no jitter in the RF signal (in the case of the broken line RFi1), a desired signal level is obtained for each of the I-side detection signal IOUT and the Q-side detection signal QOUT, and the difference value (IOUT− By calculating (QOUT), it becomes possible to further expand the signal level. On the other hand, when there is jitter in the RF signal (in the case of solid line RFi1 ′), it is possible to obtain a signal level that is difficult to perform correct demodulation with only the I-side detection signal IOUT ′ and the Q-side detection signal QOUT ′. By calculating (IOUT′−QOUT ′), a signal level equivalent to that when there is no jitter (IOUT−QOUT) can be secured. Here, the case where jitter occurs in the RF signal is taken as an example, but the same applies when the sampling point is shifted due to the jitter.

<< Details of sampling points in RW mode >>
FIGS. 7A and 7B are schematic diagrams illustrating an operation example when the sampling point of FIG. 3B is used in the wireless communication system of FIG. FIG. 7A shows an operation example when RFi2 to which ASK modulation is applied is received as the RF signal RFi2 in the RW mode RWMD. In this case, the maximum detection sensitivity is obtained at the apex of RFi2, and the minimum detection sensitivity is obtained at the zero cross point of RFi2. Therefore, as described in FIG. 3B, the sampling point SPi is set to X ° = 90 ° as a vertex, and the sampling point SPq is set to Y ° = 180 ° as a zero cross point. As a result, the detection signal IOUT based on SPi has a desired signal level reflecting the ASK modulation signal, and the detection signal QOUT based on SPq ideally has a signal level of zero.

  On the other hand, FIG. 7B shows an operation example when RFi2 to which PSK modulation is applied is received as the RF signal RFi2 in the RW mode RWMD. FIG. 7B shows an operation example in the case of the communication hole described above. That is, in the period Tp in FIG. 7B, the wireless communication system in which the IC card CD in FIG. 2B is applied with ASK modulation and is operating in the phase direction and operating in RWMD. The antenna ANT receives RFi2 to which PSK modulation is added.

  In this case, the minimum detection sensitivity is obtained at the apex of the RF signal RFi2, and the maximum detection sensitivity is obtained at the zero cross point of RFi2. Therefore, as described in FIG. 3B, the sampling point SPi is set to X ° = 90 ° as a vertex, and the sampling point SPq is set to Y ° = 180 ° as a zero cross point. As a result, the detection signal IOUT based on SPi ideally has a zero signal level, and the detection signal QOUT based on SPq has a desired signal level reflecting the PSK modulation signal.

  Therefore, by calculating the difference value between the I-side detection signal IOUT and the Q-side detection signal QOUT regardless of the presence or absence of a communication hole, the detection sensitivity for ASK modulation and the detection sensitivity for PSK modulation are complemented, and Demodulation operation with high performance can be realized. 7 (a) and 7 (b), if (IOUT−QOUT) is calculated, the signal level in FIG. 7 (a) becomes small → large → small, and the signal level in FIG. 7 (b). Becomes large → small → large. Since the correspondence between the level of the signal level and the logic 'H' level and 'L' level is appropriately determined by the preamble performed at the start of communication, the correspondence in FIGS. 7 (a) and 7 (b). Relationship reversal is not a problem. For example, in the case where the predetermined period of “H” level in the preamble is the period Tp of FIG. 7B, the small signal level may be associated with the “H” level.

  As described above, in the wireless communication system of the present embodiment, different sampling points are set in the card mode and the RW mode, and the I-side detection signal IOUT and the Q-side detection signal QOUT are commonly used in the card mode and the RW mode. The method of calculating the difference value between them is used. This makes it possible to realize a demodulation operation with high reliability (in other words, an error rate is low and accurate) regardless of the presence or absence of jitter and the presence or absence of communication holes. In addition to this, it is possible to reduce the circuit scale of the processing circuit PBK and simplify the processing contents.

  For example, as a comparative example, I-side and Q-side sampling points whose phases are different by 90 ° are appropriately determined, and the I-side detection signal IOUT and the Q-side detection signal QOUT are used as “IOUT + QOUT”, “IOUT−QOUT”, “ A method is conceivable in which “−IOUT + QOUT” and “−IOUT−QOUT” are calculated and the one having the highest signal level is selected. In this case, the circuit scale of the processing circuit PBK is increased, the processing content is complicated, and a sufficient signal level may not always be obtained. The method of the present embodiment can provide a beneficial effect even when compared with such a comparative example. The sampling points SPi and SPq shown in FIGS. 3 (a) and 3 (b) are not necessarily strictly the values shown in FIGS. 3 (a) and 3 (b). Even in the range of about 10 °, substantially the same effect can be obtained.

<< Details of sampling mixer circuit >>
FIG. 8 is a circuit diagram showing a more detailed configuration example of the mixer circuit unit in the wireless communication system of FIG. FIG. 9 is a waveform diagram showing an operation example of the sampling mixer circuit of FIG. The mixer circuit unit MIXBK1 in FIG. 8 includes an I-side sampling mixer circuit MIXi and a Q-side sampling mixer circuit MIXq, and a transconductance amplifier TA that converts the RF signal RFi received by the antenna into a current signal. Each of MIXi and MIXq has a circuit configuration called an MTDSM (Multi Tap Direct Sampling Mixer) or the like.

  The I-side sampling mixer circuit MIXi includes two banks SAZBK and SBZBK and an output unit OTBK in addition to the I-side sampling switch SWi and the I-side sampling capacitor Csi. Each of SAZBK and SBZBK includes a plurality (eight in this case) of switches SW1 to SW8 and a plurality of (here, four) capacitors Cr, and OTBK includes a plurality of switches SWr and SWd and a capacitor Cb.

  Here, as shown in FIG. 9, first, in the bank SAZBK, the switches SW5 to SW8 are turned off and only SW1 is controlled to be turned on from SW1 to SW4. In this state, the I-side sampling switch SWi is turned on. Is turned on a plurality of times by the local signal LOi. As a result, electric charges accompanying the current from the transconductance amplifier TA are sequentially stored in the capacitors Cr corresponding to the sampling capacitors Csi and SW1. By this operation, the characteristics of the moving average filter can be obtained. Next, SW2 is controlled to be turned on instead of SW1, and in this state, SWi is controlled to be turned on a plurality of times by LOi. As a result, the electric charge accompanying the current from TA is sequentially stored in the capacitor Cr corresponding to Csi and SW2. The characteristics of an IIR (Infinite Impulse Response) filter can be obtained by switching Cr while maintaining the charge of Csi.

  Thereafter, similarly, switching from SW2 to SW3 and switching from SW3 to SW4 are sequentially performed. Thereafter, by turning on SW5 to SW8, the electric charge stored in the capacitors Cr corresponding to SW1 to SW4 is distributed to the capacitor Cb via the switch SWd. An I-side detection signal IOUT is obtained by this Cb. Thereafter, the switch SWr is controlled to be on, and the charge of each Cr is discharged. Further, while the switches SW5 to SW8 are turned on, the operation of the bank SBZBK is performed in the same manner as in the case of the bank SAZBK described above.

  The configuration and operation of the Q side sampling mixer circuit MIXq are the same as those of the I side sampling mixer circuit MIXi except that the Q side local signal LOq is used. In practice, the number of switches and capacitors Cr in each of the banks SAZBK and SBZBK is appropriately set according to the frequency of the carrier signal and the frequency of the modulation signal. Various other configurations of the sampling mixer circuit are known. If the phase of the local signals LOi and LOq is adjusted based on the sampling points of the present embodiment described above, any configuration is applied. May be.

<Details of clock generation circuit>
FIG. 10 is a circuit diagram showing a more detailed configuration example of the clock generation circuit in the wireless communication system of FIG. FIG. 11 is a waveform diagram showing an operation example of FIG. The clock generation circuit CKGEN1 shown in FIG. 10 is called a DLL (Delay Locked Loop) circuit or the like, and includes a phase comparison circuit PD, a charge pump circuit CP, a loop filter LF, a driver circuit DV, and a plurality (eight in this case). ) Delay elements DLY1 to DLY8. Here, CKGEN1 further includes a selection circuit SEL that selects a clock signal (input clock signal) CLK0 in accordance with the mode signal MD. The SEL selects the extracted clock signal CKext of FIG. 1 as CLK0 when the MD indicates the card mode, and selects the reference clock signal CCosc of FIG. 1 as CLK0 when the MD indicates the RW mode.

  The clock signal (input clock signal) CLK0 is sequentially delayed through the delay elements DLY1 to DLY8, and is output from the DLY8 as a clock signal (output clock signal) CLK8. The delay elements DLY1 to DLY8 are each configured by the same circuit and have the same delay time. The phase comparison circuit PD compares the phases of CLK0 and CLK8 and outputs the phase comparison result to the charge pump circuit CP. The CP charges or discharges the loop filter LF according to the PD phase comparison result (for example, how much the phase of CLK8 is advanced or how much is delayed with respect to CLK0). The driver circuit DV generates a control voltage Vcnt according to the output level of LF, and the delay times of DLY1 to DLY8 are controlled according to this Vcnt. Thereby, the delay times of DLY1 to DLY8 are controlled so that the phases of the input clock signal and the output clock signal match.

  In the state in which the DLL circuit of FIG. 10 is locked, as shown in FIG. 11, the delay elements DLY1 to DLY8 have the same specific frequency (for example, 13.56 MHz) as the extracted clock signal CKext or the reference clock signal CCosc, and the phases are in order. Clock signals CLK1 to CLK8 shifted by 45 ° are generated. Therefore, by using, for example, CLK3 and CLK5 as the I-side and Q-side local signals (first and second local signals) LOi and LOq in the card mode CDMD, the 135 ° and 225 ° shown in FIG. Sampling points SPi and SPq can be realized. In this case, the rising edges of CLK3 and CLK5 can be SPi and SPq, and the falling edges can be SPi and SPq. Therefore, CLK7 and CLK1 may be used instead of CLK3 and CLK5.

  Further, by using, for example, CLK2 and CLK4 as the I-side and Q-side local signals (third and fourth local signals) LOi and LOq in the RW mode RWMD, the 90 ° and 180 ° shown in FIG. Sampling points SPi and SPq can be realized. In this case, the rising edges of CLK2 and CLK4 can be SPi and SPq, and the falling edges can be SPi and SPq. Therefore, CLK6 and CLK8 may be used instead of CLK2 and CLK4. Note that SPi and SPq are usually determined at the timing when the sampling switches SWi and SWq in FIG. 1 transition from on to off.

  FIG. 12 is a circuit diagram showing a detailed configuration example of a clock generation circuit different from FIG. The clock generation circuit CKGEN2 shown in FIG. 12 is called a PLL (Phase Locked Loop) circuit or the like, and includes a phase comparison circuit PD, a charge pump circuit CP, a loop filter LF, a voltage controlled oscillation circuit VCO, and a frequency dividing circuit NDIV. Is provided. Here, CKGEN2 further includes a selection circuit SEL that selects the clock signal CLK0 according to the mode signal MD, and a comparison circuit CMP that generates the I-side and Q-side local signals LOi and LOq using the signal from NDIV. With. SEL is the same as in FIG.

  The phase comparison circuit PD compares the phase of the clock signal CLK0 with the phase of the clock signal CLK0x1 output from the frequency dividing circuit NDIV, and outputs the phase comparison result to the charge pump circuit CP. The CP charges or discharges the loop filter LF according to the PD phase comparison result (for example, how much the phase of CLK0x1 is advanced or how much is delayed with respect to CLK0). The voltage controlled oscillation circuit VCO generates a clock signal CLKx4 having an oscillation frequency corresponding to the control voltage Vcnt generated by LF. NDIV divides CLKx4 from the VCO by 4 and outputs CLK0x1.

  In a state where the PLL circuit of FIG. 12 is locked, the voltage controlled oscillation circuit VCO generates a clock signal CLKx4 having an oscillation frequency four times that of the clock signal CLK0, and the frequency dividing circuit NDIV has an oscillation frequency that is one time that of CLK0. A clock signal CLKx1 is generated. The NDIV generates a clock signal CLKx2 having an oscillation frequency twice that of CLK0 in the course of this frequency division operation. At this time, NDIV can be regarded as a 3-bit counter that makes one cycle of CLK0, with CLKx4, CLKx2, and CLKx1 as 1 bit. In this case, a 1-bit count corresponds to a phase of 45 °.

  Therefore, for example, in the card mode, the local signal is generated by triggering the counter setting value ISET representing the phase of 135 ° and the counter setting value QSET representing the phase of 225 ° using the comparison circuit CMP. LOi and LOq are generated. Similarly, in the case of the RW mode, LOi and LOq are generated by triggering with ISET representing a 90 ° phase and QSET representing a 180 ° phase using CMP.

  As described above, the clock generation circuit CKGEN in FIG. 1 includes a DLL circuit and a PLL circuit. Although not shown in the drawings, the present invention can be realized by a configuration using a phase interpolation method instead of such a phase synchronization method. However, as can be seen from the comparison between FIG. 11 and FIG. 12, for example, by using a DLL circuit, the circuit configuration can be further simplified, and since it is not necessary to generate a quadruple clock or the like, power consumption can be reduced. Furthermore, it is easy to improve the accuracy of phase adjustment. Therefore, from this point of view, it is more preferable that CKGEN is configured with a DLL circuit.

  As a comparative example, if a negative feedback control loop such as a PLL circuit or a DLL circuit is not used, phase adjustment with sufficient accuracy cannot be performed depending on the conditions of PVT (process / voltage / temperature). There is a case. In particular, in the case of the communication hole in the RW mode shown in FIG. 7B, for example, if the sampling points SPi and SPq are shifted to the location shown in FIG. 3A in the card mode, the I-side detection signal IOUT Even if the difference value between the signal and the Q-side detection signal QOUT is used, correct demodulation operation may be difficult. Therefore, in order to perform phase adjustment with high accuracy, it is desirable to use a PLL circuit or a DLL circuit (particularly a DLL circuit). Further, the local signals LOi and LOq are not necessarily signals having a duty of 50% as shown in FIG. 11, and it is possible to appropriately adjust the on-duty for controlling the sampling switch to turn on in some cases.

<Details of processing circuit>
FIGS. 13A, 13B, and 13C are circuit block diagrams showing different configuration examples of the processing circuit in the wireless communication system of FIG. In the processing circuit PBK1 shown in FIG. 13A, the amplifier circuit unit AMPBK is composed of two amplifier circuits AMPi and AMPq respectively corresponding to the I side and the Q side, and the analog / digital conversion circuit unit ADCBK is also connected to the I side and the Q side. It is composed of two analog / digital conversion circuits ADCi and ADCq corresponding to the respective sides. In this case, the logic circuit unit LGBK receives the digital signals from the ADCi and ADCq, and performs a digital operation on the difference value to perform demodulation of the “H” level or the “L” level.

  In the processing circuit PBK2 shown in FIG. 13B, the amplifier circuit unit AMPBK is composed of a differential amplifier circuit AMPD that amplifies the I-side detection signal IOUT and the Q-side detection signal QOUT with a predetermined gain as differential inputs. The digital conversion circuit unit ADCBK is also composed of a differential analog / digital conversion circuit ADCD. In this case, since the digital signal from ADCD represents the difference value between IOUT and QOUT, the logic circuit unit LGBK demodulates the 'H' level or 'L' level depending on the magnitude of the digital signal. Just do it.

  In the processing circuit PBK3 shown in FIG. 13 (c), the amplifier circuit unit AMPBK is composed of one amplifier circuit AMPiq commonly used on the I side and the Q side, and the analog / digital conversion circuit unit ADCBK is also on the I side and the Q side. It is composed of one analog / digital conversion circuit ADCiq used in common. Since AMPiq and ADCiq are used in common in this way, here, a selection switch TSW1 is provided on the input side of AMPBK, and a selection switch TSW2 is provided on the output side of ADCBK. In this case, both TSW1 and TSW2 alternately select the I side and the Q side in a time division manner, and accordingly, the logic circuit unit LGBK receives the digital signal corresponding to the I side and the digital signal corresponding to the Q side. Receive alternately in time division. The LGBK performs demodulation of the “H” level or the “L” level by digitally calculating a difference value between the alternately received digital signals.

  The amplifier circuit and the analog / digital conversion circuit usually have a unique offset voltage, and if the offset voltage is different between the I side and the Q side, for example, the accuracy in demodulation may be lowered. Therefore, from this point of view, it is preferable to use the configuration example of FIG. 13B or FIG. 13C rather than FIG. Further, when comparing FIG. 13B and FIG. 13C, from the viewpoint of the switching of the selection switches TSW1 and TSW2 and the ease of processing accompanying the processing of the logic circuit unit LGBK, it is more than that of FIG. The configuration example of FIG. 13B is more desirable. As described above, since only the difference value between the I side and the Q side needs to be calculated by using the method of the present embodiment, the circuit configuration and processing of the processing circuit PBK are represented by the configuration example of FIG. The content can be simplified.

《Example of application to mobile phone system》
FIG. 14 is a block diagram illustrating a schematic configuration example of a mobile phone system including the wireless communication system of FIG. The mobile phone system shown in FIG. 14 includes a mobile phone device MDEV, and a portable antenna ANTF and an NFC antenna ANTN connected thereto. The MDEV includes an NFC chip (semiconductor device for wireless communication) NFCCP, a portable high-frequency signal processing unit RFFU, a baseband processor unit BBU, an application processor unit APPU, and various peripheral units PERU. These are mounted in one casing. Has been.

  The various peripheral units PERUU are hardware for realizing various functions provided in the mobile phone system, and are not particularly limited, but are representative of various drive circuits such as a display, a microphone, and a speaker, and a sensor circuit such as a camera. There are various things. The application processor unit APPU executes various application programs stored in the mobile phone system. For example, when the application processor unit APPU performs external communication, the baseband processor unit BBU performs various processes in the baseband required for the external communication. The portable high-frequency signal processing unit RFFU mainly performs up-conversion of baseband signals to high-frequency signals (for example, 2 GHz band, etc.) and down-converts high-frequency signals to base bend signals between the portable antennas ANTF and BBU. Convert and so on.

  The NFC chip (semiconductor device for wireless communication) NFCCP includes an NFC high-frequency signal processing unit RFNU, a security unit SECU, and the like. The NFCCP and the NFC antenna ANTN constitute an NFC unit NFCU. The antenna ANT shown in FIG. 1 corresponds to the ANTN shown in FIG. 14, and portions other than the ANT shown in FIG. 1 are included in the RFNU shown in FIG. The ANTN is composed of, for example, a coil and performs wireless communication using an electromagnetic induction method. RFNU performs up-conversion of a baseband signal (for example, about 1 MHz at the maximum) to a high-frequency signal (for example, 13.56 MHz), down-conversion of a high-frequency signal to a base bend signal based on the method described in FIG. . The SECU protects personal information and the like by performing processing such as authentication in the course of this communication processing.

  In recent years, in such mobile devices, various functions are condensed in a small area due to downsizing, high functionality, high speed, etc., and the problem of noise has become more prominent. Further, since mobile devices are used in various environments, fluctuations in temperature and the like are likely to occur. Therefore, by controlling the phase with high precision using a clock generation circuit as shown in FIG. 10 and setting the sampling point as shown in FIG. High demodulation operation can be realized.

  FIG. 15 is a block diagram showing a more detailed configuration example around the NFC chip (wireless communication semiconductor device) in FIG. 15, in addition to the NFC chip (wireless communication semiconductor device) NFCCP, the rectifier RECT provided between the NFCCP and the NFC antenna ANTN, and the NFCCP and the baseband processor unit BBU in FIG. The provided host interface device HSTIF is shown. RECT rectifies a high-frequency signal received by ANTN using a diode bridge circuit or the like to generate a power supply voltage. The power supply voltage is used, for example, in the card mode.

  The host interface device HSTIF appropriately controls communication between the NFC chip NFCCP and the baseband processor unit BBU. A crystal resonator XTAL used in the oscillation circuit (here, crystal oscillation circuit) OSC in FIG. 1 is connected to the NFCCP as an external component. The rectifiers RECT, NFCCP, and HSTIF are not particularly limited, but are mounted as a module on one wiring board. Note that RECT and HSTIF may be formed in NFCCP depending on circumstances.

  FIG. 16 is a block diagram illustrating a more detailed configuration example of the NFC chip (semiconductor device for wireless communication) in FIG. The NFC chip (semiconductor device for wireless communication) NFCCP shown in FIG. 16 includes an analog circuit unit RFABK and a digital circuit unit RFLBK for high frequency signal processing, a security circuit unit SECBK, a processor circuit CPU, a nonvolatile memory (ROM, EEPROM), and A volatile memory RAM or the like is provided. The RFABK includes a transmission system circuit unit TXBK and a reception system circuit unit RXBK.

  For example, the various analog circuits (MIXBK, FLTi, FLTq, AMPBK, ADCBK, CKEXT, OSC, CKGEN) shown in FIG. 1 are included in RFABK, and most of them are included in RXBK. Further, for example, various digital circuits (MDSET, LGBK) shown in FIG. 1 are included in the RFLBK. The processor circuit CPU executes, for example, a predetermined program (RW mode control program, card mode control program, etc.) stored in a nonvolatile memory (ROM, EEPROM) while using the volatile memory RAM for work. . In the process of executing this program, the high-frequency digital circuit section RFLBK performs digital signal processing accompanying modulation / demodulation and encoding, sequence control of the high-frequency analog circuit section RFABK, and the security circuit section SECBK performs authentication operations and the like. Do.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, here, a wireless communication system using a 13.56 MHz electromagnetic wave signal has been described as an example. However, the present invention is not limited to this, and any wireless communication system using ASK modulation may be applied similarly. The same effect can be obtained.

ADC Analog / Digital Converter Circuit ADCBK Analog / Digital Converter Circuit ADCD Differential Type Analog / Digital Converter Circuit AMP Amplifier Circuit AMPBK Amplifier Circuit Unit AMPD Differential Amplifier Circuit ANT Antenna ANTF Portable Antenna ANTN NFC Antenna APPU Application Processor Unit BBU Baseband processor unit C capacitor CD IC card CDMD card mode CK, CLK clock signal CKEXT clock extraction circuit CKGEN clock generation circuit CMP comparison circuit CP charge pump circuit CPU processor circuit CR carrier signal DLY delay element DV driver circuit FLT filter GND Ground power supply voltage HSTIF Host Interface Device ISET, QSET Count Setpoint LF loop filter LGBK logic circuit LO local signal MD mode signal MDEV mobile telephone apparatus MDSET mode setting unit MIX sampling mixer circuit MIXBK mixer circuit section NDIV divider NFCCP NFC chip (wireless communication semiconductor device)
NFCU NFC unit OSC oscillation circuit OTBK output unit OUT, OUT ', IOUT, QOUT, IOUT', QOUT 'detection signal PBK processing circuit PD phase comparison circuit PERUU various peripheral units RAM volatile memory RECT rectifier RF, RF' high frequency signal ( RF signal)
RFABK Analog circuit part RFFU Portable high frequency signal processing unit

Claims (16)

An antenna for receiving an RF signal in which amplitude modulation based on a modulation signal is added to a carrier signal of a specific frequency;
A first sampling mixer circuit that detects the RF signal by sampling at the specific frequency and a phase of X °;
A second sampling mixer circuit that detects the RF signal by sampling at the specific frequency and a phase of Y °;
A processing circuit that performs an operation in response to the first detection signal from the first sampling mixer circuit and the second detection signal from the second sampling mixer circuit;
The X ° and the Y ° are 90 ° <X ° <180 °, 180 ° <Y ° <270 °, and (180 ° −X °) ≈ (Y, where the zero cross point of the carrier signal is 0 °. (° -180 °),
The wireless communication system, wherein the processing circuit demodulates the modulation signal by calculating a difference value between a level of the first detection signal and a level of the second detection signal. The wireless communication system according to claim 1, wherein
Further, a clock for generating a first local signal having the specific frequency and the phase of X ° and a second local signal having the phase of the specific frequency and the phase of Y ° using the carrier signal included in the RF signal. A generator circuit;
The first sampling mixer circuit includes:
A first switch controlled to be turned on and off by the first local signal;
A first capacitor coupled to the first switch;
The second sampling mixer circuit includes:
A second switch controlled to be turned on / off by the second local signal;
And a second capacitor coupled to the second switch. The wireless communication system according to claim 2, wherein
The X ° is around 135 °,
The wireless communication system, wherein Y ° is around 225 °. The wireless communication system according to claim 3,
The clock generation circuit includes a DLL circuit that controls delay times of a plurality of delay elements so that a phase of an output clock signal matches a phase of the carrier signal included in the RF signal,
The wireless communication system, wherein the first and second local signals are generated at output nodes of different delay elements among the plurality of delay elements. The wireless communication system according to claim 4, wherein
The wireless communication system, wherein the specific frequency is 13.56 MHz. A setting unit for setting whether the card mode that operates as an IC card or the reader / writer mode that operates as a reader / writer;
In the card mode, a first RF signal in which amplitude modulation based on the first modulation signal is added to the first carrier signal having a specific frequency is received. In the reader / writer mode, the first RF signal is directed to an external IC card. An antenna for transmitting a second carrier signal of the specific frequency and receiving a second RF signal subjected to load modulation based on a second modulation signal by the external IC card;
In the card mode, the first RF signal is detected by sampling at the specific frequency and the phase of X1 °, and in the reader / writer mode, the second RF signal is detected at the specific frequency and X2 °. A first sampling mixer circuit that detects by sampling in phase;
In the card mode, the first RF signal is detected by sampling at the specific frequency and the phase of Y1 °, and in the reader / writer mode, the second RF signal is detected by the specific frequency and Y2 °. A second sampling mixer circuit that detects by sampling in phase;
A processing circuit that performs an operation in response to the first detection signal from the first sampling mixer circuit and the second detection signal from the second sampling mixer circuit;
The X1 ° and the Y1 ° are 90 ° <X1 ° <180 °, 180 ° <Y1 ° <270 °, and (180 ° −X1 °) ≈ where the zero cross point of the first carrier signal is 0 °. It is a value satisfying (Y1 ° -180 °),
The X2 ° and the Y2 ° are X2 ° ≈90 ° and Y2 ° ≈180 °, where the zero cross point of the second carrier signal is 0 °,
In the card mode and the reader / writer mode, the processing circuit calculates the difference value between the level of the first detection signal and the level of the second detection signal in both the card mode and the reader / writer mode. A wireless communication system that demodulates a modulated signal. The wireless communication system according to claim 6, wherein
Further, in the card mode, a first local signal having the specific frequency and the phase of X1 ° and a second local signal having the specific frequency and the phase of Y1 ° using the first carrier signal; In the reader / writer mode, a third local signal having the specific frequency and the phase of X2 ° and a fourth frequency having the specific frequency and the phase of Y2 ° are used by using the second carrier signal. A clock generation circuit for generating a local signal;
The first sampling mixer circuit includes:
A first switch that is controlled to be turned on / off by the first local signal in the card mode, and that is turned on / off by the third local signal in the reader / writer mode;
A first capacitor coupled to the first switch;
The second sampling mixer circuit includes:
A second switch that is controlled to be turned on / off by the second local signal in the card mode, and that is turned on / off by the fourth local signal in the reader / writer mode;
And a second capacitor coupled to the second switch. The wireless communication system according to claim 7, wherein
X1 ° is around 135 °,
The wireless communication system, wherein Y1 ° is around 225 °. The wireless communication system according to claim 8, wherein
And an oscillation circuit for generating the second carrier signal,
The clock generation circuit includes:
A selection circuit that selects one of the first and second carrier signals as an input clock signal;
A DLL circuit that controls delay times of a plurality of delay elements such that the phase of the output clock signal matches the phase of the input clock signal,
The wireless communication system, wherein the first to fourth local signals are generated at output nodes of different delay elements among the plurality of delay elements. The wireless communication system according to claim 9, wherein
The processing circuit is
A differential amplifier circuit that amplifies the first detection signal and the second detection signal as a differential input;
An analog-digital conversion circuit that converts an output signal of the differential amplifier circuit into a digital signal. A setting unit for setting whether the card mode that operates as an IC card or the reader / writer mode that operates as a reader / writer;
A first sampling mixer circuit that detects the first RF signal received by the antenna by sampling at a specific frequency and a phase of X1 ° during the card mode;
A second sampling mixer circuit for detecting by sampling the first RF signal at the specific frequency and a phase of Y1 ° during the card mode;
A processing circuit that performs an operation in response to the first detection signal from the first sampling mixer circuit and the second detection signal from the second sampling mixer circuit;
The first RF signal is a signal obtained by adding amplitude modulation based on a first modulation signal to the first carrier signal of the specific frequency,
The X1 ° and the Y1 ° are 90 ° <X1 ° <180 °, 180 ° <Y1 ° <270 °, and (180 ° −X1 °) ≈ where the zero cross point of the first carrier signal is 0 °. It is a value satisfying (Y1 ° -180 °),
The processing circuit demodulates the first modulation signal by calculating a difference value between the level of the first detection signal and the level of the second detection signal in the card mode. Semiconductor device. The semiconductor device for wireless communication according to claim 11,
X1 ° is around 135 °,
The Y1 ° is a semiconductor device for wireless communication that is around 225 °. The semiconductor device for wireless communication according to claim 12,
In addition, an oscillation circuit that generates a second carrier signal of the specific frequency for transmission to an external IC card in the reader / writer mode,
The first sampling mixer circuit further detects the second RF signal received by the antenna by sampling at the specific frequency and a phase of X2 ° in the reader / writer mode,
In the reader / writer mode, the second sampling mixer circuit further detects the second RF signal by sampling the second RF signal at the specific frequency and a phase of Y2 °,
The second RF signal is a signal obtained by performing load modulation on the second carrier signal based on the second modulation signal by the external IC card,
The X2 ° and the Y2 ° are X2 ° ≈90 ° and Y2 ° ≈180 °, where the zero cross point of the second carrier signal is 0 °,
The processing circuit calculates the difference value between the level of the first detection signal and the level of the second detection signal in the reader / writer mode in addition to the card mode, thereby calculating the second modulation. A semiconductor device for wireless communication that demodulates a signal. The semiconductor device for wireless communication according to claim 13,
Further, in the card mode, a first local signal having the specific frequency and the phase of X1 ° and a second local signal having the specific frequency and the phase of Y1 ° using the first carrier signal; In the reader / writer mode, a third local signal having the specific frequency and the phase of X2 ° and a fourth frequency having the specific frequency and the phase of Y2 ° are used by using the second carrier signal. A clock generation circuit for generating a local signal;
The first sampling mixer circuit includes:
A first switch that is controlled to be turned on / off by the first local signal in the card mode, and that is turned on / off by the third local signal in the reader / writer mode;
A first capacitor coupled to the first switch;
The second sampling mixer circuit includes:
A second switch that is controlled to be turned on / off by the second local signal in the card mode, and that is turned on / off by the fourth local signal in the reader / writer mode;
A semiconductor device for wireless communication, comprising: a second capacitor coupled to the second switch. The semiconductor device for wireless communication according to claim 14,
The clock generation circuit includes:
A selection circuit that selects one of the first and second carrier signals as an input clock signal;
A DLL circuit that controls delay times of a plurality of delay elements such that the phase of the output clock signal matches the phase of the input clock signal,
The semiconductor device for wireless communication, wherein the first to fourth local signals are generated at output nodes of different delay elements among the plurality of delay elements. The semiconductor device for wireless communication according to claim 15,
The processing circuit is
A differential amplifier circuit that amplifies the first detection signal and the second detection signal as a differential input;
An analog-digital conversion circuit that converts an output signal of the differential amplifier circuit into a digital signal.

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